Burr-Brown OPA2631 Dual, low power, single-supply operational amplifier Datasheet

®
OPA
OPA2631
263
1
For most current data sheet and other product
information, visit www.burr-brown.com
Dual, Low Power, Single-Supply
OPERATIONAL AMPLIFIER
TM
FEATURES
DESCRIPTION
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The OPA2631 is a dual, low power, voltage-feedback
amplifier designed to operate on a single +3V or +5V
supply. Operation on ±5V or +10V supplies is also
supported. The input range extends below ground and
to within 1V of the positive supply. Using complementary common-emitter outputs provides an output swing
to within 30mV of ground and 130mV of the positive
supply. The high output drive current and low differential gain and phase errors also make it ideal for singlesupply consumer video products.
Low distortion operation is ensured by the high gain
bandwidth (68MHz) and slew rate (100V/µs), making
the OPA2631 an ideal input buffer stage to 3V and 5V
CMOS converters. Unlike other low power, singlesupply amplifiers, distortion performance improves as
the signal swing is decreased. A low 6nV/√Hz input
voltage noise supports wide dynamic range operation.
The OPA2631 is available in an industry standard
SO-8 package. Where a single channel, single-supply
operational amplifier is required, consider the OPA631
and OPA632. Where higher full-power bandwidth and
lower distortion are required, consider the OPA2634.
HIGH BANDWIDTH: 75MHz (G = +2)
LOW SUPPLY CURRENT: 6mA/ch
+3V AND +5V OPERATION
INPUT RANGE INCLUDES GROUND
4.8V OUTPUT SWING ON +5V SUPPLY
HIGH SLEW RATE: 100V/µs
LOW INPUT VOLTAGE NOISE: 6nV/√Hz
APPLICATIONS
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DIFFERENTIAL RECEIVERS/DRIVERS
ACTIVE FILTERS
MATCHED I AND Q CHANNEL AMPLIFIERS
CCD IMAGING CHANNELS
LOW POWER ULTRASOUND
PORTABLE CONSUMER ELECTRONICS
SPICE model available at www.burr-brown.com
RELATED PRODUCTS
+3V
2.26kΩ
374Ω
VIN
SINGLES
DUALS
Medium Speed, No Disable
With Disable
OPA631
OPA632
OPA2631
—
High Speed, No Disable
With Disable
OPA634
OPA635
OPA2634
—
+3V
1/2
OPA2631
100Ω
ADS901
10-Bit
20Msps
22pF
562Ω
750Ω
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
PDS-1378A
Printed in U.S.A. August, 1999
SPECIFICATIONS: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS /2, unless otherwise noted.
OPA2631U
TYP
CONDITIONS
+25°C
+25°C
0°C to
70°C
–40°C to
+85°C
UNITS
MIN/ TEST
MAX LEVEL(1)
G = +2, VO ≤ 0.5Vp-p
G = +5, VO ≤ 0.5Vp-p
G = +10, VO ≤ 0.5Vp-p
G ≥ +10
VO ≤ 0.5Vp-p
G = +2, 2V Step
0.5V Step
0.5V Step
G = +2, 1V Step
VO = 2Vp-p, f = 5MHz
VO = 2Vp-p, f = 1MHz, RL = 1kΩ
f > 1MHz
f > 1MHz
75
16
7.6
68
5
100
5.3
5.4
17
44
84
6.0
1.9
0.5
1.2
93
50
12
5.6
51
—
64
8.0
7.5
28
40
68
6.8
2.6
—
—
—
40
10
4.2
40
—
52
11
10
38
38
66
7.6
2.9
—
—
—
32
8.5
3.7
36
—
47
12.8
11.6
42
35
62
7.9
3.6
—
—
—
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
ns
dB
dB
nV/√Hz
pA/√Hz
%
degrees
dB
min
min
min
min
typ
min
max
max
max
min
min
max
max
typ
typ
typ
B
B
B
B
C
B
B
B
B
B
B
B
B
C
C
C
62
2.5
—
11
0.3
—
56
6
—
21
1
—
50
8
—
27
1.3
—
46
11
50
40
2
7
dB
mV
µV/°C
µA
µA
nA/°C
min
max
max
max
max
max
A
A
B
A
A
B
–0.5
4.0
74
–0.1
3.7
70
–0.1
3.7
68
–0.1
3.5
60
V
V
dB
max
min
min
B
A
A
10 || 2.1
400 || 1.2
—
—
—
—
—
—
kΩ || pF
kΩ || pF
typ
typ
C
C
Figure 1, f ≤ 50kHz
0.03
0.16
4.87
4.60
80
90
100
0.6
0.06
0.17
4.8
4.4
25
38
—
—
0.09
0.20
4.7
4.4
20
24
—
—
0.12
1.7
4.6
3.1
5
10
—
—
V
V
V
V
mA
mA
mA
Ω
max
max
min
min
min
min
typ
typ
A
A
A
A
A
A
C
C
VS = +5V
V = +5V
Input Referred
—
—
6
6
59
2.7
10.5
6.4
5.8
52
2.7
10.5
6.7
5.5
49
2.7
10.5
6.9
4.8
48
V
V
mA/chan
mA/chan
dB
min
max
max
min
min
A
A
A
A
A
–40 to +85
—
—
—
°C
typ
C
125
—
—
—
°C/W
typ
C
PARAMETER
Gain Bandwidth Product
Peaking at a Gain of +1
Slew Rate
Rise Time
Fall Time
Settling Time to 0.1%
Spurious Free Dynamic Range
Input Voltage Noise
Input Current Noise
NTSC Differential Gain
NTSC Differential Phase
Channel-to-Channel Isolation
Input Referred, f = 5MHz
DC PERFORMANCE
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Offset Current Drift
INPUT
Least Positive Input Voltage
Most Positive Input Voltage
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
Current Output, Sourcing
Current Output, Sinking
Short-Circuit Current (output shorted to either supply)
Closed-Loop Output Impedance
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power Supply Rejection Ratio (PSRR)
VCM = 2.0V
VCM = 2.0V
Input Referred
RL = 1kΩ to 2.5V
RL = 150Ω to 2.5V
RL = 1kΩ to 2.5V
RL = 150Ω to 2.5V
S
AC PERFORMANCE (Figure 1)
Small-Signal Bandwidth
GUARANTEED
THERMAL CHARACTERISTICS
Specification: U
Thermal Resistance
U
SO-8
NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
®
OPA2631
2
SPECIFICATIONS: VS = +3V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS /2, unless otherwise noted.
OPA2631U
TYP
PARAMETER
AC PERFORMANCE (Figure 2)
Small-Signal Bandwidth
Gain Bandwidth Product
Peaking at a Gain of +1
Slew Rate
Rise Time
Fall Time
Settling Time to 0.1%
Spurious Free Dynamic Range
Input Voltage Noise
Input Current Noise
Channel-to-Channel Isolation
DC PERFORMANCE
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Offset Current Drift
INPUT
Least Positive Input Voltage
Most Positive Input Voltage
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
Current Output, Sourcing
Current Output, Sinking
Short Circuit Current (output shorted to either supply)
Closed-Loop Output Impedance
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power Supply Rejection Ratio (PSRR)
GUARANTEED
CONDITIONS
+25°C
+25°C
0°C to
70°C
UNITS
G = +2, VO ≤ 0.5Vp-p
G = +5, VO ≤ 0.5Vp-p
G = +10, VO ≤ 0.5Vp-p
G ≥ +10
VO ≤ 0.5Vp-p
1V Step
0.5V Step
0.5V Step
1V Step
VO = 1Vp-p, f = 5MHz
VO = 1Vp-p, f = 1MHz, RL = 1kΩ
f > 1MHz
f > 1MHz
Input Reference, f = 5MHz
61
15
7.7
63
5
95
5.6
5.6
40
44
84
6.2
2.0
93
45
11
4.6
47
—
52
9
9
63
37
67
7.0
2.6
—
35
9
4.0
34
—
46
11.3
11.3
85
34
65
7.8
2.9
—
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
ns
dB
dB
nV/√Hz
pA/√Hz
dB
min
min
min
min
typ
min
max
max
max
min
min
max
max
typ
B
B
B
B
C
B
B
B
B
B
B
B
B
C
60
0.5
—
12
0.3
—
54
3.5
—
21
1
—
50
4
45
26
1.3
2
dB
mV
µV/°C
µA
µA
nA/°C
min
max
max
max
max
max
A
A
B
A
A
B
–0.5
2
72
–0.3
1.75
66
–0.1
1.3
65
V
V
dB
max
min
min
B
A
A
10 || 2.1
400 || 1.2
—
—
—
—
kΩ || pF
kΩ || pF
typ
typ
C
C
Figure 2, f < 50kHz
0.03
0.05
2.95
2.85
55
55
80
0.6
0.05
0.15
2.85
2.66
21
21
—
—
0.05
0.16
2.84
2.60
14
14
—
—
V
V
V
V
mA
mA
mA
Ω
max
max
min
min
min
min
typ
typ
A
A
A
A
A
A
C
C
VS = +3V
VS = +3V
Input Referred
—
—
5.3
5.3
57
2.7
10.5
5.7
5.0
50
2.7
10.5
6.2
4.8
48
V
V
mA/chan
mA/chan
dB
min
max
max
min
min
A
A
A
A
A
–40 to +85
°C
typ
C
125
°C/W
typ
C
VCM = 1.0V
VCM = 1.0V
Input Referred
RL = 1kΩ to 1.5V
RL = 150Ω to 1.5V
RL = 1kΩ to 1.5V
RL = 150Ω to 1.5V
THERMAL CHARACTERISTICS
Specification: U
Thermal Resistance
U
SO-8
MIN/ TEST
MAX LEVEL(1)
NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility
for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or
licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support
devices and/or systems.
®
3
OPA2631
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Power Supply ................................................................................ +11VDC
Internal Power Dissipation .................................... See Thermal Analysis
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range .................................................... –0.5 to +VS +0.3V
Storage Temperature Range ......................................... –40°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (TJ ) ........................................................... +175°C
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored
using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.
PIN CONFIGURATIONS
Top View
SO-8
OPA2631
Out A
1
8
+VS
–In A
2
7
Out B
+In A
3
6
–In B
GND
4
5
+In B
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
OPA2631U
SO-8 Surface-Mount
182
–40°C to +85°C
OPA2631
"
"
"
"
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
OPA2631U
OPA2631U/2K5
Rails
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “OPA2631U/2K5” will get a single
2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
®
OPA2631
4
TYPICAL PERFORMANCE CURVES: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS /2, unless otherwise noted (see Figure 2).
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
6
12
VO = 200mVp-p
6
–3
3
–6
–9
G = +5
–12
–15
VO = 0.2Vp-p
9
G = +2
0
Gain (dB)
Normalized Gain (dB)
3
0
–3
VO = 1Vp-p
–6
VO = 2Vp-p
–9
G = +10
–18
–12
–21
–15
–24
VO = 4Vp-p
–18
1
10
100
300
1
Frequency (MHz)
VO
VIN
VO
VIN
Time (10ns/div)
Time (10ns/div)
CHANNEL-TO-CHANNEL CROSSTALK
OUTPUT SWING vs LOAD RESISTANCE
1.0
0.8
4.7
0.7
4.6
0.6
4.5
0.5
4.4
0.4
4.3
0.3
Minimum VO
4.1
4.0
50
0.2
–50
–60
–70
–80
–90
0.1
0.0
1000
100
Input-Refered Isolation (dB)
Maximum Output Voltage (V)
0.9
4.8
4.2
–40
Minimum Output Voltage (V)
Maximum VO
300
VO = 4Vp-p
Input and Output Voltage (500mV/div)
Input and Output Voltage (50mV/div)
VO = 200mVp-p
4.9
100
LARGE-SIGNAL PULSE RESPONSE
SMALL-SIGNAL PULSE RESPONSE
5.0
10
Frequency (MHz)
–100
1
10
100
Frequency (MHz)
RL (Ω)
®
5
OPA2631
TYPICAL PERFORMANCE CURVES: VS = +5V
(Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS /2, unless otherwise noted (see Figure 1).
HARMONIC DISTORTION vs NON-INVERTING GAIN
HARMONIC DISTORTION vs OUTPUT VOLTAGE
–30
–30
VO = 2Vp-p
f = 5MHz
–40
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
f = 5MHz
3rd Harmonic
–50
2nd Harmonic
–60
–70
–80
3rd Harmonic
–40
2nd Harmonic
–50
–60
–70
–80
0.1
1
1
4
10
Gain Magnitude (V/V)
Output Voltage (Vp-p)
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION vs INVERTING GAIN
–30
–30
VO = 2Vp-p
3rd Harmonic
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
VO = 2Vp-p
f = 5MHz
–40
2nd Harmonic
–50
–60
–70
–40
–50
3rd Harmonic
–60
–70
2nd Harmonic
–80
–80
1
10
0.1
1
Gain Magnitude (V/V)
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs SUPPLY VOLTAGE
–30
–30
VO = 2Vp-p
fO = 5MHz
–40
–50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
10
Frequency (MHz)
3rd Harmonic
–60
–70
2nd Harmonic
VO = 2Vp-p
fO = 5MHz
–40
3rd Harmonic
–50
–60
2nd Harmonic
–70
–80
–80
100
1000
3
RL (Ω)
5
6
7
8
Single Supply Voltage (V)
®
OPA2631
4
6
9
10
TYPICAL PERFORMANCE CURVES: VS = +5V
(Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS /2, unless otherwise noted (see Figure 1).
TWO-TONE, 3rd-ORDER
INTERMODULATION SPURIOUS
HARMONIC DISTORTION vs NON-INVERTING GAIN
–30
VO = 2Vp-p
f = 5MHz
fO = 10MHz
–40
Harmonic Distortion (dBc)
–50
–60
–70
fO = 5MHz
–80
3rd Harmonic
–40
2nd Harmonic
–50
–60
–70
Load Power at
Matched 50Ω Load
fO = 1MHz
–80
–90
–16
–14
–12
–10
–8
–6
–4
–2
1
0
10
Gain Magnitude (V/V)
Single-Tone Load Power (dBm)
RECOMMENDED RS vs CAPACITIVE LOAD
INPUT NOISE DENSITY vs FREQUENCY
1000
100
RS (Ω)
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
100
10
Voltage Noise, eni = 6.0nV/√Hz
10
Current Noise, ini = 1.9pA/√Hz
1
1
100
1K
10K
100K
1M
1
10M
10
FREQUENCY RESPONSE vs CAPACITIVE LOAD
2
CL =1000pF
RS = 10Ω
1
Open-Loop Gain (dB)
Normalized Gain (dB)
0
CL = 100pF
RS = 35.7Ω
–3
–4
1/2
OPA2631
–5
RS
VO
CL
–6
–7
1kΩ
+VS/2
–8
1
10
1000
OPEN-LOOP GAIN AND PHASE
CL = 10pF
RS = 249Ω
–1
–2
100
Capacitive Load (pF)
Frequency (Hz)
100
300
100
90
80
70
60
50
40
30
20
10
0
–10
–20
Open-Loop Phase
Open-Loop Gain
1K
Frequency (MHz)
0
–30
–60
–90
–120
–150
–180
–210
–240
–270
–300
–330
–360
10K
100K
1M
10M
100M
Open-Loop Phase (°)
3rd-Order Spurious Level (dBc)
–30
1G
Frequency (Hz)
®
7
OPA2631
TYPICAL PERFORMANCE CURVES: VS = +5V
(Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS /2, unless otherwise noted (see Figure 1).
CLOSED-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
Input Offset Voltage (mV)
10
1
20
4.5
18
4.0
16
3.5
14
Input Offset Voltage
3.0
12
2.5
10
2.0
8
Input Bias Current
1.5
6
10X Input Offset Current
1.0
4
0.5
2
0.0
0.1
1k
10k
100k
1M
10M
0
–40
100M
–20
0
20
40
Temperature (°C)
Frequency (Hz)
POWER SUPPLY AND OUTPUT CURRENT
vs TEMPERATURE
12
120
Sinking Output Current
10
100
Sourcing Output Current
8
6
60
Quiescent Supply Current
4
40
2
20
0
0
–40
–20
0
20
40
Temperature (°C)
®
OPA2631
80
8
60
80
100
Output Current (mA)
Quiescent Supply Current (mA)
Output Impedance (Ω)
G = +1
RF = 25Ω
5.0
60
80
100
Input Bias Current (µA)
10x Input Offset Current (µA)
INPUT DC ERRORS vs TEMPERATURE
100
TYPICAL PERFORMANCE CURVES: VS = +3V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS /2, unless otherwise noted (see Figure 1).
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
6
12
VO = 200mVp-p
9
G = +2
0
VO = 200mVp-p
6
–3
3
G = +5
Gain (dB)
Normalized Gain (dB)
3
–6
–9
–12
–15
0
–3
VO = 1Vp-p
–6
–9
G = +10
–18
–12
–21
–15
–24
VO = 2Vp-p
–18
1
10
100
300
1
10
Frequency (MHz)
100
300
Frequency (MHz)
TWO-TONE, 3rd-ORDER
INTERMODULATION SPURIOUS
RECOMMENDED RS vs CAPACITIVE LOAD
1000
–30
100
–50
RS (Ω)
–60
fO = 5MHz
–70
–80
10
fO = 1MHz
Load Power at
Matched 50Ω Load
1
–90
–16
–14
–12
–10
–8
–6
1
–4
10
CL = 1000pF
RS = 10Ω
3.0
CL = 10pF
RS = 249Ω
Normalized Gain (dB)
0
–3
–6
CL = 100pF
RS = 35.7Ω
–9
–12
1/2
OPA2631
–15
RS
VO
CL
–18
–21
1.0
2.9
Maximum Output Voltage (V)
VO = 0.2Vp-p
3
1kΩ
Maximum VO
2.8
+VS/2
100
300
0.7
0.6
2.5
0.5
2.4
0.4
2.3
0.3
2.2
0.2
Minimum VO
50
Frequency (MHz)
0.8
2.6
2.0
10
0.9
2.7
2.1
–24
1
1000
OUTPUT SWING vs LOAD RESISTANCE
FREQUENCY RESPONSE vs CAPACITIVE LOAD
6
100
Capacitive Load (pF)
Single-Tone Load Power (dBm)
Minimum Output Voltage (V)
3rd-Order Spurious Level (dBc)
fO = 10MHz
–40
0.1
0.0
1000
100
RL (Ω)
®
9
OPA2631
TYPICAL PERFORMANCE CURVES: VS = +3V
(Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS /2, unless otherwise noted (see Figure 2).
SLEW RATE AND GAIN BANDWIDTH PRODUCT
vs SUPPLY VOLTAGE
180
8
160
Quiescent Supply Current
7
140
6
120
5
100
4
80
Output Current, Sinking
3
2
60
120
Slew Rate
40
Output Current, Sourcing
1
120
100
100
80
80
Gain Bandwidth Product
60
60
40
40
20
20
20
0
0
3
4
5
6
7
8
9
0
10
Supply Voltage (V)
4
5
6
7
Supply Voltage (V)
®
OPA2631
0
3
10
8
9
10
Gain Bandwidth Product (MHz)
200
9
Slew Rate (V/µs)
10
Output Current (mA)
Quiescent Supply Current (mA/chan)
SUPPLY AND OUTPUT CURRENTS
vs SUPPLY VOLTAGE
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE-FEEDBACK OPERATION
+VS = 3V
6.8µF
+
The OPA2631 is a unity-gain stable, very high-speed, voltage-feedback op amp designed for single-supply operation
(+3V to +5V). The input stage supports input voltages below
ground, and within 1.0V of the positive supply. The complementary common-emitter output stage provides an output
swing to within 30mV of ground and 130mV of the positive
supply. It is compensated to provide stable operation with a
wide range of resistive loads.
2.26kΩ
374Ω
VIN
562Ω
SINGLE-SUPPLY ADC CONVERTER INTERFACE
The front page shows a DC-coupled, single-supply dual
ADC driver circuit. Many systems are now requiring +3V
supply capability of both the ADC and its driver. The
OPA2631 provides excellent performance in this demanding application. Its large input and output voltage ranges,
and low distortion support converters such as the ADS901
shown in this figure. The input level-shifting circuitry was
designed so that VIN can be between 0V and 0.5V, while
delivering an output voltage of 1V to 2V for the ADS901.
0.1µF
VIN
VOUT
BANDPASS FILTER
Figure 3 shows a single OPA2631 implementing a 6th-order
bandpass filter. This filter cascades two 2nd-order SallenKey sections with transmission zeros, and a double real pole
section. It has –3dB frequencies of 630kHz and 1.5MHz,
and –40dB frequencies of 230kHz and 4.2MHz. This filter
was designed to work well on +5V or ±5V supplies, while
driving an A/D converter at 6MSPS to 10MSPS (e.g., the
ADS804).
RL
150Ω
0.1µF
750Ω
750Ω
+VS
FIGURE 2. DC-Coupled Signal—Resistive Load to Supply
Midpoint.
0.1µF
+
1/2
OPA2631
750Ω
2
6.8µF
+
1.50kΩ
VOUT
RL
150Ω
+VS = 5V
53.6Ω
1/2
OPA2631
57.6Ω
Figure 1 shows the AC-coupled, gain of +2 configuration
used for the +5V Specifications and Typical Performance
Curves. For test purposes, the input impedance is set to 50Ω
with a resistor to ground. Voltage swings reported in the
Specifications are taken directly at the input and output pins.
For the circuit of Figure 1, the total effective load on the
output at high frequencies is 150Ω || 1500Ω. The 1.50kΩ
resistors at the non-inverting input provide the commonmode bias voltage. Their parallel combination equals the DC
resistance at the inverting input, minimizing the output DC
offset.
1.50kΩ
0.1µF
+
+VS
2
FIGURE 1. AC-Coupled Signal—Resistive Load to Supply
Midpoint.
The filter transfer function is based on a 4th-order elliptic
bandpass filter, with real highpass and lowpass poles added
at the output to give a 6th-order response. The components
were chosen to give this transfer function. The 20Ω resistor
isolates the first OPA2631 output from capacitive loading,
but affects the response at very high frequencies only.
Figure 4 shows the nominal response simulated by SPICE®.
Figure 2 shows the DC-coupled, gain of +2 configuration
used for the +3V Specifications and Typical Performance
Curves. For test purposes, the input impedance is set to 50Ω
with a resistor to ground. Though not strictly a “rail-to-rail”
design, this part comes very close, while maintaining excellent performance. It will deliver ≈ 2.9Vp-p on a single +3V
supply with 61MHz bandwidth. The 374Ω and 2.26kΩ
resistors at the input level-shift VIN so that VOUT is within
the allowed output voltage range when VIN = 0. See the
Typical Performance Curves for information on driving
capacitive loads.
DC LEVEL SHIFTING
Figure 5 shows a DC-coupled non-inverting amplifier that
level-shifts the input up to accommodate the desired output
voltage range. Given the desired signal gain (G), and the
amount VOUT needs to be shifted up (∆VOUT) when VIN is
®
11
OPA2631
1% Resistors
5% Capacitors
2.2nF
60.4Ω
7.32kΩ
1/2
OPA2631
681Ω
VIN
1.2nF
1.2nF
200Ω
59Ω
3.9nF
1.8nF
86.6Ω
1/2
OPA2631
VOUT
1.2nF
133Ω
73.2Ω
27pF
3.9nF
330pF
20Ω
130Ω
200Ω
46.4Ω
FIGURE 3. Bandpass Filter.
10
+VS
0
R2
Gain (dB)
–10
R1
–20
VIN
1/2
OPA2631
–30
VOUT
–40
–50
R3
–60
10K
100K
1M
10M
R4
100M
Frequency (Hz)
FIGURE 4. Nominal Filter Response.
FIGURE 5. DC Level Shifting Circuit.
at the center of its range, the following equations give the
resistor values that produce the best DC offset.
Make sure that VIN and VOUT stay within the specified input
and output voltage ranges.
NG = G + ∆VOUT/VS
The front page circuit is a good example of this type of
application. It was designed to take VIN between 0V and
0.5V, and produce VOUT between 1V and 2V, when using a
+3V supply. This means G = 2.00, and ∆VOUT = 1.50V – G
• 0.25V = 1.00V. Plugging into the above equations gives:
NG = 2.33, R1 = 375Ω, R2 = 2.25kΩ, and R3 = 563Ω. The
resistors were adjusted to the nearest standard values.
R1 = R4/G
R2 = R4/(NG – G)
R3 = R4/(NG –1)
where:
NG = 1 + R4/R3 (Noise Gain)
VOUT = (G)VIN + (NG – G)VS
®
OPA2631
12
OPERATING SUGGESTIONS
NON-INVERTING AMPLIFIER WITH
REDUCED PEAKING
Figure 6 shows a non-inverting amplifier that reduces peaking at low gains. The resistor RC compensates the OPA2631
to have higher Noise Gain (NG), which reduces the AC
response peaking (typically 5dB at G = +1 without RC)
without changing the DC gain. VIN needs to be a low
impedance source, such as an op amp. The resistor values
are low to reduce noise. Using both RT and RF helps
minimize the impact of parasitic impedances.
OPTIMIZING RESISTOR VALUES
Since the OPA2631 is a voltage feedback op amp, a wide
range of resistor values may be used for the feedback and
gain setting resistors. The primary limits on these values are
set by dynamic range (noise and distortion) and parasitic
capacitance considerations. For a non-inverting unity gain
follower application, the feedback connection should be
made with a 25Ω resistor, not a direct short (see Figure 6).
This will isolate the inverting input capacitance from the
output pin and improve the frequency response flatness.
Usually, for G > 1 application, the feedback resistor value
should be between 200Ω and 1.5kΩ. Below 200Ω, the
feedback network will present additional output loading
which can degrade the harmonic distortion performance.
Above 1.5kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional band-limiting in the amplifier response.
RT
VIN
1/2
OPA2631
RC
RG
VOUT
A good rule of thumb is to target the parallel combination of
RF and RG (Figure 1) to be less than approximately 400Ω.
The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the
feedback network and thus, a zero in the forward response.
Assuming a 3pF total parasitic on the inverting node, holding RF || RG <400Ω will keep this pole above 130MHz. By
itself, this constraint implies that the feedback resistor RF
can increase to several kΩ at high gains. This is acceptable
as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range
of interest.
RF
FIGURE 6. Compensated Non-Inverting Amplifier.
The Noise Gain can be calculated as follows:
G1 = 1 +
RF
RG
RT + RF/G1
RC
NG = G1G2
G2 = 1 +
BANDWIDTH VS GAIN: NON-INVERTING OPERATION
Voltage feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the Gain Bandwidth Product
(GBP) shown in the specifications. Ideally, dividing GBP by
the non-inverting signal gain (also called the Noise Gain, or
NG) will predict the closed-loop bandwidth. In practice, this
only holds true when the phase margin approaches 90°, as it
does in high gain configurations. At low gains (increased
feedback factors), most amplifiers will exhibit a more complex response with lower phase margin. The OPA2631 is
compensated to give a slightly peaked response in a noninverting gain of 2 (Figure 1). This results in a typical gain
of +2 bandwidth of 75MHz, far exceeding that predicted by
dividing the 68MHz GBP by 2. Increasing the gain will
cause the phase margin to approach 90° and the bandwidth
to more closely approach the predicted value of (GBP/NG).
At a gain of +10, the 7.6MHz bandwidth shown in the
Typical Specifications is close to that predicted using the
simple formula and the typical GBP.
A unity gain buffer can be designed by selecting RT = RF =
20.0Ω and RC = 40.2Ω (do not use RG ). This gives a Noise
Gain of 2, so its response will be similar to the Characteristics Plots with G = +2 which typically gives a flat frequency
response, but with less bandwidth.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
A single PC board is available to assist in the initial evaluation of circuit performance using the OPA2631. It is available free as an unpopulated PC board delivered with descriptive documentation. The summary information for this board
is shown below:
PRODUCT
PACKAGE
BOARD
PART
NUMBER
OPA2631U
8-Pin SO-8
DEM-OPA268xU
LITERATURE
REQUEST
NUMBER
MKT-352
The OPA2631 exhibits minimal bandwidth reduction going
to +3V single supply operation as compared with +5V
supply. This is because the internal bias control circuitry
retains nearly constant quiescent current as the total supply
voltage between the supply pins is changed.
Contact the Burr-Brown Applications support line to request
this board.
®
13
OPA2631
INVERTING AMPLIFIER OPERATION
The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes
part of the noise gain equation and hence influences the
bandwidth. For the example in Figure 7, the RM value
combines in parallel with the external 50Ω source impedance, yielding an effective driving impedance of 50Ω ||
576Ω = 26.8Ω. This impedance is added in series with RG
for calculating the noise gain. The resultant is 2.87 for
Figure 7, as opposed to only 2 if RM could be eliminated as
discussed above. The bandwidth will therefore be lower for
the gain of –2 circuit of Figure 7 (NG = +2.9) than for the
gain of +2 circuit of Figure 1.
Since the OPA2631 is a general purpose, wideband voltage
feedback op amp, all of the familiar op amp application
circuits are available to the designer. Figure 7 shows a
typical inverting configuration where the I/O impedances
and signal gain from Figure 1 are retained in an inverting
circuit configuration. Inverting operation is one of the more
common requirements and offers several performance benefits. The inverting configuration shows improved slew rate
and distortion. It also biases the input at VS/2 for the best
headroom. The output voltage can be independently moved
with bias adjustment resistors connected to the inverting
input.
The third important consideration in inverting amplifier
design is setting the bias current cancellation resistors on
the non-inverting input (a parallel combination of R T =
750Ω). If this resistor is set equal to the total DC resistance
looking out of the inverting node, the output DC error, due
to the input bias currents, will be reduced to (input offset
current) • RF. The inverting input's bias current flows
through RF because of the 0.1µF capacitor. Thus, we need
RT = 750Ω = 1.50kΩ||1.50kΩ To reduce the additional
high frequency noise introduced by this RT resistor, and
power supply feedthrough, it is bypassed with a capacitor.
If we had RT < 400Ω, its noise contribution would be
minimal. As a minimum, the OPA2631 requires an R T
value of 50Ω to damp out parasitic-induced peaking—a
direct short to ground on the non-inverting input runs the
risk of a very high frequency instability in the input stage.
+5V
+
0.1µF
2RT
1.50kΩ
2RT
1.50kΩ
0.1µF
50Ω
Source
1/2
OPA2631
RG
0.1µF 374Ω
6.8µF
RO
50Ω
50Ω Load
RF
750Ω
RM
57.6Ω
OUTPUT CURRENT AND VOLTAGE
The OPA2631 provides outstanding output voltage capability. Under no-load conditions at +25°C, the output voltage
typically swings closer than 130mV to either supply rail; the
guaranteed swing limit is within 400mV of either rail (VS =
+5V).
FIGURE 7. Gain of –2 Example Circuit.
In the inverting configuration, three key design consideration must be noted. The first is that the gain resistor (RG)
becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long
PC board trace or other transmission line conductor), RG
may be set equal to the required termination value and RF
adjusted to give the desired gain. This is the simplest
approach and results in optimum bandwidth and noise performance. However, at low inverting gains, the resultant
feedback resistor value can present a significant load to the
amplifier output. For an inverting gain of 2, setting RG to
50Ω for input matching eliminates the need for RM but
requires a 100Ω feedback resistor. This has the interesting
advantage that the noise gain becomes equal to 2 for a 50Ω
source impedance—the same as the non-inverting circuits
considered above. However, the amplifier output will now
see the 100Ω feedback resistor in parallel with the external
load. In general, the feedback resistor should be limited to
the 200Ω to 1.5kΩ range. In this case, it is preferable to
increase both the RF and RG values as shown in Figure 7, and
then achieve the input matching impedance with a third
resistor (RM) to ground. The total input impedance becomes
the parallel combination of RG and RM.
The minimum specified output voltage and current specifications over temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold start-up will the
output current and voltage decrease to the numbers shown in
the guaranteed tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
VBE’s (increasing the available output voltage swing) and
increasing their current gains (increasing the available output current). In steady-state operation, the available output
voltage and current will always be greater than that shown
in the over-temperature specifications since the output stage
junction temperatures will be higher than the minimum
specified operating ambient.
To maintain maximum output stage linearity, no output
short-circuit protection is provided. This will not normally
be a problem since most applications include a series matching resistor at the output that will limit the internal power
dissipation if the output side of this resistor is shorted to
ground.
®
OPA2631
14
DRIVING CAPACITIVE LOADS
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the
output noise voltage using the terms shown in Figure 8.
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter—including
additional external capacitance which may be recommended
to improve A/D linearity. A high speed, high open-loop gain
amplifier like the OPA2631 can be very susceptible to
decreased stability and closed-loop response peaking when
a capacitive load is placed directly on the output pin. When
the primary considerations are frequency response flatness,
pulse response fidelity and/or distortion, the simplest and
most effective solution is to isolate the capacitive load from
the feedback loop by inserting a series isolation resistor
between the amplifier output and the capacitive load.
ENI
1/2
OPA2631
RS
EO
IBN
ERS
RF
√ 4kTRS
The Typical Performance Curves show the recommended
RS versus capacitive load and the resulting frequency response at the load. Parasitic capacitive loads greater than
2pF can begin to degrade the performance of the OPA2631.
Long PC board traces, unmatched cables, and connections to
multiple devices can easily exceed this value. Always consider this effect carefully, and add the recommended series
resistor as close as possible to the output pin (see Board
Layout Guidelines).
IBI
RG
4kT
RG
√ 4kTRF
4kT = 1.6 • 10–20J
at 290°K
FIGURE 8. Noise Analysis Model.
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For a gain of
+2, the frequency response at the output pin is already
slightly peaked without the capacitive load, requiring relatively high values of RS to flatten the response at the load.
Increasing the noise gain will also reduce the peaking (see
Figure 6).
Equation 1:
DISTORTION PERFORMANCE
Equation 2:
EO =
(E
NI
2
)
+ ( I BN R S ) + 4kTR S NG 2 + ( I BI R F ) + 4kTR F NG
2
2
Dividing this expression by the noise gain (NG = (1+RF /RG))
will give the equivalent input-referred spot noise voltage at
the non-inverting input, as shown in Equation 2.
The OPA2631 provides good distortion performance into a
150Ω load. Relative to alternative solutions, it provides
exceptional performance into lighter loads and/or operating
on a single +3V supply. Generally, the 3rd harmonic will
dominate the distortion. Focusing then on the 3rd harmonic,
increasing the load impedance improves distortion directly.
Remember that the total load includes the feedback network;
in the non-inverting configuration (Figure 1) this is sum of
RF + RG, while in the inverting configuration, it is just RF.
I R 2 4kTR F
2
E N = E NI 2 + ( I BN R S ) + 4kTR S +  BI F  +
 NG 
NG
Evaluating these two equations for the circuit and component values shown in Figure 1 will give a total output spot
noise voltage of 13.1nV/√Hz and a total equivalent input
spot noise voltage of 6.6nV/√Hz. This is including the noise
added by the resistors. This total input-referred spot noise
voltage is not much higher than the 6.0nV/√Hz specification
for the op amp voltage noise alone. This will be the case as
long as the impedances appearing at each op amp input are
limited to the previously recommend maximum value of
400Ω, and the input attenuation is low.
NOISE PERFORMANCE
High slew rate, unity gain stable, voltage feedback op amps
usually achieve their slew rate at the expense of a higher
input noise voltage. The 6.0nV/√Hz input voltage noise for
the OPA2631 is, however, much lower than comparable
amplifiers. The input-referred voltage noise, and the two
input-referred current noise terms (1.9pA/√Hz), combine to
give low output noise under a wide variety of operating
conditions. Figure 8 shows the op amp noise analysis model
with all the noise terms included. In this model, all noise
terms are taken to be noise voltage or current density terms
in either nV/√Hz or pA/√Hz.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage feedback op
amp allows good output DC accuracy in a wide variety of
applications. The power supply current trim for the OPA2631
gives even tighter control than comparable products. Although the high-speed input stage does require relatively
high input bias current (typically 11µA out of each input
terminal), the close matching between them may be used to
®
15
OPA2631
possible internal dissipation will occur if the load requires
current to be forced into the output at high output voltages
or sourced from the output at low output voltages. This puts
a high current through a large internal voltage drop in the
output transistors.
reduce the output DC error caused by this current. This is
done by matching the DC source resistances appearing at the
two inputs. Evaluating the configuration of Figure 1 (which
has matched DC input resistances), using worst-case +25°C
input offset voltage and current specifications, gives a worstcase output offset voltage equal to: (NG = non-inverting
signal gain at DC)
BOARD LAYOUT GUIDELINES
±(NG • VOS(MAX)) ± (RF • IOS(MAX))
= ±(1 • 6.0mV) ± (750Ω • 2.0µA)
= ±6.8mV = Output Offset Range for Figure 1
Achieving optimum performance with a high frequency
amplifier like the OPA2631 requires careful attention to
board layout parasitics and external component types. Recommendations that will optimize performance include:
A fine scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques are
available for introducing DC offset control into an op amp
circuit. Most of these techniques are based on adding a DC
current through the feedback resistor. In selecting an offset
trim method, one key consideration is the impact on the
desired signal path frequency response. If the signal path is
intended to be non-inverting, the offset control is best
applied as an inverting summing signal to avoid interaction
with the signal source. If the signal path is intended to be
inverting, applying the offset control to the non-inverting
input may be considered. Bring the DC offsetting current
into the inverting input node through resistor values that are
much larger than the signal path resistors. This will insure
that the adjustment circuit has minimal effect on the loop
gain and hence the frequency response.
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbroken elsewhere on the board.
b) Minimize the distance (<0.25") from the power supply
pins to high frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power supply
connections should always be decoupled with these capacitors. An optional supply decoupling capacitor (0.1µF) across
the two power supplies (for bipolar operation) will improve
2nd harmonic distortion performance. Larger (2.2µF to
6.8µF) decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These may be
placed somewhat farther from the device and may be shared
among several devices in the same area of the PC board.
THERMAL ANALYSIS
Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below.
In no case should the maximum junction temperature be
allowed to exceed 175°C.
Operating junction temperature (TJ) is given by TA + PD•θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. PDL will depend on the
required output signal and load but would, for resistive load
connected to mid-supply (VS/2), be at a maximum when the
output is fixed at a voltage equal to VS/4 or 3VS/4. Under this
condition, PDL = VS2/(16 • RL), where RL includes feedback
network loading.
c) Careful selection and placement of external components will preserve the high frequency performance.
Resistors should be a very low reactance type. Surfacemount resistors work best and allow a tighter overall layout.
Metal film or carbon composition axially-leaded resistors
can also provide good high frequency performance. Again,
keep their leads and PC board traces as short as possible.
Never use wirewound type resistors in a high frequency
application. Since the output pin and inverting input pin are
the most sensitive to parasitic capacitance, always position
the feedback and series output resistor, if any, as close as
possible to the output pin. Other network components, such
as non-inverting input termination resistors, should also be
placed close to the package. Where double-side component
mounting is allowed, place the feedback resistor directly
under the package on the other side of the board between the
output and inverting input pins. Even with a low parasitic
capacitance shunting the external resistors, excessively high
resistor values can create significant time constants that can
degrade performance. Good axial metal film or surfacemount resistors have approximately 0.2pF in shunt with the
resistor. For resistor values > 1.5kΩ, this parasitic capaci-
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using
the circuit of Figure 1 operating at the maximum specified
ambient temperature of +85°C and driving a 150Ω load at
mid-supply, for both channels:
PD = 2 (10V • 6.9mA + 52/(16 • (150Ω || 1500Ω))) = 160mW
Maximum TJ = +85°C + (0.16W • 150°C/W) = 109°C.
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower guaranteed junction temperatures. The highest
®
OPA2631
16
doubly terminated line. If the input impedance of the destination device is low, there will be some signal attenuation
due to the voltage divider formed by the series output into
the terminating impedance.
tance can add a pole and/or zero below 500MHz that can
effect circuit operation. Keep resistor values as low as
possible consistent with load driving considerations. The
750Ω feedback used in the typical performance specifications is a good starting point for design. See Figure 6 for the
unity gain follower application.
e) Socketing a high speed part is not recommended. The
additional lead length and pin-to-pin capacitance introduced
by the socket can create an extremely troublesome parasitic
network which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are obtained
by soldering the OPA2631 onto the board.
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set RS from the
plot of Recommended RS vs Capacitive Load. Low parasitic
capacitive loads (< 5pF) may not need an RS since the
OPA2631 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an
RS are allowed as the signal gain increases (increasing the
unloaded phase margin) If a long trace is required, and the
6dB signal loss intrinsic to a doubly terminated transmission
line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline layout
techniques). A 50Ω environment is normally not necessary
on board, and in fact, a higher impedance environment will
improve distortion as shown in the distortion versus load
plots. With a characteristic board trace impedance defined
(based on board material and trace dimensions), a matching
series resistor into the trace from the output of the OPA2631
is used as well as a terminating shunt resistor at the input of
the destination device. Remember also that the terminating
impedance will be the parallel combination of the shunt
resistor and the input impedance of the destination device;
this total effective impedance should be set to match the
trace impedance. If the 6dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the trace as a
capacitive load in this case and set the series resistor value
as shown in the plot of Recommended RS vs Capacitive
Load. This will not preserve signal integrity as well as a
INPUT AND ESD PROTECTION
The OPA2631 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for this very small geometry device.
This breakdown is reflected in the Absolute Maximum
Ratings table. All device pins are protected with internal
ESD protection diodes to the power supplies as shown in
Figure 9.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with ±15V supply
parts driving into the OPA2631), current-limiting series
resistors should be added into the two inputs. Keep these
resistor values as low as possible since high values degrade
both noise performance and frequency response.
+V CC
External
Pin
Internal
Circuitry
–V CC
FIGURE 9. Internal ESD Protection.
®
17
OPA2631