Micron MT18VDDF12872HG-265 Ddr sdram sodimm Datasheet

1GB (x72, ECC, DR) 200-Pin DDR SDRAM SODIMM
Features
DDR SDRAM SODIMM
MT18VDDF12872H – 1GB
For component data sheets, refer to Micron’s Web site: www.micron.com
Figure 1:
Features
• 200-pin, small-outline dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC2100, PC2700, or PC3200
• 1GB (128 Meg x 72)
• Supports ECC error detection and correction
• VDD = VDDQ = +2.5V
(-40B: VDD = VDDQ = +2.6V)
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2-compatible)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—that is, source-synchronous
data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent
operation
• Selectable burst lengths (BL) 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes: 7.8125µs
maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum
compatibility
• Dual rank
• Gold edge contacts
200-Pin SODIMM (MO-224)
PCB height: 31.75mm (1.25in)
Options
Marking
• Operating temperature1
– Commercial (0°C ≤ TA ≤ +70°C)
– Industrial (–40°C ≤ TA ≤ +85°C)
• Package
– 200-pin DIMM (standard)
– 200-pin DIMM (Pb-free)
• Memory clock, speed, CAS latency
– 5.0ns (200 MHz), 400 MT/s, CL = 3
– 6.0ns (167 MHz), 333 MT/s, CL = 2.5
– 7.5ns (133 MHz), 266 MT/s, CL = 22
– 7.5ns (133 MHz), 266 MT/s, CL = 2.52
None
I
G
Y
-40B
-335
-26A
-265
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. Not recommended for new designs.
Table 1:
Key Timing Parameters
Data Rate (MT/s)
Speed
Grade
Industry
Nomenclature
CL = 3
CL = 2.5
CL = 2
(ns)
tRP
(ns)
tRC
(ns)
-40B
-335
-26A
-265
PC3200
PC2700
PC2100
PC2100
400
–
–
–
333
333
266
266
266
266
266
200
15
18
20
20
15
18
20
20
55
60
65
65
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DDF18C128x72H.fm - Rev. B 10/07 EN
1
tRCD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1GB (x72, ECC, DR) 200-Pin DDR SDRAM SODIMM
Features
Table 2:
Addressing
Parameter
1GB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (64 Meg x 8)
2K (A0–A9, A11)
2 (S0#, S1#)
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
Table 3:
Part Numbers and Timing Parameters – 1GB
Base device: MT46V64M8,1 512Mb DDR SDRAM
Part Number2
MT18VDDF12872HG-40B__
MT18VDDF12872HY-40B__
MT18VDDF12872HG-335__
MT18VDDF12872HY-335__
MT18VDDF12872HG-26A__
MT18VDDF12872HG-265__
Notes:
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DDF18C128x72H.fm - Rev. B 10/07 EN
Module
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
1GB
1GB
1GB
1GB
1GB
1GB
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
3.2 GB/s
3.2 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
5.0ns/400 MT/s
5.0ns/400 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
3-3-3
3-3-3
2.5-3-3
2.5-3-3
2-3-3
2.5-3-3
1. Data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes.
Example: MT18VDDF12872HY-335F1.
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, DR) 200-Pin DDR SDRAM SODIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 4:
Pin Assignments
200-Pin SODIMM Front
200-Pin SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
DQ16
DQ17
VDD
DQS2
DQ18
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
NC
VSS
CK2
CK2#
VDD
CKE1
NC
A12
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DDF18C128x72H.fm - Rev. B 10/07 EN
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
A9
VSS
A7
A5
A3
A1
VDD
A10
BA0
WE#
S0#
NC
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDDSPD
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
3
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
NC
VSS
VSS
VDD
VDD
CKE0
NC
A11
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
NC
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
VSS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, DR) 200-Pin DDR SDRAM SODIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Symbol
Type
Description
A0–A12
Input
BA0, BA1
Input
CK0, CK0#,
CK1, CK1#
CK2, CK2#
Input
CKE0, CKE1
Input
DM0–DM8
Input
S0#, S1#
Input
SA0–SA2
Input
SCL
Input
WE#, CAS#, RAS#
Input
CB0–CB7
DQ0–DQ63
DQS0–DQS8
I/O
I/O
I/O
SDA
I/O
VDD
Supply
Supply
Supply
Supply
–
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD MODE
REGISTER command.
Bank address: BA0 and BA1 define the device bank to which an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Clock: CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and the
negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW)
deactivates the internal clock, input buffers, and output drivers
Input data mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH, along with that input data, during a write
access. DM is sampled on both edges of DQS. Although DM pins are inputonly, the DM loading is designed to match that of DQ and DQS pins.
Chip selects: S# enables (registered LOW) and disables (registered HIGH) the
command decoder.
Presence-detect address inputs: These pins are used to configure the
presence-detect device.
Serial clock for presence-detect: SCL is used to synchronize the presencedetect data transfer to and from the module.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the
command being entered.
Check bits.
Data input/output: Data bus.
Data strobe: Output with read data, input with write data. DQS is edgealigned with read data, center-aligned with write data. Used to capture data.
Serial presence-detect data: SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the module.
Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V).
Serial EEPROM positive power supply: +2.3V to +3.6V.
SSTL_2 reference voltage (VDD/2).
Ground.
No connect: These pins are not connected on the module.
VDDSPD
VREF
VSS
NC
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DDF18C128x72H.fm - Rev. B 10/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, DR) 200-Pin DDR SDRAM SODIMM
Functional Block Diagram
Functional Block Diagram
Figure 2:
Functional Block Diagram
S1#
S0#
DQS0
DQS1
DM1
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ
DQ
DQ
U1
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U14
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS# DQS
DQ
DQ
DQ
U5
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U19
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS# DQS
DQ
DQ
DQ
U2
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U13
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS# DQS
DQ
DQ
DQ
U3
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U12
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS# DQS
DQ
DQ
DQ
U4
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U11
DQ
DQ
DQ
DQ
DQS3
DQS2
DM2
DM3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM CS# DQS
DQ
DQ
DQ
U6
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U18
DQ
DQ
DQ
DQ
DQS5
DM5
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS# DQS
DQ
DQ
DQ
U8
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U16
DQ
DQ
DQ
DQ
DQS7
DM7
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS# DQS
DQ
DQ
DQ
U9
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U15
DQ
DQ
DQ
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM CS# DQS
DQ
DQ
DQ
U7
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U17
DQ
DQ
DQ
DQ
DQS8
DM8
BA0, BA1
A0–A12
CK0
CK0#
U1, U2, U5,
U13, U14, U19
CK1
CK1#
U3, U4, U9,
U11, U12, U15
CK2
CK2#
U6, U7, U8,
U16, U17, U18
BA0, BA1: DDR SDRAM
A0–A12: DDR SDRAM
VDDSPD
SPD EEPROM
U10
CAS#: DDR SDRAM
VDD
DDR SDRAM
CKE0: DDR SDRAM U1–U9
VREF
DDR SDRAM
SPD EEPROM
WP A0 A1 A2
VSS
DDR SDRAM
RAS#
CAS#
RAS#: DDR SDRAM
CKE0
CKE1
CKE1: DDR SDRAM U11–U19
WE#
WE#: DDR SDRAM
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DDF18C128x72H.fm - Rev. B 10/07 EN
5
SCL
SDA
VSS SA0 SA1 SA2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, DR) 200-Pin DDR SDRAM SODIMM
General Description
General Description
The MT18VDDF12872H is a high-speed, CMOS, dynamic random access, 1GB memory
module organized in a x72 configuration. These modules use DDR SDRAM devices with
four internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single 2n-bit wide,
one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit
wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes are programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to VSS on the
module, permanently disabling hardware write protect.
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DDF18C128x72H.fm - Rev. B 10/07 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, DR) 200-Pin DDR SDRAM SODIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 6 may cause permanent damage to the
module. This is a stress rating only, and functional operation of the module at these or
any other conditions outside those indicated on the device data sheet is not implied.
Exposure to absolute maximum rating conditions for extended periods may adversely
affect reliability.
Table 6:
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
VDD
VIN, VOUT
II
VDD supply voltage relative to VSS
Voltage on any pin relative to VSS
Address inputs
Input leakage current; Any input 0V ≤ VIN ≤ VDD;
VREF input 0V ≤ VIN ≤ 1.35V (All other pins not under RAS#, CAS#, WE#, BA
test = 0V)
S#, CKE
CK, CK#
DM
Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ are DQ, DQS
disabled
DRAM ambient operating temperature1
Commercial
Industrial
–1.0
–0.5
–36
+3.6
+3.2
+36
V
V
µA
–18
–12
–4
–10
+18
+12
+4
+10
µA
0
–40
+70
+85
°C
°C
IOZ
TA
Notes:
1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available
on Micron’s Web site.
Input Capacitance
Micron encourages designers to simulate the performance of the module to achieve
optimum values. Simulations are significantly more accurate and realistic than a gross
estimation of module capacitance when inductance and delay parameters associated
with trace lengths are used in simulations. JEDEC modules are currently designed using
simulations to close timing budgets.
Component AC Timing and Operating Conditions
Recommended AC operating conditions are given in the DDR component data sheets.
Component specifications are available on Micron’s Web site. Module speed grades
correlate with component speed grades, as shown in Table 7.
Table 7:
Module and Component Speed Grades
Module Speed Grade
Component Speed Grade
-40B
-335
-26A
-265
-5
-6
-75Z
-75
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DDF18C128x72H.fm - Rev. B 10/07 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, DR) 200-Pin DDR SDRAM SODIMM
IDD Specifications
IDD Specifications
Table 8:
IDD Specifications and Conditions – 1GB
Values are shown for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
Parameter/Condition
Operating one bank active-precharge current: One device
bank; Active-precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ,
DM, and DQS inputs changing once per clock cycle; Address
and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: One
device bank; Active-read precharge; BL = 4; tRC = tRC (MIN);
tCK = tCK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
Precharge power-down standby current: All device banks
idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)
Idle standby current: CS# = HIGH; All device banks idle;
tCK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle; VIN = VREF for DQ, DQS,
and DM
Active power-down standby current: One device bank
active; Power-down mode; tCK = tCK (MIN); CKE = LOW
Active standby current: CS# = HIGH; CKE = HIGH; One
device bank; Active-precharge; tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per
clock cycle; Address and other control inputs changing once
per clock cycle
Operating burst read current: BL = 2; Continuous burst
reads; One device bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA
Operating burst write current: BL = 2; Continuous burst
writes; One device bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and
DQS inputs changing twice per clock cycle
t
Auto refresh current
REFC = tRFC (MIN)
tREFC = 7.8125µs
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank
interleaving reads; (BL = 4) with auto precharge;
tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs
change only during active READ or WRITE commands
Notes:
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DDF18C128x72H.fm - Rev. B 10/07 EN
Symbol
-40B
-335
-26A/
-265
Units
IDD01
1,440
1,215
1,080
mA
IDD11
1,710
1,485
1,350
mA
IDD2P2
90
90
90
mA
IDD2F2
990
810
720
mA
IDD3P2
810
630
540
mA
IDD3N2
1,080
900
810
mA
IDD4R1
1,755
1,530
1,350
mA
IDD4W1
1,800
1,320
1,260
mA
IDD52
6,210
198
90
4,095
5,220
180
90
3,690
5,040
180
90
3,195
mA
mA
mA
mA
IDD5A2
IDD62
IDD71
1. Value calculated as one module rank in this operating condition; all other module ranks are
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, DR) 200-Pin DDR SDRAM SODIMM
Serial Presence-Detect
Serial Presence-Detect
Table 9:
Serial Presence-Detect EEPROM DC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Units
VDDSPD
VIH
VIL
VOL
ILI
ILO
ISB
ICC
2.3
VDDSPD × 0.7
–1.0
–
–
–
–
–
3.6
VDDSPD + 0.5
VDDSPD × 0.3
0.4
10
10
30
2.0
V
V
V
V
µA
µA
µA
mA
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: IOUT = 3mA
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD
Power supply current: SCL clock frequency = 100 kHz
Table 10:
Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Notes:
Symbol
Min
Max
Units
Notes
tAA
0.2
1.3
200
–
0
0.6
0.6
–
1.3
–
–
100
0.6
0.6
–
0.9
–
–
300
–
–
–
50
–
0.3
400
–
–
–
10
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
kHz
ns
µs
µs
ms
1
tBUF
tDH
tF
tHD:DAT
tHD:STA
tHIGH
tI
tLOW
tR
fSCL
tSU:DAT
tSU:STA
t
SU:STO
t
WRC
2
2
3
4
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address.
Serial Presence-Detect Data
For the latest serial presence-detect data, refer to Micron’s SPD page:
www.micron.com/SPD.
PDF: 09005aef80e4880c/Source: 09005aef80e487d7
DDF18C128x72H.fm - Rev. B 10/07 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, DR) 200-Pin DDR SDRAM SODIMM
Module Dimensions
Module Dimensions
Figure 3:
200-Pin SODIMM
Front view
3.8 (0.15)
MAX
67.75 (2.667)
67.45 (2.656)
2.0 (0.079) R
(2X)
U1
1.8 (0.071)
(2X)
U2
U5
U3
U6
U7
U10
U4
U8
31.9 (1.256)
31.6 (1.244)
U9
20.0 (0.787)
TYP
6.0 (0.236) TYP
2.44 (0.096) TYP
0.99 (0.039)
TYP
2.0 (0.079) TYP
Pin 1
0.46 (0.018)
TYP
0.61 (0.024)
TYP
63.60 (2.504)
TYP
1.1 (0.043)
0.9 (0.035)
Pin 199
Back view
U11
U15
U12
U16
U13
U17
U14
U18
U19
Pin 200
Notes:
Pin 2
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions.
®
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[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth
herein. Although considered final, these specifications are subject to change, as further product development and data
characterization sometimes occur.
PDF: 09005aef80e4880c/Source: 09005aef80e487d7
DDF18C128x72H.fm - Rev. B 10/07 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.