AD AD9214 10-bit, 65/80/105 msps 3 v a/d converter Datasheet

a
APPLICATIONS
Battery-Powered Instruments
Hand-Held Scopemeters
Low-Cost Digital Oscilloscopes
Ultrasound Equipment
Cable Reverse Path
Broadband Wireless
Residential Power Line Networks
FUNCTIONAL BLOCK DIAGRAM
AVDD
PWRDWN
DrVDD
AD9214
DFS/GAIN
AIN
AIN
ENCODE
BUFFER
T/H
TIMING
AGND
PIPELINE 10
ADC
CORE
REF
REF REFSENSE
OUTPUT REGISTER
FEATURES
SNR = 57 dB @ 39 MHz Analog Input (–0.5 dBFS)
Low Power
190 mW at 65 MSPS
285 mW at 105 MSPS
30 mW Power-Down Mode
300 MHz Analog Bandwidth
On-Chip Reference and Track/Hold
1 V p-p or 2 V p-p Analog Input Range Option
Single 3.3 V Supply Operation (2.7 V–3.6 V)
Two’s Complement or Offset Binary Data Format Option
10-Bit, 65/80/105 MSPS
3 V A/D Converter
AD9214
OR
10
D9–D0
DGND
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9214 is a 10-bit monolithic sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit, and
is optimized for low cost, low power, small size, and ease of use.
The product operates up to 105 MSPS conversion rate with
outstanding dynamic performance over its full operating range.
High Performance—Outstanding ac performance from 65 MSPS
to 105 MSPS. SNR greater than 55 dB typical and as high
as 58 dB.
The ADC requires only a single 3.3 V (2.7 V to 3.6 V) power
supply and an encode clock for full performance operation. No
external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS compatible
and a separate output power supply pin supports interfacing
with 3.3 V or 2.5 V logic.
The clock input is TTL/CMOS compatible. In the power-down
state, the power is reduced to 30 mW. A gain option allows
support for either 1 V p-p or 2 V p-p analog signal input swing.
Low Power—The AD9214 at 285 mW consumes a fraction of
the power available in existing high-speed monolithic solutions.
In sleep mode, power is reduced to 30 mW.
Single Supply—The AD9214 uses a single 3 V supply, simplifying system power supply design. It also features a separate digital
output driver supply line to accommodate 2.5 V logic families.
Small Package—The AD9214 is packaged in a small 28-lead
surface-mount plastic package (28-SSOP).
Fabricated on an advanced CMOS process, the AD9214 is
available in a 28-lead surface-mount plastic package (28-SSOP)
specified over the industrial temperature range (–40°C to +85°C).
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD9214–SPECIFICATIONS
(AVDD = 3 V, DrVDD = 3 V; TMIN = –40ⴗC, TMAX = +85ⴗC; external 1.25 V voltage reference and rated encode
DC SPECIFICATIONS frequency used, unless otherwise noted.)
Parameter
Temp
Test
Level
Min
RESOLUTION
ACCURACY
No Missing Codes
AD9214-65
Typ
Max
Min
10
AD9214-80
Typ
Max
10
VI
VI
VI
I
I
V
I
V
TEMPERATURE DRIFT
Offset Error
Gain Error1
Reference Voltage
Full
Full
Full
V
V
V
REFERENCE (REF)
Internal Reference Voltage
Output Current3
Input Current4
Input Resistance
25°C
Full
Full
Full
VI
V
V
V
ANALOG INPUTS (AIN, AIN)
Differential Input Range
Common-Mode Voltage
Differential Input Resistance5
Differential Input Capacitance
Full
Full
Full
Full
V
V
V
V
Full
Full
IV
IV
Full
VI
64
75
90
105
Full
Full
25°C
Full
VI
VI
I
V
10
190
± 0.5
±2
15
220
10
250
±1
±2
15
300
POWER SUPPLY
Supply Voltages
AVDD
DrVDD
Supply Current
IAVDD (AVDD = 3.0 V)6
Power-Down Current7
IAVDD (AVDD = 3.0 V)
Power Consumption8
PSRR
Guaranteed
Guaranteed
–18
0
–2
–1.0
± 0.5
–1.0
–1.35
± 0.75
–1.9
+18
+8
+1.0
+1.2
+1.35
+1.9
–18
–2
–1.0
–1.0
–1.5
–1.8
16
150
80
1.18
1.28
1.18
1 or 2
AVDD/3
20
5
2.7
2.7
Guaranteed
Guaranteed
0
+18
+8
± 0.5
+1.2
+1.4
± 0.75 +1.5
+1.8
1.23
200
123
10
–18
–2
–1.0
–2.2
–2.5
2.7
2.7
Bits
0
± 0.8
± 1.5
+18
+8
+1.5
+1.7
+2.2
+2.5
16
150
80
1.28
1.18
1 or 2
AVDD/3
20
5
3.6
3.6
Unit
Guaranteed
16
150
80
1.23
200
123
10
AD9214-105
Typ
Max
10
25°C
Full
Full
25°C
25°C
Full
25°C
Full
Offset Error
Gain Error1
Differential Nonlinearity2
(DNL)
Integral Nonlinearity2
(INL)
Min
1.23
200
123
10
ppm/°C
ppm/°C
ppm/°C
1.28
1 or 2
AVDD/3
20
5
3.6
3.6
2.7
2.7
LSB
% FS
LSB
LSB
LSB
LSB
V
µA
µA
kΩ
V p-p
V
kΩ
pF
3.6
3.6
V
V
95
110
mA
10
285
±1
±2
15
325
mA
mW
LSB/V
mV/V
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference).
2
Measured with 1 V A IN range for AD9214-80 and AD9214-105. Measured with 2 V A IN range for AD9214-65.
3
REFSENSE externally connected to AGND, REF is configured as an output for the internal reference voltage.
4
REFSENSE externally connected to AV DD, REF is configured as an input for an external reference voltage.
5
10 kΩ to AVDD/3 on each input.
6
IAVDD is measured with an analog input of 10.3 MHz, 0.5 dBFS, sine wave, rated encode rate, and PWRDN = 0. See Typical Performance Characteristics and
Applications section for I DrVDD.
7
Power-down supply currents measured with PWRDN = 1; rated encode rate, A IN = full-scale dc input.
8
Power consumption measured with A IN = full-scale dc input.
Specifications subject to change without notice.
–2–
REV. D
AD9214
DIGITAL SPECIFICATIONS (AV
DD
= 3 V, DrVDD = 3 V; TMIN = –40ⴗC, TMAX = +85ⴗC)
Temp
Test
Level
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Input Capacitance
Full
Full
Full
IV
IV
V
DIGITAL OUTPUTS2
Logic Compatibility
Logic “1” Voltage
Logic “0” Voltage
Full
Full
VI
VI
Parameter
Min
AD9214-65
Typ
Max
Min
AD9214-80
Typ
Max
Min
AD9214-105
Typ
Max
Unit
1
2.0
2.0
2.0
0.8
0.8
2.0
0.8
2.0
CMOS/TTL
DrVDD – 50 mV
2.0
CMOS/TTL
DrVDD – 50 mV
50
CMOS/TTL
DrVDD – 50 mV
50
50
V
V
pF
V
V
mV
NOTES
1
Digital Inputs include ENCODE and PWRDN.
2
Digital Outputs include D0–D9 and OR.
Specifications subject to change without notice.
AC SPECIFICATIONS1
(AVDD = 3 V, DrVDD = 3 V; ENCODE = Maximum Conversion Rate; TMIN = –40ⴗC, T MAX = +85ⴗC; external
1.25 V voltage reference used, unless otherwise noted.)
Parameter
Temp
Test
Level
SNR
Analog Input
10 MHz
@ –0.5 dBFS 39 MHz
51 MHz
70 MHz
25°C
25°C
25°C
25°C
I
I
V
V
55.5
58.3
57.1
56.0
55.0
58.1
57.1
55.0
54.0
51.0
50.5
53.0
53.0
53.0
52.6
dB
dB
dB
dB
SINAD
Analog Input
10 MHz
@ –0.5 dBFS 39 MHz
51 MHz
70 MHz
25°C
25°C
25°C
25°C
I
I
V
V
55.0
57.8
56.7
55.5
54.5
57.6
56.7
54.5
50.0
50.0
52.0
52.0
52.0
52.0
dB
dB
dB
dB
EFFECTIVE NUMBER OF BITS
Analog Input
10 MHz
@ –0.5 dBFS 39 MHz
51 MHz
70 MHz
25°C
25°C
25°C
25°C
I
I
V
V
8.9
9.3
9.2
9.0
8.8
9.3
9.2
8.8
8.5
8.4
8.4
8.4
8.4
Bit
Bit
Bit
Bit
SECOND HARMONIC DISTORTION
Analog Input
10 MHz
@ –0.5 dBFS 39 MHz
51 MHz
70 MHz
25°C
25°C
25°C
25°C
I
I
V
V
–66
–79
–75
–64
–63
–74
–76
–72
–65
–62
–62
–68
–71
–64
–62
dBc
dBc
dBc
dBc
THIRD HARMONIC DISTORTION
Analog Input
10 MHz
@ –0.5 dBFS 39 MHz
51 MHz
70 MHz
25°C
25°C
25°C
25°C
I
I
V
V
–63.5
–71
–70
–63
–63
–72
–74
–78
–59
–59
–64
–67
–71
–65
dBc
dBc
dBc
dBc
SFDR
Analog Input
10 MHz
@ –0.5 dBFS 39 MHz
51 MHz
70 MHz
25°C
25°C
25°C
25°C
I
I
V
V
63.5
71
70
63
63
71
71
67
64
57
57
62
62
62
62
dBc
dBc
dBc
dBc
TWO-TONE INTERMOD DISTORTION2
Analog Input
@ –0.5 dBFS
25°C
V
76
74
72
dBFS
ANALOG INPUT BANDWIDTH
25°C
V
300
300
300
MHz
Min
AD9214-65
Typ
Max
Min
AD9214-80
Typ
Max
Min
AD9214-105
Typ
Max
Unit
NOTES
1
AC specifications based on a 1.0 V p-p full-scale input range for the AD9214-80 and AD9214-105, and a 2.0 V p-p full-scale input range for the AD9214-65. An
external reference is used.
2
F1 = 29.3 MHz, F2 = 30.3 MHz.
Specifications subject to change without notice.
REV. D
–3–
AD9214–SPECIFICATIONS
(AVDD = 3 V, DrVDD = 3 V; ENCODE = Maximum Conversion Rate; TMIN = –40ⴗC, TMAX = +85ⴗC;
SWITCHING SPECIFICATIONS external 1.25 V voltage reference used, unless otherwise noted.)
Parameter
Temp
Test
Level
ENCODE INPUT PARAMETERS*
Maximum Conversion Rate
Minimum Conversion Rate
Encode Pulsewidth High (tEH)
Encode Pulsewidth Low (tEL)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Full
Full
Full
Full
25°C
25°C
VI
IV
IV
IV
V
V
6.0
6.0
DATA OUTPUT PARAMETERS
Pipeline Delays
Output Valid Time (tV)*
Output Propagation Delay* (tPD)
Full
Full
Full
IV
V
V
3.0
TRANSIENT RESPONSE TIME
25°C
V
5
5
5
ns
OUT-OF-RANGE RECOVERY TIME
25°C
V
5
5
5
ns
Min
AD9214-65
Typ
Max
Min
65
AD9214-80
Typ
Max
80
Min
105
20
2.0
3
2.0
3
5
4.5
4.5
Clock Cycle
ns
ns
20
3.8
3.8
2.0
3
3.0
6.0
5
4.5
4.5
3.0
6.0
Unit
MSPS
MSPS
ns
ns
ns
ps rms
20
5.0
5.0
5
4.5
4.5
AD9214-105
Typ
Max
6.0
*tV and tPD are measured from the 1.5 V level of the ENCODE input to the 50% levels of the digital output swing. The digital output load during test is not to exceed
an ac load of 5 pF or a dc current of ± 40 µA.
Specifications subject to change without notice.
SAMPLE N
SAMPLE N+5
SAMPLE N+1
AIN
tA
ENCODE
SAMPLE N+2
tEH
tEL
SAMPLE N+3
SAMPLE N+4
1/FS
tPD
D9 – D0
DATA N–5
DATA N–4
DATA N–3
DATA N–2
tV
DATA N–1
DATA N
Figure 1. Timing Diagram
–4–
REV. D
AD9214
ABSOLUTE MAXIMUM RATINGS 1
EXPLANATION OF TEST LEVELS
Electrical
AVDD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V max
DrVDD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V max
Analog Input Voltage . . . . . . . . . . . –0.5 V to AVDD + 0.5 V
Analog Input Current . . . . . . . . . . . . . . . . . . . . . . . 0.4 mA
Digital Input Voltage . . . . . . . . . . . –0.5 V to AVDD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . 20 mA max
REF Input Voltage . . . . . . . . . . . . . –0.5 V to AVDD + 0.5 V
Environmental2
Operating Temperature Range (Ambient)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C
Maximum Junction Temperature . . . . . . . . . . . . . . . 150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . 150°C
Storage Temperature Range (Ambient) . . . –65°C to +150°C
I
100% production tested.
II 100% production tested at 25°C and guaranteed by design
and characterization at specified temperatures.
III Sample Tested Only
IV Parameter is guaranteed by design and characterization
testing.
V
Parameter is a typical value only.
VI 100% production tested at 25°C and guaranteed by design
and characterization for industrial temperature range.
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances (package = 28 SSOP); θJA = 49°C/W. These
measurements were taken on a 6-layer board in still air with a solid
ground plane.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9214BRS-65
AD9214BRS-80
AD9214BRS-105
AD9214-65PCB
AD9214-105PCB
–40°C to +85°C (Ambient)
–40°C to +85°C (Ambient)
–40°C to +85°C (Ambient)
25°C
25°C
28-Lead Shrink Small Outline Package
28-Lead Shrink Small Outline Package
28-Lead Shrink Small Outline Package
Evaluation Board with AD9214-65
Evaluation Board with AD9214-105
RS-28
RS-28
RS-28
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9214 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. D
–5–
WARNING!
ESD SENSITIVE DEVICE
AD9214
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
OR
2
DFS/GAIN
3
REFSENSE
4
REF
5, 8, 11
6, 7, 12
9
10
AGND
AVDD
AIN
AIN
13
14
ENCODE
PWRDN
15, 23
16, 24
17–22, 25–28
DGND
DrVDD
D0 (LSB)–D5,
D6–D9 (MSB)
CMOS Output; Out-of-Range Indicator. Logic HIGH indicates the analog input voltage was
outside the converter’s range for the current output data.
Data Format Select and Gain Mode Select. Connect externally to AVDD for two’s complement
data format and 1 V p-p analog input range. Connect externally to AGND for Offset Binary data
format and 1 V p-p analog input range. Connect externally to REF (Pin 4) for two’s complement
data format and 2 V p-p analog input range. Floating this pin will configure the device for Offset
Binary data format and a 2 V p-p analog input range.
Reference Mode Select Pin for the ADC. This pin is normally connected externally to AGND,
which enables the internal 1.25 V reference, and configures REF (Pin 4) as an analog reference
output pin. Connecting REFSENSE externally to AVDD disables the internal reference, and configures REF (Pin 4) as an external reference input. In this case, the user must drive REF with a clean
and accurate 1.25 V (± 5%) reference input.
Reference input or output as configured by REFSENSE (Pin 3). When configured as an output
(REFSENSE = AGND), the internal reference (nominally 1.25 V) is enabled and is available to
the user on this pin. When configured as an input (REFSENSE = AVDD), the user must drive
REF with a clean and accurate 1.25 V (± 5%) reference. This pin should be bypassed to AGND
with an external 0.1 µF capacitor, whether it is configured as an input or output.
Analog Ground
Analog Power Supply, Nominally 3 V
Positive terminal of the differential analog input for the ADC.
Negative terminal of the differential analog input for the ADC. This pin can be left open if
operating in single-ended mode, but it is preferable to match the impedance seen at the positive
terminal (see Driving the Analog Inputs).
Encode Clock for the ADC. The AD9214 samples the analog signal on the rising edge of ENCODE.
CMOS-compatible power-down mode select, Logic LOW for normal operation; Logic HIGH
for power-down mode (digital outputs in high impedance state). PWRDN has an internal
10 kΩ pull-down resistor to ground.
Digital Output Ground
Digital Output Driver Power Supply. Nominally 2.5 V to 3.6 V.
CMOS Digital Outputs of ADC
PIN CONFIGURATION
28-Lead Shrink Small Outline Package
OR 1
28 D9 (MSB)
DFS/GAIN 2
27 D8
REFSENSE 3
26 D7
REF 4
25 D6
24 DrVDD
AGND 5
AVDD 6
AD9214
23 DGND
AVDD 7
TOP VIEW 22 D5
AGND 8 (Not to Scale) 21 D4
AIN 9
20 D3
AIN 10
19 D2
AGND 11
18 D1
17 D0 (LSB)
AVDD 12
ENCODE 13
16 DrVDD
PWRDN 14
15 DGND
–6–
REV. D
AD9214
TERMINOLOGY
Analog Bandwidth
Harmonic Distortion, Third
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
Aperture Uncertainty (Jitter)
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
The sample-to-sample variation in aperture delay.
Maximum Conversion Rate
Differential Analog Input Resistance, Differential Analog
Input Capacitance and Differential Analog Input Impedance
The encode rate at which parametric testing is performed.
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a
network analyzer.
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Differential Analog Input Voltage Range
Output Propagation Delay
Noise (for any range within the ADC)
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single
pin and subtracting the voltage from the other pin, which is
180 degrees out of phase. Peak-to-peak differential is computed
by rotating the inputs phase 180 degrees and taking the peak
measurement again. Then the difference is computed between
both peak measurements.
Where Z is the input impedance, FS is the full-scale of the
device for the frequency in question, SNR is the value for the
particular input level and Signal is the signal level within the
ADC reported in dB below full-scale. This value includes both
thermal and quantization noise.
Differential Nonlinearity
Power Supply Rejection Ratio (PSRR)
The deviation of any code width from an ideal 1 LSB step.
The ratio of a change in input offset voltage to a change in
power supply voltage.
Effective Number of Bits
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
 Full Scale 
SINADMEASURED – 1.76 dB + 20 log 

 Actual 
ENOB =
6.02
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the ENCODE
pulse should be left in Logic “1” state to achieve rated performance;
pulsewidth low is the minimum time ENCODE pulse should be left
in low state. See timing implications of changing tENCH in text. At a
given clock rate, these specs define an acceptable Encode duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
VNOISE = Z × 0.001 × 10
FS dBm − SNRdBc − Signal dBFS
10
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 0.5 dB below full
scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
Power FULL SCALE
 V 2FULL SCALE rms

Z INPUT
= 10 log 
0.001









Gain Error
Gain error is the difference between the measured and ideal full
scale input voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
REV. D
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an intermodulation distortion product. May
be reported in dBc (i.e., degrades as signal level is lowered), or
in dBFS (always related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
–7–
AD9214
Transient Response Time
Out-of-Range Recovery Time
Transient response is defined as the time it takes for the ADC
to reacquire the analog input after a transient from 10% above
negative full scale to 10% below positive full scale.
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
EQUIVALENT CIRCUITS
AVDD
30k⍀
AVDD
VREF
30k⍀
REF
AIN
40⍀
40⍀
15k⍀
10k⍀
AIN
15k⍀
10k⍀
Figure 2. Analog Input Stage
Figure 5. REF Configured as an Output
AVDD
2.6k⍀
600⍀
ENCODE
REF
10k⍀
2.6k⍀
Figure 3. Encode Inputs
Figure 6. REF Configured as an Input
DVDD
40⍀
DX
Figure 4. Digital Output Stage
–8–
REV. D
Typical Performance Characteristics– AD9214
0
0
ENCODE: 105MSPS
AIN: 50.3MHz @ –0.5dBFS
SNR: 53.0dB
ENOB: 8.5 BITS
SFDR: 64dBFS
–10
–20
–30
–30
–40
–40
dB
dB
–20
ENCODE: 65MSPS
AIN: 15.3MHz @ –0.5dBFS
SNR: 56.9dB
ENOB: 9.2 BITS
SFDR: 70dB
–10
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
52.5
0
52.5
0
FREQUENCY– MHz
FREQUENCY – MHz
TPC 1. FFT: fS = 105 MSPS, fIN = ~50.3 MHz; AIN = –0.5 dBFS
Differential, 1 V p-p Analog Input Range
TPC 4. FFT: fS = 65 MSPS, fIN = 15.3 MHz (2 V p-p) with
AD8138 Driving AIN
100
0
ENCODE: 80MSPS
AIN: 70.3MHz @ –0.5dBFS
SNR: 54.0dB
ENOB: 8.5 BITS
SFDR: 64dBFS
–10
–20
3RD
90
2ND
–30
80
dB
dB
–40
–50
70
–60
SFDR
60
–70
–80
50
–90
40
–100
0
40
0
10
20
FREQUENCY – MHz
TPC 2. FFT: fS = 80 MSPS, fIN = 70 MHz; AIN = –0.5 dBFS,
1 V p-p Analog Input Range
60
70
TPC 5. Harmonic Distortion (Second and Third) and SFDR
vs. AIN Frequency (1 V p-p, fS = 105 MSPS)
85
0
ENCODE: 105MSPS
AIN: 70.3MHz @ –0.5dBFS
SNR: 52.6dB
ENOB: 8.4 BITS
SFDR: 62.6dBFS
–10
–20
3RD
80
2ND
75
–30
70
–40
SFDR
dB
65
dB
30
40
50
AIN FREQUENCY – MHz
–50
60
–60
55
–70
50
–80
45
–90
40
–100
0
52.5
0
FREQUENCY– MHz
TPC 3. FFT: f S = 105 MSPS; fIN = 70 MHz (1 V p-p)
REV. D
25
50
AIN FREQUENCY – MHz
75
TPC 6. Harmonic Distortion (Second and Third) and SFDR
vs. AIN Frequency (1 V p-p, fS = 80 MSPS)
–9–
AD9214
75
100
SFDR – 1V p–p
70
90
SIGNAL LEVEL – dB
2ND
80
dB
3RD
70
SFDR
60
50
SFDR – 2V p–p
60
SINAD – 1V p–p
55
SINAD – 2V p–p
50
45
40
0
20
40
FREQUENCY – MHz
60
40
20
80
TPC 7. Harmonic Distortion (Second and Third) and SFDR
vs. AIN Frequency (1 V p-p and 2 V p-p, fS = 65 MSPS)
100
80
60
ENCODE RATE – MSPS
40
120
TPC 10. SINAD and SFDR vs. Encode Rate (fIN = 10.3 MHz;
1 V p-p and 2 V p-p)
0
75
ENCODE: 80MSPS
AIN: 29.3MHz @ –6dBFS
30.3MHz @ –6dBFS
SFDR: 74dBFS
–10
–20
SFDR – 80MSPS
70
65
SIGNAL LEVEL – dB
–30
–40
dB
65
–50
–60
–70
SFDR – 105MSPS
60
55
50
SINAD – 80MSPS
45
SINAD – 105MSPS
–80
40
–90
35
30
–100
2
40
0
4
FREQUENCY – MHz
TPC 8. Two-Tone Intermodulation Distortion (29.3 MHz,
30.3 MHz; 1 V p-p, fS = 80 MSPS)
6
PULSEWIDTH HIGH – ns
8
10
TPC 11. SINAD and SFDR vs. Encode Pulsewidth High
(1 V p-p)
0
120
ENCODE: 105MSPS
AIN: 30MHz @ –6dBFS
31MHz @ –6dBFS
SFDR: 73dBFS
–10
–20
12
100
10
IAVDD
–30
dB
–50
–60
–70
–80
8
6
60
IDrVDD
40
4
20
2
IDrVDD – mA
IAVDD – mA
80
–40
–90
0
–100
0
52.5
0
FREQUENCY – MHz
TPC 9. Two-Tone Intermodulation Distortion (30 MHz and
31 MHz; 1 V p-p, fS = 105 MSPS)
–10–
20
40
60
80
ENCODE RATE – MSPS
100
0
120
TPC 12. IAVDD and IDrVDD vs. Encode Rate (fAIN = 10.3 MHz,
–0.5 dBFS, and –3 dBFS) CLOAD on Digital Outputs ~7 pF
REV. D
AD9214
1.40
58
1.35
SNR 10.3MHz/105MSPS
54
1.30
SINAD 10.3MHz/105MSPS
VREF – V
SIGNAL LEVEL – dB
56
52
50
1.20
48
1.15
46
44
–40
0
40
TEMPERATURE – ⴗC
1.10
0
100
–500 –400 –300 –200 –100
IREF – ␮A
80
TPC 13. SINAD/SNR vs. Temperature (fAIN = 10.3 MHz,
fENCODE = 105 MSPS, 1 V p-p)
4.0
1.00
3.5
0.75
3.0
0.50
2.5
0.25
2.0
300
400
500
0.00
1.5
–0.25
1.0
–0.50
0.5
–0.75
0.0
–40
200
TPC 16. ADC Reference vs. Current Load
INL – LSB
% FULL SCALE
1.25
–1.00
0
40
TEMPERATURE – ⴗC
0
80
128
TPC 14. ADC Gain vs. Temperature (with External 1.25 V
Reference)
256
384
512
CODE
640
768
896
1024
896
1024
TPC 17. INL @ 80 MSPS
1.240
1.00
1.235
0.50
DNL – LSB
REFERENCE VOLTAGE – V
0.75
1.230
1.225
0.25
0.00
–0.25
–0.50
–0.75
1.220
–40
–1.00
0
40
TEMPERATURE – ⴗC
80
0
TPC 15. ADC Reference vs. Temperature (with 200 µA Load)
REV. D
128
256
384
512
CODE
640
768
TPC 18. DNL @ 80 MSPS
–11–
AD9214
THEORY OF OPERATION
DFS/GAIN
The AD9214 architecture is a bit-per-stage pipeline converter
utilizing switch capacitor techniques. These stages determine
the 7 MSBs and drive a 3-bit flash. Each stage provides sufficient overlap and error correction allowing optimization of
comparator accuracy. The input buffer is differential and both
inputs are internally biased. This allows the most flexible use of
ac or dc and differential or single-ended input modes. The output staging block aligns the data, carries out the error correction
and feeds the data to output buffers. The output buffers are
powered from a separate supply, allowing support of different
logic families. During power-down, the outputs go to a high
impedance state.
The DFS/GAIN (Data Format Select/Gain) input (Pin 2)
controls both the output data format and gain (analog input voltage range) of the ADC. The table below describes its operation.
APPLYING THE AD9214
Encoding the AD9214
Table I. Data Format and Gain Configuration
External
DFS/GAIN
Connection
Differential
Analog Input
Voltage Range
Output Data Format
AGND
AVDD
REF
Floating
1 V p-p
1 V p-p
2 V p-p
2 V p-p
Offset Binary
Two’s Complement
Two’s Complement
Offset Binary
Driving the Analog Inputs
Any high-speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A Track/
Hold circuit is essentially a mixer. Any noise, distortion, or
timing jitter on the clock will be combined with the desired
signal at the A/D output. For that reason, considerable care has
been taken in the design of the ENCODE input of the AD9214,
and the user is advised to give commensurate thought to the clock
source. The ENCODE input is fully TTL/CMOS compatible, and
should normally be driven directly from a low jitter, crystalcontrolled TTL/CMOS oscillator.
The ENCODE input is internally biased, allowing the user to
ac-couple in the clock signal. The cleanest clock source is often
a crystal oscillator producing a pure sine wave. Figure 7 illustrates
ac coupling such a source to the ENCODE input.
The analog input to the AD9214 is a differential buffer. As
shown in the equivalent circuits, each of the differential inputs is
internally dc biased at ~AVDD/3 to allow ac-coupling of the
analog input signal. The analog signal may be dc-coupled as
well. In this case, the dc load will be equivalent to ~10 kΩ to
AVDD/3, and the dc common-mode level of the analog signals
should be within the range of AVDD/3 ±200 mV. For best dynamic
performance, impedances at AIN and AIN should match.
Driving the analog input differentially optimizes ac performance,
minimizing even order harmonics and taking advantage of
common-mode rejection of noise. A differential signal may be
transformer-coupled, as illustrated in Figure 8, or driven from a
high-performance differential amplifier such as the AD8138
illustrated in Figure 9.
AD9214
AIN
50⍀
ANALOG
SIGNAL
SOURCE
ENCODE
LOW JITTER CRYSTAL SINE OR
PULSE SOURCE 1V p-p
25⍀
0.1␮F
AD9214
1:1
25⍀
AIN
Figure 7. AC-Coupled Encode Circuit
Figure 8. Single-Ended-to-Differential Conversion Using
a Transformer
Reference Circuit
The reference circuit of the AD9214 is configured by REFSENSE
(Pin 3). By externally connecting REFSENSE to AGND, the
ADC is configured to use the internal reference (~1.25 V), and
the REF pin connection (Pin 4) is configured as an output for
the internal reference voltage.
If REFSENSE is externally connected to AVDD, the ADC is
configured to use an external reference. In this mode, the REF
pin is configured as a reference input, and must be driven by an
external 1.25 V reference.
Special care was taken in the design of the analog input section
of the AD9214 to prevent damage and corruption of data when
the input is overdriven. The optimal input range is 1.0 V p-p, but
the AD9214 can support a 2.0 V p-p input range with some degradation in performance (see DFS/GAIN pin description above).
In either configuration, the analog input voltage range (either
1 V p-p or 2 V p-p as determined by DFS/Gain) will track the
reference voltage linearly, and an external bypass capacitor should
be connected between REF and AGND to reduce noise on the
reference. In practice, no appreciable degradation in performance
occurs when an external reference is adjusted ± 5%.
–12–
REV. D
AD9214
500⍀
50⍀
ANALOG
SIGNAL
SOURCE
500⍀
AVDD
AD8138
+ –
VOCM
– +
AD9214
50⍀
AIN
15pF
50⍀
AIN
10k⍀
5k⍀
500⍀
500⍀
0.1␮F
Figure 9. DC-Coupled Analog Input Circuit
POWER SUPPLIES
The AD9214 has two power supplies, AVDD and DrVDD. AVDD
and AGND supply power to all the analog circuitry, the inputs
and the internal timing and digital error correction circuits.
AVDD supply current will vary slightly with encode rate, as noted in
the Typical Performance Characteristics section.
DrVDD and DGND supply only the CMOS digital outputs,
allowing the user to adjust the voltage level to match downstream logic.
DrVDD current will vary depending on the voltage level, external
loading capacitance, and the encode frequency. Designs that minimize external load capacitance will reduce power consumption
and reduce supply noise that may affect ADC performance. The
maximum DrVDD current can be calculated as
I DrVDD = VDrVDD × CLOAD × fencode × N
where N is the number of output bits, 10 in the case of the
AD9214. This maximum current is for the condition of every
output bit switching on every clock cycle, which can only occur
for a full scale square wave at the Nyquist frequency, fENCODE /2.
In practice, IDrVDD will be the average number of output bits
switching, which will be determined by the encode rate and the
characteristics of the analog input signal. The performance
curves section provides a reference of IDrVDD versus encode rate
for a 10.3 MHz sine wave driving the analog input.
It should also be noted that extra capacitive loading will increase
output timing and invalidate timing specifications. Digital output
timing is guaranteed with 10 pF loads.
LAYOUT INFORMATION
The schematic of the evaluation board (Figure 10) represents a
typical implementation of the AD9214. A multilayer board is
recommended to achieve best results. It is highly recommended
that high quality, ceramic chip capacitors be used to decouple
each supply pin to ground directly at the device. The pinout of
the AD9214 facilitates ease of use in the implementation of high
frequency, high resolution design practices. All of the digital
outputs and their supply and ground pin connections are segregated to one side of the package, with the inputs on the opposite
side for isolation purposes.
Care should be taken when routing the digital output traces. To
prevent coupling through the digital outputs into the analog
portion of the AD9214, minimal capacitive loading should be
placed on these outputs. It is recommended that a fan-out of
only one gate should be used for all AD9214 digital outputs.
The layout of the encode circuit is equally critical. Any noise
received on this circuitry will result in corruption in the digitization process and lower overall performance. The Encode clock
must be isolated from the digital outputs and the analog inputs.
EVALUATION BOARD
The AD9214 evaluation board offers designers an easy way to
evaluate device performance. The user must supply an analog
input signal, encode clock reference, and power supplies. The
digital outputs of the AD9214 are latched on the evaluation
board, and are available with a data ready signal at a 40-pin
edge connector. Please refer to the evaluation board schematic,
layout, and Bill of Materials.
Power Connections
Power to the board is supplied via three detachable, 4-pin power
strips (U4, U9, and U10). These 12 pins should be driven as
outlined in the Table II.
Both power supply connections should be decoupled to ground
at or near the package connections, using high quality, ceramic
chip capacitors. A single ground plane is recommended for all
ground (AGND and DGND) connections.
Table II. Power Supply Connections for AD9214
Evaluation Board
The PWRDN control pin configures the AD9214 for a sleep
mode when it is logic HIGH. PWRDN floats logic LOW for
normal operation. In sleep mode, the ADC is not active, and
will consume less power. When switching from sleep mode to
normal operation, the ADC will need ~15 clock cycles to recover to
valid output data.
Pin
Designator
1
3
LVC
+5 V
5
–5 V
Digital Outputs
7
9
11
2, 4, 6,
8, 10, 12
VCC
VDD
DAC
GND
Care must be taken when designing the data receivers for the
AD9214. It is recommended that the digital outputs drive a
series resistor (e.g., 100 Ω) followed by a gate like the 74LCX821.
To minimize capacitive loading, there should be only one gate
on each output pin. An example of this is shown in the evaluation
board schematic in Figure 10. The series resistors should be
placed as close to the AD9214 as possible to limit the amount of
current that can flow into the output stage. These switching
currents are confined between ground (DGND) and the DrVDD
pins. Standard TTL gates should be avoided since they can
appreciably add to the dynamic switching currents of the AD9214.
REV. D
External Supply
Required
3V
+5 V
(Optional Z1 Supply)
–5 V
(Optional Z1 Supply)
3V
3V
5V
Ground
Please note that the +5 V and –5 V supplies are optional, and
only required if the user adds differential op amp Z1 to the board.
–13–
AD9214
Reference Circuit
Analog Input
The evaluation board is configured at assembly to use the
AD9214’s on-board reference. To supply an external reference,
the user must connect the REFSENSE pin to VCC by removing
the jumper block connecting E25 to E26, and placing it between
E19 and E24. In this configuration, an external 1.25 V reference
must be connected to jumper connection E23. Jumper connections
E19–E21, E24, and resistors R13–R14 are omitted at assembly,
and not used in the evaluation of the AD9214.
The analog input signal is connected to the evaluation board by
SMB connector J1. As configured at assembly, the signal is ac
coupled by capacitor C10 to transformer T1. This 1:1 transformer
provides a 50 Ω termination for connector J1 via 25 Ω resistors
R1 and R4. T1 also converts the signal at J1 into a differential
signal for the analog inputs of the AD9214. Resistor R3, normally
omitted, can be used to terminate J1 if the transformer is removed.
Gain/Data Format
The evaluation board is assembled with the DFS/GAIN pin
connected to ground; this configures the AD9214 for a 1 V p-p
analog input range, and offset binary data format. The user may
remove this jumper and replace it to make one of the connections
described in the table below to configure the AD9214 for different
gain and output data format options.
Table III. Data Format and Gain Configuration for
Evaluation Board
DFS/GAIN
Jumper
Placement
DFS/GAIN
Connection
Differential Output Data
AIN Range
Format
E18 to E12
E16 to E11
E15 to E14
E17 to E13
AGND
AVDD
REF
Floating
1 V p-p
1 V p-p
2 V p-p
2 V p-p
The user can reconfigure the board to drive the AD9214 singleendedly by removing the jumper block between E1 and E3, and
replacing it between E3 and E2. In this configuration, capacitor
C2 stabilizes the self-bias of AIN, and resistor R2 provides a
matched impedance for a 50 Ω source at J1.
Transformer T1 can be bypassed by moving the jumper normally
between E40 and E38 to connect E40 to E37, and moving the
jumper normally between E39 and E10 to connect E7 to E10.
In this configuration, the analog input of the AD9214 is driven
single ended, directly from J1; and R3 (normally omitted) should
be installed to terminate any cable connected to J1.
Using the AD8138
Offset Binary
Two’s Complement
Two’s Complement
Offset Binary
Power-Down
The evaluation board is configured at assembly so that the
PWRDN input floats low for normal operating condition. The
user may add a jumper between option holes E5 and E6 to
connect PWRDN to AVCC, configuring the AD9214 for powerdown mode.
Encode Signal and Distribution
The encode input signal should drive SMB connector J5, which
has an on-board 50 Ω termination. A standard CMOS compatible
pulse source is recommended. Alternatively, the user can adjust
the dc level of an ac-coupled clock source by adding resistor
R11, normally omitted. J5 drives the AD9214 ENCODE input
and one gate of U12, which buffers and distributes the clock
signal to the on-board latch (U3), the reconstruction DAC
(U11), and the output data connector (U2). The board comes
assembled with timing options optimized for the DAC and latch;
the user may invert the DR signal at Pin 37 of edge connector
U2 by removing the jumper block between E34 and E35, and
reinstalling it between E35 and E36.
An optional driver circuit for the analog input, based on the
AD8138 differential amplifier, is included in the layout of the
AD9214 evaluation board. This portion of the evaluation circuit
is not populated when the board is manufactured, but can be
easily be added by the user. Resistors R5, R16, R18, and R25
are the feedback network that sets the gain of the AD8138.
Resistors R23 and R24 set the common-mode voltage at the
output of the op amp. Resistors R27 and R28, and capacitor
C15, form a low-pass filter at the output of the AD8138, limiting
its noise contribution into the AD9214.
Once the drive circuit is populated, the user should remove the
jumper block normally between E40 and E38, and place it between
E40 and E41. This will ac-couple the analog input signal from
SMB connector J1 to the AD8138 drive circuit. The user will also
need to remove the jumper blocks that normally connect E39 to
E10 and E1 to E3 to remove transformer T1 from the circuit.
DAC Reconstruction Circuit
The data available at output connector U2 is also reconstructed by
DAC U11, the AD9752. This 12-bit, high-speed digital-to-analog
converter is included as a tool in setting up and debugging the
evaluation board. It should not be used to measure the performance of the AD9214, as its performance will not accurately
reflect the performance of the ADC. The DAC’s output, available
at J2, will drive 50 Ω. The user can add a jumper block between
E8 and E9 to activate the SLEEP function of the DAC.
–14–
REV. D
AD9214
AD9214/PCB Bill of Material
#
Quantity
Reference Designator
Device
1
2
3
4
5
6
7
8
9
10
1
19
4
1
4
4
4
1
2
37
N/A
C1–C3, C5–C14, C16–C20, C25–C28
C21–C24
C4
R1, R2, R4, R8
R7, R10, R12, R17
U5–U8
R21
R6, R9
E1–E6, E8–E9, E11–E27, E29, E31–E41
11
12
13
14
15
16
17
18
3
1
1
1
1
1
1
3
J1, J2, J5
U12
U11
U3
U1
U2
T1
U4, U9, U10
PCB
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Resistor
Resistor
Resistor
Test Points
Jumper Connections
Connector
Clock Chip
DAC
Latch
ADC/DUT
40-Pin Header
Transformer
Power Strip
Power Connector
Package
Value
603
CAPTAJD
603
1206
1206
RPAK_742
1206
1206
0.1 µF
10 µF
0.01 µF
25 Ω
50 Ω
100 Ω
0Ω
2000 Ω
TSW-120-07-G-S
SMT-100-BK-G
51-52-220
SN74LVC86
AD9752
74LCX821
AD9214
Samtec TSW-120-07-G-D
Mini Circuits ADT1-1WT
Newark 95F5966
25.602.5453.0
SMB
SOIC
SOIC
SOIC
SOIC
The following items are included in the PCB design, but are omitted at assembly.
19
20
21
22
23
24
25
26
27
28
29
3
2
1
4
1
1
3
2
3
1
1
REV. D
C1, C20, C28
C30, C29
C15
R5, R18, R25, R26
R23
R24
R11, R15, R16
R13, R14
R27, R28, R3
R19
Z1
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Op Amp
–15–
603
CAPTAJD
603
1206
1206
1206
1206
1206
1206
1206
SOIC
0.1 µF
10 µF
15 pF
500 Ω
1 kΩ
4 kΩ
User Select
N/A
50 Ω
0Ω
AD8138
J1
OPTIONAL
R3
50⍀
J5
3
5
–16–
R12
50⍀
R11
50⍀
LVC
LVC
R5
500⍀
GND
E36
E34
R21
0⍀
8
2
1
DR
GND
C25
0.1␮F
3
ⴙ5V
R25
500⍀
ⴙ
4
R27
50⍀
R28
50⍀
U12
1
1A
2
1B
3
1Y
4
2A
5
2B
6
2Y
7 GND
14
VCC
13
4B
12
4A
11
4Y
10
3B
9
3A
8
3Y
5N74LVC86
OPTIONAL
R17
50⍀
GND
GND
R19
0⍀
Vⴚ
Vⴙ
C1
0.1␮F
E6
CLKDAC
3
4
U1
E27
GND
E32
E33
R10
50⍀
LVC
LVC
GND
D9 MSB
D8
D7
D6
DrVDD
DGND
D5
D4
D3
D2
D1
D0 LSB
DrVDD1
DGND1
AD9214A
C16
0.1␮F
E28
E31
LVC
GND
AMP
AMP
CLKLAT
C15
15pF
2
OR
DFS/GAIN
REFSENSE
REF
AGND1
AVDD
AVDD
AGND
AIN
AIN
AGND
AVDD
CLK
PWRDN
E30
DTR
GND VCC
E4
1
U9
LVC GND +5V GND
3V
1
2
C27
R14
3
0.1␮F
2k⍀
4
5
VCC 6
C3 0.1␮F
C7 0.1␮F VCC
7
8
AMP
9
E3
10
GND
11
AMP
E2
C8 0.1␮F VCC 12
GND
13
ENC
E5 14
GND
R13
GND
2k⍀
OPTIONAL
C17
0.1␮F
5
6 C20
0.1␮F
–5V
Z1
VCOM
AD8138
ⴚ
R26
500⍀
C2
0.1␮F
C6
E1
0.1␮F
ENC
E35
R18
500⍀
E41
ENC
C28
0.1␮F
R23
1k⍀
R25
4k⍀
ⴙ5V
E21
E20
GND
E25
E26
GND
GND
R2
25⍀
E17
E13
GND GND
E18
E12
VCC
E19
E24
VCC
E16
E11
C4
0.1␮F
GND
GND
R1
25⍀
R4
25⍀
E22
E23
E7
E10
E39
OPTIONAL
4
2
GND
OPTIONAL
C18
0.1␮F
E29
E38
GND
E40
C10
0.1␮F E37
1 T1 6
GND
C26
0.1␮F
E15
E14
2
3
4
1
2
3
U10
4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C8
0.1␮F
GND
D2
D1
D0 LSB
GND
GND
D9 MSB
D8
D7
D6
D5
D4
D3
C9
0.1␮F
VDD
GND
VDD
U8
11
10
9
16
15
14
13
12
16
15
14
13
12
11
10
9
U11
GND
E9
GND
R6
2k⍀
GND
GND
C11
GND
VDD
GND
R9
2k⍀
U7
U8
R7
50⍀
J2
APAK_742
1
2
3
4
5
6
7
8
R15
50⍀
GND
DR
GND
DAC
C13
0.1␮F
C14
0.1␮F
DAC
24
22
20
18
16
14
12
34
32
30
28
26
40
38
36
10
10
8
8
6
6
4
4
2
2
24
22
20
18
16
14
12
U2 40
38
36
34
32
30
28
26
4QPHA
39
39
37
37
35
35
33
33
31
31
29
29
27
27
25
25
23
23
21
21
19
19
17
17
15
15
13
13
11
11
9
9
7
7
5
5
3
3
1
1
GND
GND
D1
D0
D4
D3
D2
GND
16
15
14
13
12
11
10
9
10
9
D9 MSB
D8
D7
D6
D5
GND
16
15
14
13
12
11
OPTIONAL
R16
50⍀
CLKLAT
VDD
APAK_742
7
8
1
2
3
4
5
6
C24
10␮F
DAC
R8 GND
25⍀
C23
10␮F
GND
CLKLAT
VDD
C19
0.1␮F
C12
0.1␮F
GND
23
22
21
20
19
18
17
16
15
14
13
DAC GND
E8
0.1␮F
CLKDAC
DE U3 VCC
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
GND
CLK
GND
C22
10␮F
VCC
24
GND
C21
10␮F
LVC
74LCXB21
C29
10␮F
+5V
1
2
3
4
5
6
7
8
9
10
11
12
C30
10␮F
GND
28
CLK
27
DVDD
26
DCOM
25
NC3
24
AVDD
23
ICOMP
22
IOUTA
21
IOUTB
20
ACOM
19
NC4
18
FSADJ
17
REFIO
16
REFLO
15
SLEEP
AD9752
APAK_742
5
6
7
8
1
2
3
4
APAK_742
U7
1
DB11
2
DB10
3
DB9
4
DB8
5
DB7
6
DB6
7
DB5
8
DB4
9
DB3
10
DB2
11
DB1
12
DB0
13
NC1
14
NC2
GND
1
2
3
4
5
6
7
8
–5V GND VCC GND VDD GND DAC GND
3V
3V
1
U4
–5V
GND
AD9214
Figure 10. PCB Schematic
REV. D
AD9214
Figure 11. PCB Top Side Silkscreen
Figure 14. PCB Bottom Side Copper
Figure 12. PCB Top Side Copper
Figure 15. PCB Ground Layer—Layer TBD
Figure 13. PCB Bottom Side Silkscreen
Figure 16. PCB Power Layers—Layers 3 and 4
\
REV. D
–17–
AD9214
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Shrink Small Outline Package
(RS-28)
0.407 (10.34)
0.397 (10.08)
15
1
14
0.212 (5.38)
0.205 (5.21)
0.311 (7.9)
0.301 (7.64)
28
0.078 (1.98) PIN 1
0.068 (1.73)
0.008 (0.203) 0.0256
(0.65)
0.002 (0.050) BSC
0.07 (1.79)
0.066 (1.67)
8°
0.015 (0.38)
0°
SEATING 0.009 (0.229)
0.010 (0.25)
PLANE
0.005 (0.127)
0.03 (0.762)
0.022 (0.558)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–18–
REV. D
AD9214
Revision History
Location
Page
Data Sheet changed from REV. C to REV. D.
Edit to Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
TPC 15 replaced with new figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Edit to Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
07/01—Data Sheet changed from REV. B to REV. C.
Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
05/01—Data Sheet changed from REV. A to REV. B.
Changes to PSRR Specifications in AD9214-65, AD9214-80, AD9214-105 Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Change to SNR Specifications in AD9214-105 Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to THIRD HARMONIC DISTORTION Specifications in AD9214-105 Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
01/01—Data Sheet changed from REV. 0 to REV. A.
Changes to DC Specifications in AD9214-65, AD9214-80, AD9214-105 Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to AC Specifications in AD9214-65, AD9214-105 Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
REV. D
–19–
–20–
PRINTED IN U.S.A.
C01693–0–2/02(D)