MC1496, MC1496B Balanced Modulators/ Demodulators These devices were designed for use where the output voltage is a product of an input voltage (signal) and a switching function (carrier). Typical applications include suppressed carrier and amplitude modulation, synchronous detection, FM detection, phase detection, and chopper applications. See ON Semiconductor Application Note AN531 for additional design information. http://onsemi.com Features 1 • Excellent Carrier Suppression −65 dB typ @ 0.5 MHz • • • • • SOIC−14 D SUFFIX CASE 751A 14 −50 dB typ @ 10 MHz Adjustable Gain and Signal Handling Balanced Inputs and Outputs High Common Mode Rejection −85 dB Typical This Device Contains 8 Active Transistors Pb−Free Package is Available* PDIP−14 P SUFFIX CASE 646 14 1 PIN CONNECTIONS Signal Input 1 14 VEE Gain Adjust 2 13 N/C Gain Adjust 3 12 Output Signal Input 4 11 N/C Bias 5 Output 6 N/C 7 10 Carrier Input 9 N/C 8 Input Carrier ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 12 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2004 April, 2004 − Rev. 9 1 Publication Order Number: MC1496/D MC1496, MC1496B 0 Log Scale Id IC = 500 kHz IS = 1.0 kHz 20 40 IC = 500 kHz, IS = 1.0 kHz 60 Figure 1. Suppressed Carrier Output Waveform 499 kHz 500 kHz 501 kHz Figure 2. Suppressed Carrier Spectrum 10 IC = 500 kHz IS = 1.0 kHz Linear Scale 8.0 6.0 4.0 2.0 IC = 500 kHz IS = 1.0 kHz 0 499 kHz Figure 3. Amplitude Modulation Output Waveform 500 kHz 501 kHz Figure 4. Amplitude−Modulation Spectrum MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.) Symbol Value Unit V 30 Vdc Differential Input Signal V8 − V10 V4 − V1 +5.0 ±(5 + I5Re) Vdc Maximum Bias Current I5 10 mA RJA 100 °C/W TA 0 to +70 −40 to +125 °C Storage Temperature Range Tstg −65 to +150 °C Electrostatic Discharge Sensitivity (ESD) Human Body Model (HBM) Machine Model (MM) ESD Rating Applied Voltage (V6−V8, V10−V1, V12−V8, V12−V10, V8−V4, V8−V1, V10−V4, V6−V10, V2−V5, V3−V5) Thermal Resistance, Junction−to−Air Plastic Dual In−Line Package Operating Ambient Temperature Range MC1496 MC1496B V 2000 400 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. http://onsemi.com 2 MC1496, MC1496B ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, VEE = −8.0 Vdc, I5 = 1.0 mAdc, RL = 3.9 k, Re = 1.0 k, TA = Tlow to Thigh, all input and output characteristics are single−ended, unless otherwise noted.) (Note 1) Characteristic Carrier Feedthrough VC = 60 mVrms sine wave and offset adjusted to zero VC = 300 mVpp square wave: offset adjusted to zero offset not adjusted Fig. Note Symbol Min Typ Max fC = 1.0 kHz fC = 10 MHz 5 1 VCFT − − 40 140 − − fC = 1.0 kHz fC = 1.0 kHz − − 0.04 20 0.4 200 Unit Vrms mVrms Carrier Suppression fS = 10 kHz, 300 mVrms fC = 500 kHz, 60 mVrms sine wave fC = 10 MHz, 60 mVrms sine wave 5 2 Transadmittance Bandwidth (Magnitude) (RL = 50 ) Carrier Input Port, VC = 60 mVrms sine wave fS = 1.0 kHz, 300 mVrms sine wave Signal Input Port, VS = 300 mVrms sine wave |VC| = 0.5 Vdc 8 Signal Gain (VS = 100 mVrms, f = 1.0 kHz; | VC|= 0.5 Vdc) 10 3 Single−Ended Input Impedance, Signal Port, f = 5.0 MHz Parallel Input Resistance Parallel Input Capacitance 6 − Single−Ended Output Impedance, f = 10 MHz Parallel Output Resistance Parallel Output Capacitance 6 Input Bias Current I I1 I4 ; I I8 I10 bS bC 2 2 Input Offset Current IioS = I1−I4; IioC = I8−I10 7 7 Average Temperature Coefficient of Input Offset Current (TA = −55°C to +125°C) VCS dB 40 − 8 65 50 − − BW3dB k MHz − 300 − − 80 − AVS 2.5 3.5 − V/V rip cip − − 200 2.0 − − k pF rop coo − − 40 5.0 − − k pF IbS IbC − − 12 12 30 30 − IioS IioC − − 0.7 0.7 7.0 7.0 A 7 − TCIio − 2.0 − nA/°C Output Offset Current (I6−I9) 7 − Ioo − 14 80 A Average Temperature Coefficient of Output Offset Current (TA = −55°C to +125°C) 7 − TCIoo − 90 − nA/°C Common−Mode Input Swing, Signal Port, fS = 1.0 kHz 9 4 CMV − 5.0 − Vpp Common−Mode Gain, Signal Port, fS = 1.0 kHz, |VC|= 0.5 Vdc 9 − ACM − −85 − dB Common−Mode Quiescent Output Voltage (Pin 6 or Pin 9) 10 − Vout − 8.0 − Vpp Differential Output Voltage Swing Capability 10 − Vout − 8.0 − Vpp Power Supply Current I6 +I12 Power Supply Current I14 7 6 ICC IEE − − 2.0 3.0 4.0 5.0 mAdc 7 5 PD − 33 − mW DC Power Dissipation 1. Tlow = 0°C for MC1496 = −40°C for MC1496B Thigh = +70°C for MC1496 = +125°C for MC1496B http://onsemi.com 3 − A − MC1496, MC1496B GENERAL OPERATING INFORMATION Carrier Feedthrough Note that in the test circuit of Figure 10, VS corresponds to a maximum value of 1.0 V peak. Carrier feedthrough is defined as the output voltage at carrier frequency with only the carrier applied (signal voltage = 0). Carrier null is achieved by balancing the currents in the differential amplifier by means of a bias trim potentiometer (R1 of Figure 5). Common Mode Swing The common−mode swing is the voltage which may be applied to both bases of the signal differential amplifier, without saturating the current sources or without saturating the differential amplifier itself by swinging it into the upper switching devices. This swing is variable depending on the particular circuit and biasing conditions chosen. Carrier Suppression Carrier suppression is defined as the ratio of each sideband output to carrier output for the carrier and signal voltage levels specified. Carrier suppression is very dependent on carrier input level, as shown in Figure 22. A low value of the carrier does not fully switch the upper switching devices, and results in lower signal gain, hence lower carrier suppression. A higher than optimum carrier level results in unnecessary device and circuit carrier feedthrough, which again degenerates the suppression figure. The MC1496 has been characterized with a 60 mVrms sinewave carrier input signal. This level provides optimum carrier suppression at carrier frequencies in the vicinity of 500 kHz, and is generally recommended for balanced modulator applications. Carrier feedthrough is independent of signal level, VS. Thus carrier suppression can be maximized by operating with large signal levels. However, a linear operating mode must be maintained in the signal−input transistor pair − or harmonics of the modulating signal will be generated and appear in the device output as spurious sidebands of the suppressed carrier. This requirement places an upper limit on input−signal amplitude (see Figure 20). Note also that an optimum carrier level is recommended in Figure 22 for good carrier suppression and minimum spurious sideband generation. At higher frequencies circuit layout is very important in order to minimize carrier feedthrough. Shielding may be necessary in order to prevent capacitive coupling between the carrier input leads and the output leads. Power Dissipation Power dissipation, PD, within the integrated circuit package should be calculated as the summation of the voltage−current products at each port, i.e. assuming V12 = V6, I5 = I6 = I12 and ignoring base current, PD = 2 I5 (V6 − V14) + I5)V5 − V14 where subscripts refer to pin numbers. Design Equations The following is a partial list of design equations needed to operate the circuit with other supply voltages and input conditions. A. Operating Current The internal bias currents are set by the conditions at Pin 5. Assume: I5 = I6 = I12, IB IC for all transistors then : R5 The MC1496 has been characterized for the condition I5 = 1.0 mA and is the generally recommended value. B. Common−Mode Quiescent Output Voltage V6 = V12 = V+ − I5 RL Biasing Signal Gain and Maximum Input Level The MC1496 requires three dc bias voltage levels which must be set externally. Guidelines for setting up these three levels include maintaining at least 2.0 V collector−base bias on all transistors while not exceeding the voltages given in the absolute maximum rating table; 30 Vdc [(V6, V12) − (V8, V10)] 2 Vdc 30 Vdc [(V8, V10) − (V1, V4)] 2.7 Vdc 30 Vdc [(V1, V4) − (V5)] 2.7 Vdc The foregoing conditions are based on the following approximations: Signal gain (single−ended) at low frequencies is defined as the voltage gain, A VS where: R5 is the resistor between V 500 where: Pin 5 and ground I5 where: = 0.75 at TA = +25°C R Vo L where r e 26 mV R e2r e V I5(mA) S A constant dc potential is applied to the carrier input terminals to fully switch two of the upper transistors “on” and two transistors “off” (VC = 0.5 Vdc). This in effect forms a cascode differential amplifier. Linear operation requires that the signal input be below a critical value determined by RE and the bias current I5. V6 = V12, V8 = V10, V1 = V4 VS I5 RE (Volts peak) http://onsemi.com 4 MC1496, MC1496B Negative Supply Bias currents flowing into Pins 1, 4, 8 and 10 are transistor base currents and can normally be neglected if external bias dividers are designed to carry 1.0 mA or more. VEE should be dc only. The insertion of an RF choke in series with VEE can enhance the stability of the internal current sources. Transadmittance Bandwidth Signal Port Stability Carrier transadmittance bandwidth is the 3.0 dB bandwidth of the device forward transadmittance as defined by: i o (each sideband) v s (signal) 21C Under certain values of driving source impedance, oscillation may occur. In this event, an RC suppression network should be connected directly to each input using short leads. This will reduce the Q of the source−tuned circuits that cause the oscillation. Vo 0 Signal transadmittance bandwidth is the 3.0 dB bandwidth of the device forward transadmittance as defined by: i o (signal) 21S v (signal) s Vc 0.5 Vdc, Vo 0 Signal Input (Pins 1 and 4) 510 10 pF Coupling and Bypass Capacitors Capacitors C1 and C2 (Figure 5) should be selected for a reactance of less than 5.0 at the carrier frequency. An alternate method for low−frequency applications is to insert a 1.0 k resistor in series with the input (Pins 1, 4). In this case input current drift may cause serious degradation of carrier suppression. Output Signal The output signal is taken from Pins 6 and 12 either balanced or single−ended. Figure 11 shows the output levels of each of the two output sidebands resulting from variations in both the carrier and modulating signal inputs with a single−ended output connection. TEST CIRCUITS 1.0 k VCC 12 Vdc 1.0 k Re C1 0.1 F 51 C2 Carrier Input 0.1 F VC VS Modulating Signal Input 10 k 10 k 51 2 8 10 1 4 1.0 k I9 I6 50 k I10 V− R1 Zin +V o I5 6.8 k −8.0 Vdc NOTE: −8.0 Vdc VEE 1.0 k I6 6 MC1496 2.0 k I9 12 I10 VCC 12 Vdc 1.0 k Re 51 3 14 Shielding of input and output leads may be needed to properly perform these tests. Figure 6. Input−Output Impedance Re = 1.0 k 1.0 k 12 5 6.8 k 1.0 k 8 10 1 4 +V o Zout −V o 6 MC1496 5 VCC 12 Vdc I7 I8 I1 I4 3 14 Figure 5. Carrier Rejection and Suppression 2 2 −V o 12 14 0.5 V 8 + − 10 1 4 RL 3.9 k RL 3.9 k 6 MC1496 51 Carrier Null 3 Re = 1.0 k 5 Carrier Input 0.1 F VC VS Modulating Signal Input 10 k 0.1 F 8 10 1 4 10 k 51 51 2 1.0 k Carrier Null −8.0 Vdc VEE 3 50 50 6 MC1496 12 14 50 k 6.8 k 2.0 k 5 6.8 k V− −8.0 Vdc VEE Figure 8. Transconductance Bandwidth Figure 7. Bias and Offset Currents http://onsemi.com 5 0.01 F +V o −V o MC1496, MC1496B VCC 12 Vdc Re = 1.0 k 1.0 k VS 14 Re = 1.0 k 1.0 k 3.9 k 3 0.5 V 8 2 + − 10 1 MC1496 6 4 12 1.0 k VCC 12 Vdc 3.9 k 1.0 k +V o VS −V o 0.5 V 8 + − 10 1 4 5 50 6.8 k 50 −8.0 Vdc VEE V A 20 log o CM V S 2 3 3.9 k 6 MC1496 12 14 5 I5 = 1.0 mA 6.8 k 3.9 k +V o −V o −8.0 Vdc VEE Figure 9. Common Mode Gain Figure 10. Signal Gain and Output Swing Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave), VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25°C, unless otherwise noted. 1.0 M 2.0 r ip, PARALLEL INPUT RESISTANCE (k Ω) 1.6 Signal Input = 600 mV 1.2 400 mV 0.8 300 mV 200 mV 0.4 100 mV 0 0 50 200 100 150 VC, CARRIER LEVEL (mVrms) 500 +rip 50 10 5.0 1.0 1.0 5.0 4.0 3.0 2.0 1.0 2.0 20 10 5.0 f, FREQUENCY (MHz) 5.0 10 f, FREQUENCY (MHz) 50 100 Figure 12. Signal−Port Parallel−Equivalent Input Resistance versus Frequency 50 100 rop , PARALLEL OUTPUT RESISTANCE (k Ω) cip , PARALLEL INPUT CAPACITANCE (pF) Figure 11. Sideband Output versus Carrier Levels 0 1.0 −rip 100 Figure 13. Signal−Port Parallel−Equivalent Input Capacitance versus Frequency 140 14 120 12 100 10 rop 80 60 cop 6.0 40 4.0 20 2.0 0 1.0 0 10 f, FREQUENCY (MHz) Figure 14. Single−Ended Output Impedance versus Frequency http://onsemi.com 6 8.0 0 100 cop, PARALLEL OUTPUT CAPACITANCE (pF) VO , OUTPUT AMPLITUDE OF EACH SIDEBAND (Vrms) TYPICAL CHARACTERISTICS MC1496, MC1496B TYPICAL CHARACTERISTICS (continued) 0 1.0 0.9 Signal Port VCS, CARRIER SUPPRESION (dB) γ 21, TRANSADMITTANCE (mmho) Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave), VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25°C, unless otherwise noted. 0.8 0.7 0.6 Side Band Sideband Transadmittance I out(EachSideband) 21 V out 0 V (Signal) in 0.5 0.4 0.3 Signal Port Transadmittance I 21 out V out 0|V | 0.5Vdc C V in 10 1.0 100 fC, CARRIER FREQUENCY (MHz) 0.2 0.1 0 0.1 10 20 (70°C) 40 50 60 70 −75 1000 MC1496 30 −50 SUPPRESSION BELOW EACH FUNDAMENTAL CARRIER SIDEBAND (dB) AVS, SINGLE-ENDED VOLTAGE GAIN (dB) 10 0 −10 |VC| = 0.5 Vdc −20 RL = 3.9 k Re = 2.0 k RL = 500 Re = 1.0 k R L A V R e 2r e −30 0.01 0.1 1.0 f, FREQUENCY (MHz) 10 100 SUPPRESSION BELOW EACH FUNDAMENTAL CARRIER SIDEBAND (dB) VCFT , CARRIER OUTPUT VOLTAGE (mVrms) 1.0 0.1 0.5 1.0 5.0 10 fC, CARRIER FREQUENCY (MHz) 75 100 125 150 175 10 20 2fC 30 40 50 fC 60 70 0.05 3fC 0.1 0.5 1.0 5.0 10 fC, CARRIER FREQUENCY (MHz) 50 Figure 18. Carrier Suppression versus Frequency 10 0.1 50 0 Figure 17. Signal−Port Frequency Response 0.01 0.05 25 Figure 16. Carrier Suppression versus Temperature RL = 3.9 k Re = 500 RL = 3.9 k (Standard Re = 1.0 k Test Circuit) 0 TA, AMBIENT TEMPERATURE (°C) Figure 15. Sideband and Signal Port Transadmittances versus Frequency 20 −25 50 0 10 20 30 40 fC ± 3fS 50 fC ± 2fS 60 70 80 0 Figure 19. Carrier Feedthrough versus Frequency 200 400 600 VS, INPUT SIGNAL AMPLITUDE (mVrms) Figure 20. Sideband Harmonic Suppression versus Input Signal Level http://onsemi.com 7 800 0 0 V CS , CARRIER SUPPRESSION (dB) SUPPRESSION BELOW EACH FUNDAMENTAL CARRIER SIDEBAND (dB) MC1496, MC1496B 10 3fC ± fS 20 30 40 2fC ± fS 50 2fC ± 2fS 60 70 0.05 0.1 0.5 1.0 5.0 10 fC, CARRIER FREQUENCY (MHz) 10 20 30 40 fC = 500 kHz 50 60 70 50 fC = 10 MHz 0 100 Figure 21. Suppression of Carrier Harmonic Sidebands versus Carrier Frequency 200 300 400 VC, CARRIER INPUT LEVEL (mVrms) 500 Figure 22. Carrier Suppression versus Carrier Input Level OPERATIONS INFORMATION components and have an amplitude which is a function of the product of the input signal amplitudes. For high−level operation at the carrier input port and linear operation at the modulating signal port, the output signal will contain sum and difference frequency components of the modulating signal frequency and the fundamental and odd harmonics of the carrier frequency. The output amplitude will be a constant times the modulating signal amplitude. Any amplitude variations in the carrier signal will not appear in the output. The linear signal handling capabilities of a differential amplifier are well defined. With no emitter degeneration, the maximum input voltage for linear operation is approximately 25 mV peak. Since the upper differential amplifier has its emitters internally connected, this voltage applies to the carrier input port for all conditions. Since the lower differential amplifier has provisions for an external emitter resistance, its linear signal handling range may be adjusted by the user. The maximum input voltage for linear operation may be approximated from the following expression: The MC1496, a monolithic balanced modulator circuit, is shown in Figure 23. This circuit consists of an upper quad differential amplifier driven by a standard differential amplifier with dual current sources. The output collectors are cross−coupled so that full−wave balanced multiplication of the two input voltages occurs. That is, the output signal is a constant times the product of the two input signals. Mathematical analysis of linear ac signal multiplication indicates that the output spectrum will consist of only the sum and difference of the two input frequencies. Thus, the device may be used as a balanced modulator, doubly balanced mixer, product detector, frequency doubler, and other applications requiring these particular output signal characteristics. The lower differential amplifier has its emitters connected to the package pins so that an external emitter resistance may be used. Also, external load resistors are employed at the device output. Signal Levels The upper quad differential amplifier may be operated either in a linear or a saturated mode. The lower differential amplifier is operated in a linear mode for most applications. For low−level operation at both input ports, the output signal will contain sum and difference frequency (−) 12 (+) 6 V = (I5) (RE) volts peak. This expression may be used to compute the minimum value of RE for a given input voltage amplitude. 1.0 k Vo, Output 51 10 (−) Carrier V Input C V 0.1 F Carrier C Input VS Modulating Signal 10 k Input 8 (+) 4 (−) Signal V S 1 (+) Input 2 3 Gain Adjust Bias 5 500 500 500 12 Vdc 1.0 k 0.1 F 8 10 1 4 10 k 51 51 2 Re 1.0 k 6 12 14 5 50 k Carrier Null VEE 14 Figure 23. Circuit Schematic RL 3.9 k 6.8 k −8.0 Vdc VEE Figure 24. Typical Modulator Circuit http://onsemi.com 8 RL 3.9 k +Vo MC1496 I5 (Pin numbers per G package) 3 −Vo MC1496, MC1496B Table 1. Voltage Gain and Output Frequencies Carrier Input Signal (VC) Low−level dc Approximate Voltage Gain R V L C 2(R 2r e) KT q E Output Signal Frequency(s) fM High−level dc R L R 2r e E fM Low−level ac R V (rms) L C KT 2 2 q (R 2r e) E fC ± fM 0.637 R L fC ± fM, 3fC ± fM, 5fC ± fM, . . . R 2r e E Low−level Modulating Signal, VM, assumed in all cases. VC is Carrier Input Voltage. When the output signal contains multiple frequencies, the gain expression given is for the output amplitude ofeach of the two desired outputs, fC + fM and fC − fM. All gain expressions are for a single−ended output. For a differential output connection, multiply each expression by two. RL = Load resistance. RE = Emitter resistance between Pins 2 and 3. re = Transistor dynamic emitter resistance, at 25°C; 26 mV High−level ac 2. 3. 4. 5. 6. 7. re I5 (mA) 8. K = Boltzmann′s Constant, T = temperature in degrees Kelvin, q = the charge on an electron. The gain from the modulating signal input port to the output is the MC1496 gain parameter which is most often of interest to the designer. This gain has significance only when the lower differential amplifier is operated in a linear mode, but this includes most applications of the device. As previously mentioned, the upper quad differential amplifier may be operated either in a linear or a saturated mode. Approximate gain expressions have been developed for the MC1496 for a low−level modulating signal input and the following carrier input conditions: 1) Low−level dc 2) High−level dc 3) Low−level ac 4) High−level ac All that is required to shift from suppressed carrier to AM operation is to adjust the carrier null potentiometer for the proper amount of carrier insertion in the output signal. However, the suppressed carrier null circuitry as shown in Figure 26 does not have sufficient adjustment range. Therefore, the modulator may be modified for AM operation by changing two resistor values in the null circuit as shown in Figure 27. Product Detector The MC1496 makes an excellent SSB product detector (see Figure 28). This product detector has a sensitivity of 3.0 V and a dynamic range of 90 dB when operating at an intermediate frequency of 9.0 MHz. The detector is broadband for the entire high frequency range. For operation at very low intermediate frequencies down to 50 kHz the 0.1 F capacitors on Pins 8 and 10 should be increased to 1.0 F. Also, the output filter at Pin 12 can be tailored to a specific intermediate frequency and audio amplifier input impedance. As in all applications of the MC1496, the emitter resistance between Pins 2 and 3 may be increased or decreased to adjust circuit gain, sensitivity, and dynamic range. This circuit may also be used as an AM detector by introducing carrier signal at the carrier input and an AM signal at the SSB input. The carrier signal may be derived from the intermediate frequency signal or generated locally. The carrier signal may These gains are summarized in Table 1, along with the frequency components contained in the output signal. APPLICATIONS INFORMATION Double sideband suppressed carrier modulation is the basic application of the MC1496. The suggested circuit for this application is shown on the front page of this data sheet. In some applications, it may be necessary to operate the MC1496 with a single dc supply voltage instead of dual supplies. Figure 25 shows a balanced modulator designed for operation with a single 12 Vdc supply. Performance of this circuit is similar to that of the dual supply modulator. AM Modulator The circuit shown in Figure 26 may be used as an amplitude modulator with a minor modification. http://onsemi.com 9 MC1496, MC1496B Figures 30 and 31 show a broadband frequency doubler and a tuned output very high frequency (VHF) doubler, respectively. be introduced with or without modulation, provided its level is sufficiently high to saturate the upper quad differential amplifier. If the carrier signal is modulated, a 300 mVrms input level is recommended. Phase Detection and FM Detection The MC1496 will function as a phase detector. High−level input signals are introduced at both inputs. When both inputs are at the same frequency the MC1496 will deliver an output which is a function of the phase difference between the two input signals. An FM detector may be constructed by using the phase detector principle. A tuned circuit is added at one of the inputs to cause the two input signals to vary in phase as a function of frequency. The MC1496 will then provide an output which is a function of the input signal frequency. Doubly Balanced Mixer The MC1496 may be used as a doubly balanced mixer with either broadband or tuned narrow band input and output networks. The local oscillator signal is introduced at the carrier input port with a recommended amplitude of 100 mVrms. Figure 29 shows a mixer with a broadband input and a tuned output. Frequency Doubler The MC1496 will operate as a frequency doubler by introducing the same frequency at both input ports. TYPICAL APPLICATIONS 820 1.0 k 25 F 15 V Carrier Input 60 mVrms + Modulating − + 0.1 F 0.1 F 51 10 k 10 k 8 10 1 4 2 1.0 k 100 3.0 k 1.0 k 3.0 k 3 0.1 F Output MC1496 5 12 10 k 100 51 VC 0.1 F Carrier Input VS Modulating Signal 750 Input 750 50 k RL 0.1 F 2 Re 1.0 k 3 3.9 k 8 6 10 1 MC1496 4 12 51 51 14 5 Carrier Adjust RL 3.9 + 6 MC1496 51 51 14 − 5 I5 VEE −8.0 Vdc 6.8 k Figure 26. Balanced Modulator−Demodulator VCC 12 Vdc 1.0 k RL 3 3.9 k Re 1.0 k 12 10 k 50 k R1 Carrier Null Figure 25. Balanced Modulator (12 Vdc Single Supply) 1.0 k 0.1 F 2 8 10 1 4 51 VC 0.1 F Carrier Input VS Modulating 10 k Signal Input VCC 12 Vd 1.0 k DSB 6 25 F 14 15 V + − Signal Input 10 F 300 mVrms 15 V Carrier Null 50 k VCC 12 Vdc 1.3 k RL 3.9 k 820 0.1 F 1.0 k 2 51 +Vo Carrier Input 300 mVrms SSB Input −Vo VCC 12 Vdc 1.3 k 8 0.1 F 10 1 1.0 k 4 0.1 F 1.0 k 15 6.8 k VEE −8.0 Vdc Figure 27. AM Modulator Circuit 0.1 F 100 3.0 k 3 6 0.005 F AF 1.0 k 1.0 F Outp MC1496 14 5 12 10 k Figure 28. Product Detector (12 Vdc Single Supply) http://onsemi.com 10 3.0 k RL 10 0.005 0.005 F F MC1496, MC1496B 1.0 k VCC +8.0 Vdc 1.0 k 0.001 F Local Oscillator Input 100 mVrms 3 2 8 10 0.001 F 1 0.01 F 0.001 F 9.5 F 4 10 k 51 10 k 51 50 k Null Adjust 100 3 3.9 k 10 k 10 k 100 100 Outp MC1496 12 4 90−480 pF 3.9 k 6 10 100 F − C2+ Input 15 Vdc Max 15 mVrms 100 F 15 Vdc 1 9.0 MHz Output RL = 50 L1 12 5 5.0−80 pF 6.8 k 14 C2 1.0 k 2 8 1.0 k 6 MC1496 100 F 25 Vdc + 1.0 k − RFC 100 H 51 RF Input VCC 12 Vdc 14 5 50 k VEE −8.0 Vdc 6.8 k I5 L1 = 44 Turns AWG No. 28 Enameled Wire, Wound on Micrometals Type 44−6 Toroid Core. Figure 29. Doubly Balanced Mixer (Broadband Inputs, 9.0 MHz Tuned Output) 1.0 k Figure 30. Low−Frequency Doubler V+ 1.0 k 0.001 F 8 10 1 0.001 F 150 MHz Input 2 RFC 0.68 H 3 L1 18 nH 1.0−10 pF 6 1.0−10 pF MC1496 300 MHz Output RL = 50 4 12 10 k 10 k 50 k 100 VCC +8.0 Vdc 18 pF 0.001 F 100 VEE −8.0 Vdc Balance 100 14 5 6.8 k Balance L1 = 1 Turn AWG No. 18 Wire, 7/32″ ID VEE −8.0 Vdc Frequency fC fS fC ± fS (3fC + f S ) (3fC + 2f S ) (3f C ) (3fC − 2f S ) (3fC − fS ) (2fC + 2f S ) (2fC + 2f S ) (2fC − 2f S ) (2fC ) (2fC − 2f S ) (fC + f S ) (f + 2f ) C S (fC ) (fC − 2f S ) AMPLITUDE (fC − f S ) Figure 31. 150 to 300 MHz Doubler Balanced Modulator Spectrum DEFINITIONS fC ± nfS Fundamental Carrier Sideband Harmonics Carrier Harmonics nfC nfC ± nfS Carrier Harmonic Sidebands Carrier Fundamental Modulating Signal Fundamental Carrier Sidebands http://onsemi.com 11 MC1496, MC1496B ORDERING INFORMATION Package Shipping† MC1496D SOIC−14 55 Units/Rail MC1496DR2 SOIC−14 2500 Tape & Reel MC1496DR2G SOIC−14 (Pb−Free) 2500 Tape & Reel MC1496P PDIP−14 25 Units/Rail MC1496PG PDIP−14 (Pb−Free) 25 Units/Rail MC1496P1 PDIP−14 25 Units/Rail MC1496BD SOIC−14 55 Units/Rail MC1496BDR2 SOIC−14 2500 Tape & Reel MC1496BP PDIP−14 25 Units/Rail Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS PDIP−14 P SUFFIX CASE 646 SOIC−14 D SUFFIX CASE 751A 14 14 MC1496D AWLYWW 1 14 MC1496BD AWLYWW 14 MC1496P AWLYYWW 1 1 A WL YY, Y WW = Assembly Location = Wafer Lot = Year = Work Week http://onsemi.com 12 MC1496BP AWLYYWW 1 MC1496, MC1496B PACKAGE DIMENSIONS SOIC−14 D SUFFIX PLASTIC PACKAGE CASE 751A−03 ISSUE F −A− 14 8 −B− 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. P 7 PL 0.25 (0.010) 7 G B M M F R X 45 C −T− SEATING PLANE 0.25 (0.010) M J M K D 14 PL T B S 14 8 1 7 A S PDIP−8 P SUFFIX PLASTIC PACKAGE CASE 646−06 ISSUE M A F L C −T− SEATING PLANE J K H G D 14 PL M 0.13 (0.005) M http://onsemi.com 13 MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B N DIM A B C D F G J K M P R DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10 0.38 1.01 MC1496, MC1496B ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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