INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4731B; HEF4731V LSI Quadruple 64-bit static shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4731B; HEF4731V LSI Quadruple 64-bit static shift register Recommended supply voltage range for HEF4731B is 3 to 15 V and for HEF4731V is 4,5 to 12,5 V. DESCRIPTION The HEF4731B and HEF4731V are quadruple 64-bit static shift registers each with separate serial data inputs (DA to DD), clock inputs (CPA to CPD) and data outputs (O63A to O63D) from the 64th register position. Data are shifted to the next stage on the negative-going transitions of the clock. Low impedance outputs are provided for direct interface to TTL. Fig.2 Pinning diagram. HEF4731BP; HEF4731VP(N): 14-lead DIL; plastic (SOT27-1) HEF4731BD; HEF4731VD(F): 14-lead DIL; ceramic (cerdip) (SOT73) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category LSI See Family Specifications Fig.1 Functional diagram. January 1995 2 Philips Semiconductors Product specification HEF4731B; HEF4731V LSI Quadruple 64-bit static shift register Fig.3 Logic diagram (one of 64-bits shift register). The values given at VDD = 15 V in the following DC and AC characteristics, are not applicable to the HEF4731V, because of its reduced supply voltage range. DC CHARACTERISTICS VSS = 0 V; VI = VSS or VDD Tamb (°C) VDD V VOL V VOH V −40 SYMBOL MIN. Output (source) current HIGH MIN. MAX. + 85 MIN. MAX. 5 2,5 3 2,5 2,0 mA 5 4,6 1 0,85 0,65 mA 10 9,5 3 2,5 2,0 mA 10 15 Output (sink) MAX. + 25 −IOH 13,5 4,75 0,4 current 10 0,5 LOW 15 1,5 IOL 8,5 6,5 mA 2,3 2,0 1,6 mA 6,0 5,0 4,0 mA 20,0 18,0 14,0 mA AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns Dynamic power dissipation per package (P) VDD V TYPICAL FORMULA FOR P (µW) 5 13 000 fi + ∑ (foCL) × VDD2 where 10 55 000 fi + ∑ (foCL) × VDD2 fi = input freq. (MHz) 15 140 000 fi + ∑ (foCL) × fo = output freq. (MHz) VDD2 CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3 Philips Semiconductors Product specification HEF4731B; HEF4731V LSI Quadruple 64-bit static shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays CP → O63 HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 Transition times O63 HIGH to LOW 5 10 tTHL 15 5 LOW to HIGH 10 tTLH 15 Minimum clock 230 ns 132 ns + (0,26 ns/pF) CL 55 110 ns 47 ns + (0,16 ns/pF) CL 40 80 ns 34 ns + (0,11 ns/pF) CL 130 260 ns 138 ns + (0,45 ns/pF) CL 65 130 ns 56 ns + (0,19 ns/pF) CL 45 90 ns 39 ns + (0,13 ns/pF) CL 30 60 ns 10 ns + (0,40 ns/pF) CL 12 24 ns 3 ns + (0,18 ns/pF) CL 10 20 ns 3 ns + (0,13 ns/pF) CL 40 80 ns 8 ns + (0,65 ns/pF) CL 20 40 ns 5 ns + (0,30 ns/pF) CL 15 30 ns 5 ns + (0,20 ns/pF) CL 200 80 ns 75 30 ns 15 50 20 ns Set-up time 5 25 −5 ns D → CP 10 pulse width; HIGH Hold time D → CP 5 115 10 tWCPH 15 −5 ns 15 15 −5 ns 5 50 20 ns 30 10 ns 20 5 ns 6 MHz Note: the maximum 6 16 MHz power dissipation has 9 25 MHz to be observed 10 tsu thold 15 Maximum clock pulse frequency 5 10 15 Fig.4 2.25 fmax Waveforms showing minimum clock pulse width, set-up and hold times for D to CP. Set-up and hold times are shown as positive values but may be specified as negative values. January 1995 4 see also waveforms Fig.4