TI1 BQ3055DBTR Cedv gas gauge and battery pack manager Datasheet

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bq3055
SLUSA91C – OCTOBER 2010 – REVISED OCTOBER 2015
bq3055 CEDV Gas Gauge and Battery Pack Manager for 2-Series,
3-Series, and 4-Series Li-Ion Batteries
1 Features
3 Description
•
The bq3055 device is a fully integrated, single-chip,
pack-based solution that provides a rich array of
features for gas gauging, protection, and
authentication for 2-series, 3-series, and 4-series cell
Li-Ion and Li-Polymer battery packs.
1
•
•
•
•
•
•
•
•
•
Fully Integrated 2-Series, 3-Series, and 4-Series
Li-Ion or Li-Polymer Cell Battery Pack Manager
and Protection
Advanced Compensated End-of-Discharge
Voltage (CEDV) Gauging
High-Side N-CH Protection FET Drive
Integrated Cell Balancing
Low-Power Modes
– Low Power: < 180 µA
– Sleep < 76 µA
Full Array of Programmable Protection Features
– Voltage
– Current
– Temperature
Sophisticated Charge Algorithms
– JEITA
– Enhanced Charging
– Adaptive Charging
Supports Two-Wire SMBus v1.1 Interface
SHA-1 Authentication
Compact Package: 30-Lead TSSOP
Using its integrated high-performance analog
peripherals, the bq3055 device measures and
maintains an accurate record of available capacity,
voltage, current, temperature, and other critical
parameters in Li-Ion or Li-Polymer batteries, and
reports this information to the system host controller
over an SMBus v1.1 compatible interface.
The bq3055 provides software-based 1st-level and
2nd-level
safety
protection
for
overvoltage,
undervoltage, overtemperature, and overcharge
conditions, as well as hardware-based protection for
overcurrent in discharge and short circuit in charge
and discharge conditions.
SHA-1 authentication with secure memory for
authentication keys enables identification of genuine
battery packs beyond any doubt.
The compact 30-lead TSSOP package minimizes
solution cost and size for smart batteries while
providing maximum functionality and safety for
battery gauging applications.
2 Applications
•
•
•
Device Information(1)
Notebook and Netbook PCs
Medical and Test Equipment
Portable Instrumentation
PART NUMBER
bq3055
PACKAGE
TSSOP (30)
BODY SIZE (NOM)
7.80 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
DSG
VCC
CHG
BAT
FUSE
PACK+
PACK
PCHG
VC1
RBI
CD
VH
VC2
OUT
VDD
REG25
nd
2
VM
Level
Protector
VC3
REG33
VL
SMBD
VC4
GND
SMBD
VB
SMBC
TEST
SMBC
PRES
SRN
TS2
SRP
TS1
PRES
VSS
PACK -
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq3055
SLUSA91C – OCTOBER 2010 – REVISED OCTOBER 2015
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
6.20
6.21
6.22
6.23
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics: Supply Current................. 5
Power-On Reset (POR) ............................................ 6
Wake From Sleep ..................................................... 6
RBI RAM Backup ...................................................... 6
3.3-V Regulator ......................................................... 6
2.5-V Regulator ....................................................... 7
PRES, SMBD, SMBC ............................................. 7
CHG, DSG FET Drive ............................................. 7
PCHG FET Drive .................................................... 8
FUSE....................................................................... 8
Coulomb Counter .................................................... 8
VC1, VC2, VC3, VC4 .............................................. 8
TS1, TS2 ................................................................. 9
Internal Temperature Sensor .................................. 9
Internal Thermal Shutdown..................................... 9
High-Frequency Oscillator....................................... 9
Low-Frequency Oscillator ..................................... 10
Internal Voltage Reference ................................... 10
Flash ..................................................................... 10
6.24
6.25
6.26
6.27
6.28
6.29
OCD Current Protection........................................
SCD1 Current Protection ......................................
SCD2 Current Protection ......................................
SCC Current Protection ........................................
SBS Timing Requirements....................................
Typical Characteristics ..........................................
10
11
11
11
12
13
7
Parameter Measurement Information ................ 14
8
Detailed Description ............................................ 15
7.1 Battery Parameter Measurements .......................... 14
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
17
17
18
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application .................................................. 19
9.3 System Example ..................................................... 30
10 Power Supply Recommendations ..................... 31
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 31
12 Device and Documentation Support ................. 32
12.1
12.2
12.3
12.4
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Glossary ................................................................
32
32
32
32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2013) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section,
Community Resources section, and Mechanical, Packaging, and Orderable Information section ....................................... 1
•
Changed SRP, SRN absolute maximum values ................................................................................................................... 4
Changes from Revision A (June 2011) to Revision B
•
2
Page
Changed Electrical Characteristic for ICC Shutdown............................................................................................................... 5
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5 Pin Configuration and Functions
DBT Package
30-Pin TSSOP
Top View
CHG
1
30
DSG
BAT
2
29
PACK
VC1
3
28
PCHG
VC2
4
27
VCC
VC3
5
26
FUSE
VC4
6
25
TEST
VSS
7
24
REG33
TS1
8
23
VSS
SRP
9
22
REG25
SRN
10
21
RBI
TS2
11
20
NC
¯¯¯¯¯
PRES
12
19
NC
SMBD
13
18
NC
NC
14
17
NC
SMBC
15
16
NC
Pin Functions
PIN
(1)
NAME
NO.
TYPE (1)
DESCRIPTION
BAT
2
P
Alternate power source
CHG
1
O
Charge N-FET gate drive
DSG
30
O
Discharge N-FET gate drive
FUSE
26
O
Fuse drive
NC
14
—
Not internally connected. Connect to VSS.
NC
16
—
Not internally connected. Connect to VSS.
NC
17
—
Not internally connected. Connect to VSS.
NC
18
—
Not internally connected. Connect to VSS.
NC
19
—
Not internally connected. Connect to VSS.
NC
20
—
Not internally connected. Connect to VSS.
PACK
29
P
Alternate power source
PCHG
28
I/OD
PRES
12
I
Host system present input
RBI
21
P
RAM backup
REG25
22
P
2.5-V regulator output
REG33
24
P
3.3-V regulator output
SMBC
15
I/OD
SMBus v1.1 clock line
SMBD
13
I/OD
SMBus v1.1 data line
SRN
10
AI
Differential Coulomb Counter input
Precharge P-FET gate drive
SRP
9
AI
Differential Coulomb Counter input
TEST
25
—
Test pin, connect to VSS through 2-kΩ resistor.
TS1
8
AI
Temperature sensor 1 thermistor input
TS2
11
AI
Temperature sensor 2 thermistor input
P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output
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Pin Functions (continued)
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
VC1
3
I
Sense input for positive voltage of top most cell in stack and cell balancing input for top most
cell in stack
VC2
4
I
Sense input for positive voltage of third lowest cell in stack and cell balancing input for third
lowest cell in stack
VC3
5
I
Sense input for positive voltage of second lowest cell in stack and cell balancing input for
second lowest cell in stack
VC4
6
I
Sense input for positive voltage of lowest cell in stack and cell balancing input for lowest cell in
stack
VCC
27
P
Power supply voltage
VSS
7
P
Device ground
VSS
23
P
Device ground
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VMAX
Input voltage, VIN
MIN
MAX
UNIT
–0.3
34
V
VC1, BAT
VVC2 – 0.3
VVC2 + 8.5 V
or 34 V,
whichever is lower
VC2
VVC3 – 0.3
VVC3 + 8.5 V
VC3
VVC4 – 0.3
VVC4 + 8.5 V
VC4
VSRP – 0.3
VSRP + 8.5 V
–0.5
0.5
VCC, TEST, PACK w.r.t. VSS
SRP, SRN
SMBC, SMBD
VSS – 0.3
6.0
–0.3 V
VREG25 + 0.3 V
DSG
–0.3
VPACK + 20 V or
VSS + 34 V,
whichever is lower
CHG
–0.3
VBAT + 20 V or
VSS + 34 V,
whichever is lower
FUSE
–0.3
34
RBI, REG25
–0.3
2.75
REG33
–0.3
5.0
TS1, TS2, PRES
Output voltage, VO
Maximum VSS current, ISS
50
Current for cell balancing, ICB
10
Functional Temperature, TFUNC
–40
Lead temperature (soldering, 10 s), TSOLDER
Storage temperature, Tstg
(1)
4
–65
V
V
mA
110
°C
300
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
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6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
Electrostatic
discharge
All pins except
pins 3 to 6
±2000
Pins 3 to 6
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
(1)
(2)
UNIT
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
MIN
Supply voltage
MAX
3.8
VVC2 + 5
3
5.5
VC1, BAT
VVC2
VVC2 + 5
VC2
VVC3
VVC3 + 5
VC3
VVC4
VVC4 + 5
VC4
VSRP
VSRP + 5
0
5
Start up voltage at PACK
Input voltage range
UNIT
25
BAT
VSTARTUP
VIN
NOM
VCC, PACK
VCn – VC(n+1), (n=1, 2, 3, 4)
PACK
V
V
V
25
SRP to SRN
–0.2
0.2
CREG33
External 3.3-V REG
capacitor
1
µF
CREG25
External 2.5-V REG
capacitor
1
µF
TOPR
Operating temperature
–40
85
°C
6.4 Thermal Information
bq3055
THERMAL METRIC (1)
TSSOP (DBT)
UNIT
30 PINS
RθJA
Junction-to-ambient thermal resistance
73.1
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
17.5
°C/W
RθJB
Junction-to-board thermal resistance
34.5
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
30.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics: Supply Current
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
Normal
ICC
Sleep
TEST CONDITIONS
MIN
TYP
CHG on, DSG on, no Flash write
410
CHG on, DSG on, no SBS
communication
160
CHG off, DSG off, no SBS
communication
80
Shutdown
MAX
UNIT
µA
3.7
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6.6 Power-On Reset (POR)
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
MIN
TYP
MAX
VIT–
Negative-going voltage input
PARAMETER
At REG25
TEST CONDITIONS
1.9
2
2.1
UNIT
V
VHYS
POR Hysteresis
At REG25
65
125
165
mV
6.7 Wake From Sleep
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
VWAKE
VWAKE Threshold
VWAKE_TCO
Temperature drift of VWAKE
accuracy
tWAKE
Time from application of current and
wake of bq3055
MIN
TYP
MAX
VWAKE
TEST CONDITIONS
0.2
1.2
2
VWAKE
0.4
2.4
3.6
VWAKE
2
5
6.8
VWAKE
5.3
10
13
0.5%
0.2
UNIT
mV
°C
1
ms
6.8 RBI RAM Backup
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VRBI > V(RBI)MIN, VCC < VIT
I(RBI)
RBI data-retention input current
V(RBI)
RBI data-retention voltage
TYP
MAX
20
1100
VRBI > V(RBI)MIN, VCC < VIT,
TA= 0°C to 70°C
500
1
UNIT
nA
V
6.9 3.3-V Regulator
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
VREG33
Regulator output voltage
TEST CONDITIONS
MIN
TYP
MAX
3.8 V < VCC or BAT ≤ 5 V,
ICC ≤4 mA
2.4
5V < VCC or BAT ≤ 6.8 V,
ICC ≤13 mA
3.1
3.3
3.5
6.8 V < VCC or BAT ≤ 20 V,
ICC ≤ 30 mA
3.1
3.3
3.5
UNIT
3.5
IREG33
Regulator output current
ΔV(VDDTEMP)
Regulator output change with
temperature
VCC or BAT = 14.4 V, IREG33 = 2 mA
0.2%
ΔV(VDDLINE)
Line regulation
VCC or BAT = 14.4 V, IREG33 = 2 mA
1
13
mV
ΔV(VDDLOAD)
Load regulation
VCC or BAT = 14.4 V, IREG33 = 2 mA
5
18
mV
I(REG33MAX)
6
Current limit
2
V
mA
VCC or BAT = 14.4 V, VREG33 = 3 V
70
VCC or BAT = 14.4 V, VREG33 = 0 V
33
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6.10 2.5-V Regulator
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.5
2.55
V
Regulator output voltage
IREG25
Regulator output current
ΔV(VDDTEMP)
Regulator output change with
temperature
VCC or BAT = 14.4 V, IREG25 = 2 mA
0.25%
ΔV(VDDLINE)
Line regulation
VCC or BAT = 14.4 V, IREG25 = 2 mA
1
4
mV
ΔV(VDDLOAD)
Load regulation
VCC or BAT = 14.4 V, IREG25 = 2 mA
20
40
mV
I(REG33MAX)
Current limit
IREG25 = 10 mA
2.35
VREG25
3
mA
VCC or BAT = 14.4 V, VREG25 = 2.3 V
65
VCC or BAT = 14.4 V, VREG25 = 0 V
23
mA
6.11 PRES, SMBD, SMBC
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIH
High-level input
PRES, SMBD, SMBC
VIL
Low-level input
PRES, SMBD, SMBC
VOL
Low-level output voltage
SMBD, SMBC
CIN
Input capacitance
PRES, SMBD, SMBC
ILKG
Input leakage current
PRES, SMBD, SMBC
IWPU
Weak pullup current
PRES, VOH = VREG25 – 0.5 V
RPD(SMBx)
SMBC, SMBD pulldown
TA = –40 to 100˚C
MIN
TYP
MAX
UNIT
2.0
V
0.8
V
0.4
V
5
60
550
775
pF
1
μA
120
μA
1000
kΩ
6.12 CHG, DSG FET Drive
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
V(FETON)
V(FETOFF)
tr
tf
Output voltage, charge, and
discharge FETs on
Output voltage, charge and
discharge FETs off
Rise time
Fall time
MIN
TYP
MAX
VO(FETONDSG) = V(DSG) – VPACK, VGS
connect 10 MΩ, VCC 3.8 V to 8.4 V
TEST CONDITIONS
8
9.7
12
VO(FETONDSG) = V(DSG) – VPACK, VGS
connect 10 MΩ, VCC > 8.4 V
9
11
12
VO(FETONCHG) = V(CHG) – VBAT, VGS
connect 10 MΩ, VCC 3.8 V to 8.4 V
8
9.7
12
VO(FETONCHG) = V(CHG) – VBAT, VGS
connect 10 MΩ, VCC > 8.4 V
9
11
12
V
VO(FETOFFDSG) = V(DSG) – VPACK
–0.4
0.4
VO(FETOFFCHG) = V(CHG) – VBAT
–0.4
0.4
CL= 4700 pF
RG= 5.1 kΩ
VCC < 8.4
VDSG: VBAT to VBAT + 4 V
VCHG: VPACK to VPACK + 4 V
800
CL = 4700 pF
RG = 5.1 kΩ
VCC > 8.4
VDSG: VBAT to VBAT + 4 V
VCHG: VPACK to VPACK + 4 V
200
500
80
200
CL = 4700 pF
RG = 5.1 kΩ
VDSG: VBAT + VO(FETONDSG) to VBAT
+1V
VCHG: VPACK + VO(FETONCHG) to
VPACK + 1 V
UNIT
1400
μs
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6.13 PCHG FET Drive
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
VPU_PCHG
PCHG pullup voltage
VOL_PCHG
PCHG output voltage low
TEST CONDITIONS
IOL = 1 mA
MIN
TYP
MAX
UNIT
VCC
V
0.3
V
6.14 FUSE
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
VOH(FUSE)
High-level FUSE output
VIH(FUSE)
Weak pullup current in off state (1)
tR(FUSE)
FUSE output rise time
ZO(FUSE)
FUSE output impedance
(1)
TEST CONDITIONS
MIN
VCC = 3.8 V to 9 V
2.4
VCC = 9 V to 25 V
7
TYP
MAX
8.5
8
9
2.8
V
V
100
CL = 1 nF, VCC = 9 V to 25 V,
VOH(FUSE) = 0 V to 5 V
UNIT
nA
5
20
μs
2
5
kΩ
Verified by design. Not production tested.
6.15 Coulomb Counter
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input voltage range
SRP – SRN
Conversion time
Single conversion
Resolution (no missing codes)
MIN
TYP
–0.20
MAX
0.25
250
Single conversion, signed
Offset error
Post calibrated
Full-scale error
Bits
15
Bits
10
Offset error drift
–0.8%
µV
0.3
0.5
0.2%
0.8%
Full-scale error drift
150
Effective input resistance
V
ms
16
Effective resolution
UNIT
2.5
µV/°C
PPM/°C
mΩ
6.16 VC1, VC2, VC3, VC4
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
VIN
TEST CONDITIONS
Input voltage range
VC4 – VC3, VC3 – VC2, VC2 –
VC1, VC1 – VSS
Conversion time
Single conversion
Resolution (no missing codes)
R(BAL)
8
MIN
TYP
–0.20
MAX
8
32
V
ms
16
Bits
15
Bits
Effective resolution
Single conversion, signed
RDS(ON) for internal FET at VDS >
2V
VDS = VC4 – VC3, VC3 – VC2,
VC2 – VC1, VC1 – VSS
200
310
430
RDS(ON) for internal FET at VDS >
4V
VDS = VC4 – VC3, VC3 – VC2,
VC2 – VC1, VC1 – VSS
60
125
230
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UNIT
Ω
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6.17 TS1, TS2
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
R
Internal pullup resistor
RDRIFT
Internal pullup resistor drift from
25°C
RPAD
Internal pin pad resistance
Input voltage range
TEST CONDITIONS
MIN
TYP
MAX
16.5
17.5
19
KΩ
200
PPM/°C
Ω
84
TS1 – VSS, TS2 – VSS
0.8 ×
–0.20
Conversion time
VIN
UNIT
V
VREG25
16
Resolution (no missing codes)
16
Effective resolution
11
ms
Bits
12
Bits
6.18 Internal Temperature Sensor
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Temperature sensor voltage
V(TEMP)
MIN
TYP
MAX
UNIT
–1.9
–2
–2.1
mV/°C
Conversion time
16
Resolution (no missing codes)
16
Effective resolution
11
ms
Bits
12
Bits
6.19 Internal Thermal Shutdown
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
TMAX2
Maximum REG33 temperature
TRECOVER
Recovery hysteresis temperature
tPROTECT
Protection time
TEST CONDITIONS
MIN
TYP
125
MAX
UNIT
175
°C
10
°C
5
µs
6.20 High-Frequency Oscillator
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
f(OSC)
f(EIO)
Frequency error (1) (2)
t(SXO)
Start-up time (3)
(1)
(2)
(3)
TEST CONDITIONS
MIN
Operating frequency of CPU Clock
TYP
MAX
4.194
MHz
TA = –20°C to 70°C
–2%
±0.25%
2%
TA = –40°C to 85°C
–3%
±0.25%
3%
3
6
TA = –25°C to 85°C
UNIT
ms
The frequency error is measured from 4.194 MHz.
The frequency drift is included and measured from the trimmed frequency at VREG25 = 2.5 V, TA = 25°C.
The start-up time is defined as the time it takes for the oscillator output frequency to be ±3% when the device is already powered.
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6.21 Low-Frequency Oscillator
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
f(LOSC)
Operating frequency
f(LEIO)
Frequency error (1) (2)
t(LSXO)
Start-up time (3)
(1)
(2)
(3)
TEST CONDITIONS
MIN
TYP
MAX
32.768
kHz
TA = –20°C to 70°C
–1.5%
±0.25%
1.5%
TA = –40°C to 85°C
–2.5%
±0.25%
2.5%
TA = –25°C to 85°C
UNIT
100
μs
The frequency drift is included and measured from the trimmed frequency at VCC = 2.5 V, TA = 25°C.
The frequency error is measured from 32.768 kHz.
The start-up time is defined as the time it takes for the oscillator output frequency to be ±3%.
6.22 Internal Voltage Reference
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
VREF
TEST CONDITIONS
Internal reference voltage
VREF_DRIFT
Internal reference voltage drift
MIN
TYP
MAX
UNIT
1.215
1.225
1.230
V
TA = –25°C to 85°C
±80
TA = 0°C to 60°C
±50
PPM/°C
6.23 Flash
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER (1)
TEST CONDITIONS
Data retention
Flash programming write-cycles
MIN
TYP
MAX
10
Data Flash
Instruction Flash
UNIT
Year
20k
Cycle
1k
ICC(PROG_DF)
Data Flash-write supply current
TA = –40°C to 85°C
3
4
mA
ICC(ERASE_DF)
Data Flash-erase supply current
TA = –40°C to 85°C
3
18
mA
(1)
Verified by design. Not production tested.
6.24 OCD Current Protection
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
V(OCD)
OCD detection threshold voltage
range, typical
RSNS = 0
50
200
RSNS = 1
25
100
ΔV(OCDT)
OCD detection threshold voltage
program step
RSNS = 0
10
RSNS = 1
5
V(OFFSET)
OCD offset
V(Scale_Err)
OCD scale error
t(OCDD)
Overcurrent in discharge delay
t(OCDD_STEP)
OCDD step options
t(DETECT)
Current fault detect time
tACC
Overcurrent and short-circuit delay
Accuracy of typical delay time
time accuracy
10
–10
10
10%
31
2
VSRP – SRN = VTHRESH + 12.5 mV
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ms
160
–20%
mV
mV
–10%
1
UNIT
µs
20%
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6.25 SCD1 Current Protection
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
V(SDC1)
SCD1 detection threshold
voltage range, typical
RSNS = 0
ΔV(SCD1T)
SCD1 detection threshold
voltage program step
RSNS = 0
50
RSNS = 1
25
V(OFFSET)
SCD1 offset
V(Scale_Err)
SCD1 scale error
MAX
100
450
RSNS = 1
50
225
–10
10
–10%
10%
0
915
AFE.STATE_CNTL[SCDDx2] = 1
0
1830
Short-circuit in discharge delay
t(SCD1D_STEP)
SCD1D step options
t(DETECT)
Current fault detect time
VSRP – SRN = VTHRESH + 12.5 mV
tACC
Overcurrent and short-circuit
delay time accuracy
Accuracy of typical delay time
AFE.STATE_CNTL[SCDDx2] = 0
61
AFE.STATE_CNTL[SCDDx2] = 1
122
mV
mV
AFE.STATE_CNTL[SCDDx2] = 0
t(SCD1D)
UNIT
mV
µs
µs
160
–20%
µs
20%
6.26 SCD2 Current Protection
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
V(SDC2)
SCD2 detection threshold
voltage range, typical
RSNS = 0
ΔV(SCD2T)
SCD2 detection threshold
voltage program step
RSNS = 0
50
RSNS = 1
25
V(OFFSET)
SCD2 offset
V(Scale_Err)
SCD2 scale error
t(SCD1D)
Short-circuit in discharge delay
t(SCD2D_STEP)
SCD2D step options
t(DETECT)
Current fault detect time
VSRP – SRN = VTHRESH + 12.5 mV
tACC
Overcurrent and short-circuit
delay time accuracy
Accuracy of typical delay time
MAX
100
450
RSNS = 1
50
225
–10
10
10%
AFE.STATE_CNTL[SCDDx2] = 0
0
458
AFE.STATE_CNTL[SCDDx2] = 1
0
915
30.5
AFE.STATE_CNTL[SCDDx2] = 1
61
mV
mV
–10%
AFE.STATE_CNTL[SCDDx2] = 0
UNIT
mV
µs
µs
160
–20%
µs
20%
6.27 SCC Current Protection
Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V
to 25 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
V(SCCT)
SCC detection threshold voltage
range, typical
RSNS = 0
–100
–300
RSNS = 1
–50
–225
ΔV(SCCDT)
SCC detection threshold voltage
program step
RSNS = 0
–50
RSNS = 1
–25
V(OFFSET)
SCC offset
V(Scale_Err)
SCC scale error
t(SCCD)
Short-circuit in charge delay
t(SCCD_STEP)
SCCD step options
t(DETECT)
Current fault detect time
VSRP – SRN = VTHRESH + 12.5 mV
tACC
Overcurrent and short-circuit
delay time accuracy
Accuracy of typical delay time
UNIT
mV
–10
10
–10%
10%
0
915
61
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20%
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160
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6.28 SBS Timing Requirements
MIN
fSMB
TYP
UNIT
100
kHz
Slave mode, SMBC 50% duty cycle
fMAS
SMBus master clock frequency
Master mode, no clock low slave
extend
tBUF
Bus free time between start and stop
4.7
µs
tHD:STA
Hold time after (repeated) start
4.0
µs
tSU:STA
Repeated start setup time
4.7
µs
tSU:STO
Stop setup time
4.0
µs
tHD:DAT
Data hold time
300
ns
tSU:DAT
Data setup time
250
ns
See
10
MAX
SMBus operating frequency
51.2
(1)
tTIMEOUT
Error signal/detect
tLOW
Clock low period
tHIGH
Clock high period
See (2)
tHIGH
Clock high period
See (2)
tLOW:SEXT
Cumulative clock low slave
extend time
tLOW:MEXT
kHz
25
35
4.7
ms
µs
Disabled
50
µs
See (3)
25
ms
Cumulative clock low master
extend time
See (4)
10
ms
tF
Clock/data fall time
See (5)
300
ns
tR
Clock/data rise time
See (6)
1000
ns
(1)
(2)
(3)
(4)
(5)
(6)
4.0
The bq3055 times out when any clock low exceeds tTIMEOUT.
tHIGH, Max, is the minimum bus idle time. SMBC = 1 for t > 50 µs causes reset of any transaction involving bq3055 that is in progress.
This specification is valid when the THIGH_VAL=0. If THIGH_VAL = 1, then the value of THIGH is set by THIGH_1,2 and the time-out is
not SMBus standard.
tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
Rise time tR = VILMAX – 0.15) to (VIHMIN + 0.15)
Fall time tF = 0.9 VDD to (VILMAX – 0.15)
tR
tSU(STOP)
tF
tF
tDH(STA)
T(BUF)
SMBC
tW(H)
SMBC
SMBD
tR
tW(L)
SMBD
P
S
tHD(DATA)
tSU(DATA)
tSU(STA)
t(TIMEOUT)
SMBC
SMBC
SMBD
SMBD
S
Figure 1. SMBus Timing Diagram
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6.29 Typical Characteristics
0.1
0.10
0.05
0.00
Drift (uV/ƒC)
Drift (uV/ƒC)
0.0
±0.1
±0.2
±0.05
±0.10
±0.15
±0.20
±0.25
±0.3
±40
±20
0
20
40
60
80
±0.30
±40.0
100
Temperature (ƒC)
Figure 2. CC Input Offset Drift Overtemperature
±20.0
0.0
20.0
40.0
60.0
80.0
Temperature (ƒC)
C004
C005
Figure 3. ADC Input Offset Drift Overtemperature
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7 Parameter Measurement Information
7.1 Battery Parameter Measurements
7.1.1 Charge and Discharge Counting
The bq3055 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a
second delta-sigma ADC for individual cell and battery voltage and temperature measurement.
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolar
signals from –0.25 V to 0.25 V. The bq3055 detects charge activity when VSR = V(SRP) – V(SRN) is positive, and
discharge activity when VSR = V(SRP) – V(SRN) is negative. The bq3055 continuously integrates the signal over
time, using an internal counter. The fundamental rate of the counter is 0.65 nVh.
7.1.2 Voltage
The bq3055 updates the individual series cell voltages at 0.25-second intervals. The internal ADC of the bq3055
measures the voltage, and scales and calibrates it appropriately. This data is also used to calculate the
impedance of the cell for the CEDV gas-gauging.
7.1.3 Current
The bq3055 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current
using a 5-mΩ to 20-mΩ typ. sense resistor.
7.1.4 Auto Calibration
The bq3055 provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for
maximum charge measurement accuracy. The bq3055 performs auto-calibration when the SMBus lines stay low
continuously for a minimum of 5 s.
7.1.5 Temperature
The bq3055 has an internal temperature sensor and inputs for two external temperature sensors. All three
temperature sensor options are individually enabled and configured for cell or FET temperature. Two
configurable thermistor models are provided to allow the monitoring of cell temperature in addition to FET
temperature, which may be of a higher temperature type.
7.1.6 Communications
The bq3055 uses SMBus v1.1 with Master Mode and packet error checking (PEC) options per the SBS
specification.
7.1.6.1 SMBus On and Off State
The bq3055 detects an SMBus off state when SMBC and SMBD are low for two or more seconds. Clearing this
state requires that either SMBC or SMBD transition high. The communication bus will resume activity within
1 ms.
7.1.6.2 SBS Commands
See the bq3055 Technical Reference Manual (SLUU440) for further details.
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8 Detailed Description
8.1 Overview
The bq3055 device measures the voltage, temperature, and current to determine battery capacity and state-ofcharge (SOC). The bq3050 monitors charge and discharge activity by sensing the voltage across a small value
resistor (5 mΩ to 20 mΩ, typical) between the SRP and SRN pins and in series with the battery. By integrating
charge passing through the battery, the battery’s SOC is adjusted during battery charge or discharge.
Measurements of OCV and charge integration determine chemical SOC.
The Qmax values are taken from a cell manufacturers' data sheet multiplied by the number of parallel cells, and
is also used for the value in Design Capacity. It uses the OCV and Qmax value to determine StateOfCharge()
on battery insertion, device reset, or on command. The FullChargeCapacity() is reported as the learned capacity
available from full charge until Voltage() reaches the EDV0 threshold. As Voltage() falls below the Shutdown
Voltage for Shutdown Time and has been out of SHUTDOWN mode for at least Shutdown Time, the PF
Flags1 () [VSHUT] bit is set. For additional details, see bq3055 Technical Reference Manual (SLUU440).
Fuel gauging is derived from the Compensated End of Discharge Voltage (CEDV) method, which uses a
mathematical model to correlate remaining state of charge (RSOC) and voltage near to the end of discharge
state. This requires a full-discharge cycle for a single-point FCC update. The implementation models cell voltage
(OCV) as a function of battery SOC, temperature, and current. The impedance is also a function of SOC and
temperature, which can be satisfied by using seven parameters: EMF, C0, R0, T0, R1, TC, and C1.
8.1.1 Configuration
8.1.1.1 Oscillator Function
The bq3055 fully integrates the system oscillators and does not require any external components to support this
feature.
8.1.1.2 System Present Operation
The bq3055 checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external system, the
bq3055 detects this as system present.
8.1.1.3 2-, 3-, or 4-Cell Configuration
In a 2-cell configuration, VC1 is shorted to VC2 and VC3. In a 3-cell configuration, VC1 is shorted to VC2.
8.1.1.4 Cell Balancing
The device supports cell balancing by bypassing the current of each cell during charging or at rest. If the device's
internal bypass is used, up to 10 mA can be bypassed and multiple cells can be bypassed at the same time.
Higher cell balance current can be achieved by using an external cell balancing circuit. In external cell balancing
mode, only one cell at a time can be balanced.
The cell balancing algorithm determines the amount of charge needed to be bypassed to balance the capacity of
all cells.
8.1.1.4.1 Internal Cell Balancing
When internal cell balancing is configured, the cell balance current is defined by the external resistor RVC at the
VCx input. See Figure 4.
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Overview (continued)
RVC
VC1
RVC
VC2
RVC
VC3
RVC
VC4
VSS
Figure 4. Internal Cell Balancing with RVC
8.1.1.4.2 External Cell Balancing
When external cell balancing is configured, the cell balance current is defined by RB. See Figure 5. Only one cell
at a time can be balanced.
RVC
VC1
RVC
VC2
RVC
VC3
RVC
VC4
RB
RB
RB
RB
VSS
Figure 5. External Cell Balancing with RB
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Power Mode
Control
DSG
F USE
Fuse
Drive
CH G
GPOD
C e ll Selection
Multiplexer and
Cell Balance FETs
3.3-V LDO,
POR
GPOD
Drive
VC3
VC4
VC1
VC2
VSS
REG 33
BAT
VCC
PACK
8.2 Functional Block Diagram
N- CH
FET
Drive
High Voltage
Translation
Overcurrent
Comparator
Dela y
Wat c hdog
Timer
Short C ircuit
Comparators
AFE Control and Conf i g
SMBC
SMBD
TS1
TS2
PRES
V CC
RBI
MRST
Power
Regulation
AND
Management
VSS
REG25
32 kHz
8
RAx
8
RCx
Oscillator
INT
I nput / Out put
2
Int errupt
Cont ro lle r
EV
Syst em
Clocks
2x INT
EV
Reset *
EV
Analog Front End
Delta- Sigma ADC
AND
Int egrating C oulomb
Counter
Data(8-bit)
Cool RISC
CPU
Wake Comparator
DMAddr (1 6-bit)
SRP
SRN
AD0-7
SystemI /O (13-bit)
PMAddr
(15-bit)
SMBC
SMBD
PMInst
(22-b it)
Program Memory
FLASH
AND
Mask ROM
Data Memory
SRAM
AND
FLASH
Communicat ions
SMBus
Peripheral
Timer and PWM
8.3 Feature Description
8.3.1 Primary (1st Level) Safety Features
The bq3055 supports a wide range of battery and system protection features that can easily be configured. The
primary safety features include:
•
•
•
•
•
Cell Overvoltage and Undervoltage Protection
Charge and Discharge Overcurrent
Short-Circuit
Charge and Discharge Overtemperature
AFE Watchdog
8.3.2 Secondary (2nd Level) Safety Features
The secondary safety features of the bq3055 can be used to indicate more serious faults through the FUSE pin.
This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or
discharging. The secondary safety protection features include:
• Safety Overvoltage
• Safety Overcurrent in Charge and Discharge
• Safety Overtemperature in Charge and Discharge
• Charge FET, Discharge FET, and Precharge FET Faults
• Cell Imbalance Detection
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Feature Description (continued)
•
•
•
Fuse Blow by Secondary Voltage Protection IC
AFE Register Integrity Fault (AFE_P)
AFE Communication Fault (AFE_C)
8.3.3 Charge Control Features
The bq3055 charge control features include:
•
•
•
•
•
•
•
Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active
temperature range
Handles more complex charging profiles. Allows for splitting the standard temperature range into two subranges and allows for varying the charging current according to the cell voltage
Reports the appropriate charging current needed for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts
Reduce the charge difference of the battery cells in fully charged state of the battery pack gradually using a
voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for cell balancing to
be active. This prevents fully charged cells from overcharging and causing excessive degradation and also
increases the usable pack energy by preventing premature charge termination.
Supports precharging and zero-volt charging
Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range
Reports charging fault and also indicate charge status through charge and discharge alarms
8.3.4 Gas Gauging
The bq3055 uses the CEDV algorithm to measure and calculate the available capacity in battery cells. The
bq3055 accumulates a measure of charge and discharge currents and compensates the charge current
measurement for the temperature and state-of-charge of the battery. The bq3055 estimates self-discharge of the
battery and also adjusts the self-discharge estimation based on temperature. See the bq3055 Technical
Reference Manual (SLUU440) for further details.
8.3.5 Lifetime Data Logging Features
The bq3055 offers limited lifetime data logging for the following critical battery parameters:
• Lifetime Maximum Temperature
• Lifetime Minimum Temperature
• Lifetime Maximum Battery Cell Voltage
• Lifetime Minimum Battery Cell Voltage
8.3.6 Authentication
•
•
The bq3055 supports authentication by the host using SHA-1.
SHA-1 authentication by the gas gauge is required for unsealing and full access.
8.4 Device Functional Modes
The bq3055 supports three power modes to reduce power consumption:
• In NORMAL Mode, the bq3055 performs measurements, calculations, protection decisions, and data updates
in 0.25-s intervals. Between these intervals, the bq3055 is in a reduced power stage.
• In SLEEP Mode, the bq3055 performs measurements, calculations, protection decisions, and data updates in
adjustable time intervals. Between these intervals, the bq3055 is in a reduced power stage. The bq3055 has
a wake function that enables exit from Sleep mode when current flow or failure is detected.
• In SHUTDOWN Mode, the bq3055 is completely disabled.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The bq3055 gas gauge is a primary protection device that can be used with a 2-series, 3-series, or 4-series LiIon or Li-Polymer battery pack. To implement and design a comprehensive set of parameters for a specific
battery pack, the user needs the bqEVSW tool, which is a graphical user-interface tool installed on a PC during
development. The firmware installed in the product has default values, which are summarized in the bq3055
Technical Reference Manual (SLUU440). Using the bqEVSW tool, these default values can be changed to cater
to specific application requirements during development once the system parameters are known, such as faulttrigger thresholds for protection, enable or disable certain features for operation, configuration of cells, and more.
9.2 Typical Application
In a typical application, the bq3055 is typically paired with a 2nd-level overvoltage protection device to provide an
independent level of voltage protection. Figure 6 shows a typical application.
Figure 6. Application Schematic
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Typical Application (continued)
9.2.1 Design Requirements
For the bq3055 design example, use the parameters in Table 1 as input parameters.
Table 1. Requirements
DESIGN PARAMETER
VALUE OR STATE
Cell Configuration
3s2p (4-series with 1 Parallel)
Design Capacity
4400 mAh
Device Chemistry
Chem ID 100 (LiCoO2/graphitized carbon)
Cell Overvoltage (per cell)
4500 mV
Cell Undervoltage (per cell)
2200 mV
1st Tier Overcurrent in CHARGE Mode
6000 mA
1st Tier Overcurrent in DISCHARGE Mode
–6000 mA
AFE Overcurrent in CHARGE Mode
0.120 V/Rsense across SRP, SRN
AFE Short-Circuit in DISCHARGE Mode
0.450 V/Rsense across SRP, SRN
AFE Short-Circuit in CHARGE Mode
0.250V/Rsense across SRP, SRN
Overtemperature in CHARGE Mode
55°C
Overtemperature in DISCHARGE Mode
60°C
SAFE Pin Activation Enabled
No
Safety Overvoltage (per cell)
4600 mV
Shutdown Voltage
5250 mV
Cell Balancing Enabled
Yes
Internal or External Temperature Sensor
External Enabled
SMB BROADCAST Mode
Disabled
PRES Feature Enabled
No
9.2.2 Detailed Design Procedure
9.2.2.1 High-Current Path
The high-current path begins at the PACK+ terminal of the battery pack. As charge current travels through the
pack, it finds its way through protection FETs, a chemical fuse, the lithium-ion cells and cell connections, and the
sense resistor, and then returns to the PACK– terminal. In addition, some components are placed across the
PACK+ and PACK– terminals to reduce effects from electrostatic discharge.
9.2.2.1.1 Protection FETs
The N-channel charge and discharge FETs must be selected for a given application (Figure 7). Most portable
battery applications are a good match for the CSD17308Q3. The TI CSD17308Q3 is an 47A-A, 30-V device with
Rds(on) of 8.2 mΩ when the gate drive voltage is 10 V.
If a precharge FET is used, R28 is calculated to limit the precharge current to the desired rate. Be sure to
account for the power dissipation of the series resistor. The precharge current is limited to (Vcharger – Vbat)/R28
and maximum power dissipation is (Vcharger – Vbat)2/R28.
The gates of all protection FETs are pulled to the source with a high-value resistor between the gate and source
to ensure they are turned off if the gate drive is open.
Capacitors C16 and C17 help protect the FETs during an ESD event. The use of two devices ensures normal
operation if one of them becomes shorted. To have good ESD protection, the copper trace inductance of the
capacitor leads must be designed to be as short and wide as possible. Ensure that the voltage rating of both C16
and C17 are adequate to hold off the applied voltage if one of the capacitors becomes shorted.
20
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Figure 7. bq3055 Protection FETs
9.2.2.1.2 Chemical Fuse
The chemical fuse (Sony Chemical, Uchihashi, and so forth) is ignited under command from either the bq294705
secondary voltage protection IC or from the FUSE pin of the gas gauge. Either event applies a positive voltage to
the gate of Q1, shown in Figure 8, which then sinks current from the third terminal of the fuse, causing it to ignite
and open permanently.
It is important to carefully review the fuse specifications and match the required ignition current to that available
from the N-channel FET. Ensure that the proper voltage, current, and Rds(on) ratings are used for this device.
The fuse control circuit is discussed in detail in FUSE Circuitry.
To 2nd-Level Protector
To FUSE pin
Figure 8. FUSE Circuit
9.2.2.1.3 Lithium-Ion Cell Connections
The important thing to remember about the cell connections is that high current flows through the top and bottom
connections; therefore, the voltage sense leads at these points must be made with a Kelvin connection to avoid
any errors due to a drop in the high-current copper trace. The location marked 4P in Figure 9 indicates the Kelvin
connection of the most positive battery node. The connection marked 1N is equally important. The VC5 pin (a
ground reference for cell voltage measurement), which is in the older generation devices, is not in the bq3055
device. Hence, the single-point connection at 1N to the low-current ground is needed to avoid an undesired
voltage drop through long traces while the gas gauge is measuring the bottom cell voltage.
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Figure 9. Lithium-Ion Cell Connections
9.2.2.1.4 Sense Resistor
As with the cell connections, the quality of the Kelvin connections at the sense resistor is critical. The sense
resistor must have a temperature coefficient no greater than 75 ppm to minimize current measurement drift with
temperature (Figure 10). Choose the value of the sense resistor to correspond to the available overcurrent and
short-circuit ranges of the bq3055. Select the smallest value possible to minimize the negative voltage generated
on the bq3055 VSS nodes during a short-circuit. This pin has an absolute minimum of –0.3 V. For a pack with two
parallel cylindrical cells, 10 mΩ is generally ideal. Parallel resistors can be used as long as good Kelvin sensing
is ensured.
The ground scheme of bq3055 is different from the older generation devices. In previous devices, the device
ground (or low-current ground) is connected to the SRN side of the Rsense resistor pad. The bq3055, however,
connects the low-current ground on the SRP side of the Rsense resistor pad, close to the battery 1N terminal
(see Lithium-Ion Cell Connections). This is because the bq3055 has one less VC pin (a ground reference pin
VC5) compared to the previous devices. The pin was removed and was internally combined to SRP.
R10
0.10 75 ppm
Figure 10. Sense Resistor
9.2.2.1.5 ESD Mitigation
A pair of series 0.1-μF ceramic capacitors is placed across the PACK+ and PACK– terminals to help in the
mitigation of external electrostatic discharges. The two devices in series ensure continued operation of the pack
if one of the capacitors becomes shorted.
Optionally, a tranzorb, such as the SMBJ2A, can be placed across the terminals to further improve ESD
immunity.
9.2.2.2 Gas Gauge Circuit
The Gas Gauge Circuit includes the bq3055 and its peripheral components. These components are divided into
the following groups: Differential Low-Pass Filter, Power Supply Decoupling/RBI, System Present, SMBus
Communication, FUSE circuit, and LED.
9.2.2.2.1 Differential Low-Pass Filter
As shown in Figure 11, a differential filter must precede the current sense inputs of the gas gauge. This filter
eliminates the effect of unwanted digital noise, which can cause offset in the measured current. Even the best
differential amplifier has less common-mode rejection at high frequencies. Without a filter, the amplifier input
stage may rectify a strong RF signal, which then may appear as a DC offset error.
Five percent tolerance of the components is adequate because capacitor C15 shunts C12/C13, and reduces AC
common mode arising from component mismatch. It is also proven to reduce offset and noise error by
maintaining µa symmetrical placement pattern and adding ground shielding for the differential filter network.
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R11
100 Ω
C12
0.1 µF
C15
0.1 µF
R12
100 Ω
C13
0.1 µF
Figure 11. Differential Low-Pass Filter
9.2.2.2.2 Power Supply Decoupling and RBI
Power supply decoupling is important for optimal operation of the bq3055 advanced gas gauges. As shown in
Figure 12, a single 1-μF ceramic decoupling capacitor from REG33 to VSS and REG25 to VSS must be placed
adjacent to the IC pins.
The RBI pin is used to supply backup RAM voltage during brief transient power outages. The partial reset
mechanism makes use of the RAM to restore the critical CPU registers following a temporary loss of power. A
standard 0.1-μF ceramic capacitor is connected from the RBI pin to ground, as shown in Figure 12.
Figure 12. Power Supply Decoupling
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9.2.2.2.3 System Present
The System Present signal is used to inform the gas gauge whether the pack is installed into or removed from
the system. In the host system, this pin is grounded. The PRES pin of the bq3055 is occasionally sampled to test
for system present. To save power, an internal pullup resistor is provided by the gas gauge during a brief 4-μs
sampling pulse once per second.
Because the System Present signal is part of the pack connector interface to the outside world, it must be
protected from external electrostatic discharge events. An integrated ESD protection on the PRES device pin
reduces the external protection requirement to just R25 for an 8-kV ESD contact rating (Figure 13). However, if it
is possible that the System Present signal may short to PACK+, then R18 and D3 must be included for highvoltage protection.
Figure 13. System Present ESD and Short Protection
9.2.2.2.4 SMBus Communication
Similar to the System Present pin, the SMBus clock and data pins have integrated high-voltage ESD protection
circuits that reduce the need for external Zener diode protection. When using the circuit shown in Figure 14, the
communication lines can withstand an 8-kV (contact) ESD strike. C23 and C24 are selected with a 100-pF value
to meet the SMBus specifications. If it is desirable to provide increased protection with a larger input resistor
and/or Zener diode, carefully investigate the signal quality of the SMBus signals under worst-case
communication conditions.
The SMbus clock and data lines have internal pulldowns. When the gas gauge senses that both lines are low
(such as during removal of the pack), the device performs auto-offset calibration and then goes into sleep mode
to conserve power.
24
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Figure 14. ESD Protection for SMB Communication
9.2.2.2.5 FUSE Circuitry
The FUSE pin of the bq3055 is designed to ignite the chemical fuse if one of the various safety criteria is violated
(Figure 15). The FUSE pin also monitors the state of the secondary-voltage protection IC. Q3 ignites the
chemical fuse when its gate is high. The 7-V output of the bq29705 is divided by R13 and R14, which provides
adequate gate drive for Q1 while guarding against excessive back current into the bq29705 if the FUSE signal is
high.
Using C14 is generally a good practice, especially for RFI immunity. C14 may be removed, if desired, because
the chemical fuse is a comparatively slow device and is not affected by any sub-microsecond glitches that may
come from the SAFE output during the cell connection process.
To 2nd-Level Protector
To FUSE pin
Figure 15. FUSE Circuit
When the bq3055 is commanded to ignite the chemical fuse, the FUSE pin activates to give a typical 8-V output.
The new design makes it possible to use a higher Vgs FET for Q1. This improves the robustness of the system,
as well as widens the choices for Q1.
9.2.2.2.6 PFIN Detection
As previously mentioned, the FUSE pin has a dual role on this device. When bq3055 is not commanded to ignite
the chemical fuse, the FUSE pin defaults to sense the OUT pin status of the secondary voltage protector. When
the secondary voltage protector ignites the chemical fuse, the high voltage is sensed by the FUSE pin, and the
bq3055 sets the PFIN flag accordingly.
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9.2.2.3 Secondary-Current Protection
The bq3055 provides secondary overcurrent and short-circuit protection, cell balancing, cell voltage multiplexing,
and voltage translation. The following sections examine Cell and Battery Inputs, Pack and FET Control,
Regulator Output, Temperature Output, and Cell Balancing.
9.2.2.3.1 Cell and Battery Inputs
Each cell input is conditioned with a simple RC filter, which provides ESD protection during cell connect and acts
to filter unwanted voltage transients. The resistor value allows some trade-off for cell balancing versus safety
protection.
The internal cell balancing FETs in bq3055 provide about typically 310 Ω (310 Ω with cell voltage ≥ 2 V. The cell
balancing FETs Rds-on reduced to typically 125 Ω with cell voltage ≥ 4 V), which can be used to bypass charge
current in individual cells that may be overcharged with respect to the others (Figure 16). The purpose of this
bypass path is to reduce the current into any one cell during charging to bring the series elements to the same
voltage. Series resistors placed between the input pins and the positive series element nodes control the bypass
current value. The bq3055 device is designed to take up to 10-mA cell balancing current. Series input resistors
between 100 Ω and 1 kΩ are recommended for effective cell balancing.
The BAT input uses a diode (D1) and 1-μF ceramic capacitor (C9) to isolate and decouple it from the cells in the
event of a transient dip in voltage caused by a short-circuit event.
Also, as described previously in High-Current Path, the top and bottom nodes of the cells must be sensed at the
battery connections with a Kelvin connection to prevent voltage sensing errors caused by a drop in the highcurrent PCB copper.
Figure 16. Cell and BAT Inputs
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9.2.2.3.2 External Cell Balancing
Internal cell balancing can only support up to 10 mA. External cell balancing provides another option for faster
cell balancing. For details, refer to the application note, Fast Cell Balancing Using External MOSFET (SLUA420).
9.2.2.3.3 PACK and FET Control
The PACK and VCC inputs provide power to the bq305x from the charger. The PACK input also provides a
method to measure and detect the presence of a charger. The PACK input uses a 10-KΩ resistor, whereas the
VCC input uses a diode to guard against input transients and prevents malfunction of the date driver during shortcircuit events (Figure 17).
The N-channel charge and discharge FETs are controlled with 5.1-KΩ series gate resistors, which provide a
switching time constant of a few microseconds. The 3.01-MΩ resistors ensure that the FETs are off in the event
of an open connection to the FET drivers. Q4 is provided to protect the discharge FET (Q3) in the event of a
reverse-connected charger. Without Q4, Q3 can be driven into its linear region and suffer severe damage if the
PACK+ input becomes slightly negative.
Q4 turns on in that case to protect Q3 by shorting its gate to source. To use the simple ground gate circuit, the
FET must have a low gate turnon threshold. If it is desired to use a more standard device, such as the 2N7000
as the reference schematic, the gate should be biased up to 3.3 V with a high-value resistor. The bq3055 device
uses an external P-channel, precharge FET controlled by GPOD. When selecting the external load resistor, user
should take into account the max charger voltage and the Rdson of the internal precharge FET.
Figure 17. bq3055 PACK and FET Control
9.2.2.3.4 Regulator Output
As mentioned in Power Supply Decoupling and RBI, the two low-dropout regulators in the bq3055 require
capacitive compensation on the output. The outputs must have a 1-μF ceramic capacitor placed close to the IC
terminal pins.
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9.2.2.3.5 Temperature Output
For the bq3055 device, TS1 and TS2 provide thermistor drive-under program control (Figure 18). Each pin can
be enabled with an integrated 18-kΩ (typical) linearization pullup resistor to support the use of a 10-kΩ at 25°C
(103) NTC external thermistor, such as a Mitsubishi BN35-3H103. The reference design includes two 10-kΩ
thermistors: RT1 and RT2.
Figure 18. Thermistor Drive
9.2.2.4 Secondary-Overvoltage Protection
The bq29705 provides secondary-overvoltage protection and commands the chemical fuse to ignite if any cell
exceeds the internally referenced threshold. The peripheral components are Cell Inputs and Time Delay
Capacitor.
9.2.2.4.1 Cell Inputs
An input filter is provided for each cell input. This comprises the resistors R5, R6, R7, and R9 along with
capacitors C5, C6, C7, and C8 (Figure 19). This input network is completely independent of the filter network
used as input to thebq3055. To ensure independent safety functionality, the two devices must have separate
input filters.
Because the filter capacitors are implemented differentially, a low-voltage device can be used in each case.
Figure 19. bq29705 Cell Inputs and Time-Delay Capacitor
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9.2.2.4.2 Time-Delay Capacitor
C10 sets the time delay for activation of the output after any cell exceeds the threshold voltage. The time delay is
calculated as td = 1.2 V × DelayCap (μF)/0.18 μA.
9.2.3 Application Curves
15
2.5
-2000
-10
1
1000
2.0
10
Current Error (mA)
Voltage Error (mV)
1.5
1.0
0.5
0.0
±0.5
2600
3000
3400
3800
4200
4600
±1.0
±2.5
-100
0
100
5
0
-20
0
20
40
60
85
±5
±1.5
±2.0
-1000
-1
10
2000
Cell 1 Error
Cell 3 Error
Cell 2 Error
Cell 4 Error
±10
Cell Voltage (mV)
Temperature (ƒC)
C001
C002
Figure 20. Cell Voltage Error Across Input Range at 25°C
Figure 21. Current Error vs Temperature
Temperature Error (ƒC)
15
10
5
0
±5
±10
-20
0
20
40
60
Temperature (ƒC)
85
C003
Figure 22. TSx Error vs Temperature
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9.3 System Example
0.1 μF
0.1 μF
300 Ω
1 MΩ
PACK+
3 MΩ
3 MΩ
5.1 kΩ
5.1 kΩ
DSG
BAT
VCC
20 kΩ
FUSE
20 kΩ
CHG
0.1 μF
220 kΩ
10 kΩ
0.1 μF
5.1 kΩ
10 kΩ
0.1 μF
PACK
PCHG
1 kΩ
1 μF
VC1
CD
VH
1 kΩ
RBI
100 Ω
0.1 μF
0.1 μF
VC2
OUT
0.22 μF
VDD
nd
2
VM
Level
Protector
VL
0.1 μF
1 kΩ
REG25
100 Ω
1 μF
0.1 μF
VC3
1 kΩ
REG33
1 μF
100 Ω
0.1 μF
0.1 nF
SMBD
VC4
GND
VB
1 kΩ
SMBD
100 Ω
SMBC
200 Ω
100 Ω
PRES
200 Ω
100 Ω
TEST
0.1 μF
SMBC
PRES
0.1 μF
0.1 μF
100 Ω
0.1 μF
TS2
SRN
TS1
SRP
10 kΩ
VSS
10 kΩ
2 kΩ
100 Ω
5.6 V
1 kΩ
0.1 nF
100 Ω
5 mΩ
PACK -
Figure 23. bq3055 Implementation
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10 Power Supply Recommendations
Power supply decoupling is important for optimal operation of the bq3055 Gas Gauge. A single 1.0-μF ceramic
decoupling capacitor from REG33 to VSS and REG25 to VSS must be placed adjacent to the integrated circuit
(IC) pins.
The RBI pin is used to supply backup RAM voltage during brief transient-power outages. The partial reset
mechanism makes use of RAM to restore the critical CPU registers following a temporary loss of power. A
standard 0.1-μF ceramic capacitor is connected from the RBI pin to ground.
11 Layout
11.1 Layout Guidelines
The predominant layout concern for the bq3055 is related to the coulomb counter measurement. The external
components and PCB layout surrounding the SRP and SRN pins should be carefully considered.
11.2 Layout Example
As shown in Figure 24, a differential filter must precede the current sense inputs of the gas gauge. This filter
eliminates the effect of unwanted digital noise, which can cause offset in the measured current. Even the best
differential amplifier has less common-mode rejection at high frequencies. Without a filter, the amplifier input
stage may rectify a strong RF signal, which then may appear as a DC-offset error.
Five percent tolerance of the components is adequate, because capacitor C15 shunts C12 and C13 and reduces
AC common mode arising from a component mismatch. It is important to locate C15 as close as possible to the
gas gauge pins. The other components also must be relatively close to the IC. The ground connection of C12
and C13 must be close to the IC. It is also proven to reduce offset and noise error by maintaining a symmetrical
placement pattern and adding ground shielding for the differential filter network.
Figure 24. PCB Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• bq3055 Technical Reference Manual (SLUU440)
• Fast Cell Balancing Using External MOSFET (SLUA420)
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Mar-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ3055DBT
ACTIVE
TSSOP
DBT
30
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ3055
BQ3055DBTR
ACTIVE
TSSOP
DBT
30
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ3055
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-Mar-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ3055DBTR
Package Package Pins
Type Drawing
TSSOP
DBT
30
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ3055DBTR
TSSOP
DBT
30
2000
367.0
367.0
38.0
Pack Materials-Page 2
IMPORTANT NOTICE
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