LTM9012 Quad 14-Bit, 125Msps ADC with Integrated Drivers Description Features n n n n n n n n 4-Channel Simultaneous Sampling ADC with Integrated, Fixed Gain, Differential Drivers 68.3dB SNR 78dB SFDR Low Power: 1.27W Total, 318mW per Channel 1.8V ADC Core and 3.3V Analog Input Supply Serial LVDS Outputs: 1 or 2 Bits per Channel Shutdown and Nap Modes 11.25mm × 15mm BGA Package The LTM®9012 is a 4-channel, simultaneous sampling 14-bit µModule® analog-to-digital converter (ADC) with integrated, fixed gain, differential ADC drivers. The low noise amplifiers are suitable for single-ended drive and pulse train signals such as imaging applications. Each channel includes a lowpass filter between the driver output and ADC input. DC specs include ±1.2LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2LSBRMS. Applications n n n n The digital outputs are serial LVDS and each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit option (1-lane mode). The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. Industrial Imaging Medical Imaging Multichannel Data Acquisition Nondestructive Testing L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. Typical Application Single-Ended Sensor Digitization 3.3V 1.8V 1.8V VCC VDD OVDD IMAGE SENSOR • • • PIPELINE ADC PIPELINE ADC PIPELINE ADC VREF 0 LTM9012 –10 –20 14 14 DATA CHANNEL 1 SERIALIZER ENCODER AND CHANNEL 2 LVDS DRIVERS 14 –30 FPGA CHANNEL 3 AMPLITUDE (dBFS) PIPELINE ADC LTM9012, 125Msps, 70MHz FFT –40 –50 –60 –70 –80 –90 CHANNEL 4 14 INTERNAL REFERENCE & SUPPLY BYPASS CAPACITORS ENCODE CLOCK FR+ –110 FR– –120 DCO+ PLL SCK SDI SDO CS PAR/SER ENC+ –100 ENC– DCO– 0 5 10 15 20 25 30 35 40 45 50 55 60 FREQUENCY (MHz) 9012 TA01b 9012 TA01a 9012f 1 LTM9012 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) Supply Voltages VDD, OVDD................................................. –0.3V to 2V VCC........................................................ –0.3V to 5.5V Analog Input Voltage (CHn +, CHn –, SHDNn ) (Note 3)........................................................–0.3V to VCC Analog Input Voltage (PAR/SER, SENSE) (Note 4)......................................... –0.3V to (VDD + 0.2V) Digital Input Voltage (ENC +, ENC –, CS, SDI, SCK) (Note 5)...................................................... –0.3V to 3.9V SDO (Note 5)............................................. –0.3V to 3.9V Digital Output Voltage................. –0.3V to (OVDD + 0.3V) Operating Temperature Range LTM9012C................................................ 0°C to 70°C LTM9012I.............................................–40°C to 85°C Storage Temperature Range................... –65°C to 150°C TOP VIEW 1 2 3 4 CH4+ CH4– 5 6 CH3+ CH3– 7 8 9 10 CH2+ CH2– 11 12 13 CH1+ CH1– A B VCC3 SHDN3 VCC2 C SHDN2 D E F SHDN4 VCC4 SHDN1 G VCC1 H J K L SDI VDD ENC+ ENC – CS D4B – D4B+ SENSE M VDD N SDO PAR/SER P REF Q D1A+ D1A– R S D3A– D3A+ FR– FR+ D4A– D4A+ D3B– D3B+ SCK DCO– DCO+ D2B– D2B+ OVDD D2A– D2A+ D1B– D1B+ ALL ELSE = GND BGA PACKAGE 221-LEAD (15mm × 11.25mm) TJMAX = 125°C, θJA = 16.5°C/W, θJCtop = 15°C/W, θJCbottom = 6.3°C/W, θJBOARD = 10.4°C/W θ VALUES DETERMINED PER JESD 51-9 WEIGHT = 1.07g Order Information LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM9012CY-AB#PBF LTM9012CY-AB#PBF LTM9012YAB 221-Lead (15mm × 11.25mm) Plastic BGA 0°C to 70°C LTM9012IY-AB#PBF LTM9012IY-AB#PBF LTM9012YAB 221-Lead (15mm × 11.25mm) Plastic BGA –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ 9012f 2 LTM9012 Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 6) PARAMETER CONDITIONS MIN Resolution (No Missing Codes) l 14 TYP MAX UNITS Bits Integral Linearity Error Differential Analog Input (Note 7) l –5 ±1.2 5 LSB Differential Linearity Error Differential Analog Input l –0.9 ±0.3 0.9 LSB Offset Error (Note 8) l –37 ±3 37 mV Gain Error Internal Reference External Reference l –3.6 –1.3 –1.3 3.0 %FS %FS Offset Drift ±20 µV/°C Full-Scale Drift Internal Reference External Reference ±35 ±25 ppm/°C ppm/°C Gain Matching External Reference ±0.2 %FS ±3 mV 1.2 LSBRMS Offset Matching Transition Noise External Reference Analog Input The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 6) SYMBOL PARAMETER CONDITIONS VIN Differential Analog Input Range (CH+ – CH – ) LTM9012-AB VIN(CM) Analog Input Common Mode (CH+ + CH – )/2 Differential Analog Input (Note 9) VSENSE External Voltage Reference Applied to SENSE External Reference Mode RIN Differential Input Resistance LTM9012-AB at –1dBFS MIN TYP MAX UNITS 0.2 l VP-P 0 to 1.5 l 0.625 1.250 V 1.300 V 100 Ω IIN(P/S) Input Leakage Current 0 < PAR/SER < VDD l –3 3 µA IIN(SENSE) Input Leakage Current 0.625V < SENSE < 1.3V l –6 6 µA tAP Sample-and-Hold Acquisition Delay Time 0 0.15 ns tJITTER Sample-and-Hold Acquisition Delay Jitter CMRR Analog Input Common Mode Rejection Ratio 90 psRMS dB BW-3dB 3dB Corner of Internal Lowpass Filter 90 MHz Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 6) SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 70MHz Input SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic 70MHz Input Spurious Free Dynamic Range 4th Harmonic or Higher S/N+D MIN TYP MAX UNITS l 66.5 68.3 dBFS l 66.9 78 dBFS 70MHz Input l 76.9 86 dBFS Signal-to-Noise Plus Distortion Ratio 70MHz Input l 64.7 66.7 dBFS Crosstalk, Near Channel 10MHz (Note 12) 70 dBc Crosstalk, Far Channel 10MHz (Note 12) 90 dBc 9012f 3 LTM9012 Internal Reference Characteristics full operating temperature range, otherwise specifications are at TA = 25°C. The l denotes the specifications which apply over the PARAMETER CONDITIONS MIN TYP MAX VREF Output Voltage IOUT = 0 1.225 1.250 1.275 VREF Output Temperature Drift UNITS V ±25 VREF Output Resistance –400μA < IOUT < 1mA VREF Line Regulation 1.7V < VDD < 1.9V ppm/°C 7 Ω 0.6 mV/V Digital Inputs and Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 6) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC–) Differential Encode Mode (ENC– Not Tied to GND) VID Differential Input Voltage (Note 9) l 0.2 VICM Common Mode Input Voltage Internally Set Externally Set (Note 9) l 1.1 l 0.2 VIN Input Voltage Range ENC+, ENC– to GND RIN Input Resistance (See Figure 3) CIN Input Capacitance V 1.2 1.6 V V 3.6 V 10 kΩ 3.5 pF Single-Ended Encode Mode (ENC– Tied to GND) VIH High Level Input Voltage VDD = 1.8V 1.26 V VIL Low Level Input Voltage VDD = 1.8V 0.54 V VIN Input Voltage Range ENC+ to GND 0 to 3.6 RIN Input Resistance (See Figure 4) 30 kΩ CIN Input Capacitance 3.5 pF V Digital Inputs (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VIH High Level Input Voltage VDD = 1.8V l VIL Low Level Input Voltage VDD = 1.8V l IIN Input Current VIN = 0V to 3.6V l CIN Input Capacitance 1.3 V –10 0.6 V 10 µA 3 pF 200 Ω SDO Output (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used) ROH Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V IOH Logic High Output Leakage Current SDO = 0V to 3.6V COUT Output Capacitance l –10 10 3 µA pF Digital Input (SHDN) VIH High Level Input Voltage VCC = 3.3V l VIL Low Level Input Voltage VCC = 3.3V l 0.6 0.97 0.95 1.4 V RSHDN SHDN Pull-Up Resistor VSHDN = 0V to 0.5V l 90 150 210 kΩ mV mV V Digital Data Outputs VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 247 125 350 175 454 250 VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 1.125 1.125 1.250 1.250 1.375 1.375 RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 V V Ω 9012f 4 LTM9012 Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 6) SYMBOL PARAMETER CONDITIONS MIN TYP MAX VDD ADC Supply Voltage (Note 10) l 1.7 1.8 1.9 UNITS V OVDD ADC Output Supply Voltage (Note 10) l 1.7 1.8 1.9 V VCC Amplifier Supply Voltage (Note 10) l 2.7 3.3 3.6 V IVDD ADC Supply Current Sine Wave Input l 298 320 mA IOVDD ADC Output Supply Current 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 27 49 31 54 mA mA IVCC Amplifier Supply Current l 208 224 mA l l 1271 1311 1473 1517 mW mW PDISS 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode PSLEEP 3 mW PNAP 85 mW 20 mW PDIFFCLK Power Decrease with Single-Ended Encode Mode Enabled Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 6) SYMBOL PARAMETER CONDITIONS fS Sampling Frequency (Note 10, Note 11) l MIN 5 tENCL ENC Low Time (Note 9) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 3.8 2 tENCH ENC High Time (Note 9) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 3.8 2 tAP Sample-and-Hold Acquisition Delay Time TYP MAX UNITS 125 MHz 4 4 100 100 ns ns 4 4 100 100 ns ns 0 ns 1/(8•fS) 1/(7•fS) 1/(6•fS) 1/(16•fS) 1/(14•fS) 1/(12•fS) sec sec sec sec sec sec Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output) tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization 2-Lanes, 14-Bit Serialization 2-Lanes, 12-Bit Serialization 1-Lane, 16-Bit Serialization 1-Lane, 14-Bit Serialization 1-Lane, 12-Bit Serialization tFRAME FR to DCO Delay (Note 9) l tDATA DATA to DCO Delay (Note 9) l 0.35•tSER tPD Propagation Delay (Note 9) l 0.7n + 2•tSER tR Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tF Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-Cycle Jitter tSER = 1ns 0.35•tSER Pipeline Latency 0.5•tSER 0.65•tSER sec 0.5•tSER 0.65•tSER sec 1.1n + 2•tSER 1.5n + 2•tSER sec 60 psP-P 6 Cycles SPI Port Timing (Note 9) tSCK SCK Period tS Write Mode Read Back Mode, CSDO = 20pF, RPULLUP = 2k l l 40 250 ns ns CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 tDO SCK Falling to SDO Valid Read Back Mode, CSDO = 20pF, RPULLUP = 2k l ns 125 ns 9012f 5 LTM9012 Electrical Characteristics Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND (unless otherwise noted). Note 3: Input pins are protected by steering diodes to either supply. If the inputs should exceed either supply voltage, the input current should be limited to less than 10mA. In addition, the inputs CHn +, CHn – are protected by a pair of back-to-back diodes. If the differential input voltage exceeds 1.4V, the input current should be limited to less than 10mA. Note 4: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below GND or above VDD without latchup. Note 5: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents greater than 100mA below GND without latchup. Note 6: VCC = 3.3V, VDD = OVDD = 1.8V, fSAMPLE = 125MHz, 2-lane output mode, differential ENC+/ENC – = 2VP-P sine wave, input range = 200mVP-P with differential drive, unless otherwise noted. Note 7: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2’s complement output mode. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1000Mbps so tSER must be greater than or equal to 1ns. Note 12: Near-channel crosstalk refers to CH1 and CH2. Far channel crosstalk refers to CH1 to CH4. Timing Diagrams 2-Lane Output Mode, 16-Bit Serialization* tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A– OUT#A+ OUT#B– OUT#B+ tDATA tSER tPD tSER D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 9012 TD01 *SEE THE DIGITAL OUTPUTS SECTION 9012f 6 LTM9012 Timing Diagrams 2-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+2 N tENCH ENC– N+1 tENCL ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A– OUT#A+ OUT#B– OUT#B+ tDATA tSER tPD tSER D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 9012 TD02 NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– 2-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT N N+1 tENCH ENC– tENCL ENC+ tSER DCO– DCO+ FR+ tFRAME tDATA tPD tSER FR– OUT#A– OUT#A+ OUT#B– OUT#B+ tSER D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9 D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 9012 TD03 9012f 7 LTM9012 Timing Diagrams 1-Lane Output Mode, 16-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A– OUT#A+ tDATA tSER tPD D1 D0 0 tSER 0 SAMPLE N-6 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 SAMPLE N-5 0 D13 D12 D11 D10 SAMPLE N-4 9012 TD04 OUT#B+, OUT#B– ARE DISABLED 1-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A– OUT#A+ tDATA tSER tPD D3 D2 SAMPLE N-6 D1 tSER D0 D13 D12 D11 D10 D9 SAMPLE N-5 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 SAMPLE N-4 9012 TD05 OUT#B+, OUT#B– ARE DISABLED 9012f 8 LTM9012 Timing Diagrams 1-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A– OUT#A+ tDATA tSER tPD D5 D4 D3 tSER D2 D13 D12 D11 D10 D9 SAMPLE N-6 D8 D7 D6 D5 D4 D3 D2 D13 D12 D11 SAMPLE N-5 SAMPLE N-4 9012 TD06 OUT#B+, OUT#B– ARE DISABLED SPI Port Timing (Readback Mode) tDS tS tDH tSCK tH CS SCK tDO SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 XX D7 HIGH IMPEDANCE XX D6 XX D5 XX D4 XX D3 XX D2 XX XX D1 D0 SPI Port Timing (Write Mode) CS SCK SDI SDO R/W HIGH IMPEDANCE A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 9012 TD07 9012f 9 LTM9012 Typical Performance Characteristics IOVDD vs Sample Rate, 5MHz Sine Wave Input –1dBFS 60 0 50 64K Point FFT, fIN = 5MHz, –1dBFS, SENSE = VDD 0 –10 –10 –20 –20 –30 IOVDD (mA) 30 20 1-LANE 1.75mA 1-LANE 3.5mA 2-LANE 1.75mA 2-LANE 3.5mA 10 0 0 25 50 75 100 SAMPLE RATE (Msps) 125 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –30 40 –40 –50 –60 –70 –80 –90 –110 –110 –120 –120 0 5 10 15 20 25 30 35 40 45 50 55 60 FREQUENCY (MHz) 0 –10 –20 –20 0.5 0.4 0.3 DNL ERROR (LSB) –40 –50 –60 –70 –80 0.2 0.1 0 –0.1 –0.2 –90 –100 –100 –110 –110 –0.4 –120 –120 –0.5 5 10 15 20 25 30 35 40 45 50 55 60 FREQUENCY (MHz) –0.3 0 5 10 15 20 25 30 35 40 45 50 55 60 FREQUENCY (MHz) 9012 G04 Pulse Response 1.5 14000 –5 1.0 12000 –10 0.5 10000 –15 0 8000 –0.5 6000 –25 –1.0 4000 –30 –1.5 2000 –35 8192 12288 OUTPUT CODE 16384 9012 G07 0 dBFS 0 4096 8192 12288 OUTPUT CODE 0 16384 Frequency Response 16000 0 4096 9012 G06 2.0 –2.0 0 9012 G05 Integral Non-Linearity (INL) vs Output Code INL ERROR (LSB) Differential Non-Linearity (DNL) vs Output Code –90 0 5 10 15 20 25 30 35 40 45 50 55 60 FREQUENCY (MHz) 9012 G03 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –30 –80 0 9012 G02 64K Point 2-Tone FFT, fIN = 70MHz and fIN = 75MHz, –7dBFS per Tone, SENSE = VDD 0 –70 –70 –80 –100 –10 –50 –50 –60 –90 9012 G01 –60 –40 –100 64K Point 2-Tone FFT, fIN = 4.8MHz and fIN = 5.2MHz, –7dBFS per Tone, SENSE = VDD –40 64K Point FFT, fIN = 70MHz, –1dBFS, SENSE = VDD 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 TIME (µs) 1 9012 G08 –20 –40 1 10 100 BASEBAND FREQUENCY (MHz) 1000 9012 G09 9012f 10 LTM9012 Pin Functions VCC1 (H10, H13): Channel 1 Amplifier Supply. VCC is internally bypassed to ground with 0.1µF in parallel with 0.01µF ceramic capacitors, additional bypass capacitance is optional. The recommended operating voltage is 3.3V. VCC2 (C8, C12): Channel 2 Amplifier Supply. VCC is internally bypassed to ground with 0.1µF in parallel with 0.01µF ceramic capacitors, additional bypass capacitance is optional. The recommended operating voltage is 3.3V. VCC3 (C2, C6): Channel 3 Amplifier Supply. VCC is internally bypassed to ground with 0.1µF in parallel with 0.01µF ceramic capacitors, additional bypass capacitance is optional. The recommended operating voltage is 3.3V. VCC4 (H1, H4): Channel 4 Amplifier Supply. VCC is internally bypassed to ground with 0.1µF in parallel with 0.01µF ceramic capacitors, additional bypass capacitance is optional. The recommended operating voltage is 3.3V. VDD (N4, N5, N9, N10): ADC Analog Supply. VDD is internally bypassed to ground with 0.1µF ceramic capacitors, additional bypass capacitance is optional. The recommended operating voltage is 1.8V. OVDD (R7, R8, S8): ADC Digital Output Supply. OVDD is internally bypassed to ground with 0.1µF ceramic capacitors, additional bypass capacitance is optional. The recommended operating voltage is 1.8V. GND: Ground. Use multiple vias close to pins. CH1+ (A11): Channel 1 Noninverting Analog Input. CH1– (A12): Channel 1 Inverting Analog Input. CH2+ (A8): Channel 2 Noninverting Analog Input. CH2– (A9): Channel 2 Inverting Analog Input. CH3+ (A5): Channel 3 Noninverting Analog Input. CH3– (A6): Channel 3 Inverting Analog Input. CH4+ (A2): Channel 4 Noninverting Analog Input. CH4– (A3): Channel 4 Inverting Analog Input. SHDN1 (G11): Channel 1 Amplifier Shutdown. Connecting SHDN1 to VCC or floating results in normal (active) operating mode. Connecting SHDN1 to GND results in a low power shutdown state on amplifier 1. SHDN2 (D9): Channel 2 Amplifier Shutdown. Connecting SHDN2 to VCC or floating results in normal (active) operating mode. Connecting SHDN2 to GND results in a low power shutdown state on amplifier 2. SHDN3 (D3): Channel 3 Amplifier Shutdown. Connecting SHDN3 to VCC or floating results in normal (active) operating mode. Connecting SHDN3 to GND results in a low power shutdown state on amplifier 3. SHDN4 (G1): Channel 4 Amplifier Shutdown. Connecting SHDN4 to VCC or floating results in normal (active) operating mode. Connecting SHDN4 to GND results in a low power shutdown state on amplifier 4. ENC+ (N1): Encode Input. Conversion starts on the rising edge. ENC– (P1): Encode Complement Input. Conversion starts on the falling edge. CS (P4): In serial programming mode, (PAR/SER = 0V), CS is the serial interface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/ SER = VDD), CS selects 2-lane or 1-lane output mode. CS can be driven with 1.8V to 3.3V logic. SCK (P5): In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In the parallel programming mode (PAR/SER = VDD), SCK selects 3.5mA or 1.75mA LVDS output currents. SCK can be driven with 1.8V to 3.3V logic. SDI (P3): In serial programming mode, (PAR/SER = 0V), SDI is the serial interface data Input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the parallel programming mode (PAR/SER = VDD), SDI can be used to power down the part. SDI can be driven with 1.8V to 3.3V logic. SDO (P9): In serial programming mode, (PAR/SER = 0V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an opendrain NMOS output that requires an external 2k pull-up resistor to 1.8V – 3.3V. If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In the parallel programming mode (PAR/SER = VDD), SDO is an input that enables internal 100Ω termination resistors. When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. 9012f 11 LTM9012 Pin Functions PAR/SER (P10): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI and SDO become a serial interface that controls the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK, SDI and SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. LVDS Outputs VREF (P11): Reference Voltage Output. VREF is internally bypassed to ground with a 2.2μF ceramic capacitor, nominally 1.25V. OUT2A–/OUT2A+, OUT2B–/OUT2B+ (R9/R10, S11/S12): Serial data outputs for Channel 2. In 1-lane output mode only OUT2A–/OUT2A+ are used. SENSE (N11): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±0.1V input range. Connecting SENSE to ground selects the internal reference and a ±0.05V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.08 • VSENSE. SENSE is internally bypassed to ground with a 0.1μF ceramic capacitor. OUT3A–/OUT3A+, OUT3B–/OUT3B+ (S2/S3, R4/R5): Serial data outputs for Channel 3. In 1-lane output mode only OUT3A–/OUT3A+ are used. All pins in this section are differential LVDS outputs. The output current level is programmable. There is an optional internal 100Ω termination resistor between the pins of each LVDS output pair. OUT1A–/OUT1A+, OUT1B–/OUT1B+ (Q9/Q10, R11/R12): Serial data outputs for Channel 1. In 1-lane output mode only OUT1A–/OUT1A+ are used. OUT4A–/OUT4A+, OUT4B–/OUT4B+ (R2/R3, Q4/Q5): Serial data outputs for Channel 4. In 1-lane output mode only OUT4A–/OUT4A+ are used. FR–/FR+ (S4/S5): Frame Start Output. DCO–/DCO+ (S9/S10): Data Clock Output. Pin Configuration Table 1 2 3 4 5 6 7 8 9 10 11 12 13 A GND CH4+ CH4– GND CH3+ CH3– GND CH2+ CH2– GND CH1+ CH1– GND B GND GND GND GND GND GND GND GND GND GND GND GND GND C GND VCC3 GND GND GND VCC3 GND VCC2 GND GND GND VCC2 GND D GND GND SHDN3 GND GND GND GND GND SHDN2 GND GND GND GND E GND GND GND GND GND GND GND GND GND GND GND GND GND F GND GND GND GND GND GND GND GND GND GND GND GND GND G SHDN4 GND GND GND GND GND GND GND GND GND SHDN1 GND GND H VCC4 GND GND VCC4 GND GND GND GND GND VCC1 GND GND VCC1 J GND GND GND GND GND GND GND GND GND GND GND GND GND K GND GND GND GND GND GND GND GND GND GND GND GND GND L GND GND GND GND GND GND GND GND GND GND GND GND GND M GND GND GND GND GND GND GND GND GND GND GND GND GND N ENC+ GND GND VDD VDD GND GND GND VDD VDD SENSE GND GND P ENC– GND SDI CS SCK GND GND GND SDO PAR/SER REF GND GND Q GND GND GND D4B– D4B+ GND GND GND D1A– D1A+ GND GND GND R GND D4A– D4A+ D3B– D3B+ GND OVDD OVDD D2A– D2A+ D1B– D1B+ GND GND D3A– D3A+ FR– FR+ OVDD DCO– DCO+ D2B– D2B+ GND S GND GND 9012f 12 LTM9012 Block Diagram 3.3V 1.8V VCC LTM9012 1.8V VDD OVDD OUT1A+ CH 1 ANALOG INPUT OUT1A– 14-BIT ADC CORE SHDN1 OUT1B+ OUT1B– DATA SERIALIZER VDD/2 OUT2A+ CH 2 ANALOG INPUT OUT2A– 14-BIT ADC CORE OUT2B+ OUT2B– SHDN2 OUT3A+ CH 3 ANALOG INPUT OUT3A– 14-BIT ADC CORE OUT3B+ OUT3B– SHDN3 VDD/2 OUT4A+ CH 4 ANALOG INPUT OUT4A– 14-BIT ADC CORE OUT4B+ OUT4B– SHDN4 ENC+ DCO± PLL ENC– VREF FR± 1.25V REFERENCE REFH REFL RANGE SELECT REF BUFFER SENSE SDO SDI SCK CS PAR/SER MODE CONTROL REGISTERS DIFF. REF. AMP. GND 9012 BD Figure 1. Block Diagram 9012f 13 LTM9012 Applications Information Converter Operation The LTM9012 is a low power, 4-channel, 14-bit, 125Msps A/D converter that is powered by a 1.8V ADC supply and 3.3V driver supplies. Each input includes a fixed gain, differential amplifier. The analog inputs can be driven differentially or single-ended. The encode input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption. The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). Many additional features can be chosen by programming the mode control registers through a serial SPI port. LTM9012 (1 CHANNEL SHOWN) SIGNAL ¼ LTC6254 VREF 0.1µF The differential input can support single-ended operation by connecting the inverting input to a fixed DC voltage or ground. However, if ground is used, there will be a 6dB loss of dynamic range. For maximum dynamic range, connect the inverting inputs of the LTM9012 to a DC voltage equal to the median of the voltage excursions of the noninverting input. An op amp provides an excellent means of providing a low impedance voltage source capable of sourcing and sinking small amounts of current. Note the value of this DC voltage should fall between the limits of allowable input common mode voltages. See Figure 2 for an example. – + 9012 F02 RF SET VREF EQUAL TO THE DC MEDIAN OF THE SIGNAL VOLTAGE Figure 2. Single-Ended Operation Analog Inputs The analog inputs for each channel of the LTM9012 consist of a differential amplifier with fixed gain followed by a lowpass filter. The 10x gain version has 49.9Ω series resistance in each input. – + The gain of the LTM9012 may also be decreased from the nominal value by adding resistance in series with the signal inputs. The internal op amps are fed by 49.9Ω series resistors and employ 511Ω feedback resistors. The voltage gain of the stage is set by the ratio of the feedback resistance to the total series resistance. Unity gain, for example, can be realized by adding a 464Ω resistor in series with each input. Reference The LTM9012 has an internal 1.25V voltage reference. For a 2V input range using the internal reference with a unity gain internal amplifier configuration, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE. The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 • VSENSE. The reference is shared by all four ADC channels, so it is not possible to independently adjust the input range of individual channels. 9012f 14 LTM9012 Applications Information Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals—do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 3), and the single-ended encode mode (Figure 4). The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figure 5 and Figure 6). The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken LTM9012 above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC– should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode. For good jitter performance ENC+ should have fast rise and fall times. The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC– is connected to ground and ENC+ is driven with a square wave encode input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times. VDD DIFFERENTIAL COMPARATOR VDD LTM9012 15k ENC+ 1.8V TO 3.3V 0V ENC– ENC+ ENC– 30k 30k CMOS LOGIC BUFFER 9012 F04 9012 F03 Figure 3. Equivalent Encode Input Circuit for Differential Encode Mode 0.1µF ENC+ T1 50Ω 0.1µF Figure 4. Equivalent Encode Input Circuit for Single-Ended Encode Mode LTM9012 100Ω 0.1µF 50Ω 0.1µF PECL OR LVDS CLOCK ENC– 9012 F05 T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE Figure 5. Sinusoidal Encode Drive ENC+ LTM9012 0.1µF ENC– 9012 F06 Figure 6. PECL or LVDS Encode Drive 9012f 15 LTM9012 Applications Information Clock PLL and Duty Cycle Stabilizer The encode clock is multiplied by an internal phase-locked loop (PLL) to generate the serial digital output data. If the encode signal changes frequency or is turned off, the PLL requires 25μs to lock onto the input clock. A clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. In the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. In the parallel programming mode the duty cycle stabilizer is always enabled. Digital Outputs The digital outputs of the LTM9012 are serialized LVDS signals. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The data can be serialized with 16-, 14-, or 12-bit serialization (see the Timing Diagrams for details). Note that with 12-bit serialization the two LSBs are not available—this mode is included for compatibility with potential 12-bit versions of these parts. The output data should be latched on the rising and falling edges of the data clock out (DCO). A data frame output (FR) can be used to determine when the data from a new conversion result begins. In the 2-lane, 14-bit serialization mode, the frequency of the FR output is halved. The maximum serial data rate for the data outputs is 1Gbps, so the maximum sample rate of the ADC will depend on the serialization mode as well as the speed grade of the ADC (see Table 1). The minimum sample rate for all serialization modes is 5Msps. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD which is isolated from the A/D core power. Programmable LVDS Output Current The default output driver current is 3.5mA. This current can be adjusted by control register A2 in the serial programming mode. Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the parallel programming mode the SCK pin can select either 3.5mA or 1.75mA. Table 1. Maximum Sampling Frequency for All Serialization Modes. The Sampling Frequency for Potential Slower Speed Grades Cannot Exceed fSAMPLE(MAX). SERIALIZATION MODE MAXIMUM SAMPLING FREQUENCY, fS (MHz) DCO FREQUENCY FR FREQUENCY SERIAL DATA RATE 2-Lane 16-Bit Serialization 125 4 • fS fS 8 • fS 2-Lane 14-Bit Serialization 125 3.5 • fS 0.5 • fS 7 • fS 2-Lane 12-Bit Serialization 125 3 • fS fS 6 • fS 1-Lane 16-Bit Serialization 62.5 8 • fS fS 16 • fS 1-Lane 14-Bit Serialization 71.4 7 • fS fS 14 • fS 1-Lane 12-Bit Serialization 83.3 6 • fS fS 12 • fS 9012f 16 LTM9012 Applications Information Optional LVDS Driver Internal Termination Digital Output Randomizer In most cases using just an external 100Ω termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can be enabled by serially programming mode control register A2. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. In the parallel programming mode the SDO pin enables internal termination. Internal termination should only be used with 1.75mA, 2.1mA or 2.5mA LVDS output current modes. Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. Data Format Table 2 shows the relationship between the analog input voltage and the digital data output bits. By default the output data format is offset binary. The 2’s complement format can be selected by serially programming mode control register A1. Table 2. Output Codes vs Input Voltage CHn + TO CHn – (0.2V RANGE) D13 TO D0 (OFFSET BINARY) D13 TO D0 (2’s COMPLEMENT) >0.1000000V +0.0999878V +0.0999756V 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 +0.0000122V +0.0000000V –0.0000122V –0.0000244V 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1111 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 –0.0999878V –0.1000000V <–0.1000000V 00 0000 0000 0000 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0000 10 0000 0000 0000 The digital output is randomized by applying an exclusiveOR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied —an exclusive-OR operation is applied between the LSB and all other bits. The FR and DCO outputs are not affected. The output randomizer is enabled by serially programming mode control register A1. Digital Output Test Pattern To allow in-circuit testing of the digital interface to the A/D, there is a test mode that forces the A/D data outputs (D13-D0) of all channels to known values. The digital output test patterns are enabled by serially programming mode control registers A3 and A4. When enabled, the test patterns override all other formatting modes: 2’s complement and randomizer. Output Disable The digital outputs may be disabled by serially programming mode control register A2. The current drive for all digital outputs including DCO and FR are disabled to save power or enable in-circuit testing. When disabled the common mode of each output pair becomes high impedance, but the differential impedance may remain low. 9012f 17 LTM9012 Applications Information Sleep and Nap Modes Parallel Programming Mode The A/D may be placed in sleep or nap modes to conserve power. In sleep mode the entire chip is powered down, resulting in 3mW power consumption. Sleep mode is enabled by mode control register A1 (serial programming mode), or by SDI (parallel programming mode). The amount of time required to recover from sleep mode depends on the size of the bypass capacitors on VREF, REFH, and REFL. For the internal capacitor values and no additional external capacitance, the A/D will stabilize after 2ms. To use the parallel programming mode, PAR/SER should be tied to VDD. The CS, SCK, SDI and SDO pins are binary logic inputs that set certain operating modes. These pins can be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V CMOS logic. When used as an input, SDO should be driven through a 1k series resistor. Table 3 shows the modes set by CS, SCK, SDI and SDO. In nap mode any combination of A/D channels can be powered down while the internal reference circuits and the PLL stay active, allowing faster wakeup than from sleep mode. Recovering from nap mode requires at least 100 clock cycles. If the application demands very accurate DC settling then an additional 50μs should be allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current as the A/D leaves nap mode. Nap mode is enabled by mode control register A1 in the serial programming mode. Driver Amplifier Shutdown (SHDN) The ADC drivers may be placed in shutdown mode to conserve power independently from the ADC core. Each ADC driver has an independent SHDN pin but it is expected that all four will be tied together. Device Programming Modes The operating modes of the LTM9012 can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes. Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD) PIN DESCRIPTION CS 2-Lane/1-Lane Selection Bit 0 = 2-Lane, 16-Bit Serialization Output Mode 1 = 1-Lane, 14-Bit Serialization Output Mode SCK LVDS Current Selection Bit 0 = 3.5mA LVDS Current Mode 1 = 1.75mA LVDS Current Mode SDI Power Down Control Bit 0 = Normal Operation 1 = Sleep Mode SDO Internal Termination Selection Bit 0 = Internal Termination Disabled 1 = Internal Termination Enabled Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address bits (A6:A0) will be read back on the SDO pin (see the Timing Diagrams sections). During a read back command the register is not updated and data on SDI is ignored. 9012f 18 LTM9012 Applications Information The SDO pin is an open-drain output that pulls to ground with a 200Ω impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and read back is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 4 shows a map of the mode control registers. Software Reset If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset is complete, bit D7 is automatically set back to zero. Table 4. Serial Programming Mode Register Map (PAR/SER = GND) REGISTER A0: RESET REGISTER (ADDRESS 00h) WRITE ONLY D7 D6 D5 D4 D3 D2 D1 D0 RESET X X X X X X X RESET Bit 7 Software Reset Bit 0 = Not Used 1 = Software Reset. All mode control registers are reset to 00h. The ADC is momentarily placed in Sleep mode. This bit is automatically set back to zero at the end of the SPI Write command. The Reset register is Write only. Data read back from the reset register will be random. Bits 6-0 Unused, Don’t Care Bits. REGISTER A1: FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CS = GND) D7 D6 D5 D4 D3 D2 D1 D0 DCSOFF RAND TWOSCOMP SLEEP NAP_4 NAP_3 NAP_2 NAP_1 Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer On 1 = Clock Duty Cycle Stabilizer Off. This is not recommended. Bit 6 RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On Bit 5 TWOSCOMP Two’s Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two’s Complement Data Format Bits 4-0 SLEEP: NAP_X Sleep/Nap Mode Control Bits 00000 = Normal Operation 0XXX1 = Channel 1 in Nap Mode 0XX1X = Channel 2 in Nap Mode 0X1XX = Channel 3 in Nap Mode 01XXX = Channel 4 in Nap Mode 1XXXX = Sleep Mode. Channels 1, 2, 3 and 4 are Disabled Note: Any combination of these channels can be placed in Nap mode. 9012f 19 LTM9012 Applications Information REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h) D7 D6 D5 ILVDS2 ILVDS1 ILVDS0 Bits 7-5 D4 TERMON D3 OUTOFF D2 OUTMODE2 D1 OUTMODE1 D0 OUTMODE0 ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current Bit 4 Bit 3 Bits 2-0 111 = 1.75mA LVDS Output Driver Current TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current is 2× the Current Set by ILVDS2:ILVDS0. Internal termination should only be used with 1.75mA, 2.1mA or 2.5mA LVDS output current modes. OUTOFF Output Disable Bit 0 = Digital Outputs are Enabled. 1 = Digital Outputs are Disabled. OUTMODE2:OUTMODE0 000 = 2-Lanes, 16-Bit Serialization Digital Output Mode Control Bits 001 = 2-Lanes, 14-Bit Serialization 010 = 2-Lanes, 12-Bit Serialization 011 = Not Used 100 = Not Used 101 = 1-Lane, 14-Bit Serialization 110 = 1-Lane, 12-Bit Serialization 111 = 1-Lane, 16-Bit Serialization REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h) D7 D6 D5 OUTTEST X TP13 Bit 7 Bit 6 Bit 5-0 OUTTEST 0 = Digital Output Test Pattern Off D3 TP11 D2 TP10 D1 TP9 D0 TP8 D2 TP2 D1 TP1 D0 TP0 Digital Output Test Pattern Control Bit 1 = Digital Output Test Pattern On Unused, Don’t Care Bit. TP13:TP8 Test Pattern Data Bits (MSB) TP13:TP8 Set the Test Pattern for Data Bit 13(MSB) Through Data Bit 8. REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h) D7 D6 D5 TP7 TP6 TP5 Bit 7-0 D4 TP12 D4 TP4 D3 TP3 TP7:TP0 Test Pattern Data Bits (LSB) TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0(LSB). 9012f 20 LTM9012 Applications Information Grounding and Bypassing Table 5. Internal Trace Lengths PIN NAME (mm) Q9 01A– 0.535 Q10 01A+ 0.350 R11 01B– 2.185 R12 01B+ 2.216 R9 02A– 0.174 R10 02A+ 0.667 S11 02B– 2.976 S12 02B+ 2.972 S2 03A– 3.033 S3 03A+ 3.031 R4 03B– 0.752 R5 03B+ 0.370 R2 04A– 2.130 R3 04A+ 2.125 Q4 04B– 0.332 The pin assignments of the LTM9012 allow a flow-through layout that makes it possible to use multiple parts in a small area when a large number of ADC channels are required. The LTM9012 has similar layout rules to other BGA packages. The layout can be implemented with 6mil blind vias and 5mil traces. The pinout has been designed to minimize the space required to route the analog and digital traces. The analog and digital traces can essentially be routed within the width of the package. This allows multiple packages to be located close together for high channel count applications. Trace lengths for the analog inputs and digital outputs should be matched as well as possible. Table 5 lists the trace lengths for the analog inputs and digital outputs inside the package from the die pad to the package pad. These should be added to the PCB trace lengths for best matching. Q5 04B+ 0.527 A12 CH1– 7.741 A11 CH1+ 7.723 A9 CH2– 4.632 A8 CH2+ 4.629 A6 CH3– 3.987 A5 CH3+ 3.988 A3 CH4– 7.892 A2 CH4+ 7.896 P1 CLK– 3.317 N1 CLK+ 3.325 P4 CS 0.241 S9 DCO– 1.912 S10 DCO+ 1.927 S4 FR– 2.097 S5 FR+ 2.082 Figures 7 through Figure 11 show an example of a good PCB layout. P10 PAR/SER 0.226 P5 SCK 1.553 P9 SD0 0.957 Heat Transfer P3 SDI 1.184 The LTM9012 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane in the first layer beneath the ADC is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. Bypass capacitors are integrated inside the package; additional capacitance is optional. The analog inputs, encode signals, and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. Layout Recommendations Most of the heat generated by the LTM9012 is transferred from the die through the bottom side of the package through numerous ground pins onto the printed circuit board. For good electrical and thermal performance, these pins should be connected to the internal ground planes by an array of vias. 9012f 21 LTM9012 Applications Information Figure 7. Layer 1 Component Side 9012f 22 LTM9012 Applications Information Figure 8. Layer 2 9012f 23 LTM9012 Applications Information Figure 9. Layer 3 9012f 24 LTM9012 Applications Information Figure 10. Back Side 9012f 25 J6 TP5 GND TP4 5V TO 6V TP2 GND TP1 V+ 3V TO 6V C28 OPT R69 0Ω R13 OPT R18 0Ω C11 1µF C2 1µF 3 1 3 1 J14 2 3 1 2 R64 1k VDD C31 0.01µF • • J8 CLK– C30 0.01µF C32 OPT R24 OPT T1 MABA-007159-000000 3 1 R63 1k VDD GND BYP OUT SEN/ADJ LT1763 J13 R14 OPT 2 R62 1k VDD SHDN IN GND BYP OUT SEN/ADJ LT1763-1.8 SHDN C21 0.01µF J12 2 R61 1k VDD R60 DNS J11 C10 4.7µF C1 4.7µF IN R16 0Ω C12 1µF R26 OPT R25 OPT + C14 100µF L3 BEAD R70 0Ω C5 100µF L2 BEAD J5 OPT C29 C20 OPT C22 C39, 0.01µF C37, 0.01µF C35, 0.01µF C33, 0.01µF VCC C6 1µF J3 R36, 0Ω R35, 0Ω R34, 0Ω R33, 0Ω R32, 0Ω R31, 0Ω R30, 0Ω 3 3 1 2 R6 1k SHDN1 SHDN2 SHDN3 SHDN4 CLK+ CLK– CH4– CH4+ CH3– CH3+ CH2– CH2+ CH1– CH1+ J2 2 VDD R3 31.6k R5 1k 1 VDD R29, 0Ω 3 2 R11 1k 1 VDD OVDD1 3.3V R1 10k 3 R8 100Ω J1 1 2 VCC R2 1k VDD Figure 11. Simplified Schematic for Example Layout R23 OPT R21 OPT R17 OPT R15 OPT R12 OPT C40, 0.01µF C38, 0.01µF C36, 0.01µF C34, 0.01µF C13 1µF + L4 OPT C4 1µF R20 R22 49.9Ω 0Ω R19 49.9Ω VDD IN4– IN4+ IN3– IN3 + IN2 – IN2+ IN1– IN1+ R9 1k R7 2k C3 1µF L1 BEAD VDD1 R71 0Ω VCC1 VCC1 VCC2 VCC2 VCC3 VCC3 VCC4 VCC4 OVDD 3 1 2 C8 1µF VDD GND* LTM9012 C7 2.2µF TP3 J4 R10 1k VDD PAR/SER CS SCK SDO SDI VREF R72 0Ω SENSE 26 R4 1k C24 0.1µF C23 0.1µF OVDD1 VDD1 9012 F11 OGND OGND OGND * OTHER GND PINS OMITTED FOR CLARITY. C25 0.1µF C9 1µF OVDD OVDD OVDD VDD VDD VDD VDD VDD C26 0.1µF OUT1A+ OUT1A– OUT2A+ OUT2A– OUT3A+ OUT3A– OUT4A+ OUT4A– OUT1B+ OUT1B– OUT2B+ OUT2B– OUT3B+ OUT3B– OUT4B+ OUT4B– DCO+ DCO– FR+ FR– C27 0.1µF LTM9012 Typical Application 9012f 0.50 ±0.025 Ø 221x PACKAGE TOP VIEW 0.80 1.60 2.40 SUGGESTED PCB LAYOUT TOP VIEW 0.00 4 0.80 PIN “A1” CORNER 3.75 4.25 4.00 E 1.60 aaa Z 4.80 4.00 3.20 2.40 3.20 4.80 Y Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 6.40 5.60 4.80 4.00 3.20 2.40 1.60 0.80 0.00 0.80 1.60 2.40 3.20 4.00 4.80 5.60 6.40 D X 5.85 5.35 aaa Z // bbb Z SYMBOL A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee H1 SUBSTRATE A1 NOM 2.82 0.40 2.42 0.50 0.50 15.0 11.25 0.80 12.80 9.60 0.42 2.00 A MAX 2.97 0.45 2.52 0.55 0.55 NOTES DETAIL B PACKAGE SIDE VIEW A2 0.47 2.05 0.15 0.10 0.12 0.15 0.08 TOTAL NUMBER OF BALLS: 221 0.37 1.95 b1 DIMENSIONS ddd M Z X Y eee M Z MIN 2.67 0.35 2.32 0.45 0.45 DETAIL A Øb (221 PLACES) DETAIL B H2 MOLD CAP ccc Z Z Z (Reference LTC DWG# 05-08-1886 Rev Ø) 221-Lead (15mm × 11.25mm × 2.82mm) Package Rev Ø) (Reference LTC DWGBGA # 05-08-1886 BGA Package 221-Lead (15mm × 11.25mm × 2.82mm) F e 13 12 11 e 10 8 G 7 6 5 4 PACKAGE BOTTOM VIEW 9 b 3 2 1 DETAIL A DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE BALL DESIGNATION PER JESD MS-028 AND JEP95 S R Q P N M L K J H G F E D C B A PIN 1 TRAY PIN 1 BEVEL BGA 221 0710 REV Ø PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX µModule 6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu OR Sn Pb EUTECTIC 5. PRIMARY DATUM -Z- IS SEATING PLANE 4 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 COMPONENT PIN “A1” b 3 SEE NOTES LTM9012 Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. Package Description 9012f 27 LTM9012 Typical Application Single-Ended Drive with Unity Gain Example SENSE VDD OVDD VCC4 VCC3 VCC1 1.8V VCC2 3.3V LTM9012 464Ω 1% 0V TO 3V PULSE SIGNAL 464Ω 1% 3V OUTA– • • • • • • SHDN1 SDO SHDN2 FR– +IN + SHDN3 FR+ ¼ LTC6254 –IN – SHDN4 DCO– PAR/SER DCO+ GND ENC– ENC+ VREF CS 1k 1% SDI 0.1µF OUTA+ CH1– SCK 1.5V REFERENCE CH1+ 9012 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC2170-14/LTC2171-14/ LTC2172-14 14-Bit, 25Msps/40Msps/65Msps 1.8V Quad ADCs, Ultralow Power 178mW/234mW/360mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 LTC2173-14/LTC2174-14/ LTC2175-14 14-Bit, 80Msps/105Msps/125Msps 1.8V Quad ADCs, Ultralow Power 376mW/450mW/558mW, 73.4 dB SNR, 88dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 LTC2263-14/LTC2264-14/ LTC2265-14 14-Bit, 25Msps/40Msps/65Msps 1.8V Dual ADCs, Ultralow Power 99mW/126mW/191mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-40 LTC2266-14/LTC2267-14/ LTC2268-14 14-Bit, 80Msps/105Msps/125Msps 1.8V Dual ADCs, Ultralow Power 216mW/250mW/293mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-40 LTM9009-14/LTM9010-14/ LTM9011-14 14-Bit, 80Msps/105Msps/125Msps 1.8V Octal ADCs, Ultralow Power 752mW/900mW/1116mW, 73.1dB SNR, 88dB SFDR, Serial LVDS Outputs, 11.25mm × 9mm BGA-140 9012f 28 Linear Technology Corporation LT 0412 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2012