Freescale MCF5275CVM133 Integrated microprocessor family hardware specification Datasheet

Freescale Semiconductor
Hardware Specification
Document Number: MCF5275EC
Rev. 2, 08/2006
MCF5275 Integrated
Microprocessor Family Hardware
Specification
by: Microcontroller Division
The MCF5275 family is a highly integrated
implementation of the ColdFire® family of reduced
instruction set computing (RISC) microprocessors. This
document describes pertinent features and functions
characteristics of the MCF5275 family. The MCF5275
family includes the MCF5275, MCF5275L, MCF5274
and MCF5274L microprocessors. The differences
between these parts are summarized in Table 1. This
document is written from the perspective of the
MCF5275 and unless otherwise noted, the information
applies also to the MCF5275L, MCF5274 and
MCF5274L.
The MCF5275 family delivers a new level of
performance and integration on the popular version 2
ColdFire core with up to 159 (Dhrystone 2.1) MIPS @
166MHz. These highly integrated microprocessors build
upon the widely used peripheral mix on the popular
MCF5272 ColdFire microprocessor (10/100 Mbps
Ethernet MAC and USB device) by adding a second
10/100 Mbps Ethernet MAC (MCF5274 and MCF5275)
and hardware encryption (MCF5275L and MCF5275).
© Freescale Semiconductor, Inc., 2006. All rights reserved.
• Preliminary—Subject to Change Without Notice
Contents
1
2
3
4
5
6
7
8
9
10
MCF5275 Family Configurations . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . 9
Mechanicals/Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Preliminary Electrical Characteristics . . . . . . . . . . . . . . 18
Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
MCF5275 Family Configurations
In addition, the MCF5275 family features an enhanced multiply accumulate unit (EMAC), large on-chip
memory (64 Kbytes SRAM, 16 Kbytes configurable cache), and a 16-bit DDR SDRAM memory
controller.
These devices are ideal for cost-sensitive applications requiring significant control processing for file
management, connectivity, data buffering, and user interface, as well as signal processing in a variety of
key markets such as security, imaging, networking, gaming, and medical. This leading package of
integration and high performance allows fast time to market through easy code reuse and extensive third
party tool support.
To locate any published errata or updates for this document, refer to the ColdFire products website at
http://www.freescale.com/coldfire.
1
MCF5275 Family Configurations
Table 1. MCF5275 Family Configurations
Module
MCF5274L
MCF5275L
MCF5274
MCF5275
ColdFire Version 2 Core with EMAC (Enhanced Multiply-Accumulate Unit)
x
x
x
x
System Clock
up to 166 MHz
Performance (Dhrystone 2.1 MIPS)
up to 159
Instruction/Data Cache
16 Kbytes (configurable)
Static RAM (SRAM)
64 Kbytes
Interrupt Controllers (INTC)
2
2
2
2
Edge Port Module (EPORT)
x
x
x
x
External Interface Module (EIM)
x
x
x
x
4-channel Direct-Memory Access (DMA)
x
x
x
x
DDR SDRAM Controller
x
x
x
x
Fast Ethernet Controller (FEC)
1
1
2
2
Watchdog Timer Module (WDT)
x
x
x
x
4-channel Programmable Interval Timer Module (PIT)
x
x
x
x
32-bit DMA Timers
4
4
4
4
USB
x
x
x
x
QSPI
x
x
x
x
UART(s)
3
3
3
3
I2
C
x
x
x
x
PWM
4
4
4
4
General Purpose I/O Module (GPIO)
x
x
x
x
CIM = Chip Configuration Module + Reset Controller Module
x
x
x
x
Debug BDM
x
x
x
x
JTAG - IEEE 1149.1 Test Access Port
x
x
x
x
Hardware Encryption
—
x
—
x
Package
196 MAPBGA 196 MAPBGA 256 MAPBGA 256 MAPBGA
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Block Diagram
2
Block Diagram
The superset device in the MCF5275 family comes in a 256 Mold Array Plastic Ball Grid Array
(MAPBGA) package.
Figure 1 shows a top-level block diagram of the MCF5275, the superset device.
EIM
DDR
CHIP
SELECTS
(To/From SRAM backdoor)
QSPI
I2C_SDA
I2C_SCL
INTC0
Arbiter
TXDx
EBI
INTC1
RXDx
RTSx
CTSx
DTOUTx
FAST ETHERNET
CONTROLLER
(FEC0)
(To/From PADI)
DTINx
FEC0
UART
0
FAST ETHERNET
CONTROLLER
(FEC1)
DTIM
0
(To/From
PADI)
UART
2
UART
1
DTIM
1
I2 C
QSPI
SDRAMC
DTIM
3
DTIM
2
4 CH DMA
PADI – Pin Muxing
(To/From PADI)
FEC1
USB
PWMx
D[31:16]
A[23:0]
R/W
CS[3:0]
TA
JTAG
TAP
DACK[3:0]
BDM
DREQ[1:0]
V2 ColdFire CPU
JTAG_EN
TRST
TCLK
EMAC
DIV
TMS
MUX
TDI
TDO
JTAG_EN
TSIZ[1:0]
(To/From
PADI)
(To/From PADI)
64 Kbytes
SRAM
(8Kx16)x4
4 CH PWM
RNGA
SKHA
Cryptography
Modules
BS[3:2]
PORTS
(GPIO)
Watchdog
Timer
MDHA
TEA
16 Kbytes
CACHE
(1Kx32)x4
CIM
(To/From Arbiter backdoor)
USB 2.0
Full Speed
Edge
Port
PLL
CLKGEN
PIT0
PIT1
PIT2
PIT3
(To/From PADI) (To/From INTC)
Figure 1. MCF5275 Block Diagram
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
Features
3
Features
For a detailed feature list see the MCF5275 Reference Manual (MCF5275RM).
4
Signal Descriptions
This section describes signals that connect off chip, including a table of signal properties. For a more
detailed discussion of the MCF5275 signals, consult the MCF5275 Reference Manual (MCF5275RM).
Table 2 lists the signals for the MCF5275 in functional group order. The “Dir” column is the direction for
the primary function of the pin. Refer to Section 6, “Mechanicals/Pinouts,” for package diagrams.
NOTE
In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., A24), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO will default to their GPIO functionality.
Table 2. MCF5274 and MCF5275 Signal Information and Muxing
Signal Name
GPIO
Alternate1
Alternate2 Dir.1
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
Reset
RESET
—
—
—
I
N15
K12
RSTOUT
—
—
—
O
N14
L12
Clock
EXTAL
—
—
—
I
L16
M14
XTAL
—
—
—
O
M16
N14
CLKOUT
—
—
—
O
T12
P9
Mode Selection
CLKMOD[1:0]
—
—
—
I
N13, P13
M11, N11
RCON
—
—
—
I
P8
M6
A11, B11, C11
A8, B8, C8
External Memory Interface and Ports
A[23:21]
PADDR[7:5]
CS[6:4]
—
O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Signal Descriptions
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
O
A12, B12, C12,
A13, B13, C13,
A14, B14, C14,
B15, C15, B16,
C16, D14, D15,
E14:16, F14:16
B9, D9, C9,
C10, B10, A11,
C11, B11, A12,
D11, C12, B13,
C13, D12, E11,
D13, E12, F11,
D14, E13, F13
—
O
M1, N1, N2, N3,
P1, P2, R1, R2,
P3, R3, T3, N4,
P4, R4, T4, N5
J3, L1, K2, K3,
M1, L2, L3, L4,
K4, J4, M2, N1,
N2, M3, M4, N3
CAS[3:2]
—
O
M3, R5
K1, L5
PBUSCTL[7]
—
—
O
K1
H4
TA
PBUSCTL[6]
—
—
I
L13
K14
TEA
PBUSCTL[5]
DREQ1
—
I
T8
—
R/W
PBUSCTL[4]
—
—
O
P7
L6
TSIZ1
PBUSCTL[3]
DACK1
—
O
D16
B14
TSIZ0
PBUSCTL[2]
DACK0
—
O
G16
E14
TS
PBUSCTL[1]
DACK2
—
O
L4
H2
TIP
PBUSCTL[0]
DREQ0
—
O
P6
—
Alternate2 Dir.1
Signal Name
GPIO
Alternate1
A[20:0]
—
—
—
D[31:16]
—
—
BS[3:2]
PBS[3:2]
OE
Chip Selects
CS[7:1]
PCS[7:1]
—
—
O
D10:13, E13,
F13, N7
D8, A9, A10,
D10, B12, C14,
P4
CS0
—
—
—
O
R6
N5
DDR SDRAM Controller
DDR_CLKOUT
—
—
—
O
T7
P6
DDR_CLKOUT
—
—
—
O
T6
P5
SD_CS[1:0]
PSDRAM[7:6]
CS[3:2]
—
O
M2, T5
H3, M5
SD_SRAS
PSDRAM[5]
—
—
O
L2
H1
SD_SCAS
PSDRAM[4]
—
—
O
L1
G3
SD_WE
PSDRAM[3]
—
—
O
K2
G4
SD_A10
—
—
—
O
N6
N4
SD_DQS[3:2]
PSDRAM[2:1]
—
—
I/O
M4, P5
J2, P3
SD_CKE
PSDRAM[0]
—
—
O
L3
J1
SD_VREF
—
—
—
I
A15, T2
A13, P2
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
Signal Descriptions
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate1
Alternate2 Dir.1
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
External Interrupts Port
IRQ[7:5]
PIRQ[7:5]
—
—
I
G13, H16, H15
F14, G13, G14
IRQ[4]
PIRQ[4]
DREQ2
—
I
H14
H11
IRQ[3:2]
PIRQ[3:2]
DREQ[3:2]
—
I
J14, J13
H14, H12
IRQ1
PIRQ[1]
—
—
I
K13
J13
FEC0
FEC0_MDIO
PFECI2C[5]
I2C_SDA
U2RXD
I/O
A7
A3
FEC0_MDC
PFECI2C[4]
I2C_SCL
U2TXD
O
B7
C5
FEC0_TXCLK
PFEC0H[7]
—
—
I
C3
C1
FEC0_TXEN
PFEC0H[6]
—
—
O
D4
C3
FEC0_TXD[0]
PFEC0H[5]
—
—
O
G4
D2
FEC0_COL
PFEC0H[4]
—
—
I
A6
B4
FEC0_RXCLK
PFEC0H[3]
—
—
I
B6
B3
FEC0_RXDV
PFEC0H[2]
—
—
I
B5
C4
FEC0_RXD[0]
PFEC0H[1]
—
—
I
C6
D5
FEC0_CRS
PFEC0H[0]
—
—
I
C7
A2
FEC0_TXD[3:1]
PFEC0L[7:5]
—
—
O
E3, F3, F4
D1, E3, D3
FEC0_TXER
PFEC0L[4]
—
—
O
D3
C2
FEC0_RXD[3:1]
PFEC0L[3:1]
—
—
I
D5, C5, D6
D4, B1, B2
FEC0_RXER
PFEC0L[0]
—
—
I
C4
E4
FEC1
FEC1_MDIO
PFECI2C[3]
—
—
I/O
G1
—
FEC1_MDC
PFECI2C[2]
—
—
O
G2
—
FEC1_TXCLK
PFEC1H[7]
—
—
I
C1
—
FEC1_TXEN
PFEC1H[6]
—
—
O
D2
—
FEC1_TXD[0]
PFEC1H[5]
—
—
O
F1
—
FEC1_COL
PFEC1H[4]
—
—
I
A5
—
FEC1_RXCLK
PFEC1H[3]
—
—
I
B4
—
FEC1_RXDV
PFEC1H[2]
—
—
I
A3
—
FEC1_RXD[0]
PFEC1H[1]
—
—
I
B3
—
FEC1_CRS
PFEC1H[0]
—
—
I
A4
—
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Signal Descriptions
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
O
E1, E2, F2
—
—
O
D1
—
—
—
I
B1, B2, A2
—
—
—
I
C2
—
Alternate2 Dir.1
Signal Name
GPIO
Alternate1
FEC1_TXD[3:1]
PFEC1L[7:5]
—
—
FEC1_TXER
PFEC1L[4]
—
FEC1_RXD[3:1]
PFEC1L[3:1]
FEC1_RXER
PFEC1L[0]
I2C
I2C_SDA
PFECI2C[1]
U2RXD
—
I/O
B10
B7
I2C_SCL
PFECI2C[0]
U2TXD
—
I/O
C10
A7
—
—
DMA
DACK[3:0] and DREQ[3:0] do not have a dedicated bond pads.
Please refer to the following pins for muxing:
PCS3/PWM3 for DACK3, PCS2/PWM2 for DACK2, TSIZ1 for
DACK1, TSIZ0 for DACK0, IRQ3 for DREQ3, IRQ2 and TA for
DREQ2, TEA for DREQ1, and TIP for DREQ0.
QSPI
QSPI_CS[3:2]
PQSPI[6:5]
PWM[3:2]
DACK[3:2]
O
R13, N12
P10, N9
QSPI_CS1
PQSPI[4]
—
—
O
T14
N10
QSPI_CS0
PQSPI[3]
—
—
O
P12
M9
QSPI_CLK
PQSPI[2]
I2C_SCL
—
O
T15
L11
QSPI_DIN
PQSPI[1]
I2C_SDA
—
I
T13
M10
QSPI_DOUT
PQSPI[0]
—
—
O
R12
L10
UARTs
U2RXD
PUARTH[3]
—
—
I
T9
—
U2TXD
PUARTH[2]
—
—
O
R9
—
U2CTS
PUARTH[1]
PWM1
—
I
P9
—
U2RTS
PUARTH[0]
PWM0
—
O
R8
—
U1RXD
PUARTL[7]
—
—
I
A9
A6
U1TXD
PUARTL[6]
—
—
O
B9
D7
U1CTS
PUARTL[5]
—
—
I
C9
C7
U1RTS
PUARTL[4]
—
—
O
D9
B6
U0RXD
PUARTL[3]
—
—
I
A8
A4
U0TXD
PUARTL[2]
—
—
O
B8
A5
U0CTS
PUARTL[1]
—
—
I
C8
C6
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
7
Signal Descriptions
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate1
U0RTS
PUARTL[0]
—
Alternate2 Dir.1
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
—
O
D7
B5
USB
USB_SPEED
PUSBH[0]
—
—
I/O
G14
G11
USB_CLK
PUSBL[7]
—
—
I
G15
F12
USB_RN
PUSBL[6]
—
—
I
J16
H13
USB_RP
PUSBL[5]
—
—
I
J15
J11
USB_RXD
PUSBL[4]
—
—
I
L15
L14
USB_SUSP
PUSBL[3]
—
—
O
M13
N13
USB_TN
PUSBL[2]
—
—
O
K14
J14
USB_TP
PUSBL[1]
—
—
O
K15
J12
USB_TXEN
PUSBL[0]
—
—
O
L14
K13
Timers (and PWMs)
DT3IN
PTIMERH[3]
DT3OUT
U2RTS
I
J4
G2
DT3OUT
PTIMERH[2]
PWM3
U2CTS
O
K3
G1
DT2IN
PTIMERH[1]
DT2OUT
—
I
J2
F3
DT2OUT
PTIMERH[0]
PWM2
—
O
J3
F4
DT1IN
PTIMERL[3]
DT1OUT
—
I
H1
F1
DT1OUT
PTIMERL[2]
PWM1
—
O
H2
F2
DT0IN
PTIMERL[1]
DT0OUT
—
I
H3
E1
DT0OUT
PTIMERL[0]
PWM0
—
O
G3
E2
BDM/JTAG2
DSCLK
—
TRST
—
I
P14
P13
PSTCLK
—
TCLK
—
O
P16
P12
BKPT
—
TMS
—
I
R15
N12
DSI
—
TDI
—
I
R16
M12
DSO
—
TDO
—
O
P15
K11
JTAG_EN
—
—
—
I
R14
P11
DDATA[3:0]
—
—
—
O
P10, N10, P11, M7, N7, P8, L9
N11
PST[3:0]
—
—
—
O
T10, R10, T11,
R11
P7, L8, M8, N8
Test
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
8
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Design Recommendations
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
I
N9
N6
I
M14
—
Alternate2 Dir.1
Signal Name
GPIO
Alternate1
TEST
—
—
—
PLL_TEST
—
—
—
Power Supplies
VDDPLL
—
—
—
I
M15
M13
VSSPLL
—
—
—
I
K16
L13
VSS
—
—
—
I
A1, A10, A16,
E5, E12, F6,
F11, G7:10,
H7:10, J1,
J7:10, K7:10,
L6, L11, M5,
N16, R7, T1,
T16
F7, F8, G6:9,
H6:9, J7, J8
OVDD
—
—
—
I
E6:8, F5, F7, F8,
G5, G6, H5, H6,
J11, J12, K11,
K12, L9, L10,
L12, M9:11
E5:7, F5, F6,
H10, J9, J10,
K8:10
VDD
—
—
—
I
D8, H13, K4, N8 D6, G5, G12, L7
SD_VDD
—
—
—
I
E9:11, F9, F10, E8:10, F9, F10,
F12, G11, G12, G10, H5, J5, J6,
H11, H12, J5,
K5:7
J6, K5, K6, L5,
L7, L8, M6, M7,
M8
1
Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO
mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM.
2 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not
responsible for assigning these pins.
5
Design Recommendations
5.1
Layout
•
•
•
Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power
and ground planes for the MCF5275.
See application note AN1259 System Design and Layout Techniques for Noise Reduction in
MCU-Based Systems.
Match the PC layout trace width and routing to match trace length to operating frequency and board
impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the
PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
9
Design Recommendations
analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace
and separation. Clocks get extra separation and more precise balancing.
5.2
•
Power Supply
33uF, 0.1 µF, and 0.01 µF across each power supply
5.2.1
Supply Voltage Sequencing and Separation Cautions
DC Power Supply Voltage
Figure 2 shows situations in sequencing the I/O VDD (OVDD), SDRAM VDD (SDVDD), PLL VDD
(PLLVDD), and Core VDD (VDD).
OVDD, SDVDD
3.3V
Supplies Stable
2.5V
1.5V
SDVDD (2.5V)
VDD, PLLVDD
1
2
0
Time
Notes:
1. VDD should not exceed OVDD, SDVDD or PLLVDD by more than
0.4 V at any time, including power-up.
2. Recommended that VDD/PLLVDD should track OVDD/SDVDD up to
0.9 V, then separate for completion of ramps.
3. Input voltage must not be greater than the supply voltage (OVDD, SDVDD,
VDD, or PLLVDD) by more than 0.5 V at any time, including during power-up.
4. Use 1 ms or slower rise time for all supplies.
Figure 2. Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and OVDD is non-critical during power-up and power-down sequences.
Both SDVDD (2.5V or 3.3V) and OVDD are specified relative to VDD.
5.2.1.1
Power Up Sequence
If OVDD/SDVDD are powered up with VDD at 0 V, then the sense circuits in the I/O pads will cause all pad
output drivers connected to the OVDD/SDVDD to be in a high impedance state. There is no limit on how
long after OVDD/SDVDD powers up before VDD must powered up. VDD should not lead the OVDD,
SDVDD or PLLVDD by more than 0.4 V during power ramp-up, or there will be high current in the internal
ESD protection diodes. The rise times on the power supplies should be slower than 1 µs to avoid turning
on the internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
1. Use 1 µs or slower rise time for all supplies.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
10
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Design Recommendations
2. VDD/PLLVDD and OVDD/SDVDD should track up to 0.9 V, then separate for the completion of
ramps with OVDD/SD VDD going to the higher external voltages. One way to accomplish this is to
use a low drop-out voltage regulator.
5.2.1.2
Power Down Sequence
If VDD/PLLVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to
be in a high impedance state. There is no limit on how long after VDD and PLLVDD power down before
OVDD or SDVDD must power down. VDD should not lag OVDD, SDVDD, or PLLVDD going low by more
than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There
are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop VDD/PLLVDD to 0 V.
2. Drop OVDD/SDVDD supplies.
5.3
•
•
5.4
•
5.5
•
5.6
•
•
•
•
•
•
•
•
Decoupling
Place the decoupling capacitors as close to the pins as possible, but they can be outside the footprint
of the package.
0.1 µF and 0.01 µF at each supply input
Buffering
Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses
when excessive loading is expected. See electricals.
Pull-up Recommendations
Use external pull-up resistors on unused inputs. See pin table.
Clocking Recommendations
Use a multi-layer board with a separate ground plane.
Place the crystal and all other associated components as close to the EXTAL and XTAL (oscillator
pins) as possible.
Do not run a high frequency trace around crystal circuit.
Ensure that the ground for the bypass capacitors is connected to a solid ground trace.
Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop currents
in the vicinity of the crystal.
Tie the ground pin to the most solid ground in the system.
Do not connect the trace that connects the oscillator and the ground plane to any other circuit
element. This tends to make the oscillator unstable.
Tie XTAL to ground when an external oscillator is clocking the device.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
11
Design Recommendations
5.7
Interface Recommendations
5.7.1
DDR SDRAM Controller
5.7.1.1
SDRAM Controller Signals in Synchronous Mode
Table 3 shows the behavior of SDRAM signals in synchronous mode.
Table 3. Synchronous DRAM Signal Connections
Signal
Description
SD_SRAS
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be
latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM
SD_SRAS. Do not confuse SD_SRAS with the DRAM controller’s SDRAM_CS[1:0], which
should not be interfaced to the SDRAM SD_SRAS signals.
SD_SCAS
Synchronous column address strobe. Indicates a valid column address is present and can be
latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled
SD_SCAS on the SDRAM.
SD_WE
DRAM read/write. Asserted for write operations and negated for read operations.
SD_CS[1:0]
Row address strobe. Select each memory block of SDRAMs connected to the MCF5275. One
SDRAM_CS signal selects one SDRAM block and connects to the corresponding CS signals.
SD_CKE
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of
SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can
enter a power-down mode where operations are suspended or they can enter self-refresh
mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external
multiplexing, setting COC allows SD_CKE to provide command-bit functionality.
BS[3:2]
Column address strobe. For synchronous operation, BS[3:2] function as byte enables to the
SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs.
DDR_CLKOUT
5.7.1.2
Bus clock output. Connects to the CLK input of SDRAMs.
Address Multiplexing
See the SDRAM controller module chapter in the MCF5275 Reference Manual for details on address
multiplexing.
5.7.2
Ethernet PHY Transceiver Connection
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10
Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3
standard defines and the FEC module supports 18 signals. These are shown in Table 4.
Table 4. MII Mode
Signal Description
MCF5275 Pin
Transmit clock
FECn_TXCLK
Transmit enable
FECn_TXEN
Transmit data
FECn_TXD[3:0]
Transmit error
FECn_TXER
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
12
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Design Recommendations
Table 4. MII Mode (continued)
Signal Description
MCF5275 Pin
Collision
FECn_COL
Carrier sense
FECn_CRS
Receive clock
FECn_RXCLK
Receive enable
FECn_RXDV
Receive data
FECn_RXD[3:0]
Receive error
FECn_RXER
Management channel clock
FECn_MDC
Management channel serial data
FECn_MDIO
The serial mode interface operates in what is generally referred to as AMD mode. The MCF5275
configuration for seven-wire serial mode connections to the external transceiver are shown in Table 5.
Table 5. Seven-Wire Mode Configuration
Signal Description
MCF5275 Pin
Transmit clock
FECn_TXCLK
Transmit enable
FECn_TXEN
Transmit data
FECn_TXD[0]
Collision
FECn_COL
Receive clock
FECn_RXCLK
Receive enable
FECn_RXDV
Receive data
FECn_RXD[0]
Unused, configure as PB14
FECn_RXER
Unused input, tie to ground
FECn_CRS
Unused, configure as PB[13:11]
FECn_RXD[3:1]
Unused output, ignore
FECn_TXER
Unused, configure as PB[10:8]
FECn_TXD[3:1]
Unused, configure as PB15
FECn_MDC
Input after reset, connect to ground
FECn_MDIO
Refer to the M5275EVBevaluation board user’s manual for an example of how to connect an external
PHY. Schematics for this board are accessible at the MCF5275 site by navigating to:
http://www.freescale.com/coldfire.
5.7.3
BDM
Use the BDM interface as shown in the M5275EVB evaluation board user’s manual. The schematics for
this board are accessible at the MCF5275 site by navigating to: http://www.freescale.com/coldfire.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
13
Mechanicals/Pinouts
6
Mechanicals/Pinouts
6.1
256 MAPBGA Pinout
Figure 3 is a consolidated MCF5274/75 pinout for the 256 MAPBGA package. Table 2 lists the signals by
group and shows which signals are muxed and bonded on each of the device packages.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
VSS
FEC1_
RXD1
FEC1_
RXDV
FEC1_
CRS
FEC1_
COL
FEC0_
COL
FEC0_
MDIO
U0RXD
U1RXD
VSS
A23
A20
A17
A14
SD_
VREF
VSS
A
B
FEC1_
RXD3
FEC1_
RXD2
FEC1_
RXD0
FEC1_
RXCLK
FEC0_
RXDV
FEC0_
RXCLK
FEC0_
MDC
U0TXD
U1TXD
I2C_
SDA
A22
A19
A16
A13
A11
A9
B
C
FEC1_
TXCLK
FEC1_
RXER
FEC0_
TXCLK
FEC0_
RXER
FEC0_
RXD2
FEC0_
RXD0
FEC0_
CRS
U0CTS
U1CTS
I2C_
SCL
A21
A18
A15
A12
A10
A8
C
D
FEC1_
TXER
FEC1_
TXEN
FEC0_
TXER
FEC0_
TXEN
FEC0_
RXD3
FEC0_
RXD1
U0RTS
VDD
U1RTS
CS7
CS6
CS5
CS4
A7
A6
TSIZ1
D
E
FEC1_
TXD3
FEC1_
TXD2
FEC0_
TXD3
NC
VSS
OVDD
OVDD
OVDD SD_VDD SD_VDD SD_VDD
VSS
CS3
A5
A4
A3
E
F
FEC1_
TXD0
FEC1_
TXD1
FEC0_
TXD2
FEC0_
TXD1
OVDD
VSS
OVDD
OVDD SD_VDD SD_VDD
SD_VDD
CS2
A2
A1
A0
F
G
FEC1_
MDIO
FEC1_
MDC
DT0OUT
FEC0_
TXD0
OVDD
OVDD
VSS
VSS
VSS
VSS
SD_VDD SD_VDD
IRQ7
USB_
SPEED
USB_
CLK
TSIZ0
G
H
DT1IN
DT1OUT
DT0IN
NC
OVDD
OVDD
VSS
VSS
VSS
VSS
SD_VDD SD_VDD
VDD
IRQ4
IRQ5
IRQ6
H
J
VSS
DT2IN
DT2OUT
DT3IN
SD_VDD
SD_VDD
VSS
VSS
VSS
VSS
OVDD
OVDD
IRQ2
IRQ3
K
OE
SD_WE
DT3OUT
VDD
SD_VDD
SD_VDD
VSS
VSS
VSS
VSS
OVDD
OVDD
IRQ1
L
SD_
SCAS
SD_
SRAS
SD_CKE
TS
SD_VDD
VSS
SD_VDD SD_VDD OVDD
OVDD
VSS
OVDD
TA
USB_
TXEN
USB_
RXD
EXTAL
L
M
D31
SD_CS1
BS3
SD_DQS3
VSS
SD_VDD
SD_VDD SD_VDD OVDD
OVDD
OVDD
NC
USB_
SUSP
PLL_
TEST
VDDPLL
XTAL
M
N
D30
D29
D28
D20
D16
SD_A10
CS1
VDD
DDATA2 DDATA0
QSPI_
CS2
CLK
MOD1
RSTOUT RESET
VSS
N
P
D27
D26
D23
D19
SD_DQS2
TIP
R/W
RCON
U2CTS DDATA3 DDATA1
QSPI_
CS0
CLK
MOD0
TRST/
DSCLK
TDO/
DSO
TCLK/
P
PSTCLK
R
D25
D24
D22
D18
BS2
CS0
VSS
U2RTS
U2TXD
PST2
PST0
QSPI_
DOUT
QSPI_
CS3
JTAG_
EN
TMS/
BKPT
TDI/DSI R
T
VSS
SD_
VREF
D21
D17
SD_CS0
TEA
U2RXD
PST3
PST1
CLKOUT
QSPI_
DIN
QSPI_
CS1
QSPI_
CLK
VSS
1
2
3
4
5
8
9
10
11
12
13
14
15
16
DDR_CLK DDR_CLK
OUT
OUT
6
7
TEST
VSS
USB_RP USB_RN J
USB_TN USB_TP VSSPLL K
Figure 3. MCF5274 and MCF5275 Pinout (256 MAPBGA)
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
14
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
T
Mechanicals/Pinouts
6.2
Package Dimensions - 256 MAPBGA
Figure 6 shows MCF5275 256 MAPBGA package dimensions.
X
D
M
LASER MARK FOR PIN A1
IDENTIFICATION IN
THIS AREA
Y
5
K
A
0.30 Z
A2
A1
256X
Z
E
4
0.15 Z
DETAIL K
ROTATED 90 °CLOCKWISE
M
0.20
15X
e
S
16151413121110
15X
e
METALIZED MARK FOR
PIN A1 IDENTIFICATION
IN THIS AREA
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
S
256X
b
3
0.25
M
Z X Y
0.10
M
Z
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER,
PARALLEL TO DATUM PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
5. PARALLELISM MEASUREMENT SHALL
EXCLUDE ANY EFFECT OF MARK ON TOP
SURFACE OF PACKAGE.
VIEW M-M
DIM
A
A1
A2
b
D
E
e
S
MILLIMETERS
MIN
MAX
1.25
1.60
0.27
0.47
1.16 REF
0.40
0.60
17.00 BSC
17.00 BSC
1.00 BSC
0.50 BSC
Figure 4. 256 MAPBGA Package Dimensions
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
15
Mechanicals/Pinouts
6.3
196 MAPBGA Pinout
Figure 5 is a consolidated MCF5274L/75L pinout for the 196 MAPBGA package. Table 2 lists the signals
by group and shows which signals are muxed and bonded on each of the device packages.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
NC
FEC0_
CRS
FEC0_
MDIO
U0RXD
U0TXD
U1RXD
I2C_SCL
A23
CS6
CS5
A15
A12
SD_
VREF
NC
A
B
FEC0_
RXD2
FEC0_
RXD1
FEC0_
RXCLK
FEC0_
COL
U0RTS
U1RTS
I2C_SDA
A22
A20
A16
A13
CS3
A9
TSIZ1
B
C
FEC0_
TXCLK
FEC0_
TXER
FEC0_
TXEN
FEC0_
RXDV
FEC0_
MDC
U0CTS
U1CTS
A21
A18
A17
A14
A10
A8
CS2
C
D
FEC0_
TXD3
FEC0_
TXD0
FEC0_
TXD1
FEC0_
RXD3
FEC0_
RXD0
VDD
U1TXD
CS7
A19
CS4
A11
A7
A5
A2
D
E
DT0IN
DT0OUT
FEC0_
TXD2
FEC0_
RXER
OVDD
OVDD
OVDD
A6
A4
A1
TSIZ0
E
F
DT1IN
DT1OUT
DT2IN
DT2OUT
OVDD
OVDD
VSS
VSS
A3
USB_CLK
A0
IRQ7
F
G
DT3OUT
DT3IN
SD_CAS
SD_WE
VDD
VSS
VSS
VSS
VSS
SD_VDD2
USB_
SPEED
VDD
IRQ6
IRQ5
G
TS
SD_CS1
OE
SD_VDD1
VSS
VSS
VSS
VSS
OVDD
IRQ4
IRQ2
USB_RN
IRQ3
H
VSS
VSS
OVDD
OVDD
USB_RP
USB_TP
IRQ1
USB_TN
J
OVDD
OVDD
OVDD
TDO/DSO
RESET
USB_
TXEN
TA
K
QSPI_
DOUT
QSPI_CLK
RSTOUT
VSSPLL
QSPI_DIN CLKMOD1
TDI/DSI
VDDPLL
EXTAL
M
USB_
SUSP
XTAL
N
NC
P
H SD_SRAS
SD_VDD2 SD_VDD2 SD_VDD2
SD_VDD2 SD_VDD2
J
SD_CKE
SD_DQS3
D31
D22
SD_VDD1 SD_VDD1
K
BS3
D29
D28
D23
SD_VDD1 SD_VDD1 SD_VDD1
L
D30
D26
D25
D24
BS2
R/W
VDD
PST2
DDATA0
M
D27
D21
D18
D17
SD_CS0
RCON
DDATA3
PST1
QSPI_
CS0
N
D20
D19
D16
SD_A10
CS0
TEST
DDATA2
PST0
QSPI_
CS2
QSPI_
CS1
CLKMOD0 TMS/BKPT
P
NC
SD_
VREF
SD_DQS2
CS1
PST3
DDATA1
CLKOUT
QSPI_
CS3
JTAG_EN
1
2
3
4
7
8
9
10
11
DDR_CLK DDR_CLK
OUT
OUT
5
6
TCLK/PST TRST/DSC
CLK
LK
12
13
USB_RXD L
14
Figure 5. MCF5274L and MCF5275L Pinout (196 MAPBGA)
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
16
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Mechanicals/Pinouts
6.4
Package Dimensions - 196 MAPBGA
Figure 6 shows MCF5275 196 MAPBGA package dimensions.
X
D
Y
Laser mark for pin 1
identification in
this area
NOTES:
1. Dimensions are in millimeters.
2. Interpret dimensions and tolerances
per ASME Y14.5M, 1994.
3. Dimension b is measured at the
maximum solder ball diameter,
parallel to datum plane Z.
4. Datum Z (seating plane) is defined
by the spherical crowns of the solder
balls.
5. Parallelism measurement shall
exclude any effect of mark on top
surface of package.
M
K
E
Millimeters
DIM
Min
Max
A
1.25
1.60
A1
0.27
0.47
A2
M
b
TOL
13X e
S
14 13 12 11 10 9
6
5
4
3
2
Metalized mark for
pin 1 identification
in this area
1
1.16 REF
0.45
0.55
D
15.00 BSC
E
15.00 BSC
e
1.00 BSC
S
0.50 BSC
A
B
C
5
D
S
E
13X e
F
A
0.20 Z
A2
G
H
J
A1
K
L
M
Z
4
0.10 Z
196X
Detail K
Rotated 90° Clockwise
N
P
3
196X
b
View M-M
0.15 Z X Y
0.08 Z
Figure 6. 196 MAPBGA Package Dimensions
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
17
Ordering Information
7
Ordering Information
Table 6. Orderable Part Numbers
8
Freescale Part
Number
Description
Speed
Temperature
MCF5274LVM133
MCF5274L RISC Microprocessor, 196 MAPBGA
133MHz
0° to +70° C
MCF5274LVM166
MCF5274L RISC Microprocessor, 196 MAPBGA
166MHz
0° to +70° C
MCF5274VM133
MCF5274 RISC Microprocessor, 256 MAPBGA
133MHz
0° to +70° C
MCF5274VM166
MCF5274 RISC Microprocessor, 256 MAPBGA
166MHz
0° to +70° C
MCF5275LCVM133
MCF5275L RISC Microprocessor, 196 MAPBGA
133MHz
-40° to +85° C
MCF5275LCVM166
MCF5275L RISC Microprocessor, 196 MAPBGA
166MHz
-40° to +85° C
MCF5275CVM133
MCF5275 RISC Microprocessor, 256 MAPBGA
133MHz
-40° to +85° C
MCF5275CVM166
MCF5275 RISC Microprocessor, 256 MAPBGA
166MHz
-40° to +85° C
Preliminary Electrical Characteristics
This appendix contains electrical specification tables and reference timing diagrams for the MCF5275
microcontroller unit. This section contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications of MCF5275.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however
for production silicon these specifications will be met. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this appendix supersede any values found in the
module specifications.
8.1
Maximum Ratings
Table 7. Absolute Maximum Ratings1, 2
Rating
Symbol
Value
Unit
VDD
– 0.5 to +2.0
V
I/O Pad Supply Voltage (3.3V)
OVDD
– 0.3 to +4.0
V
Memory Interface SSTL 2.5V Pad Supply Voltage
SDVDD
– 0.3 to + 2.8
V
Memory Interface SSTL 3.3V Pad Supply Voltage
SDVDD
– 0.3 to +4.0
V
PLL Supply Voltage
VDDPLL
– 0.3 to +4.0
V
VIN
– 0.3 to + 4.0
V
EXTAL pin voltage
VEXTAL
0 to 3.3
V
XTAL pin voltage
VXTAL
0 to 3.3
V
Core Supply Voltage
Digital Input Voltage 3
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
18
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 7. Absolute Maximum Ratings1, 2 (continued)
Rating
Instantaneous Maximum Current
Single pin limit (applies to all pins) 4, 5
Operating Temperature Range (Packaged)
Storage Temperature Range
1
2
3
4
5
8.2
Symbol
Value
Unit
ID
25
mA
TA
(TL - TH)
– 40 to 85
°C
Tstg
– 65 to 150
°C
Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings
are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond those
listed may affect device reliability or cause permanent damage to the device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS or O VDD).
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use
the larger of the two values.
All functional non-supply pins are internally clamped to VSS and O VDD.
Power supply must maintain regulation within operating O VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > O VDD) is greater than IDD, the
injection current may flow out of O VDD and could result in external power supply going out of
regulation. Insure external O VDD load will shunt current greater than maximum injection current. This
will be the greatest risk when the MCU is not consuming power (ex; no clock).Power supply must
maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions.
Thermal Characteristics
Table 8 lists thermal resistance values
Table 8. Thermal characteristics
Characteristic
Symbol
256MBGA
196MBGA
Unit
Four layer board (2s2p)
θJMA
261,2
321,2
°C/W
Four layer board (2s2p)
θJMA
231,2
291,2
°C/W
Junction to board
θJB
153
3
20
°C/W
Junction to case
θJC
104
104
°C/W
Junction to top of package
Ψjt
21,5
21,5
°C/W
Tj
105
105
oC
Junction to ambient, natural convection
Junction to ambient (@200 ft/min)
Natural convection
Maximum operating junction temperature
θJMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of θJmA and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures
can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature
specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power
dissipation, and the method described in EIA/JESD Standard 51-2.
2
Per JEDEC JESD51-6 with the board horizontal.
3
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
4 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
1
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
19
Preliminary Electrical Characteristics
5
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
in conformance with Psi-JT.
The average chip-junction temperature (TJ) in °C can be obtained from:
T J = T A + ( P D × Θ JMA ) (1)
Where:
TA
= Ambient Temperature, °C
ΘJMA
= Package Thermal Resistance, Junction-to-Ambient, °C/W
PD
= PINT + PI/O
PINT
= IDD × VDD, Watts - Chip Internal Power
PI/O
= Power Dissipation on Input and Output Pins — User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is
neglected) is:
P D = K ÷ ( T J + 273°C )
(2)
Solving equations 1 and 2 for K gives:
K = PD × (TA + 273 °C) + ΘJMA × PD 2 (3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at
equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1)
and (2) iteratively for any value of TA.
8.3
ESD Protection
Table 9. ESD Protection Characteristics1, 2
Characteristics
ESD Target for Human Body Model
ESD Target for Machine Model
Symbol
Value
Units
HBM
2000
V
MM
200
V
HBM Circuit Description
Rseries
1500
Ω
C
100
pF
MM Circuit Description
Rseries
0
Ω
pF
C
200
Number of pulses per pin (HBM)
positive pulses
negative pulses
—
—
1
1
Number of pulses per pin (MM)
positive pulses
negative pulses
—
—
3
3
Interval of Pulses
—
1
—
—
sec
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive
Grade Integrated Circuits.
2
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the
device specification requirements. Complete DC parametric and functional testing is
performed per applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
20
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
8.4
DC Electrical Specifications
Table 10. DC Electrical Specifications1
Characteristic
Symbol
Min
Max
Unit
VDD
1.4
1.6
V
I/O Pad Supply Voltage
OVDD
3.0
3.6
V
SSTL I/O Pad Supply Voltage
SDVDD
2.3
2.7
V
SSTL I/O Pad Supply Voltage
Core Supply Voltage
SDVDD
3.0
3.6
V
SSTL Memory pads reference voltage (SD VDD = 2.5V)
VREF
0.5 SD VDD
—2
V
SSTL Memory pads reference voltage (SD VDD = 3.3V)
VREF
0.45 SD VDD
—2
V
VIH
0.7 x OVDD
3.6
V
Input High Voltage 3.3V I/O Pads
Input Low Voltage 3.3V I/O Pads
VIL
VSS – 0.3
0.35 x OVDD
V
Output High Voltage 3.3V I/O Pads
IOH = –2.0 mA
VOH
OVDD - 0.5
—
V
Output Low Voltage 3.3V I/O Pads
IOL = 2.0mA
VOL
—
0.5
V
VHYS
0.06 x VDD
—
mV
VIH
VREF + 0.3
SDVDD + 0.3
V
Input Hysteresis 3.3V I/O Pads
Input High Voltage SSTL 3.3V/2.5V3
Input Low Voltage SSTL
3.3V/2.5V3
VIL
VSS - 0.3
VREF - 0.3
V
Output High Voltage SSTL 3.3V/2.5V4
IOH = –5.0 mA
VOH
SDVDD - 0.25V
—
V
Output Low Voltage SSTL 3.3V/2.5V4
IOL = 5.0 mA
VOL
—
0.35
V
Input Leakage Current
Vin = VDD or VSS, Input-only pins
Iin
-1.0
1.0
µA
High Impedance (Off-State) Leakage Current
Vin = VDD or VSS, All input/output and output pins
IOZ
-1.0
1.0
µA
Weak Internal Pull Up Device Current, tested at VIL Max.5
IAPU
-10
-130
µA
—
—
7
7
6
Input Capacitance
All input-only pins
All input/output (three-state) pins
Load Capacitance7
Low Drive Strength
High Drive Strength
Cin
pF
pF
CL
Core Operating Supply Current 8
Master Mode
WAIT
DOZE
STOP
IDD
I/O Pad Operating Supply Current
Master Mode
Low Power Modes
OIDD
DC Injection Current 3, 9, 10, 11
VNEGCLAMP =VSS– 0.3 V, VPOSCLAMP = VDD + 0.3
Single Pin Limit
Total MCU Limit, Includes sum of all stressed pins
25
50
—
—
—
—
175
15
10
100
mA
mA
mA
µA
—
—
250
250
mA
µA
IIC
mA
-1.0
-10
1.0
10
1
Refer to Table 11 for additional PLL specifications.
VREF is specified as a nominal value only instead of a range, so no maximum value is listed.
3 This specification is guaranteed by design and is not 100% tested.
2
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
21
Preliminary Electrical Characteristics
4
The actual VOH and VOL values for SSTL pads are dependent on the termination and drive strength used. The specifications
numbers assume no parallel termination.
5
Refer to the MCF5274 signals chapter for pins having weak internal pull-up devices.
6
This parameter is characterized before qualification rather than 100% tested.
7
pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces
require transmission line analysis to determine proper drive strength and termination.
8
Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load.
9
All functional non-supply pins are internally clamped to VSS and their respective VDD.
10
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
11
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Insure external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, system clock is not
present during the power-up sequence until the PLL has attained lock.
8.5
Oscillator and Phase Lock Loop (PLLMRFM) Electrical
Specifications
Table 11. PLL Electrical Specifications1
Characteristic
PLL Reference Frequency Range
Crystal reference
External reference
1:1 Mode (NOTE: fsys/2 = 2 × fref_1:1)
Loss of Reference Frequency 3, 5
Crystal Start-up Time
Min
Max
fref_crystal
fref_ext
fref_1:1
8
8
24
25
25
83
4, 5
5, 6
83
83
MHz
MHz
fLOR
100
1000
kHz
fSCM
TBD
TBD
MHz
tcst
—
10
ms
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
—
TBD
5
30
pF
—
750
µs
—
—
11
750
ms
µs
EXTAL Input Low Voltage
Crystal Mode
All other modes (Dual Controller (1:1), Bypass, External)
VILEXT
VILEXT
XTAL Output High Voltage
IOH = 1.0 mA
VOH
XTAL Output Low Voltage
IOL = 1.0 mA
VOL
XTAL Load Capacitance7
tlpll
Time 6, 9
Power-up To Lock
With Crystal Reference
Without Crystal Reference10
MHz
0
fref / 32
VIHEXT
VIHEXT
PLL Lock Time
166
fsys/2
EXTAL Input High Voltage
Crystal Mode
All other modes (Dual Controller (1:1), Bypass, External)
8
Unit
MHz
fcore
Core frequency
CLKOUT Frequency 2
External reference
On-Chip PLL Frequency
Self Clocked Mode Frequency
Symbol
V
V
V
V
tlplk
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
22
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 11. PLL Electrical Specifications1 (continued)
Characteristic
Symbol
Min
Max
Unit
tskew
-1
1
ns
tdc
40
60
% fsys/2
Frequency un-LOCK Range
fUL
-3.8
4.1
% fsys/2
Frequency LOCK Range
fLCK
-1.7
2.0
% fsys/2
—
—
5
.01
% fsys/2
1:1 Mode Clock Skew (between CLKOUT and EXTAL) 11
Duty Cycle of reference
5
5, 6, 9,12, 13
CLKOUT Period Jitter,
Measured at fsys/2 Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter (Averaged over 2 ms interval)
Cjitter
Frequency Modulation Range Limit14, 15
(fsys/2Max must not be exceeded)
Cmod
0.8
2.2
% fsys/2
ICO Frequency. fico = fref * 2 * (MFD+2)16
fico
48
83
MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
8.6
All values given are initial design targets and subject to change.
All internal registers retain data at 0 Hz.
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self
clocked mode.
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below
fLOR with default MFD/RFD settings.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
Load Capacitance determined from crystal manufacturer specifications and will include circuit board parasitics.
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
Assuming a reference is available at power up, lock time is measured from the time VDD and VDDPLL are valid to
RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time
must be added to the PLL lock time to determine the total start-up time.
tlpll = (64 * 4 * 5 + 5 x τ) x Tref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and τ = 1.57x10-6 x 2(MFD + 2)
PLL is operating in 1:1 PLL mode.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the jitter percentage for a given interval.
Based on slow system clock of 33MHz maximum frequency.
Modulation percentage applies over an interval of 10µs, or equivalently the modulation rate is 100KHz.
Modulation rate selected must not result in fsys/2 value greater than the fsys/2 maximum specified value. Modulation
range determined by hardware design.
fsys/2 = fico / (2 * 2RFD)
External Interface Timing Characteristics
Table 12 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.
All other timing relationships can be derived from these values.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
23
Preliminary Electrical Characteristics
Table 12. Processor Bus Input Timing Specifications
Characteristic1
Name
B0
CLKOUT
Symbol
Min
Max Unit
tCYC
12
—
ns
tCVCH
9
—
ns
Control Inputs
B1a
Control input valid to CLKOUT high2
3
B1b
BKPT valid to CLKOUT high
tBKVCH
9
—
ns
B2a
CLKOUT high to control inputs invalid2
tCHCII
0
—
ns
B2b
CLKOUT high to asynchronous control input BKPT invalid3
tBKNCH
0
—
ns
Data Inputs
B4
Data input (D[31:16]) valid to CLKOUT high
tDIVCH
4
—
ns
B5
CLKOUT high to data input (D[31:16]) invalid
tCHDII
0
—
ns
1
Timing specifications have been indicated taking into account the full drive strength for the pads.
TEA and TA pins are being referred to as control inputs.
3 Refer to figure A-19.
2
Timings listed in Table 12 are shown in Figure 7.
* The timings are also valid for inputs sampled on the negative clock edge.
CLKOUT (83MHz)
TSETUP
Input Setup And Hold
Input Rise Time
Input Fall Time
CLKOUT
Invalid
THOLD
Valid
Vh = VIH
Vl = VIL
Vh = VIH
Invalid
trise
tfall
Vl = VIL
B4
B5
Inputs
Figure 7. General Input Timing Requirements
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
24
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
8.7
Processor Bus Output Timing Specifications
Table 13 lists processor bus output timings.
Table 13. External Bus Output Timing Specifications
Name
Characteristic
Symbol
Min
Max
Unit
Control Outputs
B6a
CLKOUT high to chip selects (CS[7:0]) valid 1
tCHCV
—
0.5tCYC + 5.5
ns
B6b
CLKOUT high to byte enables (BS[3:2]) valid2
tCHBV
—
0.5tCYC + 5.5
ns
B6c
CLKOUT high to output enable (OE) valid3
tCHOV
—
0.5tCYC + 5.5
ns
B7
CLKOUT high to control output (BS[3:2], OE) invalid
tCHCOI
0.5tCYC + 1.0
—
ns
B7a
CLKOUT high to chip selects invalid
tCHCI
0.5tCYC + 1.0
—
ns
Address and Attribute Outputs
B8
CLKOUT high to address (A[23:0]) and control (TS,
TSIZ[1:0], TIP, R/W) valid
tCHAV
—
9
ns
B9
CLKOUT high to address (A[23:0]) and control (TS,
TSIZ[1:0], TIP, R/W) invalid
tCHAI
1.0
—
ns
Data Outputs
B11
CLKOUT high to data output (D[31:16]) valid
tCHDOV
—
9
ns
B12
CLKOUT high to data output (D[31:16]) invalid
tCHDOI
1.0
—
ns
B13
CLKOUT high to data output (D[31:16]) high impedance
tCHDOZ
—
9
ns
1
CS transitions after the falling edge of CLKOUT.
BS transitions after the falling edge of CLKOUT.
3
OE transitions after the falling edge of CLKOUT.
2
Read/write bus timings listed in Table 13 are shown in Figure 8, Figure 9, and Figure 10.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
25
Preliminary Electrical Characteristics
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT
B7a
B7a
CSn
A[23:0]
TSIZ[1:0]
TS
B6a
B6a
B8
B8
B8
B9
B9
B9
B8
TIP
B9
B8
B6c
B0
B7
OE
B8
B9
R/W (H)
B6b
B6b
BS[3:2]
D[31:16]
B7
B7
B11
B4
B5
B12
B13
TA (H)
TEA (H)
Figure 8. Read/Write (Internally Terminated) SRAM Bus Timing
Figure 9 shows a bus cycle terminated by TA showing timings listed in Table 13.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
26
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
S0
S1
S2
S3
S4
S5
S0
S1
CLKOUT
B6a
CSn
B7a
B8
B9
A[23:0]
TSIZ[1:0]
B8
B9
TS
B8
B9
TIP
B6c
OE
B7
R/W (H)
B6b
BS[3:2]
B7
B5
B4
D[31:16]
B2a
TA
B1a
TEA (H)
Figure 9. SRAM Read Bus Cycle Terminated by TA
Figure 10 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 13.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
27
Preliminary Electrical Characteristics
S0
S1
S2
S4
S3
S5
S0
S1
CLKOUT
B6a
B7a
CSn
B8
B9
A[23:0]
TSIZ[1:0]
B8
TS
B9
B8
TIP
B9
B6c
B7
OE
R/W (H)
B6b
B7
BS[3:2]
D[31:16]
TA (H)
B1a
TEA
B2a
Figure 10. SRAM Read Bus Cycle Terminated by TEA
8.8
DDR SDRAM AC Timing Characteristics
The DDR SDRAM controller uses SSTL2 and I/O drivers. Either Class I or Class II drive strength is
available and is user programmable. DDR Clock timing specifications are given in Table 14 and Figure 11.
Table 14. DDR Clock Timing Specifications1
Symbol
Characteristic
Min
Max
Unit
VMP
Clock output mid-point voltage
1.05
1.45
V
VOUT
Clock output voltage level
-0.3
SDVDD + 0.3
V
VID
Clock output differential voltage (peak to peak swing)
0.7
SDVDD + 0.6
V
VIX
Clock crossing point voltage
1.05
1.45
V
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
28
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
1
SD VDD is nominally 2.5V.
SDCLK
VIX
VMP
VIX
VID
SDCLK
Figure 11. DDR Clock Timing Diagram
When using the DDR SDRAM controller the timing numbers in Table 15 must be followed to properly
latch or drive data onto the memory bus. All timing numbers are relative to the two DQS byte lanes.
Table 15. DDR Timing
Characteristic1
NUM
Frequency of operation
1
2
3
4
5
6
7
Symbol
2
Min
Max
Unit
TBD
83
MHz
DD1
Clock Period (DDR_CLKOUT)
tCK
12
TBD
ns
DD2
Pulse Width High3
tCKH
0.45
0.55
tCK
DD3
Pulse Width Low3
tCKl
0.45
0.55
tCK
DD4
DDR_CLKOUT high to DDR address, SD_CKE,
SD_CS[1:0], SD_SCAS, SD_SRAS, SD_WE valid
tCMV
—
0.5 x tCK + 1
ns
DD5
DDR_CLKOUT high to DDR address, SD_CKE, SD_CS,
SD_SCAS, SD_SRAS, SD_WE invalid
tCMH
2
—
ns
DD6
Write command to first SD_DQS Latching Transition
tDQSS
—
1.25
tCK
DD7
SD_DQS high to Data and DM valid (write) - setup4,5
tQS
1.5
—
ns
tQH
1
—
ns
tIS
—
1
ns
hold4
DD8
SD_DQS high to Data and DM invalid (write) -
DD9
SD_DQS high to Data valid (read) - setup6
DD10
SD_DQS high to Data invalid (read) -
hold7
DD11
SD_DQS falling edge to CLKOUT high - setup
DD12
DD13
DD14
DQS input read postamble width (tRPST)
DD15
DQS output write preamble width (tWPRE)
DD16
DQS output write postamble width (tWPST)
tWPST
tIH
0.25 x tCK + 1
—
ns
tDSS
0.5
—
ns
SD_DQS falling edge to CLKOUT high - hold
tDSH
0.5
—
ns
DQS input read preamble width (tRPRE)
tRPRE
0.9
1.1
tCK
tRPST
0.4
0.6
tCK
tWPRE
0.25
—
tCK
0.4
0.6
tCK
All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
DDR_CLKOUT operates at half the frequency of the PLLMRFM output and the ColdFire core.
tCKH + tCKL must be less than or equal to tCK.
D[31:24] is relative to SD_DQS3 and D[23:16] is relative to SD_DQS2.
The first data beat will be valid before the first rising edge of SD_DQS and after the SD_DQS write preamble. The
remaining data beats will be valid for each subsequent SD_DQS edge
Data input skew is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the last data
line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or
other factors).
Data input hold is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the first data
line becomes invalid.
Figure 13 shows a DDR SDRAM write cycle.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
29
Preliminary Electrical Characteristics
DDR_CLKOUT
VIX
VMP
VIX
VID
DDR_CLKOUT
Figure 12. DDR_CLKOUT and DDR_CLKOUT Crossover Timing
DD1
DD2
DDR_CLKOUT
DD3
DDR_CLKOUT
DD5
SD_CSn,SD_WE,
SD_SRAS,SD_SCAS
CMD
DD6
DD4
A[13:0]
ROW
COL
DD7
DM[3:2]
DD8
SD_DQS[3:2]
DD7
D[31:16]
WD1 WD2 WD3 WD4
DD8
Figure 13. DDR Write Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
30
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
DD1
DD2
CLKOUT
DD3
CLKOUT
CL=2
DD5
SD_CSn,SD_WE,
SD_SRAS,SD_SCAS
CMD
CL=2.5
DD4
A[13:0]
ROW
COL
DQS Read
Preamble
CL = 2
SD_DQS[3:2]
DD9
DQS Read
Postamble
DD10
D[31:16]
WD1 WD2 WD3 WD4
DQS Read
DQS Read
Preamble
Postamble
CL = 2.5
SD_DQS[3:2]
D[31:16]
WD1 WD2 WD3 WD4
Figure 14. DDR Read Timing
8.9
General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR Control, TIMERS, UARTS, FEC0, FEC1,
Interrupts and USB interfaces. When in GPIO mode the timing specification for these pins is given in
Table 16 and Figure 15.
Table 16. GPIO Timing
NUM
Characteristic
Symbol
Min
Max
Unit
G1
CLKOUT High to GPIO Output Valid
tCHPOV
—
10
ns
G2
CLKOUT High to GPIO Output Invalid
tCHPOI
1.0
—
ns
G3
GPIO Input Valid to CLKOUT High
tPVCH
9
—
ns
G4
CLKOUT High to GPIO Input Invalid
tCHPI
1.5
—
ns
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
31
Preliminary Electrical Characteristics
CLKOUT
G2
G1
GPIO Outputs
G4
G3
GPIO Inputs
Figure 15. GPIO Timing
8.10
Reset and Configuration Override Timing
Table 17. Reset and Configuration Override Timing
(VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1
NUM
1
2
Characteristic
Symbol
Min
Max
Unit
R1
RESET Input valid to CLKOUT High
tRVCH
9
—
ns
R2
CLKOUT High to RESET Input invalid
tCHRI
1.5
—
ns
tRIVT
5
—
tCYC
2
R3
RESET Input valid Time
R4
CLKOUT High to RSTOUT Valid
tCHROV
—
10
ns
R5
RSTOUT valid to Config. Overrides valid
tROVCV
0
—
ns
R6
Configuration Override Setup Time to RSTOUT invalid
tCOS
20
—
tCYC
R7
Configuration Override Hold Time after RSTOUT invalid
tCOH
0
—
ns
R8
RSTOUT invalid to Configuration Override High Impedance
tROICZ
—
1 x tCYC
ns
All AC timing is shown with respect to 50% OVDD levels unless otherwise noted.
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted
asynchronously to the system. Thus, RESET must be held a minimum of 100 ns.
CLKOUT
R1
RESET
R2
R3
R4
R4
RSTOUT
R8
R5
R6
R7
Configuration Overrides1:
(RCON, Override pins])
1. Refer to the Coldfire Integration Module (CIM) section for more information.
RESET and Configuration Override Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
32
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
8.11
Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
8.11.1
MII Receive Signal Timing (FECn_RXD[3:0], FECn_RXDV,
FECn_RXER, and FECn_RXCLK)
The receiver functions correctly up to a FECn_RXCLK maximum frequency of 25 MHz +1%. The
processor clock frequency must exceed twice the FECn_RXCLK frequency.
Table 18 lists MII receive channel timings.
Table 18. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
FECn_RXD[3:0], FECn_RXDV, FECn_RXER to
FECn_RXCLK setup
5
—
ns
M2
FECn_RXCLK to FECn_RXD[3:0], FECn_RXDV,
FECn_RXER hold
5
—
ns
M3
FECn_RXCLK pulse width high
35%
65%
FECn_RXCLK
period
M4
FECn_RXCLK pulse width low
35%
65%
FECn_RXCLK
period
Figure 16 shows MII receive signal timings listed in Table 18.
M3
M4
FECn_RXCLK (input)
FECn_RXD[3:0] (inputs)
FECn_RXDV
FECn_RXER
M1
M2
Figure 16. MII Receive Signal Timing Diagram
8.11.2
MII Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN,
FECn_TXER, FECn_TXCLK)
Table 19 lists MII transmit channel timings.
The transmitter functions correctly up to a FECn_TXCLK maximum frequency of 25 MHz +1%. The
processor clock frequency must exceed twice the FECn_TXCLK frequency.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
33
Preliminary Electrical Characteristics
Table 19. MII Transmit Channel Timing
Num
Characteristic
Min
Max
Unit
M5
FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN,
FECn_TXER invalid
5
—
ns
M6
FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN,
FECn_TXER valid
—
25
ns
M7
FECn_TXCLK pulse width high
35%
65%
FECn_TXCLK period
M8
FECn_TXCLK pulse width low
35%
65%
FECn_TXCLK period
Figure 17 shows MII transmit signal timings listed in Table 19.
M8
M7
FECn_TXCLK (input)
M5
FECn_TXD[3:0] (outputs)
FECn_TXEN
FECn_TXER
M6
Figure 17. MII Transmit Signal Timing Diagram
8.11.3
MII Async Inputs Signal Timing (FECn_CRS and FECn_COL)
Table 20 lists MII asynchronous inputs signal timing.
Table 20. MII Asynchronous Input Signal Timing
Num
M9
Characteristic
Min
Max
Unit
1.5
—
FECn_TXCLK period
FECn_CRS, FECn_COL minimum pulse width
Figure 18 shows MII asynchronous input timings listed in Table 20.
FECn_CRS
FECn_COL
M9
Figure 18. MII Async Inputs Timing Diagram
8.11.4
MII Serial Management Channel Timing (FECn_MDIO and
FECn_MDC)
Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum
MDC frequency of 2.5 MHz.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
34
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 21. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10
FECn_MDC falling edge to FECn_MDIO output invalid (minimum
propagation delay)
0
—
ns
M11
FECn_MDC falling edge to FECn_MDIO output valid (max prop delay)
—
25
ns
M12
FECn_MDIO (input) to FECn_MDC rising edge setup
10
—
ns
M13
FECn_MDIO (input) to FECn_MDC rising edge hold
0
—
ns
M14
FECn_MDC pulse width high
40%
60%
MDC period
M15
FECn_MDC pulse width low
40%
60%
MDC period
Figure 19 shows MII serial management channel timings listed in Table 21.
M14
M15
FECn_MDC (output)
M10
FECn_MDIO (output)
M11
FECn_MDIO (input)
M12
M13
Figure 19. MII Serial Management Channel Timing Diagram
8.11.5
USB Interface AC Timing Specifications
Table 22 lists USB Interface timings.
Table 22. USB Interface Timing
Num
Characteristic
Min
Max
Units
US1
USB_CLK frequency of operation
48
48
MHz
US2
USB_CLK fall time (VIH = 2.4 V to VIL = 0.5 V)
—
2
ns
US3
USB_CLK rise time (VIL = 0.5 V to VIH = 2.4 V)
—
2
ns
US4
USB_CLK duty cycle (at 0.5 x O VDD)
45
55
%
6
—
ns
Data Inputs
US5
USB_RP, USB_RN, USB_RXD valid to USB_CLK high
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
35
Preliminary Electrical Characteristics
Table 22. USB Interface Timing (continued)
Num
US6
Characteristic
Min
Max
Units
6
—
ns
USB_CLK high to USB_RP, USB_RN, USB_RXD invalid
Data Outputs
US7
USB_CLK high to USB_TP, USB_TN, USB_SUSP valid
—
12
ns
US8
USB_CLK high to USB_TP, USB_TN, USB_SUSP invalid
3
—
ns
Figure 20 shows USB interface timings listed in Table 22.
US1
USB_CLK
US8
US7
USB Outputs
US5
US6
USB Inputs
trise
Input Rise Time
Vh = VIH
Vl = VIL
Input Fall Time
Vh = VIH
Vl = VIL
tfall
Figure 20. USB Signals Timing Diagram
8.12
I2C Input/Output Timing Specifications
Table 23 lists specifications for the I2C input timing parameters shown in Figure 21.
Table 23. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I1
Start condition hold time
2 x tCYC
—
ns
I2
Clock low period
8 x tCYC
—
ns
I3
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
1
ms
I4
Data hold time
0
—
ns
I5
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
1
ms
I6
Clock high time
4 x tCYC
—
ns
I7
Data setup time
0
—
ns
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
36
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 23. I2C Input Timing Specifications between I2C_SCL and I2C_SDA (continued)
Num
Characteristic
Min
Max
Units
I8
Start condition setup time (for repeated start condition only)
2 x tCYC
—
ns
I9
Stop condition setup time
2 x tCYC
—
ns
Table 24 lists specifications for the I2C output timing parameters shown in Figure 21.
Table 24. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
I11
Characteristic
Min
Max
Units
Start condition hold time
6 x tCYC
—
ns
I2
1
Clock low period
10 x tCYC
—
ns
I3
2
I2C_SCL/I2C_SDA rise time
(VIL = 0.5 V to VIH = 2.4 V)
—
—
µs
7 x tCYC
—
ns
—
3
ns
I4 1
Data hold time
I5 3
I2C_SCL/I2C_SDA fall time
(VIH = 2.4 V to VIL = 0.5 V)
I6 1
Clock high time
10 x tCYC
—
ns
I7 1
Data setup time
2 x tCYC
—
ns
Start condition setup time (for repeated start
condition only)
20 x tCYC
—
ns
Stop condition setup time
10 x tCYC
—
ns
I8
1
I9 1
1
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed
with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in
Table 24. The I2C interface is designed to scale the actual data transition time to move it to the
middle of the I2C_SCL low period. The actual position is affected by the prescale and division
values programmed into the IFDR; however, the numbers given in Table 24 are minimum values.
2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only
actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external
signal capacitance and pull-up resistor values.
3 Specified at a nominal 50-pF load.
Figure 21 shows timing for the values in Table 23 and Table 24.
I2
SCL
I1
I6
I4
I5
I7
I8
I3
I9
SDA
Figure 21. I2C Input/Output Timings
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
37
Preliminary Electrical Characteristics
8.13
DMA Timers Timing Specifications
Table 25. Timer Module AC Timing Specifications
Characteristic 1
Name
1
Min
Max
Unit
T1
T0IN / T1IN / T2IN / T3IN cycle time
3 x tCYC
—
ns
T2
T0IN / T1IN / T2IN / T3IN pulse width
1 x tCYC
—
ns
All timing references to CLKOUT are given to its rising edge.
8.14
QSPI Electrical Specifications
Table 26. QSPI Modules AC Timing Specifications
Name
Characteristic
Min
Max
Unit
QS1
QSPI_CS[3:0] to QSPI_CLK
1
510
tCYC
QS2
QSPI_CLK high to QSPI_DOUT valid.
—
10
ns
QS3
QSPI_CLK high to QSPI_DOUT invalid (Output hold)
2
—
ns
QS4
QSPI_DIN to QSPI_CLK (Input setup)
9
—
ns
QS5
QSPI_DIN to QSPI_CLK (Input hold)
9
—
ns
QS1
QSPI_CS[3:0]
QSPI_CLK
QS2
QSPI_DOUT
QS3
QS4
QS5
QSPI_DIN
Figure 22. QSPI Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
38
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
8.15
JTAG and Boundary Scan Timing
Table 27. JTAG and Boundary Scan Timing
Characteristics1
Num
1
Symbol
Min
Max
Unit
J1
TCLK Frequency of Operation
fJCYC
DC
1/4
fsys/2
J2
TCLK Cycle Period
tJCYC
4 x tCYC
—
ns
J3
TCLK Clock Pulse Width
tJCW
26
—
ns
J4
TCLK Rise and Fall Times
tJCRF
0
3
ns
J5
Boundary Scan Input Data Setup Time to TCLK Rise
tBSDST
4
—
ns
J6
Boundary Scan Input Data Hold Time after TCLK Rise
tBSDHT
26
—
ns
J7
TCLK Low to Boundary Scan Output Data Valid
tBSDV
0
33
ns
J8
TCLK Low to Boundary Scan Output High Z
tBSDZ
0
33
ns
J9
TMS, TDI Input Data Setup Time to TCLK Rise
tTAPBST
4
—
ns
J10
TMS, TDI Input Data Hold Time after TCLK Rise
tTAPBHT
10
—
ns
J11
TCLK Low to TDO Data Valid
tTDODV
0
26
ns
J12
TCLK Low to TDO High Z
tTDODZ
0
8
ns
J13
TRST Assert Time
tTRSTAT
100
—
ns
J14
TRST Setup Time (Negation) to TCLK High
tTRSTST
10
—
ns
JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
J2
J3
J3
VIH
TCLK
(input)
J4
VIL
J4
Figure 23. Test Clock Input Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
39
Preliminary Electrical Characteristics
TCLK
VIL
VIH
J5
Data Inputs
J6
Input Data Valid
J7
Data Outputs
Output Data Valid
J8
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 24. Boundary Scan (JTAG) Timing
TCLK
VIL
VIH
J9
TDI
TMS
J10
Input Data Valid
J11
TDO
Output Data Valid
J12
TDO
J11
TDO
Output Data Valid
Figure 25. Test Access Port Timing
TCLK
14
TRST
13
Figure 26. TRST Timing
8.16
Debug AC Timing Specifications
Table 28 lists specifications for the debug AC timing parameters shown in Figure 28.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
40
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 28. Debug AC Timing Specification
166 MHz
Num
1
Characteristic
Units
Min
Max
D0
PSTCLK cycle time
—
0.5
tCYC
D1
PST, DDATA to PSTCLK setup
4
—
ns
D2
CLKOUT to PST, DDATA hold
1.0
—
ns
D3
DSI-to-DSCLK setup
1 x tCYC
—
ns
D4 1
DSCLK-to-DSO hold
4 x tCYC
—
ns
D5
DSCLK cycle time
5 x tCYC
—
ns
D6
BKPT input data setup time to PSTCLK Rise
4
—
ns
D7
BKPT input data hold time to PSTCLK Rise
1.5
—
ns
D8
PSTCLK high to BKPT high Z
0.0
10.0
ns
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input
relative to the rising edge of PSTCLK.
Figure 27 shows real-time trace timing for the values in Table 28.
PSTCLK
D1
D2
PST[3:0]
DDATA[3:0]
Figure 27. Real-Time Trace AC Timing
Figure 28 shows BDM serial port AC timing for the values in Table 28.
PSTCLK
D5
DSCLK
D3
DSI
Current
Next
D4
DSO
Past
Current
Figure 28. BDM Serial Port AC Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
41
Documentation
9
Documentation
Documentation regarding the MCF5275 and their development support tools is available from a local
Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center,
or through the Freescale web address at http://www.freescale.com/coldfire.
10
Revision History
Table 29 provides a revision history for this hardware specification.
Table 29. Document Revision History
Rev. No.
Substantive Change(s)
0
• Initial release.
1
• Added Figure 6.
1.1
• Removed duplicate information in the module description sections. The information is all in the
Signals Description Table.
1.2
• Removed Overview, Features, Signal Descriptions, Modes of Operation, and Address
Multiplexing sections. This information can be found in the MCF5275 Reference Manual.
• Removed list of documentation in Section 9, “Documentation.”. An up-to-date list is always
available on our web site.
• Changed CLKOUT -> PSTCLK in Section 8.16, “Debug AC Timing Specifications.”
• Table 10: Update VDD spec from 1.35-1.65 to 1.4-1.6.
• Table 13: Timings B6a, B6b, B6c, B7, B7a, B9, B12 updated:
B6a, B6b, B6c maximum changed from “0.5tCYC + 5” to “0.5tCYC + 5.5”
B7, B7a minimum changed from “0.5tCYC + 1.5” to “0.5tCYC + 1.0”
B9, B11 minimum changed from “1.5” to “1.0”
1.3
• Added Section 5.2.1, “Supply Voltage Sequencing and Separation Cautions.”
• Added thermal characteristics for 196 MAPBGA in Table 8.
• Updated package dimensions drawing, Figure 6.
2
• Removed second sentence from Section 8.11.1, “MII Receive Signal Timing
(FECn_RXD[3:0], FECn_RXDV, FECn_RXER, and FECn_RXCLK),” and Section 8.11.2, “MII
Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN, FECn_TXER, FECn_TXCLK),”
regarding no minimum frequency requirement for TXCLK.
• Removed third and fourth paragraphs from Section 8.11.2, “MII Transmit Signal Timing
(FECn_TXD[3:0], FECn_TXEN, FECn_TXER, FECn_TXCLK),” as this feature is not
supported on this device.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
42
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Revision History
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
43
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Document Number: MCF5275EC
Rev. 2
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Preliminary—Subject to Change Without Notice
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