Cypress CY7C09179V-12AXC 3.3 v 32 k/64 k/128 k ã 8/9 synchronous dual-port static ram Datasheet

CY7C09079V/89V/99V
CY7C09179V/89V/99V
CY7C09089V/99V
CY7C09179V/99V
3.3 V 32 K/64 K/128 K × 8/9
Synchronous Dual-Port Static RAM
3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM
Features
■
High speed clock to data access 6.5[1]/7.5[1]/9/12 ns (max.)
■
True Dual-Ported memory cells which enable simultaneous
access of the same memory location
■
3.3 V low operating power
■
Active = 115 mA (typical)
■
Flow-through and Pipelined devices
■
Standby = 10 A (typical)
■
32 K × 9 organizations (CY7C09179V)
■
Fully synchronous interface for easier operation
■
64 K × 8 organizations (CY7C09089V)
■
Burst counters increment addresses internally
■
128 K × 8/9 organizations (CY7C09099V/199V)
■
Shorten cycle times
■
3 Modes
■
Minimize bus noise
■
Flow-through
■
Supported in Flow-through and Pipelined modes
■
Pipelined
■
Dual Chip Enables for easy depth expansion
■
Burst
■
Automatic power down
■
Pipelined output mode on both ports enables fast 100 MHz
operation
■
Commercial and Industrial temperature ranges
0.35-micron CMOS for optimum speed and power
■
Available in 100-pin TQFP
■
■
Pb-free packages available
Note
1. See page 9 and page 10 for Load Conditions.
Cypress Semiconductor Corporation
Document #: 38-06043 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 25, 2011
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CY7C09089V/99V
CY7C09179V/99V
Logic Block Diagram
R/WL
R/WR
OEL
OER
CE0L
CE1L
1
0
0
0/1
1
0/1
FT/PipeL
[3]
A0–A14/15/16L
CLKL
ADSL
CNTENL
CNTRSTL
0/1
0
0
1
0/1
8/9
[2]
I/O0L–I/O7/8L
CE0R
CE1R
1
FT/PipeR
8/9
I/O
Control
[2]
I/O0R–I/O7/8R
I/O
Control
15/16/17
15/16/17
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
[3]
A0–A14/15/16R
CLKR
ADSR
CNTENR
CNTRSTR
Notes
2. I/O0–I/O7 for ×8 devices, I/O0–I/O8 for ×9 devices.
3. A0–A14 for 32K, A0–A15 for 64K, and A0–A16 for 128K devices.
Document #: 38-06043 Rev. *F
Page 2 of 28
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CY7C09089V/99V
CY7C09179V/99V
Functional Description
The CY7C09089V/99V and CY7C09179V/99V are high speed
synchronous CMOS 64 K/128 K × 8 and 32 K/128 K × 9 dual-port
static RAMs. Two ports are provided, permitting independent,
simultaneous access for reads and writes to any location in
memory.[4] Registers on control, address, and data lines enable
minimal setup and hold times. In pipelined output mode, data is
registered for decreased cycle time. Clock to data valid
tCD2 = 6.5 ns[5] (pipelined). Flow-through mode can also be used
to bypass the pipelined output register to eliminate access
latency. In flow-through mode, data is available tCD1 = 18 ns after
the address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the
LOW-to-HIGH transition of the clock signal. The internal write
pulse is self-timed to enable the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. The
use of multiple Chip Enables enables easier banking of multiple
chips for depth expansion configurations. In the pipelined mode,
one cycle is required with CE0 LOW and CE1 HIGH to reactivate
the outputs.
Counter enable inputs are provided to stall the operation of the
address input and use the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter increments on each LOW-to-HIGH transition of
that port’s clock signal. This reads/writes one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array and loops
back to the start. Counter Reset (CNTRST) is used to reset the
burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Notes
4. When writing simultaneously to the same location, the final value cannot be guaranteed.
5. See page 9 and page 10 for Load Conditions.
Document #: 38-06043 Rev. *F
Page 3 of 28
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CY7C09089V/99V
CY7C09179V/99V
Contents
Pin Configurations ........................................................... 5
Selection Guide ................................................................ 7
Pin Definitions .................................................................. 7
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
Electrical Characteristics ................................................. 8
Capacitance ...................................................................... 9
Switching Characteristics .............................................. 11
Switching Waveforms .................................................... 12
Read/Write and Enable Operation ................................. 23
Address Counter Control Operation ............................. 23
Ordering Information ...................................................... 24
64 K × 8 3.3 V Synchronous Dual-Port SRAM .......... 24
128 K × 8 3.3 V Synchronous Dual-Port SRAM ........ 24
Document #: 38-06043 Rev. *F
32 K × 9 3.3 V Synchronous Dual-Port SRAM .......... 24
128 K × 9 3.3 V Synchronous Dual-Port SRAM ........ 24
Ordering Code Definitions ......................................... 24
Package Diagram ............................................................ 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 28
Worldwide Sales and Design Support ....................... 28
Products .................................................................... 28
PSoC Solutions ......................................................... 28
Page 4 of 28
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CY7C09089V/99V
CY7C09179V/99V
Pin Configurations
NC
NC
A6R
A5R
A4R
A3R
A2R
A1R
A0R
CNTENR
CLKR
ADSR
GND
ADSL
CLKL
CNTENL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
NC
NC
Figure 1. 100-pin TQFP (Top View) - CY7C09089V (64 K × 8), CY7C09099V (128 K × 8)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
1
75
NC
NC
2
74
NC
A7L
3
73
A7R
A8L
4
72
A8R
A9L
5
71
A9R
A10L
6
70
A10R
A11L
7
69
A11R
A12L
8
68
A12R
A13L
9
67
A13R
A14L
10
66
A14R
A15L
11
65
A15R
A16L
12
64
A16R [6]
VCC
13
63
GND
NC
14
62
NC
NC
15
61
NC
NC
16
60
NC
NC
17
59
NC
CE0L
18
58
CE0R
CE1L
19
57
CE1R
CNTRSTL
20
56
CNTRSTR
R/WL
21
55
R/WR
OEL
22
54
OER
FT/PIPEL
23
53
FT/PIPER[7]
NC
24
52
GND
NC
25
51
NC
[6]
[7]
NC
NC
NC
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
VCC
I/O2R
I/01R
I/O0R
GND
VCC
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
NC
GND
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes
6. This pin is NC for CY7C09089V.
7. For CY7C09089V, pin #23 connected to VCC is pin compatible with an IDT 5 V, ×8 pipelined device; connecting pin #23 and #53 to GND is pin compatible with an
IDT 5 V, ×16 flow-through device.
Document #: 38-06043 Rev. *F
Page 5 of 28
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CY7C09089V/99V
CY7C09179V/99V
NC
A6R
A5R
A4R
A3R
A2R
A1R
A0R
CNTENR
CLKR
ADSR
GND
GND
ADSL
CLKL
CNTENL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
NC
NC
Figure 2. 100-pin TQFP (Top View) - CY7C09179V (32 K × 9), CY7C09199V (128 K × 9)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
1
75
NC
NC
2
74
NC
A7L
3
73
A7R
A8L
4
72
A8R
A9L
5
71
A9R
A10L
6
70
A10R
A11L
7
69
A11R
A12L
8
68
A12R
A13L
9
67
A13R
A14L
10
66
A14R
[8] A15L
[9]
11
65
A15R [8]
A16L
12
64
A16R [9]
VCC
13
63
GND
NC
14
62
NC
NC
15
61
NC
NC
16
60
NC
NC
17
59
NC
CE0L
18
58
CE0R
CE1L
19
57
CE1R
CNTRSTL
20
56
CNTRSTR
R/WL
21
55
R/WR
OEL
22
54
OER
FT/PIPEL
23
53
FT/PIPER
NC
24
52
GND
NC
25
51
NC
NC
NC
I/O8R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
VCC
I/O2R
I/01R
I/O0R
GND
VCC
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
GND
I/O8L
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes
8. This pin is NC for CY7C09179V.
9. This pin is NC for CY7C09179V and CY7C09189V.
Document #: 38-06043 Rev. *F
Page 6 of 28
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CY7C09089V/99V
CY7C09179V/99V
Selection Guide
CY7C09179V
-6[10]
CY7C09099V
-7[10]
CY7C09199V
-9
CY7C09089V/99V
CY7C09179V
-12
fMAX2 (MHz) (Pipelined)
100
83
67
50
Max. Access Time (ns) (Clock to Data,
Pipelined)
6.5
7.5
9
12
Description
Typical Operating Current ICC (mA)
175
155
135
115
Typical Standby Current for ISB1 (mA)
(Both Ports TTL Level)
25
25
20
20
Typical Standby Current for ISB3 (A)
(Both Ports CMOS Level)
10
10
10
10
Pin Definitions
Left Port
Right Port
Description
A0L–A16L
A0R–A16R
Address Inputs (A0–A14 for 32K; A0–A15 for 64K; and A0–A16 for 128K devices).
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads
the burst counter with the address present on the address pins.
CE0L, CE1L
CE0R, CE1R
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted
to their active states (CE0  VIL and CE1 VIH).
CLKL
CLKR
Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its
respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O8L
I/O0R–I/O8R
Data Bus Input/Output (I/O0–I/O7 for ×8 devices; I/O0–I/O8 for ×9 devices).
OEL
OER
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during
read operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
FT/PIPEL
FT/PIPER
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
GND
Ground Input.
NC
No Connect.
VCC
Power Input.
Note
10. See page 9 and page 10 for Load Conditions.
Document #: 38-06043 Rev. *F
Page 7 of 28
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CY7C09089V/99V
CY7C09179V/99V
Maximum Ratings
Output Current into Outputs (LOW) ............................20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.[11]
Storage Temperature .............................. –65 °C to +150 °C
Static Discharge Voltage .........................................> 2001 V
Latch-Up Current ...................................................> 200 mA
Operating Range
Ambient Temperature
with Power Applied ...................................–55 °C to +125 °C
Supply Voltage to Ground Potential ............ –0.5 V to +4.6 V
Range
Ambient
Temperature
VCC
DC Voltage Applied to
Outputs in High Z State .......................–0.5 V to VCC + 0.5 V
Commercial
0 °C to +70 °C
3.3 V  300 mV
–40 °C to +85 °C
3.3 V  300 mV
[12]
Industrial
DC Input Voltage .................................–0.5 V to VCC + 0.5 V
Electrical Characteristics
Over the Operating Range
VOH
VOL
VIH
VIL
IOZ
ICC
ISB1
ISB2
ISB3
ISB4
Output HIGH Voltage (VCC = Min.,
2.4
–
–
2.4
–
–
2.4
–
–
2.4
–
–
IOH = –4.0 mA)
–
0.4
–
0.4
–
0.4
–
0.4
Output LOW Voltage (VCC = Min.,
IOH = +4.0 mA)
Input HIGH Voltage
2.0
–
2.0
–
2.0
–
2.0
–
Input LOW Voltage
–
0.8
–
0.8
–
0.8
–
0.8
Output Leakage Current
–10
10 –10
10 –10
10 –10
10
Operating Current
Commercial – 175 320 – 155 275 – 135 225 – 115 205
(VCC = Max., IOUT = 0 mA) Industrial[12]
–
275 390
185 295
–
–
Outputs Disabled
Standby Current
Commercial
25 95
25 85
20 65
20 50
(Both Ports TTL Level)[14] Industrial[12]
–
85 120
35 75
–
–
CEL & CER  VIH, f = fMAX
Standby Current
Commercial
115 175
105 165
95 150
85 140
(One Port TTL Level)[14]
–
165 210
105 160
–
–
Industrial[12]
CEL | CER  VIH, f = fMAX
Commercial
10 250
10 250
10 250
10 250
Standby Current
[12]
(Both Ports CMOS
Industrial
–
10
250
10
250
–
–
Level)[14]
CEL & CER  VCC – 0.2 V,
f=0
Standby Current
Commercial
105 135
95 125
85 115
75 100
(One Port CMOS Level)[14] Industrial[12]
–
125 170
95 125
–
–
CEL | CER  VIH, f = fMAX
Unit
Max
Typ
Min
-12
Max
Typ
Min
Max
Typ
Min
Max
Typ
-6[13]
Description
Min
Parameter
CY7C09079V/89V/99V
CY7C09179V/89V/99V
-7[13]
-9
V
V
V
V
A
mA
mA
mA
mA
mA
mA
A
A
mA
mA
Notes
11. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
12. Industrial parts are available in CY7C09099V and CY7C09199V only.
13. See page 9 and page 10 for Load Conditions.
14. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0  VIL and CE1 VIH).
Document #: 38-06043 Rev. *F
Page 8 of 28
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CY7C09089V/99V
CY7C09179V/99V
Capacitance
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = 3.3 V
Max
Unit
10
pF
10
pF
Figure 3. AC Test Loads
3.3 V
3.3 V
R1 = 590 
OUTPUT
C = 30 pF
OUTPUT
RTH = 250 
R1 = 590 
OUTPUT
C = 30 pF
R2 = 435 
C = 5 pF
R2 = 435 
VTH = 1.4 V
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 2)
(Used for tCKLZ, tOLZ, & tOHZ
including scope and jig)
Figure 4. AC Test Loads (Applicable to -6 and -7 only)[15]
ALL INPUT PULSES
Z0 = 50  R = 50 
OUTPUT
3.0 V
C
GND
VTH = 1.4 V
10%
 3 ns
90%
90%
10%
 3 ns
(a) Load 1 (-6 and -7 only)
Note
15. Test Conditions: C = 10 pF.
Document #: 38-06043 Rev. *F
Page 9 of 28
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CY7C09089V/99V
CY7C09179V/99V
Figure 5. Load Derating Curve
0. 60
(ns) for all -7 access times
0. 50
0. 40
0. 30
0. 20
0. 1 0
0. 00
10
15
20
25
30
35
Capacitance (pF)
Document #: 38-06043 Rev. *F
Page 10 of 28
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CY7C09089V/99V
CY7C09179V/99V
Switching Characteristics
Over the Operating Range
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Parameter
Description
-6[16]
-7[16]
-9
Unit
-12
Min
Max
Min
Max
Min
Max
Min
Max
–
53
–
45
–
40
–
33
MHz
fMAX1
fMax Flow-through
fMAX2
fMax Pipelined
–
100
–
83
–
67
–
50
MHz
tCYC1
Clock Cycle Time - Flow-through
19
–
22
–
25
–
30
–
ns
tCYC2
Clock Cycle Time - Pipelined
10
–
12
–
15
–
20
–
ns
tCH1
Clock HIGH Time - Flow-through
6.5
–
7.5
–
12
–
12
–
ns
tCL1
Clock LOW Time - Flow-through
6.5
–
7.5
–
12
–
12
–
ns
tCH2
Clock HIGH Time - Pipelined
4
–
5
–
6
–
8
–
ns
tCL2
Clock LOW Time - Pipelined
4
–
5
–
6
–
8
–
ns
tR
Clock Rise Time
–
3
–
3
–
3
–
3
ns
tF
Clock Fall Time
tSA
Address Set-Up Time
tHA
Address Hold Time
tSC
Chip Enable Set-Up Time
tHC
Chip Enable Hold Time
tSW
R/W Set-Up Time
tHW
R/W Hold Time
tSD
Input Data Set-Up Time
tHD
Input Data Hold Time
tSAD
ADS Set-Up Time
tHAD
ADS Hold Time
tSCN
CNTEN Set-Up Time
tHCN
CNTEN Hold Time
tSRST
CNTRST Set-Up Time
tHRST
tOE
–
3
–
3
–
3
–
3
ns
3.5
–
4
–
4
–
4
–
ns
0
–
0
–
1
–
1
–
ns
3.5
–
4
–
4
–
4
–
ns
0
–
0
–
1
–
1
–
ns
3.5
–
4
–
4
–
4
–
ns
0
–
0
–
1
–
1
–
ns
3.5
–
4
–
4
–
4
–
ns
0
–
0
–
1
–
1
–
ns
3.5
–
4
–
4
–
4
–
ns
0
–
0
–
1
–
1
–
ns
3.5
–
4.5
–
5
–
5
–
ns
0
–
0
–
1
–
1
–
ns
3.5
–
4
–
4
–
4
–
ns
CNTRST Hold Time
0
–
0
–
1
–
1
–
ns
Output Enable to Data Valid
–
8
–
9
–
10
–
12
ns
[17, 18]
OE to Low Z
2
–
2
–
2
–
2
–
ns
tOHZ[17, 18]
OE to High Z
1
7
1
7
1
7
1
7
ns
tCD1
Clock to Data Valid - Flow-through
–
15
–
18
–
20
–
25
ns
tCD2
Clock to Data Valid - Pipelined
–
6.5
–
7.5
–
9
–
12
ns
tDC
Data Output Hold After Clock HIGH
2
–
2
–
2
–
2
–
ns
tCKHZ[17, 18]
Clock HIGH to Output High Z
2
9
2
9
2
9
2
9
ns
tCKLZ[17, 18]
Clock HIGH to Output Low Z
2
–
2
–
2
–
2
–
ns
tOLZ
Notes
16. See page 9 and page 10 for Load Conditions.
17. Test conditions used are Load 2.
18. This parameter is guaranteed by design, but it is not production tested.
Document #: 38-06043 Rev. *F
Page 11 of 28
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CY7C09089V/99V
CY7C09179V/99V
Switching Characteristics (continued)
Over the Operating Range
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Parameter
Description
-6[16]
-7[16]
-9
Unit
-12
Min
Max
Min
Max
Min
Max
Min
Max
Port to Port Delays
tCWDD
Write Port Clock HIGH to Read Data Delay
–
30
–
35
–
40
–
40
ns
tCCS
Clock to Clock Set-Up Time
–
9
–
10
–
15
–
15
ns
Switching Waveforms
Figure 6. Read Cycle for Flow-through Output (FT/PIPE = VIL)[19, 20, 21, 22]
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
tSW
tSA
tHW
tHA
tSC
tHC
CE1
R/W
ADDRESS
An
An+1
tCD1
DATAOUT
An+2
tCKHZ
tDC
Qn
tCKLZ
An+3
Qn+1
tOHZ
Qn+2
tDC
tOLZ
OE
tOE
Notes
19. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
20. ADS = VIL, CNTEN and CNTRST = VIH.
21. The output is disabled (high-impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock.
22. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
Document #: 38-06043 Rev. *F
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Switching Waveforms (continued)
Figure 7. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[23, 24, 25, 26]
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
tSW
tSA
tHW
tHA
tSC
tHC
CE1
R/W
ADDRESS
An
DATAOUT
An+1
1 Latency
An+2
tDC
tCD2
Qn
tCKLZ
An+3
Qn+1
tOHZ
Qn+2
tOLZ
OE
tOE
Notes
23. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
24. ADS = VIL, CNTEN and CNTRST = VIH.
25. The output is disabled (high-impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock.
26. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
Document #: 38-06043 Rev. *F
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Switching Waveforms (continued)
Figure 8. Bank Select Pipelined Read[27, 28]
-
tCH2
tCYC2
tCL2
CLKL
tHA
tSA
ADDRESS(B1)
A0
A1
A3
A2
A4
A5
tHC
tSC
CE0(B1)
tCD2
tHC
tSC
tCD2
tHA
tSA
A0
ADDRESS(B2)
tDC
A1
tDC
tSC
tCKLZ
A3
A2
tCKHZ
D3
D1
D0
DATAOUT(B1)
tCD2
tCKHZ
A4
A5
tHC
CE0(B2)
tSC
tHC
tCD2
DATAOUT(B2)
tCKHZ
tCD2
D4
D2
tCKLZ
tCKLZ
Notes
27. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet.
ADDRESS(B1) = ADDRESS(B2).
28. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
Document #: 38-06043 Rev. *F
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Switching Waveforms (continued)
Figure 9. Left Port Write to Flow-through Right Port Read[29, 30, 31, 32]
CLKL
tSW
tHW
tSA
tHA
R/WL
ADDRESSL
NO
MATCH
MATCH
tHD
tSD
DATAINL
VALID
tCCS
CLKR
R/WR
ADDRESSR
tCD1
tSW
tSA
tHW
tHA
NO
MATCH
MATCH
tCWDD
DATAOUTR
tCD1
VALID
tDC
VALID
tDC
Notes
29. The same waveforms apply for a right port write to flow-through left port read.
30. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
31. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to.
32. It tCCS  maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data is not
valid until tCCS + tCD1. tCWDD does not apply in this case.
Document #: 38-06043 Rev. *F
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Switching Waveforms (continued)
Figure 10. Pipelined Read-to-Write-to-Read (OE = VIL)[33, 34, 35, 36]
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
tSA
An+1
An+2
tHA
DATAIN
An+2
An+3
An+4
tSD tHD
tCD2
tCKHZ
Dn+2
tCD2
tCKLZ
Qn
DATAOUT
READ
Qn+3
NO OPERATION
WRITE
READ
Notes
33. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
34. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
35. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
36. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity.
Document #: 38-06043 Rev. *F
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Switching Waveforms (continued)
Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled)[37, 38, 39, 40]
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
CE1
R/W
ADDRESS
tSW tHW
tSW
tHW
An
tSA
An+1
An+2
tHA
An+3
An+4
An+5
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
DATAOUT
tCKLZ
tCD2
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Notes
37. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
38. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
39. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
40. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity.
Document #: 38-06043 Rev. *F
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Switching Waveforms (continued)
Figure 12. Flow-through Read-to-Write-to-Read (OE = VIL)[41, 42, 43, 44, 45]
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
An+1
tSA
DATAIN
An+2
tSD
tHA
An+3
An+4
tHD
Dn+2
tCD1
DATAOUT
An+2
tCD1
Qn
tCD1
Qn+1
tDC
tCKHZ
READ
tCD1
Qn+3
NO
OPERATION
tCKLZ
WRITE
tDC
READ
Notes
41. ADS = VIL, CNTEN and CNTRST = VIH.
42. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
43. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
44. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
45. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity.
Document #: 38-06043 Rev. *F
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Switching Waveforms (continued)
Figure 13. Flow-through Read-to-Write-to-Read (OE Controlled)[46, 47, 48, 49, 50]
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
tSA
DATAIN
An+1
tSD
tHA
An+3
An+4
An+5
tHD
Dn+2
tDC
tCD1
DATAOUT
An+2
Dn+3
tOE
tCD1
Qn
tCD1
Qn+4
tOHZ
tCKLZ
tDC
OE
READ
WRITE
READ
Notes
46. ADS = VIL, CNTEN and CNTRST = VIH.
47. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet.
ADDRESS(B1) = ADDRESS(B2).
48. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
49. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
50. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity.
Document #: 38-06043 Rev. *F
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Switching Waveforms (continued)
Figure 14. Pipelined Read with Address Counter Advance[51]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
Qx-1
tCD2
Qx
READ
EXTERNAL
ADDRESS
Qn
tDC
Qn+1
READ WITH COUNTER
Qn+2
COUNTER HOLD
Qn+3
READ WITH COUNTER
Figure 15. Flow-through Read with Address Counter Advance[51]
tCH1
tCYC1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
tCD1
Qx
Qn
Qn+1
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
Qn+3
Qn+2
COUNTER HOLD
READ
WITH
COUNTER
Note
51. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH.
Document #: 38-06043 Rev. *F
Page 20 of 28
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Switching Waveforms (continued)
Figure 16. Write with Address Counter Advance (Flow-through or Pipelined Outputs)[52, 53]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
tSAD
tHAD
tSCN
tHCN
An+1
An+2
An+3
An+4
ADS
CNTEN
Dn
DATAIN
tSD
tHD
WRITE EXTERNAL
ADDRESS
Dn+1
Dn+1
WRITE WITH
COUNTER
Dn+2
WRITE COUNTER
HOLD
Dn+3
Dn+4
WRITE WITH COUNTER
Notes
52. CE0 and R/W = VIL; CE1 and CNTRST = VIH.
53. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH.
Document #: 38-06043 Rev. *F
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Switching Waveforms (continued)
Figure 17. Counter Reset (Pipelined Outputs)[54, 55, 56, 57]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
AX
0
tSW
tHW
tSD
tHD
1
An+1
An
An+1
R/W
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
ADS
CNTEN
CNTRST
DATAIN
D0
DATAOUT
Q0
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
Q1
Qn
READ
ADDRESS n
Notes
54. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
55. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
56. CE0 = VIL; CE1 = VIH.
57. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Document #: 38-06043 Rev. *F
Page 22 of 28
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Read/Write and Enable Operation [58, 59, 60]
Inputs
OE
CE0
CE1
R/W
X
H
X
X
High Z
Deselected[61]
X
X
L
X
High Z
Deselected[61]
X
L
H
L
DIN
Write
L
L
H
H
DOUT
Read[61]
L
H
X
High Z
Outputs Disabled
H
CLK
Outputs
X
I/O0–I/O9
Operation
Address Counter Control Operation [58, 62, 63, 64]
Address
Previous
Address
X
CLK
ADS
CNTEN
X
X
X
An
X
L
X
An
X
An
CNTRST
I/O
Mode
Operation
L
Dout(0)
Reset
Counter Reset to Address 0
X
H
Dout(n)
Load
Address Load into Counter
H
H
H
Dout(n)
Hold
External Address Blocked—Counter
Disabled
H
L
H
Dout(n+1)
Increment
Counter Enabled—Internal Address
Generation
Notes
58. “X” = “Don’t Care”, “H” = VIH, “L” = VIL.
59. ADS, CNTEN, CNTRST = “Don’t Care.”
60. OE is an asynchronous input signal.
61. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
62. CE0 and OE = VIL; CE1 and R/W = VIH.
63. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
64. Counter operation is independent of CE0 and CE1.
Document #: 38-06043 Rev. *F
Page 23 of 28
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Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
64 K × 8 3.3 V Synchronous Dual-Port SRAM
Speed (ns)
12
Ordering Code
Package Name
Package Type
A100
100-pin Thin Quad Flat Pack (Pb-free)
CY7C09089V-12AXI
Operating Range
Industrial
128 K × 8 3.3 V Synchronous Dual-Port SRAM
Speed (ns)
[65]
7.5
12
Ordering Code
Package Name
Package Type
Operating Range
CY7C09099V-7AXI
A100
100-pin Thin Quad Flat Pack (Pb-free)
Industrial
CY7C09099V-12AXC
A100
100-pin Thin Quad Flat Pack (Pb-free)
Commercial
32 K × 9 3.3 V Synchronous Dual-Port SRAM
Speed (ns)
[65]
6.5
12
Ordering Code
Package Name
Package Type
Operating Range
CY7C09179V-6AXC
A100
100-pin Thin Quad Flat Pack (Pb-free)
Commercial
CY7C09179V-12AXC
A100
100-pin Thin Quad Flat Pack (Pb-free)
Commercial
128 K × 9 3.3 V Synchronous Dual-Port SRAM
Speed (ns)
9
Ordering Code
Package Name
Package Type
A100
100-pin Thin Quad Flat Pack (Pb-free)
CY7C09199V-9AXC
Operating Range
Commercial
Ordering Code Definitions
CY 7C 09
X
X9 V - XX
A X
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
X = Pb-free (RoHS Compliant)
Package Type:
A = 100-pin TQFP
Speed Grade: 12 ns or 7.5 ns or 6.5 ns or 9 ns
V = 3.3 V
X9 = Depth: X = 7 or 8 or 9
7 = 32K; 8 = 64K; 9 = 128K
X = Width: X = 0 or 1
0 = × 8; 1 = × 9
09 = Sync
7C = Dual Port SRAM
Company ID: CY = Cypress Device
Note
65. See page 9 and page 10 for Load Conditions.
Document #: 38-06043 Rev. *F
Page 24 of 28
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Package Diagram
Figure 18. 100-pin TQFP 14 × 14 × 1.4 mm A100SA (51-85048)
51-85048 *E
Document #: 38-06043 Rev. *F
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Acronyms
Document Conventions
Acronym
Description
Units of Measure
CMOS
complementary metal oxide semiconductor
I/O
input/output
°C
degree Celcius
Symbol
Unit of Measure
OE
output enable
MHz
Mega Hertz
SRAM
static random access memory
µA
micro Amperes
TQFP
thin quad flat pack
mA
milli Amperes
TTL
transistor transistor logic
mm
milli meter
WE
write enable
ms
milli seconds
mV
milli Volts
Document #: 38-06043 Rev. *F
ns
nano seconds

Ohms
%
percent
pF
pico Farad
V
Volts
W
Watts
Page 26 of 28
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Document History Page
Document Title: CY7C09089V/99V, CY7C09179V/99V, 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM
Document Number: 38-06043
Rev.
ECN No.
Orig. of
Change
Orig. of
Change
**
110191
SZV
09/29/01
Change from Spec number: 38-00667 to 38-06043
Power up requirements added to Operating Conditions Information
Description of Change
*A
122293
RBI
12/27/02
*B
365034
PCN
See ECN Added Pb-Free Logo
Added Pb-Free Part Ordering Information:
CY7C09089V-6AXC, CY7C09089V-12AXC, CY7C09099V-6AXC,
CY7C09099V-7AI, CY7C09099V-7AXI, CY7C09099V-12AXC,
CY7C09179V-6AXC, CY7C09179V-12AXC, CY7C09189V-6AXC,
CY7C09189V-12AXC, CY7C09199V-6AXC, CY7C09199V-7AXC,
CY7C09199V-9AXC, CY7C09199V-9AXI, CY7C09199V-12AXC
*C
2623658
VKN/PYRS
12/17/08
Added CY7C09089V-12AXI part in the Ordering information table
*D
2897159
RAME
03/22/10
Removed inactive parts from ordering information table. Updated package
diagram. Added Note in ordering information section.
*E
3110406
ADMU
12/14/2010 Updated Ordering Information.
Added Ordering Code Definitions.
*F
3264673
ADMU
05/24/2011 Updated Document Title to read “CY7C09089V/99V, CY7C09179V/99V,
3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM”.
Updated Features.
Updated Pin Configurations (Removed the Note “This pin is NC for
CY7C09079V.” in page 5).
Updated Selection Guide.
Updated Package Diagram.
Added Acronyms and Units of Measure.
Updated in new template.
Document #: 38-06043 Rev. *F
Page 27 of 28
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
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© Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06043 Rev. *F
Revised May 25, 2011
Page 28 of 28
All products and company names mentioned in this document may be the trademarks of their respective holders.
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