1/4 ◇Structure ◇Product name ◇Type ◇Applications ◇Functions Silicon Monolithic integrated circuit Audio interface + Video driver LSI BU7636MWV DVC, DSC, etc. ＜Audio part＞ ･Stereo 16 bit ΔΣＣＯＤＥＣ ・3-input stereo selector ・Stereo microphone amplifier with ALC function ・Stereo line amplifier ・BTL output speaker amplifier （300mW@8Ω） ・64-step electronic volume with ALC function ・Master clock：256fs/384fs/512fs/1024fs ・Sampling rate：8kHz～48ｋHz ・Three-line serial interface （power on reset function） ・Audio IF format MSB First，2’s ｃｏｍｐｌｉｍｅｎｔ ＜ADC＞ 16bit word lengths Left justified，I2S ＜DAC＞ 16bit word lengths Left, Right justified, I2S ＜Video part＞ ・Sync-tip-clamp, 6th LPF, Y/C/V output video driver ・Output coupling condenser unnecessary ・Aspect ratio identification signal output ◇Absolute maximum ratings （Ta=25℃） Parameter Supply voltage Symbol Limits Unit LVDD1 -0.3～4.5 Ｖ LVDD2 -0.3～4.5 V HVDD -0.3～6.0 V Input voltage VIN -0.3 ～ supply voltage + 0.3 Ｖ Storage temperature range TSTG -50～125 ℃ Operating temperature range TOPE -20～85 ℃ Power dissipation *1 PD 800 ｍＷ ＊１：In the case of use at Ta=25℃ or more, 8.0mW should be reduced per 1℃. （t=1.6mm, 74.2mm x 74.2mm, 1-layer board, Cu surface radiate foil 0mm2） Radiation resistance design is not arranged. Comment AVDD、DVDD、SPVDD、VVDD CPVDD VVDD_SDC keep each limits upon ◇Operating conditions （Ta=25℃） Parameter Supply voltage Symbol Limits Unit Comment LVDD1 2.7～3.6 Ｖ AVDD、DVDD、SPVDD、VVDD LVDD2 2.7～3.4 V CPVDD HVDD 4.5～5.5 V VVDD_SDC （note） AVDD、DVDD、SPVDD、VVDD are not needed to be same voltage. （note） Please do not set SPVDD lower than AVDD-0.3V. REV. A 2/4 ◇Electrical characteristics （Unless specified, Ta=25℃、AVDD=SPVDD=DVDD=VVDD=CPVDD= 3.3V、VVDD_SDC=5.0V、AVSS=SPVSS=DVSS=VVSS= 0V、B.W.=22Hz～22kHz、fs=48kHz、fin=1kHz） Parameter Symbol Limits Unit Condition MIN. TYP. MAX. < Current consumption > #MCLK=24MHz Power-down mode IDDS 0.03 0.1 ｍＡ #PWAP=0 Rec mode IDDR 8.5 16 ｍＡ #MDREC=1 Play mode IDDP 7.5 16 ｍＡ #MDPB=MDSP= 1 Video mode IDDV 33 80 ｍＡ #PWVD=PWCP=1 <ＭＲＥＧ> output voltage VOREG 0.75AVDD- 0.75AVDD 0.75AVDD+ Ｖ 2.2kΩ load 0.2 0.2 <Logic interface> Ｌ input voltage VIL DVSS － 0.3DVDD V Ｈ input voltage VIH 0.7DVDD － DVDD V Input current IIL -10 － 10 μA Ｌ output voltage VOL 0 － 0.5 V IOL=-1mA Ｈ output voltage VOH DVDD-0.5 － DVDD V IOL=1mA <REC path （MICIN→ADOUT）> #ALC1=OFF, MIC GAIN 22dB (MGAIN=42dB, MLIM=-20dB) Input impedance ZIN 70 100 130 kΩ Input level VIN -26 -24 -22 dBV DOUT=0dBFS L/R gain mismatch △GV -1.0 0 +1.0 dB DOUT=0dBFS Distortion THD+N 62 70 dB DOUT=-6dBFS@1kHz ＳＮＲ SNR 79 84 dB B.W.=JIS-A L/R separation SEPR 79 100 dB DOUT=-6dBFS@1kHz ＡＬＣ１ output level DOALC -6 dBFS ALC1=ON <PB path1 （DAIN→LINEOUT）> #LGAIN=+5dB Output level VO -5.5 -4.0 -2.5 dBV DIN=-6dBFS L/R gain mismatch △GV -1.0 0 +1.0 dB DIN=-6dBFS Distortion THD+N 70 80 dB DIN=-6dBFS@1kHz ＳＮＲ SNR 82 90 dB B.W.=JIS-A L/R separation SEPR 80 100 dB DIN=-6dBFS@1kHz <PB path2 （DAIN→EVROUT→SPIN→SPOUT BTL 出力）> #ALC2=OFF, EVR=-6dB, RL=8Ω Output level VO 1.0 3.0 5.0 dBV DIN=0dBFS Distortion THD+N 50 60 dB DIN=0dBFS@1kHz ＳＮＲ SNR 76 83 dB B.W.=JIS-A ＡＬＣ２ output level VOALC 1.0 3.0 5.0 dBV ALC2=ON, EVR=8dB < Video path （YIN→YOUT, VOUT）(CIN→COUT, VOUT)> Voltage gain GV +5.5 +6.0 +6.5 dB VIN=100KHz, 1.0Vpp Maximum output level VOM 2.2 2.6 Vpp f=10KHz, THD=1% Frequency characteristic 1 GF1 -3.0 0 dB f=6MHz/100KHz Frequency characteristic 1 GF2 -27 -18 dB f=18MHz/100KHz Differential gain DG 1.0 3.0 % VIN=1.0Vpp Standard stair step signal Differential phase DP 1.0 3.0 deg VIN=1.0Vpp Standard stair step signal Y signal output S/N SNY +50 +65 dB Band 100k～6MHz Terminal impedance 150Ω 100% white video signal S-DC L VSDCL 0.1 0.5 V RL=10kΩ+100kΩ output voltage M VSDCM 1.8 2.1 2.4 V RL=10kΩ+100kΩ H VSDCH 4.0 4.6 V RL=10kΩ+100kΩ (note） Input level of REC and Output level of PB are relative to AVDD. (note) VSDCM，VSDCH is relative to VVDD_SDC. REV. A 3/4 ◇Serial interface Control commands are entered on the CSB, SCLK, and SDATA pins, using 3 line 16 bit serial input (MSB first). The input cycle is started on the CSB falling edge, and each bit of data is read in on the SCLK rising edge. The data is loaded to register on the CSB rising edge. CSB Register Address : A5 - A0 Control Data : D7 - D0 SCLK SDATA “x” “x” 1 0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ◇Register map Address 00H 01H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 12H 13H Register D7 D6 D5 Power control 0 PWSV PWAP Power control 0 COMENB 0 Gain control 1 0 ADA Gain control SLMIN1 SLMIN0 0 Clock control FMCK1 FMCK0 0 Clock control 0 0 0 Clock control 0 BFPD 0 ALC control 0 MDALC1 MDEVR1 ALC control ATMC1 ATMC0 RCMC1 ALC control RC2MC1 RC2MC0 0 Time control RINI2 RINI1 RINI0 Volume control 0 MLIM6 MLIM5 Filter control 0 0 DEM1 Volume control DVOL7 DVOL6 DVOL5 Volume control 0 0 EVR5 Volume control 0 0 SPVOL1 Fade control 0 0 0 Video control 1 1 1 （note） Do not write to the address except for the above. D4 PWMRG 0 0 0 1 0 DLEN MDEVR0 RCMC0 0 PINI1 MLIM4 DEM0 DVOL4 EVR4 SPVOL0 0 SDC1 D3 PWVD MDSP 0 MUSP 0 SFS1 0 0 ATSP1 RCLM PINI0 MLIM3 HPFR3 DVOL3 EVR3 0 DVLSK SDC2 D2 PWCP MDPB LGAIN MUBSP DIF2 SFS0 0 0 ATSP0 0 0 MLIM2 HPFR2 DVOL2 EVR2 BVOL2 DVLT2 0 D1 0 MDREC MGAIN1 MULO DIF1 DIV1 0 0 RCSP1 0 0 MLIM1 HPFR1 DVOL1 EVR1 BVOL1 DVLT1 0 ◇Pin Functional Descriptions No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin name CPVDD C4 C3 C2 VVEE CIN VVSS YIN VVDD YOUT VOUT COUT SDCOUT VVDD_SDC DVDD DAIN ADOUT BCLK LRCLK MCLK DVSS SDATA Function Charge pump power supply Flying condenser terminal 4 Flying condenser terminal 3 Flying condenser terminal 2 Video negative power supply Chroma signal input Video ground Luminance signal input Video power supply Luminance signal output Composite signal outut Chroma signal output SDC signal output SDC power supply Digital power supply CODEC DA serial data input CODEC AD serial data output CODEC bit clock in/output CODEC LR clock in/output CODEC master clock input Digital ground 3-wire serial data input No 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 REV. A Pin name SCLK CSB MICINR3 MICINR2 MICINR1 MREG MICINL1 MICINL2 MICINL3 BIAS AVSS AVDD LINEOUTR LINEOUTL EVROUT SPIN SPNEG SPVSS SPVDD SPPOS BEEPIN C1 Function 3-wire serial clock input 3-wire chip select input MICRch input 3 MICRch input 2 MICRch input 1 MIC power supply MICLch input 1 MICLch input 2 MICLch input 3 Bias （1/2AVDD） Analog ground Analog power supply LINE output LINE output EVR output SP input SP negative output SP ground SP power supply SP positive output BEEP input Flying condenser terminal 1 D0 PWDRG 0 MGAIN0 MUDVL DIF0 DIV0 0 MDDVL RCSP0 0 EVRT MLIM0 HPFR0 DVOL0 EVR0 BVOL0 DVLT0 0 4/4 SDATA SCLK CSB MICINR3 MICINR2 MICINR1 MICINL1 MICINL2 BIAS MICINL3 ◇Block diagram・External dimensions BU7636 MREG BIAS Control AVSS ALC1 Lot No. DVDD ALC1 AVDD DVSS LINEOUTR MCLK ＋ LINEOUTL LRCLK EVR EVROUT BEEPIN BCLK ALC2 SPIN DAC ADC ＋ ADOUT DAIN Digital Filters SPNEG Audio Interface SPVDD VVDD_SDC SDC SDC_OUT SPVSS COUT LPF SPPOS ＋ CLAMP VOUT Figure 1 YOUT VVSS VVDD YIN CIN LPF VVEE C4 C3 C2 C1 CPVDD CHARGE PUMP Block diagram Figure 2 External dimension（Unit：ｍｍ） PKG：UQFN044V6060 Drawing No.：EX475-6002 ◇Caution （１） About absolute maximum rating When the absolute maximum rating such as the applied voltage and the ranges of the operating temperature is exceeded, LSI might be destroyed. Please apply neither voltage nor the temperature that exceeds the absolute maximum rating. Please execute physical measures for safety such as fuse when it is thought to exceed the absolute maximum rating, and examine it so that the condition to exceed the absolute maximum rating is not applied to LSI. （２） About GND Voltage In any state of operation must be the lowest voltage about the voltage of the terminal GND. Please actually confirm the voltage of each terminal is not a voltage that is lower than the terminal GND including excessive phenomenon. （３） About design of overheating malfunction preventive circuit Please design overheating malfunction preventive circuit with an enough margin in consideration of a permissible loss in the state of using actually. （４） About the short between terminals and the mounting by mistake Please note the direction and the gap of position of LSI enough about LSI when you mount on the substrate. LSI might be destroyed when mounting by mistake and energizing. Moreover, LSI might be destroyed when short-circuited by entering of the foreign substances between the terminal and GND, between terminals, between the terminal and the power supply of LSI. （５） About operation in strong electromagnetic field Use in strong electromagnetic field has the possibility of malfunctioning and evaluate it enough, please. （６） Please note not to be beyond the package permissible range, When SPVDD is set. （７） About charge pump For prevent the undetermined state of charge pump, recommend to put together CPVDD and DVDD pins. And to avoid the IC’s broken or smoke, you must not supply the external voltage or current to C1, C2, C3, C4, and VEE pins. REV. A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. 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