ON NOIV1SN1300A-XXC Vita 1300 1.3 megapixel 150 fps global shutter cmos image sensor Datasheet

NOIV1SN1300A,
NOIV2SN1300A
VITA 1300 1.3 Megapixel
150 FPS Global Shutter
CMOS Image Sensor
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Features
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SXGA: 1280 x 1024 Active Pixels
4.8 mm x 4.8 mm Pixel Size
1/2 inch Optical Format
Monochrome (SN) or Color (SE)
150 Frames per Second (fps) at Full Resolution (LVDS)
37 Frames per Second (fps) at Full Resolution (CMOS)
On-chip 10-bit Analog-to-Digital Converter (ADC)
8-bit or 10-bit Output Mode
Four LVDS Serial Outputs or Parallel CMOS Output
Random Programmable Region of Interest (ROI) Readout
Pipelined and Triggered Global Shutter, Rolling Shutter
On-chip Fixed Pattern Noise (FPN) Correction
Serial Peripheral Interface (SPI)
Automatic Exposure Control (AEC)
Phase Locked Loop (PLL)
High Dynamic Range (HDR)
Dual Power Supply (3.3 V and 1.8 V)
−40°C to +85°C Operational Temperature Range
48-pin LCC and Bare Die
475 mW Power Dissipation (LVDS)
290 mW Power Dissipation (CMOS)
These Devices are Pb−Free and are RoHS Compliant
Figure 1. VITA 1300 Photograph
Applications
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Machine Vision
Motion Monitoring
Security
Barcode Scanning (2D)
Description
The VITA 1300 is a 1/2 inch Super-eXtended Graphics Array (SXGA) CMOS image sensor with a pixel array of 1280 by 1024.
The high sensitivity 4.8 mm x 4.8 mm pixels support pipelined and triggered global shutter readout modes and can also be
operated in a low noise rolling shutter mode. In rolling shutter mode, the sensor supports correlated double sampling readout,
reducing noise and increasing the dynamic range.
The sensor has on-chip programmable gain amplifiers and 10-bit A/D converters. The integration time and gain parameters
can be reconfigured without any visible image artifact. Optionally the on-chip automatic exposure control loop (AEC) controls
these parameters dynamically. The image’s black level is either calibrated automatically or can be adjusted by adding a user
programmable offset.
A high level of programmability using a four wire serial peripheral interface enables the user to read out specific regions
of interest. Up to 8 regions can be programmed, achieving even higher frame rates.
The image data interface of the V1-SN/SE part consists of four LVDS lanes, facilitating frame rates up to 150 frames per
second. Each channel runs at 620 Mbps. A separate synchronization channel containing payload information is provided to
facilitate the image reconstruction at the receive end. The V2-SN/SE part provides a parallel CMOS output interface at reduced
frame rate.
The VITA 1300 is packaged in a 48-pin LCC package and is available in a monochrome and color version.
Contact your local ON Semiconductor office for more information.
© Semiconductor Components Industries, LLC, 2014
December, 2016 − Rev. 10
1
Publication Order Number:
NOIV1SN1300A/D
NOIV1SN1300A, NOIV2SN1300A
ORDERING INFORMATION
Part Number
Mono/Color
NOIV1SN1300A-QDC
LVDS Interface mono
NOIV1SE1300A-QDC
LVDS Interface color
NOIV2SN1300A-QDC
CMOS Interface mono
NOIV2SE1300A-QDC
CMOS Interface color
NOIV1SN1300A-XXC
Die sales, mono
Package
48−pin LCC
Die Sales
The V1-SN/SE base part is used to reference the mono and
color versions of the LVDS interface; the V2-SN/SE base
part is used to reference the mono and color versions of the
CMOS interface.
ORDERING CODE DEFINITION
PACKAGE MARK
Following is the mark on the bottom side of the package with Pin 1 to the left center
Line 1: NOI xxxx 1300A where xxxx denotes LVDS (V1) / CMOS (V2), mono micro lens (SN) /color micro lens (SE) option
Line 2: -QDC
Line 3: AWLYYWW
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NOIV1SN1300A, NOIV2SN1300A
CONTENTS
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering Code Definition . . . . . . . . . . . . . . . . . . . . . . 2
Package Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sensor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Image Sensor Timing and Readout . . . . . . . . . . . . . .
Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Output Format . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifications and Useful References . . . . . . . . . . . . .
Silicon Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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15
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50
66
72
73
74
75
NOIV1SN1300A, NOIV2SN1300A
SPECIFICATIONS
Key Specifications
Table 2. ELECTRO−OPTICAL SPECIFICATIONS
Table 1. GENERAL SPECIFICATIONS
Parameter
Specification
Parameter
Specification
Pixel type
Global shutter pixel architecture
Active pixels
1280 (H) x 1024 (V)
Shutter type
Pipelined and triggered global shutter,
rolling shutter
Pixel size
4.8 mm x 4.8 mm
Frame rate
at full resolution
V1-SN/SE: 150 fps
V2-SN/SE: 37 fps
Optical format
1/2 inch
Conversion gain
Master clock
V1-SN/SE:
62 MHz when PLL is used,
310 MHz (10-bit) / 248 MHz (8-bit)
when PLL is not used
V2-SN/SE: 62 MHz
0.072 LSB10/e90 mV/e-
Dark noise
2.2 LSB10, 30e- in global shutter
0.9 LSB10, 14e-in rolling shutter
Responsivity at 550 nm
24 LSB10 /nJ/cm2, 4.6 V/lux.s
Parasitic Light
Sensitivity (PLS)
<1/450
Full well charge
13700 e-
Windowing
8 Randomly programmable windows.
Normal, sub-sampled and binned readout modes
ADC resolution (1)
10-bit, 8-bit
Quantum efficiency
53% at 550 nm
LVDS outputs
V1-SN/SE: 4 data + sync + clock
Pixel FPN
CMOS outputs
V2-SN/SE: 10-bit parallel output,
frame_valid, line_valid, clock
rolling shutter: 0.5 LSB10
global shutter: 1.0 LSB10
PRNU
< 2% of signal
Data rate
V1-SN/SE:
4 x 620 Mbps (10-bit) /
4 x 496 Mbps (8-bit)
V2-SN/SE: 62 MHz
MTF
60% @ 630 nm - X-dir & Y-dir
PSNL @ 25°C
100 LSB10/s, 1360 e-/s
Dark signal @ 25°C
4.5 e-/s, 0.33 LSB10/s
Power dissipation
475 mW for V1-SN/SE in 10-bit mode
290 mW for V2-SN/SE
Dynamic range
60 dB in rolling shutter mode
53 dB in global shutter mode
Package type
48-pin LCC, bare die
Signal to Noise Ratio
(SNR max)
41 dB
Table 3. RECOMMENDED OPERATING RATINGS (Note 2)
Symbol
TJ
Description
Operating temperature range
Min
Max
Units
−40
85
°C
Table 4. ABSOLUTE MAXIMUM RATINGS (Notes 3 and 4)
Symbol
Parameter
Min
Max
Units
2.2
V
ABS (1.8 V supply group)
ABS rating for 1.8 V supply group
–0.5
ABS (3.3 V supply group)
ABS rating for 3.3 V supply group
–0.5
4.3
V
ABS storage temperature range
−40
+150
°C
85
%RH
TS
ABS storage humidity range at 85°C
Electrostatic discharge (ESD)
LU
Human Body Model (HBM): JS−001−2010
2000
Charged Device Model (CDM): JESD22−C101
500
Latch-up: JESD−78
140
V
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The ADC is 11−bit, down−scaled to 10−bit. The VITA 1300 uses a larger word−length internally to provide 10−bit on the output.
2. Operating ratings are conditions in which operation of the device is intended to be functional.
3. ON Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer
to Application Note AN52561. Long term exposure toward the maximum storage temperature will accelerate color filter degradation.
4. Caution needs to be taken to avoid dried stains on the underside of the glass due to condensation. The glass lid glue is permeable and can
absorb moisture if the sensor is placed in a high % RH environment.
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NOIV1SN1300A, NOIV2SN1300A
Table 5. ELECTRICAL SPECIFICATIONS
Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. (Notes 5, 6 and 7)
Description
Parameter
Min
Typ
Max
Units
Power Supply Parameters - V1-SN/SE LVDS
vdd_33
Supply voltage, 3.3 V
3.0
3.3
3.6
V
Idd_33
Current consumption 3.3 V supply
90
110
130
mA
vdd_18
Supply voltage, 1.8 V
1.6
1.8
2.0
V
Idd_18
Current consumption 1.8 V supply
45
60
75
mA
vdd_pix
Supply voltage, pixel
3.0
3.3
3.6
V
Idd_pix
Current consumption pixel supply
0.8
1.8
2.5
mA
Ptot
Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V
375
475
575
mW
Pstby_lp
Power consumption in low power standby mode. See Silicon Errata
on page 66
50
mW
Popt
Power consumption at lower pixel rates
Configurable
Power Supply Parameters - V2-SN/SE CMOS
vdd_33
Supply voltage, 3.3 V
3.0
3.3
3.6
V
Idd_33
Current consumption 3.3 V supply
70
90
110
mA
vdd_18
Supply voltage, 1.8 V
1.6
1.8
2.0
V
Idd_18
Current consumption 1.8 V supply
4
7
10
mA
vdd_pix
Supply voltage, pixel
3.0
3.3
3.6
V
Idd_pix
Current consumption pixel supply
0.5
1
mA
Ptot
Total power consumption
290
360
mW
Pstby_lp
Power consumption in low power standby mode. See Silicon Errata
on page 66
50
mW
Popt
Power consumption at lower pixel rates
220
Configurable
I/O - V2-SN/SE CMOS (JEDEC- JESD8C-01): Conforming to standard/additional specifications and deviations listed
fpardata
Data rate on parallel channels (10-bit)
62
Mbps
Cout
Output load (only capacitive load)
10
pF
tr
Rise time (10% to 90% of input signal)
2.5
4.5
6.5
ns
tf
Fall time (10% to 90% of input signal)
2
3.5
5
ns
I/O - V1-SN/SE LVDS (EIA/TIA-644): Conforming to standard/additional specifications and deviations listed
fserdata
Data rate on data channels
DDR signaling - 4 data channels, 1 synchronization channel;
620
Mbps
fserclock
Clock rate of output clock
Clock output for mesochronous signaling
310
MHz
Vicm
LVDS input common mode level
2.2
V
Tccsk
Channel to channel skew (Training pattern allows per channel skew
correction)
50
ps
0.3
1.25
V1-SN/SE LVDS Electrical/Interface
fin
Input clock rate when PLL used
62
MHz
fin
Input clock when LVDS input used
310
MHz
tidc
Input clock duty cycle when PLL used
60
%
tj
Input clock jitter
fspi
SPI clock rate when PLL used at fin = 62 MHz
10
MHz
62
MHz
40
50
20
ps
V2-SN/SE CMOS Electrical/Interface
fin
Input clock rate
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NOIV1SN1300A, NOIV2SN1300A
Table 5. ELECTRICAL SPECIFICATIONS
Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. (Notes 5, 6 and 7)
Parameter
Description
tj
Input clock jitter
fspi
SPI clock rate at fin = 62 MHz
Min
Typ
Max
20
Units
ps
2.5
MHz
Frame Specifications (V1-SN/SE-LVDS - Global Shutter)
fps
Frame rate at full resolution
150
fps
fps_roi1
Xres x Yres = 1024 x 1024
180
fps
fps_roi2
Xres x Yres = 640 x 480
540
fps
fps_roi3
Xres x Yres = 512 x 512
590
fps
fps_roi4
Xres x Yres = 256 x 256
1650
fps
FOT
Frame Overhead Time
45
ms
ROT
Row Overhead Time
1.1
ms
fpix
Pixel rate (4 channels at 62 Mpix/s)
248
Mpix/s
37
fps
Frame Specifications (V2-SN/SE CMOS - Global Shutter)
fps
Frame rate at full resolution
5. All parameters are characterized for DC conditions after thermal equilibrium is established.
6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is recommended
that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit.
7. Minimum and maximum limits are guaranteed through test and design.
For recommendations on power supply management
guidelines, refer to application note AN65463: VITA 1300
HSMC Cyclone Reference Board Design Recommendations.
Y
Color Filter Array
The V1SE and V2SE sensors are processed with a Bayer
RGB color pattern as shown in Figure 2. Pixel (0,0) has a red
filter situated to the bottom left.
pixel (0;0)
X
Figure 2. Color Filter Array for the Pixel Array
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NOIV1SN1300A, NOIV2SN1300A
Spectral Response Curve
Figure 3. Spectral Response Curve for Mono and Color
Note that green pixels on a Green−Red (Green 1) and Green−Blue (Green 2) row have similar responsivity to wavelength
trend as is depicted by the legend “Green”.
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NOIV1SN1300A, NOIV2SN1300A
OVERVIEW
are fed into the data formatting block. This block adds
synchronization information to the data stream based on the
frame timing. For the V1-SN/SE version, the data then goes
to the low voltage serial (LVDS) interface block which sends
the data out through the I/O ring. The V2-SN/SE sensor does
not have an LVDS interface but sends out the data through
a 10-bit parallel interface.
On-chip programmability is achieved through the Serial
Peripheral Interface (SPI). See the Register Map on page 50
for register details.
A bias block generates bias currents and voltages for all
analog blocks on the chip. By controlling the bias current,
the speed-versus-power of each block can be tuned. All
biasing programmability is contained in the bias block.
The sensor can automatically control exposure and gain
by enabling the automatic exposure control block (AEC).
This block regulates the integration time along with the
analog and digital gains to reach the desired intensity.
Figure 4 and Figure 5 give an overview of the major
functional blocks of the V1-SN/SE and V2-SN/SE sensor
respectively. The system clock is received by the CMOS
clock input. A PLL generates the intenal, high speed, clocks,
which are distributed to the other blocks. Optionally, the
V1-SN/SE can also accept a high speed LVDS clock, in
which case the PLL will be disabled.
The sequencer defines the sensor timing and controls the
image core. The sequencer is started either autonomously
(master mode) or on assertion of an external trigger (slave
mode). The image core contains all pixels and readout
circuits. The column structure selects pixels for readout and
performs correlated double sampling (CDS) or double
sampling (DS). The data comes out sequentially and is fed
into the analog front end (AFE) block. The programmable
gain amplifier (PGA) of the AFE adds the offset and gain.
The output is a fully differential analog signal that goes to the
ADC, where the analog signal is converted to a 10-bit data
stream. Depending on the operating mode, eight or ten bits
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NOIV1SN1300A, NOIV2SN1300A
Block Diagram
Image Core
Row Decoder
Image Core Bias
Pixel Array
(1280x1024)
Column Structure
Automatic
Exposure
Control
(AEC)
8 analog channels
Analog Front End (AFE)
8 x 10 bit
digital channels
Control &
Registers
Data Formatting
Clock
Distribution
4 x 10 bit
digital channels
Serializers & LVDS Interface
4 LVDS Channels
1 LVDS Sync Channel
1 LVDS Clock Channel
Reset
Triggers
LVDS Clock
Input
SPI Interface
CMOS Clock
Input
LVDS Receiver
LVDS Interface
External
PLL
Figure 4. Block Diagram − V1−SN/SE
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NOIV1SN1300A, NOIV2SN1300A
Block Diagram
Image Core
Row Decoder
Image Core Bias
Pixel Array
(1280x1024)
Column Structure
Automatic
Exposure
Control
(AEC)
8 analog channels
Analog Front End (AFE)
8 x 10 bit
digital channels
Control &
Registers
Data Formatting
4 x 10 bit
digital channels
Clock
Distribution
Output MUX
Reset
Triggers
10 bit Parallel Data
Frame Valid Indication
Line Valid Indication
CMOS Interface
External
CMOS Clock
Input
SPI Interface
PLL
Figure 5. Block Diagram − V2−SN/SE
Image Core
sequencer and can access the pixel array in global and rolling
shutter modes.
The pixel biasing block guarantees that the data on a pixel
is transferred properly to the column multiplexer when the
row drivers select a pixel line for readout.
The image core consists of:
• Pixel Array
• Address Decoders and Row Drivers
• Pixel Biasing
The pixel array contains 1280 (H) x 1024 (V) readable
pixels with a pixel pitch of 4.8 mm. Four dummy pixel rows
and columns are placed at every side of the pixel array to
eliminate possible edge effects. The sensor uses a 5T pixel
architecture, which makes it possible to read out the pixel
array in global shutter mode with double sampling (DS), or
in rolling shutter mode with correlated double sampling
(CDS).
The function of the row drivers is to access the image array
line by line, or all lines together, to reset or read the pixel
data. The row drivers are controlled by the on-chip
Phase Locked Loop
The PLL accepts a (low speed) clock and generates the
required high speed clock. Optionally this PLL can be
bypassed. Typical input clock frequency is 62 MHz.
LVDS Clock Receiver
The LVDS clock receiver receives an LVDS clock signal
and distributes the required clocks to the sensor.
Typical input clock frequency is 310 MHz in 10-bit mode
and 248 MHz in 8-bit mode. The clock input needs to be
terminated with a 100 W resistor.
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NOIV1SN1300A, NOIV2SN1300A
Column Multiplexer
Serializer and LVDS Interface (V1−SN/SE only)
All pixels of one image row are stored in the column
sample-and-hold (S/H) stages. These stages store both the
reset and integrated signal levels.
The data stored in the column S/H stages is read out
through 8 parallel differential outputs operating at a
frequency of 31 MHz.
At this stage, the reset signal and integrated signal values
are transferred into an FPN-corrected differential signal.
The column multiplexer also supports read-1-skip-1 and
read-2-skip-2 mode. Enabling this mode can speed up the
frame rate, with a decrease in resolution.
The serializer and LVDS interface block receives the
formatted (10-bit or 8-bit) data from the data formatting
block. This data is serialized and transmitted by the LVDS
output driver.
In 10-bit mode, the maximum output data rate is 620 Mbps
per channel. In 8-bit mode, the maximum output data rate is
496 Mbps per channel.
In addition to the LVDS data outputs, two extra LVDS
outputs are available. One of these outputs carries the output
clock, which is skew aligned to the output data channels. The
second LVDS output contains frame format synchronization
codes to serve system-level image reconstruction.
Bias Generator
The bias generator generates all required reference
voltages and bias currents that the on-chip blocks use. An
external resistor of 47 kW, connected between pin
IBIAS_MASTER and gnd_33, is required for the bias
generator to operate properly.
Output MUX (V2−SN/SE only)
The output MUX multiplexes the four data channels to
one channel and transmits the data words using a 10-bit
parallel CMOS interface.
Frame synchronization information is communicated by
means of frame and line valid strobes.
Analog Front End
The AFE contains 8 channels, each containing a PGA and
a 10-bit ADC.
For each of the 8 channels, a pipelined 10-bit ADC is used
to convert the analog image data into a digital signal, which
is delivered to the data formatting block. A black calibration
loop is implemented to ensure that the black level is mapped
to match the correct ADC input level.
Sequencer
•
•
•
Data Formatting
•
The data block receives data from two ADCs and
multiplexes this data to one data stream. A cyclic
redundancy check (CRC) code is calculated on the passing
data.
A frame synchronization data block is foreseen to transmit
synchronization codes such as frame start, line start, frame
end, and line end indications.
The data block calculates a CRC once per line for every
channel. This CRC code can be used for error detection at the
receiving end.
•
The sequencer:
Controls the image core. Starts and stops integration in
rolling and global shutter modes and control pixel
readout.
Operates the sensor in master or slave mode.
Applies the window settings. Organizes readouts so that
only the configured windows are read.
Controls the column multiplexer and analog core.
Applies gain settings and subsampling modes at the
correct time, without corrupting image data.
Starts up the sensor correctly when leaving standby
mode.
Automatic Exposure Control
The AEC block implements a control system to modulate
the exposure of an image. Both integration time and gains
are controlled by this block to target a predefined
illumination level.
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NOIV1SN1300A, NOIV2SN1300A
OPERATING MODES
The VITA 1300 sensor is able to operate in the following
shutter modes:
• Global Shutter Mode
♦ Pipelined Global Shutter
- Master
- Slave
♦ Triggered Global Shutter
- Master
- Slave
• Rolling Shutter Mode
Global Shutter Mode
In the global shutter mode, light integration takes place on
all pixels in parallel, although subsequent readout is
sequential. Figure 6 shows the integration and readout
sequence for the synchronous shutter. All pixels are light
sensitive at the same period of time. The whole pixel core is
reset simultaneously and after the integration time all pixel
values are sampled together on the storage node inside each
pixel. The pixel core is read out line by line after integration.
Note that the integration and readout can occur in parallel or
sequentially.
Figure 6. Global Shutter Operation
Pipelined Global Shutter
In pipelined global shutter mode, the integration and
readout are done in parallel. Images are continuously read
and integration of frame N is ongoing during readout of the
previous frame N-1. The readout of every frame starts with
a Frame Overhead Time (FOT), during which the analog
value on the pixel diode is transferred to the pixel memory
element. After the FOT, the sensor is read out line per line
and the readout of each line is preceded by the Row
Overhead Time (ROT). Figure 7 shows the exposure and
readout time line in pipelined global shutter mode.
• Master
In this operation mode, the integration time is set through
the register interface and the sensor integrates and reads out
the images autonomously. The sensor acquires images
without any user interaction.
Reset
N
Integration Time
Handling
Readout
Handling
Exposure Time N
FOT
Reset
N+1
Exposure Time N+1
FOT
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
É
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
É
FOT
ROT
Readout Frame N-1
FOT
Readout Frame N
FOT
Line Readout
Figure 7. Integration and Readout for Pipelined Shutter
• Slave
and integration starts. The integration continues until the
external pin is de-asserted by the system. Now, the image is
sampled and the readout is started. Figure 8 shows the
relation between the external trigger signal and the
exposure/readout timing.
The slave mode adds more manual control to the sensor.
The exposure time registers are ignored in this mode and the
integration time is controlled by an external pin. As soon as
the control pin is asserted, the pixel array goes out of reset
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NOIV1SN1300A, NOIV2SN1300A
External Trigger
Integration Time
Handling
Readout
Handling
Reset
N
FOT
Exposure Time N
FOT
Readout N−1
Reset
N+1
FOT
Exposure T im e N+1
Readout N
FOT
FOT
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉ
ROT
Line Readout
Figure 8. Pipelined Shutter Operated in Slave Mode
The triggered global mode is also controlled in a master
or slave mode fashion.
• Master
In this mode, a rising edge on the synchronization pin is
used to trigger the start of integration and readout. The
integration time is defined by a register setting. The sensor
autonomously integrates during this predefined time, after
which the FOT starts and the image array is readout
sequentially. A falling edge on the synchronization pin does
not have any impact on the readout or integration and
subsequent frames are started again for each rising edge.
Figure 9 shows the relation between the external trigger
signal and the exposure/readout timing.
If a rising edge is applied on the external trigger before the
exposure time and FOT of the previous frame is complete,
it is ignored by the sensor.
Triggered Global Shutter
In this mode, manual intervention is required to control
both the integration time and the start of readout. After the
integration time, indicated by a user controlled pin, the
image core is read out. After this sequence, the sensor goes
to an idle mode until a new user action is detected.
The three main differences with the pipelined global
shutter mode are
• Upon user action, one single image is read.
• Integration and readout are done sequentially. However,
the user can control the sensor in such a way that two
consecutive batches are overlapping, that is, having
concurrent integration and readout.
• Integration and readout is under user control through an
external pin.
This mode requires manual intervention for every frame.
The pixel array is kept in reset state until requested.
No effect on falling edge
External Trigger
Integration Time
Handling
Reset
N
Exposure Time N
FOT
Reset
N+1
Exposure Time N+1
FOT
Readout N
FOT
Register Controlled
Readout
Handling
FOT
Readout N-1
FOT
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
É
ROT
Line Readout
Figure 9. Triggered Shutter Operated in Master Mode
• Slave
FOT starts. The analog value on the pixel diode is
transferred to the pixel memory element and the image
readout can start. A request for a new frame is started when
the synchronization pin is asserted again.
Integration time control is identical to the pipelined
shutter slave mode. An external synchronization pin
controls the start of integration. When it is de-asserted, the
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13
NOIV1SN1300A, NOIV2SN1300A
Rolling Shutter Mode
Figure 10 schematically indicates the relative shift of the
integration times of different lines during the rolling shutter
operation. Each row is read and reset in a sequential way.
Each row in a particular frame is integrated for the same
time, but all lines in a frame ‘see’ a different stare time. As
a consequence, fast horizontal moving objects in the field of
view give rise to motion artifacts in the image; this is an
unavoidable property of a rolling shutter.
In rolling shutter mode, the pixel Fixed Pattern Noise
(FPN) is corrected on-chip by using the CDS technique.
After light integration on all pixels in a row is complete, the
storage node in the pixel is reset. Afterwards the integrated
signal is transferred to that pixel storage node. The
difference between the reset level and integrated signal is the
FPN corrected signal. The advantage of this technique,
compared to the DS technique used in the global shutter
modes, is that the reset noise of the pixel storage node is
cancelled. This results in a lower temporal noise level.
Another shutter mode supported by the sensor is the
rolling shutter mode. The shutter mechanism is an electronic
rolling shutter and the sensor operates in a streaming mode
similar to a video. This mechanism is controlled by the
on-chip sequencer logic. There are two Y pointers. One
points to the row that is to be reset for rolling shutter
operation, the other points to the row to be read out.
Functionally, a row is reset first and selected for read out
sometime later. The time elapsed between these two
operations is the exposure time.
Figure 10. Rolling Shutter Operation
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14
NOIV1SN1300A, NOIV2SN1300A
SENSOR OPERATION
Flowchart
Low Power Standby
In low power standby state, all power supplies are on, but
internally every block is disabled. No internal clock is
running (PLL / LVDS clock receiver is disabled).
All register settings are unchanged.
Only a subset of the SPI registers is active for read/write
in order to be able to configure clock settings and leave the
low power standby state. The only SPI registers that should
be touched are the ones required for the ‘Enable Clock
Management’ action described in Enable Clock
Management − Part 1 on page 17
Standby (1)
In standby state, the PLL/LVDS clock receiver is running,
but the derived logic clock signal is not enabled.
Standby (2)
In standby state, the derived logic clock signal is running.
All SPI registers are active, meaning that all SPI registers
can be accessed for read or write operations. All other blocks
are disabled.
Idle
In the idle state, all internal blocks are enabled, except the
sequencer block. The sensor is ready to start grabbing
images as soon as the sequencer block is enabled.
Running
In running state, the sensor is enabled and grabbing
images. The sensor can be operated in different
rolling/global master/slave modes.
Figure 11 shows the sensor operation flowchart. The
sensor can be in six different ‘states’. Every state is indicated
with the oval circle. These states are:
• Power off
• Low power standby
• Standby (1)
• Standby (2)
• Idle
• Running
These states are ordered by power dissipation. In
‘power-off’ state, the power dissipation is minimal; in
‘running’ state the power dissipation is maximal.
On the other hand, the lower the power consumption, the
more actions (and time) are required to put the sensor in
‘running’ state and grab images.
This flowchart allows the trade-off between power saving
and enabling time of the sensor.
Next to the six ‘states’ a set of ‘user actions’, indicated by
arrows, are included in the flowchart. These user actions
make it possible to move from one state to another.
Sensor States
Power Off
In this state, the sensor is inactive. All power supplies are
down and the power dissipation is zero.
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15
NOIV1SN1300A, NOIV2SN1300A
Power Off
Power Down
Sequence
Power Up Sequence
Low-Power Standby
Disable Clock Management
Part 1
Enable Clock Management - Part 1
Poll Lock Indication
(only when PLL is enabled)
Enable Clock Management - Part 2
(First Pass after Hard Reset)
Intermediate Standby
Required Register
Upload
Standby (2)
Sensor (re-)configuration
(optional)
Soft Power-Down
Soft Power-Up
Sensor (re-)configuration
(optional)
Idle
Disable Sequencer
Enable Sequencer
Sensor (re-)configuration
(optional)
Running
Figure 11. Sensor Operation Flowchart
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16
Assertion of reset_n Pin
Disable Clock Management
Part 2
Enable Clock Management - Part 2
(Not First Pass after Hard Reset)
Standby (1)
NOIV1SN1300A, NOIV2SN1300A
User Actions: Power Up Functional Mode Sequences
Enable Clock Management − Part 1
The ‘Enable Clock Management’ action configures the
clock management blocks and activates the clock generation
and distribution circuits in a pre-defined way. First, a set of
clock settings must be uploaded through the SPI register.
These settings are dependent on the desired operation mode
of the sensor.
Table 6 shows the SPI uploads to be executed to configure
the sensor for V1-SN/SE 8-bit serial, V1-SN/SE 10-bit
serial, or V2-SN/SE 10-bit parallel mode, with and without
the PLL.
In the serial modes, if the PLL is not used, the LVDS clock
input must be running.
In the V2-SN/SE10-bit parallel mode, the PLL is
bypassed. The clk_pll clock is used as sensor clock.
It is important to follow the upload sequence listed in
Table 6.
Power Up Sequence
Figure 12 shows the power up sequence of the sensor. The
figure indicates that the first supply to ramp-up is the vdd_18
supply, followed by vdd_33 and vdd_pix respectively. It is
important to comply with the described sequence. Any other
supply ramping sequence may lead to high current peaks
and, as consequence, a failure of the sensor power up.
The clock input should start running when all supplies are
stabilized. When the clock frequency is stable, the reset_n
signal can be de-asserted. After a wait period of 10 ms, the
power up sequence is finished and the first SPI upload can
be initiated.
NOTE: The ‘clock input’ can be the CMOS PLL clock
input (clk_pll), or the LVDS clock input
(lvds_clock_inn/p) in case the PLL is bypassed.
Use of Phase Locked Loop
If PLL is used, the PLL is started after the upload of the
SPI registers. The PLL requires (dependent on the settings)
some time to generate a stable output clock. A lock detect
circuit detects if the clock is stable. When complete, this is
flagged in a status register.
NOTE: The lock detect status must not be checked for
the V2-SN/SE sensor.
Check this flag by reading the SPI register. When the flag
is set, the ‘Enable Clock Management- Part 2’ action can be
continued. When PLL is not used, this step can be bypassed
as shown in Figure 11 on page 16.
clock input
reset_n
vdd_18
vdd_33
vdd_pix
SPI Upload
> 10us
> 10us
> 10us
> 10us
> 10us
Figure 12. Power Up Sequence
Table 6. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 1
Upload #
Address
Data
Description
V1-SN/SE 8-bit mode with PLL
1
2
0x0000
Monochrome sensor
0x0001
Color sensor
2
32
0x200C
Configure clock management
3
20
0x0000
Configure clock management
4
17
0X210F
Configure PLL
5
26
0x1180
Configure PLL lock detector
6
27
0xCCBC
Configure PLL lock detector
7
8
0x0000
Release PLL soft reset
8
16
0x0003
Enable PLL
0x0000
Monochrome sensor
V1-SN/SE 8-bit mode without PLL
1
2
0x0001
Color sensor
2
32
0x2008
Configure clock management
3
20
0x0001
Enable LVDS clock input
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NOIV1SN1300A, NOIV2SN1300A
Table 6. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 1
Upload #
Address
Data
Description
V1-SN/SE 10-bit mode with PLL
1
2
0x0000
Monochrome sensor
0x0001
Color sensor
2
32
0x2004
Configure clock management
3
20
0x0000
Configure clock management
4
17
0x2113
Configure PLL
5
26
0x2280
Configure PLL lock detector
6
27
0x3D2D
Configure PLL lock detector
7
8
0x0000
Release PLL soft reset
8
16
0x0003
Enable PLL
0x0000
Monochrome sensor
0x0001
Color sensor
V1-SN/SE 10-bit mode without PLL
1
2
2
32
0x2000
Configure clock management
3
20
0x0001
Enable LVDS clock input
1
2
0x0002
Monochrome sensor parallel mode selection
0x0003
Color sensor parallel mode selection
2
32
0x200C
Configure clock management
3
20
0x0000
Configure clock management
4
16
0x0007
Configure PLL bypass mode
V2-SN/SE 10-bit mode
The required uploads are listed in Table 4. Note that it is
important to follow the upload sequence listed in Table 7.
Enable Clock Management - Part 2
The next step to configure the clock management consists
of SPI uploads which enables all internal clock distribution.
Table 7. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 2
Upload #
Address
Data
Description
V1-SN/SE 8-bit mode with PLL
1
9
0x0000
Release clock generator soft reset
2
32
0x200E
Enable logic clock
3
34
0x0001
Enable logic blocks
V1-SN/SE 8-bit mode without PLL
1
9
0x0000
Release clock generator soft reset
2
32
0x200A
Enable logic clock
3
34
0x0001
Enable logic blocks
V1-SN/SE 10-bit mode with PLL
1
9
0x0000
Release clock generator soft reset
2
32
0x2006
Enable logic clock
3
34
0x0001
Enable logic blocks
V1-SN/SE 10-bit mode without PLL
1
9
0x0000
Release clock generator soft reset
2
32
0x2002
Enable logic clock
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NOIV1SN1300A, NOIV2SN1300A
Table 7. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 2
Upload #
Address
Data
Description
3
34
0x0001
Enable logic blocks
1
9
0x0000
Release clock generator soft reset
2
32
0x200E
Enable logic clock
3
34
0x0001
Enable logic blocks
V2-SN/SE 10-bit mode
and may cause the sensor to malfunction. The required
uploads are listed in Table 8.
Required Register Upload
In this phase, the ‘reserved’ register settings are uploaded
through the SPI register. Different settings are not allowed
Table 8. REQUIRED REGISTER UPLOAD
Upload #
Address
Data
Description
1
41
0x085A
2
129[13]
0x0
10-bit mode
0x1
8-bit mode
Configure image core
3
65
0x288B
Configure CP biasing
4
66
0x53C5
Configure AFE biasing
5
67
0x0344
Configure MUX biasing
6
68
0x0085
Configure LVDS biasing
7
70
0x4800
Configure AFE biasing
8
128
0x4710
Configure black calibration
9
197
0x0103
Configure black calibration
10
176
0x00F5
Configure AEC
11
180
0x00FD
Configure AEC
12
181
0x0144
Configure AEC
13
387
0x549F
Configure sequencer
14
388
0x549F
Configure sequencer
15
389
0x5091
Configure sequencer
16
390
0x1011
Configure sequencer
17
391
0x111F
Configure sequencer
18
392
0x1110
Configure sequencer
19
431
0x0356
Configure sequencer
20
432
0x0141
Configure sequencer
21
433
0x214F
Configure sequencer
22
434
0x214A
Configure sequencer
23
435
0x2101
Configure sequencer
24
436
0x0101
Configure sequencer
25
437
0x0B85
Configure sequencer
26
438
0x0381
Configure sequencer
27
439
0x0181
Configure sequencer
28
440
0x218F
Configure sequencer
29
441
0x218A
Configure sequencer
30
442
0x2101
Configure sequencer
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NOIV1SN1300A, NOIV2SN1300A
Table 8. REQUIRED REGISTER UPLOAD
Upload #
Address
Data
Description
31
443
0x0100
Configure sequencer
32
447
0x0B55
Configure sequencer
33
448
0x0351
Configure sequencer
34
449
0x0141
Configure sequencer
35
450
0x214F
Configure sequencer
36
451
0x214A
Configure sequencer
37
452
0x2101
Configure sequencer
38
453
0x0101
Configure sequencer
39
454
0x0B85
Configure sequencer
40
455
0x0381
Configure sequencer
41
456
0x0181
Configure sequencer
42
457
0x218F
Configure sequencer
43
458
0x218A
Configure sequencer
44
459
0x2101
Configure sequencer
45
460
0x0100
Configure sequencer
46
469
0x2184
Configure sequencer
47
472
0x1347
Configure sequencer
48
476
0x2144
Configure sequencer
49
480
0x8D04
Configure sequencer
50
481
0x8501
Configure sequencer
51
484
0xCD04
Configure sequencer
52
485
0xC501
Configure sequencer
53
489
0x0BE2
Configure sequencer
54
493
0x2184
Configure sequencer
55
496
0x1347
Configure sequencer
56
500
0x2144
Configure sequencer
57
504
0x8D04
Configure sequencer
58
505
0x8501
Configure sequencer
59
508
0xCD04
Configure sequencer
60
509
0xC501
Configure sequencer
stream. This action exists of a set of SPI uploads. The soft
power up uploads are listed in Table 9.
Soft Power Up
During the soft power up action, the internal blocks are
enabled and prepared to start processing the image data
Table 9. SOFT POWER UP REGISTER UPLOADS FOR MODE DEPENDENT REGISTERS
Upload #
Address
Data
Description
V1-SN/SE 8-bit mode with PLL
1
32
0x200F
Enable analog clock distribution
2
10
0x0000
Release soft reset state
3
64
0x0001
Enable biasing block
4
72
0x0203
Enable charge pump
5
40
0x0003
Enable column multiplexer
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NOIV1SN1300A, NOIV2SN1300A
Table 9. SOFT POWER UP REGISTER UPLOADS FOR MODE DEPENDENT REGISTERS
Upload #
Address
Data
Description
6
48
0x0001
Enable AFE
7
112
0x0007
Enable LVDS transmitters
V1-SN/SE 8-bit mode without PLL
1
32
0x200B
Enable analog clock distribution
2
10
0x0000
Release soft reset state
3
64
0x0001
Enable biasing block
4
72
0x0203
Enable charge pump
5
40
0x0003
Enable column multiplexer
6
48
0x0001
Enable AFE
7
112
0x0007
Enable LVDS transmitters
V1-SN/SE 10-bit mode with PLL
1
32
0x2007
Enable analog clock distribution
2
10
0x0000
Release soft reset state
3
64
0x0001
Enable biasing block
4
72
0x0203
Enable charge pump
5
40
0x0003
Enable column multiplexer
6
48
0x0001
Enable AFE
7
112
0x0007
Enable LVDS transmitters
V1-SN/SE 10-bit mode without PLL
1
32
0x2003
Enable analog clock distribution
2
10
0x0000
Release soft reset state
3
64
0x0001
Enable biasing block
4
72
0x0203
Enable charge pump
5
40
0x0003
Enable column multiplexer
6
48
0x0001
Enable AFE
7
112
0x0007
Enable LVDS transmitters
1
32
0x200F
Enable analog clock distribution
2
10
0x0000
Release soft reset state
3
64
0x0001
Enable biasing block
4
72
0x0203
Enable charge pump
5
40
0x0003
Enable column multiplexer
6
48
0x0001
Enable AFE
7
112
0x0000
Configure I/O
V2-SN/SE 10-bit mode
The ‘Enable Sequencer’ action consists of a set of register
uploads. The required uploads are listed in Table 10.
Enable Sequencer
During the ‘Enable Sequencer’ action, the frame grabbing
sequencer is enabled. The sensor starts grabbing images in
the configured operation mode. Refer to Sensor States on
page 15.
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21
NOIV1SN1300A, NOIV2SN1300A
Table 10. ENABLE SEQUENCER REGISTER UPLOAD
Upload #
Address
Data
Description
1
192[0]
0x1
Enable sequencer.
Note that this address contains other configuration bits to select the operation mode.
User Actions: Functional Modes to Power Down
Sequences
Disable Sequencer
During the ‘Disable Sequencer’ action, the frame
grabbing sequencer is stopped. The sensor stops grabbing
images and returns to the idle mode.
The ’Disable Sequencer’ action consists of a set of register
uploads. as listed in Table 11.
Refer to Silicon Errata on page 73 for standby power
considerations.
Table 11. DISABLE SEQUENCER REGISTER UPLOAD
Upload #
Address
Data
Description
1
192[0]
0x0
Disable sequencer.
Note that this address contains other configuration bits to select the operation mode.
current dissipation. This action exists of a set of SPI uploads.
The soft power down uploads are listed in Table 12.
Soft Power Down
During the soft power down action, the internal blocks are
disabled and the sensor is put in standby state to reduce the
Table 12. SOFT POWER DOWN REGISTER UPLOAD
Upload #
Address
Data
Description
1
112
0x0000
Disable LVDS transmitters
2
48
0x0000
Disable AFE
3
40
0x0000
Disable column multiplexer
4
72
0x0200
Disable charge pump
5
64
0x0000
Disable biasing block
6
10
0x0999
Soft reset
This action can be implemented with the SPI uploads as
shown in Table 13.
Disable Clock Management - Part 2
The ‘Disable Clock Management’ action stops the
internal clocking to further decrease the power dissipation.
Table 13. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 2
Upload #
Address
Data
Description
V1-SN/SE 8-bit mode with PLL
1
34
0x0000
Disable logic blocks
2
32
0x200C
Disable logic clock
3
9
0x0009
Soft reset clock generator
V1-SN/SE 8-bit mode without PLL
1
34
0x0000
Disable logic blocks
2
32
0x2008
Disable logic clock
3
9
0x0009
Soft reset clock generator
0x0000
Disable logic blocks
V1-SN/SE 10-bit mode with PLL
1
34
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22
NOIV1SN1300A, NOIV2SN1300A
Table 13. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 2
Upload #
Address
Data
Description
2
32
0x2004
Disable logic clock
3
9
0x0009
Soft reset clock generator
V1-SN/SE 10-bit mode without PLL
1
34
0x0000
Disable logic blocks
2
32
0x2000
Disable logic clock
3
9
0x0009
Soft reset clock generator
1
34
0x0000
Disable logic blocks
2
32
0x200C
Disable logic clock
3
9
0x0009
Soft reset clock generator
V2-SN/SE 10-bit mode
This action can be implemented with the SPI uploads as
shown in Table 14.
Disable Clock Management - Part 1
The ‘Disable Clock Management’ action stops the
internal clocking to further decrease the power dissipation.
Table 14. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 1
Upload #
Address
Data
Description
1
16
0x0000
Disable PLL
2
8
0x0099
Soft reset PLL
3
20
0x0000
Configure clock management
Power Down Sequence
Figure 13 illustrates the timing diagram of the preferred
power down sequence. It is important that the sensor is in
reset before the clock input stops running. Otherwise, the
internal PLL becomes unstable and the sensor gets into an
unknown state. This can cause high peak currents.
The same applies for the ramp down of the power
supplies. The preferred order to ramp down the supplies is
first vdd_pix, second vdd_33, and finally vdd_18. Any other
sequence can cause high peak currents.
NOTE: The ‘clock input’ can be the CMOS PLL clock
input (clk_pll), or the LVDS clock input
(lvds_clock_inn/p) in case the PLL is bypassed.
clock input
reset_n
vdd_18
vdd_33
vdd_pix
> 10us
> 10us
> 10us
> 10us
Figure 13. Power Down Sequence
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NOIV1SN1300A, NOIV2SN1300A
Sensor Re−configuration
Sensor Configuration
During the standby, idle, or running state several sensor
parameters can be reconfigured.
• Frame Rate and Exposure Time: Frame rate and
exposure time changes can occur during standby, idle,
and running states.
• Signal Path Gain: Signal path gain changes can occur
during standby, idle, and running states.
• Windowing: Changes with respect to windowing can
occur during standby, idle, and running states. Refer to
Multiple Window Readout on page 33 for more
information.
• Subsampling: Changes of the subsampling mode can
occur during standby, idle, and running states. Refer to
Subsampling on page 34 for more information.
• Shutter Mode: The shutter mode can only be changed
during standby or idle mode. Reconfiguring the shutter
mode during running state is not supported.
This device contains multiple configuration registers.
Some of these registers can only be configured while the
sensor is not acquiring images (while register 192[0] = 0),
while others can be configured while the sensor is acquiring
images. For the latter category of registers, it is possible to
distinguish the register set that can cause corrupted images
(limited number of images containing visible artifacts) from
the set of registers that are not causing corrupted images.
These three categories are described here.
Static Readout Parameters
Some registers are only modified when the sensor is not
acquiring images. Re-configuration of these registers while
images are acquired can cause corrupted frames or even
interrupt the image acquisition. Therefore, it is
recommended to modify these static configurations while
the sequencer is disabled (register 192[0] = 0). The registers
shown in Table 15 should not be reconfigured during image
acquisition. A specific configuration sequence applies for
these registers. Refer to the operation flow and startup
description.
Table 15. STATIC READOUT PARAMETERS
Group
Addresses
Description
Clock generator
32
Configure according to recommendation
Image core
40
Configure according to recommendation
AFE
48
Configure according to recommendation
Bias
64–71
Configure according to recommendation
LVDS
112
Configure according to recommendation
Sequencer mode selection
192 [6:1]
All reserved registers
Operation modes are:
• Rolling shutter enable
• triggered_mode
• slave_mode
Keep reserved registers to their default state, unless otherwise described in the
recommendation
an image containing visible artifacts. A typical example of
a corrupted image is an image which is not uniformly
exposed.
The effect is transient in nature and the new configuration
is applied after the transient effect.
Dynamic Configuration Potentially Causing Image
Artifacts
The category of registers as shown in Table 16 consists of
configurations that do not interrupt the image acquisition
process, but may lead to one or more corrupted images
during and after the re-configuration. A corrupted image is
Table 16. DYNAMIC CONFIGURATION POTENTIALLY CAUSING IMAGE ARTIFACTS
Group
Addresses
Description
Black level configuration
128–129
197[8]
Re-configuration of these registers may have an impact on the black-level calibration algorithm. The effect is a transient number of images with incorrect black level
compensation.
Sync codes
129[13]
130–135
Incorrect sync codes may be generated during the frame in which these registers
are modified.
Datablock test configurations
144–150
Modification of these registers may generate incorrect test patterns during
a transient frame.
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NOIV1SN1300A, NOIV2SN1300A
shown in Table 17. Some re-configuration may lead to one
frame being blanked. This happens when the modification
requires more than one frame to settle. The image is blanked
out and training patterns are transmitted on the data and sync
channels.
Dynamic Readout Parameters
It is possible to reconfigure the sensor while it is acquiring
images. Frame-related parameters are internally
re-synchronized to frame boundaries, such that the modified
parameter does not affect a frame that has already started.
However, there can be restrictions to some registers as
Table 17. DYNAMIC READOUT PARAMETERS
Group
Addresses
Subsampling/binning
192[7]
192[8]
Description
Subsampling or binning is synchronized to a new frame start.
Black lines
197
Re-configuration of these parameters causes one frame to be blanked out in rolling shutter operation mode, as the reset pointers need to be recalculated for the new frame timing.
No blanking in global shutter mode
Dummy lines
198
Re-configuration of these parameters causes one frame to be blanked out in rolling shutter operation mode, as the reset pointers need to be recalculated for the new frame timing.
No blanking in global shutter mode.
ROI configuration
195
256–279
Optionally, it is possible to blank out one frame after re-configuration of the active ROI in
rolling shutter mode. Therefore, register 206[8] must be asserted (blank_roi_switch configuration).
A ROI switch is only detected when a new window is selected as the active window
(re-configuration of register 195). Re-configuration of the ROI dimension of the active
window does not lead to a frame blank and can cause a corrupted image.
Exposure re-configuration
199-203
Exposure re-configuration does not cause artifact. However, a latency of one frame is
observed unless reg_seq_exposure_sync_mode is set to ‘1’ in triggered global mode
(master).
Gain re-configuration
204
Gains are synchronized at the start of a new frame. Optionally, one frame latency can be
incorporated to align the gain updates to the exposure updates (refer to register 204[13] gain_lat_comp).
of registers can be programmed in the sync_configuration
registers, which can be found at the SPI address 206.
Figure 14 shows a re-configuration that does not use the
sync_configuration option. As depicted, new SPI
configurations are synchronized to frame boundaries.
With sync_configuration = ‘1’. Configurations are
synchronized to the frame boundaries.
Figure 15 shows the usage of the sync_configuration
settings. Before uploading a set of registers, the
corresponding sync_configuration is de-asserted. After the
upload is completed, the sync_configuration is asserted
again and the sensor resynchronizes its set of registers to the
coming frame boundaries. As seen in the figure, this ensures
that the uploads performed at the end of frame N+2 and the
start of frame N+3 become active in the same frame (frame
N+4).
Freezing Active Configurations
Though the readout parameters are synchronized to frame
boundaries, an update of multiple registers can still lead to
a transient effect in the subsequent images, as some
configurations require multiple register uploads. For
example, to reconfigure the exposure time in master global
mode, both the fr_length and exposure registers need to be
updated. Internally, the sensor synchronizes these
configurations to frame boundaries, but it is still possible
that the re-configuration of multiple registers spans over two
or even more frames. To avoid inconsistent combinations,
freeze the active settings while altering the SPI registers by
disabling synchronization for the corresponding
functionality before re-configuration. When all registers are
uploaded, re-enable the synchronization. The sensor’s
sequencer then updates its active set of registers and uses
them for the coming frames. The freezing of the active set
Time Line
Frame NFrame N+1 Frame N+2 Frame N+3
Frame N+4
SPI Registers
Active Registers
Figure 14. Frame Synchronization of Configurations (no freezing)
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NOIV1SN1300A, NOIV2SN1300A
Frame NFrame N+1 Frame N+2 Frame N+3 Frame N+4
Time Line
sync_configuration
This configuration is not taken into
account as sync_register is inactive.
SPI Registers
Active Registers
Figure 15. Re−configuration Using Sync_configuration
NOTE: SPI updates are not taken into account while sync_configuration is inactive. The active configuration is frozen
for the sensor. Table 18 lists the several sync_configuration possibilities along with the respective registers being
frozen.
Table 18. ALTERNATE SYNC CONFIGURATIONS
Group
Affected Registers
Description
sync_rs_x_length
rs_x_length
Update of x-length configuration (rolling shutter only) is not synchronized at start of
frame when ’0’. The sensor continues with its previous configurations.
sync_black_lines
black_lines
Update of black line configuration is not synchronized at start of frame when ‘0’. The
sensor continues with its previous configurations.
sync_dummy_lines
sync_exposure
sync_gain
sync_roi
dummy_lines
Update of dummy line configuration is not synchronized at start of frame when ‘0’. The
sensor continues with its previous configurations.
mult_timer
fr_length
exposure
Update of exposure configurations is not synchronized at start of frame when ‘0’. The
sensor continues with its previous configurations.
mux_gainsw
afe_gain
Update of gain configurations is not synchronized at start of frame when ‘0’. The sensor continues with its previous configurations.
roi_active0[7:0]
subsampling
binning
Update of active ROI configurations is not synchronized at start of frame when ‘0’. The
sensor continues with its previous configurations.
Note: The window configurations themselves are not frozen. Re-configuration of active windows is not gated by this setting.
Window Configuration
window configurations. Note that switching between two
different windows might result in a corrupted frame. This is
inherent in the rolling shutter mechanism, where each line
must be reset sequentially before being read out. This
corrupted window can be blanked out by setting register
206[8]. In this case, a dead time is noted on the LVDS
interface when the window-switch occurs in the sensor.
During this blank out, training patterns are sent out on the
data and sync channels for the duration of one frame.
Global Shutter Mode
Up to 8 windows can be defined in global shutter mode
(pipelined or triggered). The windows are defined by
registers 256 to 279. Each window can be activated or
deactivated separately using register 195. It is possible to
reconfigure the windows while the sensor is acquiring
images. It is also possible to reconfigure the inactive
windows or to switch between predefined windows.
One can switch between predefined windows by
reconfiguring the register 195. This way a minimum number
of registers need to be uploaded when it is necessary to
switch between two or more sets of windows. As an example
of this, scanning the scene at higher frame rates using
multiple windows and switching to full frame capture when
the object is traced. Switching between the two modes only
requires an upload of one register.
Black Calibration
The sensor automatically calibrates the black level for
each frame. Therefore, the device generates a configurable
number of electrical black lines at the start of each frame.
The desired black level in the resulting output interface can
be configured and is not necessarily targeted to ‘0’.
Configuring the target to a higher level yields some
information on the left side of the black level distribution,
while the other end of the distribution tail is clipped to ‘0’
when setting the black level target to ‘0’.
The black level is calibrated for the 8 columns contained
in one kernel. Configurable parameters for the black-level
algorithm are listed in Table 19.
Rolling Shutter Mode
In rolling shutter mode it is not possible to read multiple
windows. Do not activate more than one window (register
195). However, it is possible to configure more than one
window and dynamically switch between the different
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NOIV1SN1300A, NOIV2SN1300A
Table 19. Configurable Parameters for Black Level Algorithm
Group
Addresses
Description
black_lines
This register configures the number of black lines that are generated at the start of a
frame. At least one black line must be generated. The maximum number is 255.
Note: When the automatic black-level calibration algorithm is enabled, make sure that this
register is configured properly to produce sufficient black pixels for the black-level filtering.
The number of black pixels generated per line is dependent on the operation mode and
window configurations:
Global Shutter - Each black line contains 160 kernels.
Rolling Shutter - As the line length is fundamental for rolling shutter operation, the length of
a black line is defined by the active window.
gate_first_line
When asserting this configuration, the first black line of the frame is blanked out and is not
used for black calibration. It is recommended to enable this functionality, because the first
line can have a different behavior caused by boundary effects. When enabling, the number
of black lines must be set to at least two in order to have valid black samples for the calibration algorithm.
auto_blackcal_enable
Internal black-level calibration functionality is enabled when set to ‘1’. Required black level
offset compensation is calculated on the black samples and applied to all image pixels.
When set to ‘0’, the automatic black-level calibration functionality is disabled. It is possible
to apply an offset compensation to the image pixels, which is defined by the registers
129[10:1].
Note: Black sample pixels are not compensated; the raw data is sent out to provide external statistics and, optionally, calibrations.
129[9:1]
blackcal_offset
Black calibration offset that is added or subtracted to each regular pixel value when auto_blackcal_enable is set to ‘0’. The sign of the offset is determined by register 129[10]
(blackcal_offset_dec).
Note: All channels use the same offset compensation when automatic black calibration is
disabled.
129[10]
blackcal_offset_dec
Sign of blackcal_offset. If set to ‘0’, the black calibration offset is added to each pixel. If set
to ‘1’, the black calibration offset is subtracted from each pixel.
This register is not used when auto_blackcal_enable is set to ‘1’.
black_samples
The black samples are low-pass filtered before being used for black level calculation. The
more samples are taken into account, the more accurate the calibration, but more samples
require more black lines, which in turn affects the frame rate.
The effective number of samples taken into account for filtering is 2^ black_samples.
Note: An error is reported by the device if more samples than available are requested
(refer to register 136).
Black Line Generation
197[7:0]
197[8]
Black Value Filtering
129[0]
128[10:8]
Black Level Filtering Monitoring
136
blackcal_error0
An error is reported by the device if there are requests for more samples than are available
(each bit corresponding to one data path). The black level is not compensated correctly if
one of the channels indicates an error. There are three possible methods to overcome this
situation and to perform a correct offset compensation:
• Increase the number of black lines such that enough samples are generated at the
cost of increasing frame time (refer to register 197).
• Relax the black calibration filtering at the cost of less accurate black level determination (refer to register 128).
• Disable automatic black level calibration and provide the offset via SPI register upload.
Note that the black level can drift in function of the temperature. It is thus recommended
to perform the offset calibration periodically to avoid this drift.
NOTE: The maximum number of samples taken into account for black level statistics is half the number of kernels.
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NOIV1SN1300A, NOIV2SN1300A
Serial Peripheral Interface
indicated in Figure 16. The sensor samples this
data on a rising edge of the sck clock (mosi needs
to be driven by the system on the falling edge of
the sck clock).
3. The tenth bit sent by the master indicates the type
of transfer: high for a write command, low for a
read command.
4. Data transmission:
- For write commands, the master continues
sending the 16-bit data, most significant bit first.
- For read commands, the sensor returns the
requested address on the miso pin, most significant
bit first. The miso pin must be sampled by the
system on the falling edge of sck (assuming
nominal system clock frequency and maximum
10 MHz SPI frequency).
5. When data transmission is complete, the system
deselects the sensor one clock period after the last
bit transmission by pulling ss_n high.
Maximum frequency for the SPI depends on the input
clock and type of sensor. The frequency is 1/6th of the PLL
input clock or 1/30th (in 10-bit mode) and 1/24th (in 8-bit
mode) of the LVDS input clock frequency.
At nominal input frequency (62 Mhz / 310 MHz /
248 MHz), the maximum frequency for the SPI is 10 MHz.
Bursts of SPI commands can be issued by leaving at least
two SPI clock periods between two register uploads.
Deselect the chip between the SPI uploads by pulling the
ss_n pin high.
The sensor configuration registers are accessed through
an SPI. The SPI consists of four wires:
• sck: Serial Clock
• ss_n: Active Low Slave Select
• mosi: Master Out, Slave In, or Serial Data In
• miso: Master In, Slave Out, or Serial Data Out
The SPI is synchronous to the clock provided by the
master (sck) and asynchronous to the sensor’s system clock.
When the master wants to write or read a sensor’s register,
it selects the chip by pulling down the Slave Select line
(ss_n). When selected, data is sent serially and synchronous
to the SPI clock (sck).
Figure 16 shows the communication protocol for read and
write accesses of the SPI registers. The VITA 1300 sensor
uses 9-bit addresses and 16-bit data words.
Data driven by the system is colored blue in Figure 16,
while data driven by the sensor is colored yellow. The data
in grey indicates high-Z periods on the miso interface. Red
markers indicate sampling points for the sensor (mosi
sampling); green markers indicate sampling points for the
system (miso sampling during read operations).
The access sequence is:
1. Select the sensor for read or write by pulling down
the ss_n line.
2. One SPI clock cycle after selecting the sensor, the
9-bit data is transferred, most significant bit first.
The sck clock is passed through to the sensor as
SP I − W R ITE
ss_n
t_sc ks s
ts ck
t_sssck
sck
ts _mos i
mo si
A8
th_mosi
A7
..
..
..
A1
A0
`1'
D15
D14
..
..
..
..
D1
D0
miso
SPI − REA D
ss_n
t_sssck
t_sc ks s
ts ck
sck
ts_mosi
mo si
A8
th_mosi
A7
..
..
..
A1
A0
`0'
th_mi so
ts _mi so
miso
D15
D14
..
..
Figure 16. SPI Read and Write Timing Diagram
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..
..
D1
D0
NOIV1SN1300A, NOIV2SN1300A
Table 20. SPI TIMING REQUIREMENTS
Group
Addresses
Description
Units
100 (*)
ns
ss_n low to sck rising edge
tsck
ns
tsckss
sck falling edge to ss_n high
tsck
ns
ts_mosi
Required setup time for mosi
20
ns
th_mosi
Required hold time for mosi
20
ns
ts_miso
Setup time for miso
tsck/2-10
ns
th_miso
Hold time for miso
tsck/2-20
ns
tspi
Minimal time between two consecutive SPI accesses (not shown in figure)
2 x tsck
ns
tsck
sck clock period
tsssck
*Value indicated is for nominal operation. The maximum SPI clock frequency depends on the sensor configuration (operation mode, input clock).
tsck is defined as 1/fSPI. See text for more information on SPI clock frequency restrictions.
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NOIV1SN1300A, NOIV2SN1300A
IMAGE SENSOR TIMING AND READOUT
reset period, the global photodiode reset condition is
abandoned. This indicates the start of the integration or
exposure time. The length of the exposure time is defined by
the registers exposure and mult_timer.
NOTE: The start of the exposure time is synchronized to
the start of a new line (during ROT) if the
exposure period starts during a frame readout.
As a consequence, the effective time during
which the image core is in a reset state is
extended to the start of a new line.
• Make sure that the sum of the reset time and exposure
time exceeds the time required to readout all lines. If
this is not the case, the exposure time is extended until
all (active) lines are read out.
• Alternatively, it is possible to specify the frame time
and exposure time. The sensor automatically calculates
the required reset time. This mode is enabled by the
fr_mode register. The frame time is specified in the
register fr_length.
The following sections describe the configurations for
single slope reset mechanism. Dual and triple slope handling
during global shutter operation is similar to the single slope
operation. Extra integration time registers are available.
Global Shutter Mode
Pipelined Global Shutter (Master)
The integration time is controlled by the registers
fr_length[15:0] and exposure[15:0]. The mult_timer
configuration defines the granularity of the registers
reset_length and exposure. It is read as number of system
clock cycles (16.129 ns nominal at 62 MHz) for the
V1-SN/SE version and 15.5 MHz cycles (64.516 ns
nominal) for the V2-SN/SE version.
The exposure control for (Pipelined) Global Master mode
is depicted in Figure 17.
The pixel values are transferred to the storage node during
FOT, after which all photo diodes are reset. The reset state
remains active for a certain time, defined by the reset_length
and mult_timer registers, as shown in the figure. Note that
meanwhile the image array is read out line by line. After this
Frame N
Exposure State
FOT
Readout
FOT
Reset
Frame N+1
Integrating
FOT
Reset
Integrating
FOT
FOT
FOT
Image Array Global Reset
reset_length
x
mult_timer
exposure
x
mult_timer
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 17. Integration Control for (Pipelined) Global Shutter Mode (Master)
exposure and mult_timer, as in the master pipelined global
mode. The fr_length configuration is not used. This
operation is graphically shown in Figure 18.
Triggered Global Shutter (Master)
In master triggered global mode, the start of integration
time is controlled by a rising edge on the trigger0 pin. The
exposure or integration time is defined by the registers
Frame N
Exposure State
FOT
Integrating
FOT
Reset
Integrating
FOT
(No effect on falling edge)
trigger0
Readout
Reset
Frame N+1
FOT
FOT
FOT
Image Array Global Reset
exposure x mult_timer
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 18. Exposure Time Control in Triggered Shutter Mode (Master)
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NOIV1SN1300A, NOIV2SN1300A
the pixel storage node and readout of the image array. In
other words, the high time of the trigger pin indicates the
integration time, the period of the trigger pin indicates the
frame time.
The use of the trigger during slave mode is shown in
Figure 19.
Notes:
• The falling edge on the trigger pin does not have any
impact. Note however the trigger must be asserted for
at least 100 ns.
• The start of the exposure time is synchronized to the
start of a new line (during ROT) if the exposure period
starts during a frame readout. As a consequence, the
effective time during which the image core is in a reset
state is extended to the start of a new line.
• If the exposure timer expires before the end of readout,
the exposure time is extended until the end of the last
active line.
• The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
Notes:
• The registers exposure, fr_length, and mult_timer are
not used in this mode.
• The start of exposure time is synchronized to the start
of a new line (during ROT) if the exposure period starts
during a frame readout. As a consequence, the effective
time during which the image core is in a reset state is
extended to the start of a new line.
• If the trigger is de-asserted before the end of readout,
the exposure time is extended until the end of the last
active line.
• The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
Triggered Global Shutter (Slave)
Exposure or integration time is fully controlled by means
of the trigger pin in slave mode. The registers fr_length,
exposure and mult_timer are ignored by the sensor.
A rising edge on the trigger pin indicates the start of the
exposure time, while a falling edge initiates the transfer to
Frame N
Exposure State
FOT
Reset
Frame N+1
Integrating
FOT
Reset
Integrating
FOT
trigger0
Readout
FOT
FOT
FOT
Image Array Global Reset
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 19. Exposure Time Control in Global−Slave Mode
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NOIV1SN1300A, NOIV2SN1300A
Rolling Shutter Mode
frame rate by adding so called dummy lines. A dummy line
lasts for the same time as a regular line, but no pixel data is
transferred to the system. The number of dummy lines is
controlled by the register dummy_lines. The rolling shutter
exposure mechanism is graphically shown in Figure 20.
The exposure time during rolling shutter mode is always
an integer multiple of line-times. The exposure time is
defined by the register exposure and expressed in number of
lines. The register fr_length and mult_timer are not used in
this mode.
The maximum exposure time is limited by the frame time.
It is possible to increase the exposure time at the cost of the
Figure 20. Integration Control in Rolling Shutter Mode
It is clear that when the number of rows and/or the length
of a row are reduced (by windowing or subsampling), the
frame time decreases and consequently the frame rate
increases.
To be able to artificially increase the frame time, it is
possible to:
• add dummy clock cycles to a row time
• add dummy rows to the frame
Note:
The duration of one line is the sum of the ROT and the time
required to read out one line (depends on the number of
active kernels in the window). Optionally, this readout time
can be extended by the configuration rs_x_length. This
register, expressed in number of periods of the logic clock
(16.129 ns for the V1-SN/SE version and 64.516 ns for the
V2-SN/SE version), determines the length of the x-readout.
However, the minimum for rs_x_length is governed by the
window size (x-size).
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NOIV1SN1300A, NOIV2SN1300A
ADDITIONAL FEATURES
Multiple Window Readout
Up to eight windows can be defined, possibly (partially)
overlapping, as illustrated in Figure 22.
The VITA 1300 sensor supports multiple window
readout, which means that only the user-selected Regions Of
Interest (ROI) are read out. This allows limiting data output
for every frame, which in turn allows increasing the frame
rate.
• In global shutter mode, up to eight ROIs can be
configured.
• In rolling shutter mode, only a single ROI is supported.
All multiple windowing features described further in
this section are only valid for global shutter mode.
1280 pixels
y1_end
ROI 1
1024 pixels
y0_end
y1_start
ROI 0
Window Configuration
Figure 24 shows the four parameters defining a region of
interest (ROI).
y0_start
1280 pixels
x0_start
y-end
x0_end
x1_start
x1_end
Figure 22. Overlapping Multiple Window
Configuration
1024 pixels
ROI 0
y-start
The sequencer analyses each line that need to be read out
for multiple windows.
Restrictions
The following restrictions for each line are assumed for
the user configuration:
• Windows are ordered from left to right, based on their
x−start address:
x_start_roi(i) v x_start_roi(j) AND
x-start x-end
Figure 21. Region of Interest Configuration
x_end_roi(i) vx_end_roi(j)
• x−start[7:0]
Where j > i
x-start defines the x-starting point of the desired window.
The sensor reads out 8 pixels in one single clock cycle. As
a consequence, the granularity for configuring the x-start
position is also 8 pixels for no sub sampling. The value
configured in the x-start register is multiplied by 8 to find the
corresponding column in the pixel array.
• x-end[7:0]
This register defines the window end point on the x-axis.
Similar to x-start, the granularity for this configuration is
one kernel. x-end needs to be larger than x-start.
• y-start[9:0]
The starting line of the readout window. The granularity
of this setting is one line, except with color sensors where it
needs to be an even number.
• y-end[9:0]
The end line of the readout window. y-end must be
configured larger than y-start. This setting has the same
granularity as the y-start configuration.
Processing Multiple Windows
The sequencer control block houses two sets of counters
to construct the image frame. As previously described, the
y-counter indicates the line that needs to be read out and is
incremented at the end of each line. For the start of the frame,
it is initialized to the y-start address of the first window and
it runs until the y-end address of the last window to be read
out. The last window is configured by the configuration
registers and it is not necessarily window #7.
The x-counter starts counting from the x-start address of
the window with the lowest ID which is active on the
addressed line. Only windows for which the current
y-address is enclosed are taken into account for scanning.
Other windows are skipped.
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NOIV1SN1300A, NOIV2SN1300A
• The x-pointer starting position is equal to the x-start
ROI 2
ys
ROI 3
•
ROI 4
ROI 1
•
ROI 0
configuration of the first active window on the current
line addressed. This window is not necessarily window
#0.
The x-pointer is not necessarily incremented by one
each cycle. At the end of a window it can jump to the
start of the next window.
Each window can be activated separately. There is no
restriction on which window and how many of the 8
windows are active.
Subsampling
Subsampling is used to reduce the image resolution. This
allows increasing the frame rate. Two subsampling modes
are supported: for monochrome sensors (V1/V2-SN) and
color sensors (V1/V2-SE).
Figure 23. Scanning the Image Array with Five
Windows
Figure 23 illustrates a practical example of a configuration
with five windows. The current position of the read pointer
(ys) is indicated by a red line crossing the image array. For
this position of the read pointer, three windows need to be
read out. The initial start position for the x-kernel pointer is
the x-start configuration of ROI1. Kernels are scanned up to
the ROI3 x-end position. From there, the x-pointer jumps to
the next window, which is ROI4 in this illustration. When
reaching ROI4’s x-end position, the read pointer is
incremented to the next line and xs is reinitialized to the
starting position of ROI1.
Notes:
• The starting point for the readout pointer at the start of
a frame is the y-start position of the first active window.
• The read pointer is not necessarily incremented by one,
but depending on the configuration, it can jump in
y-direction. In Figure 23, this is the case when reaching
the end of ROI0 where the read pointer jumps to the
y-start position of ROI1
Monochrome Sensors
For monochrome sensors, the read-1-skip-1 subsampling
scheme is used. Subsampling occurs both in x- and ydirection.
Color Sensors
For color sensors, the read-2-skip-2 subsampling scheme
is used. Subsampling occurs both in x- and y- direction.
Figure 24 shows which pixels are read and which ones are
skipped.
Binning
Pixel binning is a technique in which different pixels are
averaged in the analog domain. A 2x1 binning mode is
available on the monochrome sensors (V1/V2-SN). When
enabled, two neighboring pixels in the x-direction are
averaged while line readout happens in a read-1-skip-1
manner.
Pixel binning is not supported on V1/V2-SE.
Figure 24. Subsampling Scheme for Monochrome and Color Sensors
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NOIV1SN1300A, NOIV2SN1300A
Multiple Slope Integration
To increase the dynamic range of the sensor, a second
slope is applied in the dual slope mode (green curve). The
sensor has the same responsivity in the black as for a single
slope, but from ‘knee point 1’ on, the sensor is less
responsive to incoming light. The result is that the saturation
point is at a higher light power level.
To further increase the dynamic range, a third slope can be
applied, resulting in a second knee point.
The multiple slope function is only available in global
shutter modes. Refer to section Global Shutter Mode on
page 30 for general notes applicable to the global shutter
operation and more particular to the use of the trigger0 pin.
‘Multiple Slope Integration’ is a method to increase the
dynamic range of the sensor. The VITA 1300 supports up to
three slopes.
Figure 25 shows the sensor response to light when the
sensor is used with one slope, two slopes, and three slopes.
The X-axis represents the light power; the Y-axis shows the
sensor output signal. The kneepoint of the multiple slope
curves are adjustable in both position and voltage level.
It is clear that when using only one slope (red curve), the
sensor has the same responsivity over the entire range, until
the output saturates at the point indicated with ‘single slope
saturation point’.
output
1023
slope 3
`kneepoint 2'
slope 1 slope 2
`kneepoint 1'
0
single slope
saturation point
light
triple slope
saturation point
dual slope
saturation point
Figure 25. Multiple Slope Operation
Required Register Uploads
Multiple slope integration requires the uploads as
described in the following table. Note that these are
cumulative with the required register uploads (Table 21)
Table 21. REQUIRED UPLOADS FOR MULTIPLE
SLOPE INTEGRATION
Upload #
Address
Data
Description
1
194[3]
0x1
Configure sequencer
2
385
0x321F
Configure sequencer
3
386
0x321F
Configure sequencer
4
387
0x321F
Configure sequencer
5
388
0x321F
Configure sequencer
6
389
0x101F
Configure sequencer
15
415
0x703F
Configure sequencer
16
416
0x7034
Configure sequencer
17
417
0x7030
Configure sequencer
18
423
0x705F
Configure sequencer
19
424
0x7054
Configure sequencer
20
425
0x7050
Configure sequencer
To disable multiple slope integration, the following
uploads are required on top of disabling dual_slope_enable
and triple_slope_enable.
Table 22. REQUIRED UPLOADS FOR RETURNING TO
SINGLE SLOPE INTEGRATION
Upload #
Address
Data
Description
1
385
0x549F
Configure sequencer
2
386
0x549F
Configure sequencer
7
390
0x549F
Configure sequencer
8
391
0x549F
Configure sequencer
9
392
0x549F
Configure sequencer
3
387
0x549F
Configure sequencer
10
393
0x549F
Configure sequencer
4
388
0x549F
Configure sequencer
11
394
0x5091
Configure sequencer
5
389
0x5091
Configure sequencer
12
395
0x1011
Configure sequencer
6
390
0x1011
Configure sequencer
391
0x111F
Configure sequencer
392
0x1110
Configure sequencer
13
396
0x111F
Configure sequencer
7
14
397
0x1110
Configure sequencer
8
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NOIV1SN1300A, NOIV2SN1300A
dual_slope_enable and triple_slope_enable and their values
are defined by the registers exposure_ds and exposure_ts.
NOTE: Dual and triple slope sequences must start after
readout of the previous frame is fully completed.
Figure 26 shows the frame timing for pipelined master
mode with dual and triple slope integration and
fr_mode = ‘0’ (fr_length representing the reset length).
In triggered master mode, the start of integration is
initiated by a rising edge on trigger0, while the falling edge
does not have any relevance. Exposure duration and
dual/triple slope points are defined by the registers.
Kneepoint Configuration (Multiple Slope Reset Levels)
The kneepoint reset levels are configured by means of
DAC configurations in the image core. The dual slope
kneepoint is configured with the dac_ds configuration,
while the triple slope kneepoint is configured with the
dac_ts register setting. Both are located on address 41.
Multiple Slope Integration in “Master Mode” (Pipelined or
Triggered)
In master mode, the time stamps for the double and triple
slope resets are configured in a similar way as the exposure
time. They are enabled through the registers
Figure 26. Multiple Slope Operation in Master Mode for fr_mode = ‘0’ (Pipelined)
initiates the triple slope reset sequence. Rising edges on
trigger1 and trigger2 do not have any impact.
NOTE: Dual and triple slope sequences must start after
readout of the previous frame is fully completed.
Slave Mode
In slave mode, the register settings for integration control
are ignored. The user has full control through the trigger0,
trigger1 and trigger2 pins. A falling edge on trigger1
initiates the dual slope reset while a falling edge on trigger2
Figure 27. Multiple Slope Operation in Slave Mode
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Black Reference
exposure time and gain are reconfigured together, as an
exposure time update always has one frame latency.
The sensor reads out one or more black lines at the start of
every new frame. The number of black lines to be generated
is programmable and is minimal equal to 1. The length of the
black lines depends on the operation mode: for Rolling
Shutter mode, the length of the black line is equal to the line
length configured in the active window. For Global Shutter
mode, the sensor always reads out the entire line (160
kernels), independent of window configurations.
The black references are used to perform black calibration
and offset compensation in the data channels. The raw black
pixel data is transmitted over the usual output interface,
while the regular image data is compensated (can be
bypassed).
On the output interface, black lines can be seen as a
separate window, however without Frame Start and Ends
(only Line Start/End). The Sync code following the Line
Start and Line End indications (“window ID”) contains the
active window number for Rolling Shutter operation, while
it is 0 for Snapshot Shutter operation. Black reference data
is classified by a BL code.
Table 23. SIGNAL PATH GAIN STAGES
(Analog Gain Stages)
Signal Path Gain
gain_stage1
Gain
Stage 1
gain_stage2
Gain
Stage 2
GAIN total
0x2
1.00
0xF
1.00
1.00
0x2
1.00
0x7
1.14
1.14
0x2
1.00
0x3
1.33
1.33
0x2
1.00
0x5
1.60
1.60
0x2
1.00
0x1
2.00
2.00
0x1
2.00
0x7
1.14
2.29
0x1
2.00
0x3
1.33
2.67
0x1
2.00
0x5
1.60
3.20
0x1
2.00
0x1
2.00
4.00
0x1
2.00
0x6
2.67
5.33
0x1
2.00
0x2
4.00
8.00
Digital Gain Stage
The digital gain stage allows fine gain adjustments on the
digitized samples. The gain configuration is an absolute 5.7
unsigned number (5 digits before and 7 digits after the
decimal point).
Analog Gain Stages
Two gain steps are available in the analog data path to
apply gain to the analog signal before it is digitized. The gain
amplifier can apply a gain of 1x to 8x to the analog signal.
The moment a gain re-configuration is applied and
becomes valid can be controlled by the gain_lat_comp
configuration.
With ‘gain_lat_comp’ set to ‘0’, the new gain
configurations are applied from the very next frame.
With ‘gain_lat_comp’ set to ‘1’, the new gain settings are
postponed by one extra frame. This feature is useful when
Automatic Exposure Control
Requested Illumination Level
(Target)
AEC
Statistics
Total Gain
Requested Gain
Changes
The exposure control mechanism has the shape of a
general feedback control system. Figure 28 shows the high
level block diagram of the exposure control loop.
AEC
Filter
AEC
Enforcer
Integration Time
Analog Gain (Coarse Steps)
Digital Gain (Fine Steps)
Image Capture
Figure 28. Automatic Exposure Control Loop
Three main blocks can be distinguished:
• The statistics block compares the average of the current
•
•
image’s samples to the configured target value for the
average illumination of all pixels
The relative gain change request from the statistics
block is filtered in the time domain (low pass filter)
before being integrated. The output of the filter is the
total requested gain in the complete signal path.
The enforcer block accepts the total requested gain and
distributes this gain over the integration time and gain
stages (both analog and digital)
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NOIV1SN1300A, NOIV2SN1300A
The automatic exposure control loop is enabled by
asserting the aec_enable configuration in register 160.
NOTE: Dual and Triple slope integration is not
supported in conjunction with the AEC.
Color Sensor
The weight of each color can be configured for color
sensors by means of scale factors. Note these scale factor are
only used to calculate the statistics in order to compensate
for (off-chip) white balancing and/or color matrices. The
pixel values itself are not modified.
The scale factors are configured as 3.7 unsigned numbers
(0x80 = unity).
AEC Statistics Block
The statistics block calculates the average illumination of
the current image. Based on the difference between the
calculated illumination and the target illumination the
statistics block requests a relative gain change.
Table 26. COLOR SCALE FACTORS
Statistics Subsampling and Windowing
For average calculation, the statistics block will
sub-sample the current image or windows by taking every
fourth sample into account. Note that only the pixels read out
through the active windows are visible for the AEC. In the
case where multiple windows are active, the samples will be
selected from the total samples. Samples contained in a
region covered by multiple (overlapping) window will be
taking into account only once.
It is possible to define an AEC specific sub-window on
which the AEC will calculate it’s average. For instance, the
sensor can be configured to read out a larger frame, while the
illumination is measured on a smaller region of interest, e.g.
center weighted.
Name
Description
192[10]
roi_aec_enable
When 0x0, all active windows are selected for statistics calculation.
When 0x1, the AEC samples are
selected from the active pixels contained in the region of interest defined
by roi_aec
253-255
roi_aec
These registers define a window from
which the AEC samples will be selected when roi_aec_enable is asserted.
Configuration is similar to the regular
region of interests.
The intersection of this window with
the active windows define the selected pixels. It is important that this window at least overlaps with one or
more active windows.
Table 25. AEC TARGET ILLUMINATION
CONFIGURATION
Name
Description
desired_in­
tensity
Target intensity value, on 10­bit scale.
For 8­bit mode, target value is con­
figured on desired_intensity[9:2]
162[9:0]
red_scale_factor
Red scale factor for AEC statistics
163[9:0]
green1_scale_factor
Green1 scale factor for AEC
statistics
164[9:0]
green2_scale_factor
Green2 scale factor for AEC
statistics
165[9:0]
blue_scale_factor
Blue scale factor for AEC statistics
Exposure Control Parameters
The several gain parameters are described below, in the
order in which these are controlled by the AEC for large
adjustments. Small adjustments are regulated by digital gain
only.
• Exposure Time
In rolling shutter mode, the exposure time is the time
elapsed between resetting a particular line and reading it out.
This time is constant for all lines in a frame, lest the image
be non-uniformly exposed. The exposure time is always an
integer multiple of the line time.
In a snapshot shutter mode, the exposure is the time
between the global image array reset de-assertion and the
pixel charge transfer. The granularity of the integration time
steps is configured by the mult_timer register.
NOTE: The exposure_time register is ignored when the
AEC is enabled. The register fr_length defines
the frame time and needs to be configured
accordingly.
Target Illumination
The target illumination value is configured by means of
register desired_intensity.
Register
Description
AEC Enforcer Block
The enforcer block calculates the four different gain
parameters, based on the required total gain, thereby
respecting a specific hierarchy in those configurations.
Some (digital) hysteresis is added so that the (analog) sensor
settings don’t need to change too often.
Important note for rolling shutter operation: a minimum
of 4 dummy lines is required when using the automatic
exposure controller.
161[9:0]
Name
Configure these factors to their default value for
monochrome sensors.
AEC Filter Block
The filter block low-pass filters the gain change requests
received from the statistics block.
The filter can be restarted by asserting the restart_filter
configuration of register 160.
Table 24. AEC SAMPLE SELECTION
Register
Register
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NOIV1SN1300A, NOIV2SN1300A
• Analog Gain
The sensor has two analog gain stages, configurable
independently from each other. Typically the AEC shall first
regulate the first stage. Optionally this behavior can be
inverted by setting the amp_pri register.
• Digital Gain
The last gain stage is a gain applied on the digitized
samples. The digital gain is represented by a 5.7 unsigned
number (i.e. 7 bits after the decimal point). While the analog
gain steps are coarse, the digital gain stage makes it possible
to achieve very fine adjustments.
AEC Control Range
The control range for each of the exposure parameters can
be pre-programmed in the sensor. Note that for rolling
shutter operation the maximum integration time should not
exceed the number of lines read out (i.e. the sum of black
lines, active window-defined lines and dummy lines).
Table 27 lists the relevant registers.
Register
Name
Description
min_exposure
Lower bound for the integration
time applied by the AEC
169[1:0]
min_mux_gain
Lower bound for the first stage
analog amplifier.
This stage has two configurations with the following approximative gains:
0x0 = 1x
0x1 = 2x
169[3:2]
169[15:4]
min_afe_gain
min_digital_gain
Upper bound for the integration
time applied by the AEC
171[1:0]
max_mux_gain
Upper bound for the first stage
analog amplifier.
This stage has two configurations with the following approximative gains:
0x0 = 1x
0x1 = 2x
171[15:4]
max_digital_gain
Upper bound for the digital gain
stage. This configuration specifies the effective gain in 5.7
unsigned format
Register
Name
Description
AEC Status Registers
Lower bound for the digital gain
stage. This configuration specifies the effective gain in 5.7
unsigned format
max_exposure
Upper bound for the second
stage analog amplifier
This stage has four configurations with the following approximative gains:
0x0 = 1.00x
0x1 = 1.33x
0x2 = 2.00x
0x3 = 2.50x
Table 28. EXPOSURE CONTROL STATUS REGISTERS
Lower bound for the second
stage analog amplifier
This stage has four configurations with the following approximative gains:
0x0 = 1.00x
0x1 = 1.33x
0x2 = 2.00x
0x3 = 2.50x
170[15:0]
max_afe_gain
AEC Update Frequency
As an integration time update has a latency of one frame,
the exposure control parameters are evaluated and updated
every other frame.
Note: The gain update latency must be postpone to match
the integration time latency. This is done by asserting the
gain_lat_comp register on address 204[13].
Exposure Control Status Registers
Configured integration and gain parameters are reported
to the user by means of status registers. The sensor provides
two levels of reporting: the status registers reported in the
AEC address space are updated once the parameters are
recalculated and requested to the internal sequencer. The
status registers residing in the sequencer’s address space on
the other hand are updated once these parameters are taking
effect on the image readout. The first set shall thus lead the
second set of status registers.
Table 27. MINIMUM AND MAXIMUM EXPOSURE
CONTROL PARAMETERS
168[15:0]
171[3:2]
184[15:0]
total_pixels
Total number of pixels taken into
account for the AEC statistics.
186[9:0]
average
Calculated average illumination level for the current frame.
187[15:0]
exposure
AEC calculated exposure.
Note: this parameter is updated at
the frame end.
188[1:0]
mux_gain
AEC calculated analog gain (1st
stage)
Note: this parameter is updated at
the frame end.
188[3:2]
afe_gain
AEC calculated analog gain (2st
stage)
Note: this parameter is updated at
the frame end.
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NOIV1SN1300A, NOIV2SN1300A
188[15:4]
digital_gain
Temperature Sensor
AEC calculated digital gain (5.7 unsigned format)
Note: this parameter is updated at
the frame end.
The VITA 1300 has an on-chip temperature sensor which
can output a digital code (Tsensor) of the silicon junction
temperature. The Tsensor output is a 8-bit digital count
between 0 and 255, proportional to the temperature of the
silicon substrate. This reading can be translated directly to
a temperature reading in °C by calibrating the 8-bit readout
at 0°C and 85°C to achieve an output accuracy of ±2°C. The
Tsensor output can also be calibrated using a single
temperature point (example: room temperature or the
ambient temperature of the application), to achieve an
output accuracy of ±5°C.
The resolution of the temperature sensor in ºC / bit is made
almost constant over process variations by design.
Therefore any process variation will result in an offset in the
bit count and this offset will remain within ±5°C over the
temperature range of 0°C and 85°C.
Tsensor output digital code can be read out through the
SPI interface. Refer to the Register Map on page 50
The output of the temperature sensor to the SPI:
tempd_reg_temp<7:0>: This is the 8-bit N count readout
proportional to temperature.
The input from the SPI:
The reg_tempd_enable is a global enable and this enables
or disables the temperature sensor when logic high or logic
low respectively. The temperature sensor is reset or disabled
when the input reg_tempd_enable is set to a digital low state.
Sequencer Status Registers
208[15:0]
mult_timer
mult_timer for current frame (global
shutter only).
Note: this parameter is updated
once it takes effect on the image.
209[15:0]
reset_length
Image array reset length for the current frame (global shutter only).
Note: this parameter is updated
once it takes effect on the image.
210[15:0]
exposure
Exposure for the current frame.
Note: this parameter is updated
once it takes effect on the image.
211[15:0]
exposure_ds
Dual slope exposure for the current
frame. Note this parameter is not
controlled by the AEC.
Note: this parameter is updated
once it takes effect on the image.
212[15:0]
exposure_ts
Triple slope exposure for the current frame. Note this parameter is
not controlled by the AEC.
Note: this parameter is updated
once it takes effect on the image.
213[4:0]
mux_gainsw
1st stage analog gain for the current
frame.
Note: this parameter is updated
once it takes effect on the image.
213[12:5]
afe_gain
2st stage analog gain for the current
frame.
Note: this parameter is updated
once it takes effect on the image.
214[11:0]
db_gain
Digital gain configuration for the
current frame (5.7 unsigned format).
Note: this parameter is updated
once it takes effect on the image.
214[11:0]
dual_slope
Dual slope configuration for the current frame
Note 1: this parameter is updated
once it takes effect on the image.
Note 2: This parameter is not controlled by the AEC.
214[11:0]
triple_slope
Triple slope configuration for the
current frame.
Note 1: this parameter is updated
once it takes effect on the image.
Note 2: This parameter is not controlled by the AEC.
Calibration using one temperature point
The temperature sensor resolution is fixed for a given type
of package for the operating range of 0°C to +85°C and
hence devices can be calibrated at any ambient temperature
of the application, with the device configured in the mode of
operation.
Interpreting the actual temperature for the digital code
readout:
The formula used is
TJ = R (Nread - Ncalib) + Tcalib
TJ = junction die temperature
R = resolution in degrees/LSB (typical 0.75 deg/LSB)
Nread = Tsensor output (LSB count between 0 and 255)
Tcalib = Tsensor calibration temperature
Ncalib = Tsensor output reading at Tcalib
Monitor Pins
The internal sequencer has two monitor outputs (Pin 44
and Pin 45) that can be used to communicate the internal
states from the sequencer. A three-bit register configures the
assignment of the pins.
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NOIV1SN1300A, NOIV2SN1300A
Table 29. REGISTER SETTING FOR THE MONITOR SELECT PIN
monitor_select [2:0]
192 [13:11]
monitor pin
0x0
monitor0
monitor1
‘0’
‘0’
0x1
monitor0
monitor1
Integration Time
ROT Indication (‘1’ during ROT, ‘0’ outside)
0x2
monitor0
monitor1
Integration Time
Dual/Triple Slope Integration (asserted during DS/TS FOT sequence)
0x3
monitor0
monitor1
Start of x-Readout Indication
Black Line Indication (‘1’ during black lines, ‘0’ outside)
0x4
monitor0
monitor1
Frame Start Indication
Start of ROT Indication
0x5
monitor0
monitor1
First Line Indication (‘1’ during first line, ‘0’ for all others)
Start of ROT Indication
0x6
monitor0
monitor1
ROT Indication (‘1’ during ROT, ‘0’ outside)
Start of X-Readout Indication
0x7
monitor0
monitor1
Start of X-readout Indication for Black Lines
Start of X-readout Indication for Image Lines
Description
DATA OUTPUT FORMAT
The VITA 1300 is available in two different versions:
Frame Format
The frame format in 8-bit mode is identical to the 10-bit
mode with the exception that the Sync and data word depth
is reduced to eight bits.
The frame format in 10-bit mode is explained by example
of the readout of two (overlapping) windows as shown in
Figure 29 (a).
The readout of a frame occurs on a line-by-line basis. The
read pointer goes from left to right, bottom to top.
Figure 29 indicates that, after the FOT is completed, the
sensor reads out a number of black lines for black calibration
purposes. After these black lines, the windows are
processed. First a number of lines which only includes
information of ‘ROI 0’ are sent out, starting at position
y0_start. When the line at position y1_start is reached, a
number of lines containing data of ‘ROI 0’ and ‘ROI 1’ are
sent out, until the line position of y0_end is reached. From
there on, only data of ‘ROI 1’ appears on the data output
channels until line position y1_end is reached
During read out of the image data over the data channels,
the sync channel sends out frame synchronization codes
which give information related to the image data that is sent
over the four data output channels.
Each line of a window starts with a Line Start (LS)
indication and ends with a Line End (LE) indication. The
line start of the first line is replaced by a Frame Start (FS);
the line end of the last line is replaced with a Frame End
indication (FE). Each such frame synchronization code is
followed by a window ID (range 0 to 7). For overlapping
windows, the line synchronization codes of the overlapping
windows with lower IDs are not sent out (as shown in the
• V1-SN/SE: Four LVDS output channels, together with
•
an LVDS clock output and an LVDS synchronization
output channel.
V2-SN/SE: A 10-bit parallel CMOS output, together
with a CMOS clock output and ‘frame valid’ and ‘line
valid’ CMOS output signals.
V1-SN/SE: LVDS Interface Version
LVDS Output Channels
The image data output occurs through four LVDS data
channels. A synchronization LVDS channel and an LVDS
output clock signal is foreseen to synchronize the data.
The four data channels are used to output the image data
only. The sync channel transmits information about the data
sent over these data channels (includes codes indicating
black pixels, normal pixels, and CRC codes).
8-bit / 10-bit Mode
The sensor can be used in 8-bit or 10-bit mode.
In 10-bit mode, the words on data and sync channel have
a 10-bit length. The output data rate is 620 Mbps.
In 8-bit mode, the words on data and sync channel have an
8-bit length, the output data rate is 496 Mbps.
Note that the 8-bit mode can only be used to limit the data
rate at the consequence of image data word depth. It is not
supported to operate the sensor in 8-bit mode at a higher
clock frequency to achieve higher frame rates.
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NOIV1SN1300A, NOIV2SN1300A
illustration: no LE/FE is transmitted for the overlapping part
of window 0).
NOTE: In Figure 29, only Frame Start and Frame End
Sync words are indicated in (b). CRC codes are
also omitted from the figure.
y1_end
ROI 1
y0_end
y1_start
ROI 0
y0_start
x0_start
x0_end
x1_start
x1_end
(a)
Integration Time
Handling
Readout
Handling
FOT
É
É
B
L
Reset
N
Exposure Time N
Readout Frame N-1
ROI
1
ROI 0
FS0
FS1
Reset
N+1
FOT
FOT
FE1
É
É
B
L
Exposure Time N+1
FOT
Readout Frame N
ROI
1
ROI 0
FS0
FS1
FOT
FE1
(b)
Figure 29. V1−SN/SE: Frame Sync Codes
Figure 30 shows the detail of a black line readout during global or full-frame readout.
Sequencer
Internal State
FOT
ROT
ROT
black
line Ys
ROT
ROT
line Ys+1
line Ye
data channels
sync channel
data channels
sync channel
Training
TR
Training
LS
BL
timeslot
0
timeslot
1
BL
BL
BL
timeslot
157
BL
timeslot
158
BL
LE
timeslot
159
CRC
CRC
timeslot
Figure 30. V1−SN/SE: Time Line for Black Line Readout
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NOIV1SN1300A, NOIV2SN1300A
Figure 31 shows shows the details of the readout of a number of lines for single window readout, at the beginning of the frame.
Sequencer
Internal State
FOT
ROT
black
ROT
line Ys+1
ROT
line Ys
line Ye
ROT
data channels
sync channel
Training
data channels
TR
sync channel
Training
FS
ID
timeslot
Xstart
IMG
IMG
IMG
timeslot
Xstart + 1
IMG
timeslot
Xend - 2
IMG
IMG
timeslot
Xend - 1
ID
LE
CRC
timeslot
Xend
TR
CRC
timeslot
Figure 31. V1−SN/SE: Time Line for Single Window Readout (at the start of a frame)
Figure 32 shows the detail of the readout of a number of lines for readout of two overlapping windows.
Sequencer
Internal State
FOT
ROT
ROT
black
line Ys
ROT
ROT
line Ys+1
line Ye
data channels
sync channel
data channels
sync channel
Training
Training
TR
LS
IDM
IMG
IMG
LS
timeslot
XstartM
IDN
IMG
IMG
IMG LE
timeslot
XstartN
IDN
CRC
TR
timeslot
XendN
Figure 32. V1−SN/SE: Time Line Showing the Readout of Two Overlapping Windows
active at the same time, the sync channel transmits the frame
synchronization codes of the window with highest index
only.
Frame Synchronization for 10−bit Mode
Table 30 shows the structure of the frame synchronization
code. Note that the table shows the default data word
(configurable) for 10-bit mode. If more than one window is
Table 30. FRAME SYNCHRONIZATION CODE DETAILS FOR 10-BIT MODE
Sync Word Bit
Position
Register
Address
Default Value
9:7
N/A
0x5
Frame start indication
9:7
N/A
0x6
Frame end indication
9:7
N/A
0x1
Line start indication
Line end indication
9:7
N/A
0x2
6:0
131[6:0]
0x2A
Description
These bits indicate that the received sync word is a frame synchronization code. The
value is programmable by a register setting
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43
NOIV1SN1300A, NOIV2SN1300A
• Window Identification
• Data Classification Codes
Frame synchronization codes are always followed by a
3-bit window identification (bits 2:0). This is an integer
number, ranging from 0 to 7, indicating the active window.
If more than one window is active for the current cycle, the
highest window ID is transmitted.
For the remaining cycles, the sync channel indicates the
type of data sent through the data links: black pixel data
(BL), image data (IMG), or training pattern (TR). These
codes are programmable by a register setting. The default
values are listed in Table 31.
Table 31. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES FOR 10-BIT MODE
Sync Word Bit
Position
Register
Address
Default
Value
9:0
132 [9:0]
0x015
Black pixel data (BL). This data is not part of the image. The black pixel data is used internally to correct channel offsets.
9:0
133 [9:0]
0x035
Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of the
image).
9:0
134 [9:0]
0x059
CRC value. The data on the data output channels is the CRC code of the finished image
data line.
9:0
135 [9:0]
0x3A6
Training pattern (TR). The sync channel sends out the training pattern which can be programmed by a register setting.
Description
and not sent out. Table 32 shows the structure of the frame
synchronization code, together with the default value, as
specified in SPI registers. The same restriction for
overlapping windows applies in 8-bit mode.
Frame Synchronization in 8-bit Mode
The frame synchronization words are configured using
the same registers as in 10-bit mode. The two least
significant bits of these configuration registers are ignored
Table 32. FRAME SYNCHRONIZATION CODE DETAILS FOR 8-BIT MODE
Sync Word Bit
Position
Register
Address
Default
Value
7:5
N/A
0x5
Frame start (FS) indication
7:5
N/A
0x6
Frame end (FE) indication
7:5
N/A
0x1
Line start (LS) indication
7:5
N/A
0x2
Line end (LE) indication
4:0
[6:2]
0x0A
Description
These bits indicate that the received sync word is a frame synchronization code. The value is programmable by a register setting.
• Window Identification
• Data Classification Codes
Similar to 10-bit operation mode, the frame
synchronization codes are followed by a window
identification. The window ID is located in bits 4:2 (all other
bit positions are ‘0’). The same restriction for overlapping
windows applies in 8-bit mode.
BL, IMG, CRC, and TR codes are defined by the same
registers as in 10-bit mode. Bits 9:2 of the respective
configuration registers are used as classification code with
default values shown in Table 33.
Table 33. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES FOR 8-BIT MODE
Sync Word Bit
Position
Register
Address
Default
Value
7:0
132 [9:2]
0x05
Black pixel data (BL). This data is not part of the image. The black pixel data is used internally to correct channel offsets.
7:0
133 [9:2]
0x0D
Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of
the image).
7:0
134 [9:2]
0x16
CRC value. The data on the data output channels is the CRC code of the finished image
data line.
7:0
135 [9:2]
0xE9
Training Pattern (TR). The sync channel sends out the training pattern which can be programmed by a register setting.
Description
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44
NOIV1SN1300A, NOIV2SN1300A
In 8-bit mode, the training pattern for the data channels is
defined by the same register as in 10-bit mode, where the
lower two bits are omitted; see Table 35.
Training Patterns on Data Channels
In 10-bit mode, during idle periods, the data channels
transmit training patterns, indicated on the sync channel by
a TR code. These training patterns are configurable
independent of the training code on the sync channel as
shown in Table 34.
Table 34. TRAINING CODE ON SYNC CHANNEL IN 10-BIT MODE
Sync Word Bit
Position
Register
Address
Default Value
[9:0]
130 [9:0]
0x3A6
Description
Data channel training pattern. The data output channels send out the training pattern,
which can be programmed by a register setting. The default value of the training pattern
is 0x3A6, which is identical to the training pattern indication code on the sync channel.
Table 35. TRAINING PATTERN ON DATA CHANNEL IN 8-BIT MODE
Data Word Bit
Position
Register
Address
Default Value
[7:0]
130 [9:2]
0xE9
Description
Data Channel Training Pattern (Training pattern).
kernel (kernel [0, 0]) is located in the bottom left corner. The
data order of this image data on the data output channels
depends on the subsampling mode.
Cyclic Redundancy Code
At the end of each line, a CRC code is calculated to allow
error detection at the receiving end. Each data channel
transmits a CRC code to protect the data words sent during
the previous cycles. Idle and training patterns are not
included in the calculation.
The sync channel is not protected. A special character
(CRC indication) is transmitted whenever the data channels
send their respective CRC code.
The polynomial in 10-bit operation mode is
x10 + x9 + x6 + x3 + x2 + x + 1. The CRC encoder is seeded
at the start of a new line and updated for every (valid) data
word received. The CRC seed is configurable using the
crc_seed register. When ‘0’, the CRC is seeded by all-‘0’;
when ‘1’ it is seeded with all-‘1’.
In 8-bit mode, the polynomial is x8 + x6 + x3 + x2 + 1.
The CRC seed is configured by means of the crc_seed
register.
Note The CRC is calculated for every line. This implies
that the CRC code can protect lines from multiple windows.
kernel
(159,1023)
pixel array
ROI
kernel
(x_start,y_start)
kernel
(0,0)
0
1
2
3
5
6
7
Figure 33. Kernel Organization in Pixel Array
• V1−SN/SE: No Subsampling
The image data is read out in kernels of eight pixels in
x-direction by one pixel in y-direction. One data channel
output delivers two pixel values of one kernel sequentially.
Figure 34 shows how a kernel is read out over the four
output channels. For even positioned kernels, the kernels are
read out ascending, while for odd positioned kernels the data
order is reversed (descending).
Data Order
To read out the image data through the output channels,
the pixel array is organized in kernels. The kernel size is
eight pixels in x-direction by one pixel in y-direction.
Figure 33 indicates how the kernels are organized. The first
www.onsemi.com
45
NOIV1SN1300A, NOIV2SN1300A
kernel 12
kernel 13
kernel 14
kernel 15
time
LSB
MSB
7
7
6
5
4
3
2
1
0
channel #3
6
channel #2
5
channel #0
4
channel #1
3
channel #3
2
channel #2
1
channel #0
0
pixel # (odd kernel)
channel #1
pixel # (even kernel)
LSB
MSB
Note: The bit order is always MSB first,
regardless the kernel number
10-bit
10-bit
Figure 34. V1−SN/SE: Data Output Order when Subsampling is Disabled
• V1−SN/SE: Subsampling on Monochrome Sensor
pixel positions inside that kernel are read out. Figure 35
shows the data order.
Note that there is no difference in data order for even/odd
kernel numbers, as opposed to the ‘no-subsampling’
readout.
To read out the image data with subsampling enabled on
a monochrome sensor, two neighboring kernels are
combined to a single kernel of 16 pixels in the x-direction
and one pixel in the y-direction. Only the pixels at the even
kernel 12
kernel 13
kernel 14
kernel 15
time
2
12
MSB
LSB
channel #1
MSB
4
10
6
8
channel #3
14
channel #2
0
channel #0
pixel #
LSB
Note: The bit order is always MSB first,
regardless the kernel number
10-bit
10-bit
Figure 35. V1−SN/SE: Data Output Order in Subsampling Mode on a Monochrome Sensor
• V1−SN/SE: Subsampling on Color Sensor
the y-direction. Only the pixels 0, 1, 4, 5, 8, 9, 12, and 13 are
read out. Figure 36 shows the data order.
Note that there is no difference in data order for even/odd
kernel numbers, as opposed to the ‘no-subsampling’
readout.
To read out the image data with subsampling enabled on
a color sensor, two neighboring kernels are combined to a
single kernel of 16 pixels in the x-direction and one pixel in
www.onsemi.com
46
NOIV1SN1300A, NOIV2SN1300A
kernel 12
kernel 13
kernel 14
kernel 15
time
13
LSB
MSB
4
channel #1
12
MSB
5
9
8
channel #3
1
channel #2
0
channel #0
pixel #
LSB
Note: The bit order is always MSB first,
regardless the kernel number
10-bit
10-bit
Figure 36. V1−SN/SE: Data Output Order in Subsampling Mode on a Color Sensor
V2−SN/SE: CMOS Interface Version
The frame_valid indication is asserted at the start of a new
frame and remains asserted until the last line of the frame is
completely transmitted.
The line_valid indication serves the following needs:
• While the line_valid indication is asserted, the data
channels contain valid pixel data.
• The line valid communicates frame timing as it is
asserted at the start of each line and it is de-asserted at
the end of the line. Low periods indicate the idle time
between lines (ROT).
• The data channels transmit the calculated CRC code
after each line. This can be detected as the data words
right after the falling edge of the line valid.
CMOS Output Signals
The image data output occurs through a single 10-bit
parallel CMOS data output, operating at 62 MSps. A CMOS
clock output, ‘frame valid’ and ‘line valid’ signal is foreseen
to synchronize the output data.
No windowing information is sent out by the sensor.
8-bit/10-bit Mode
The 8-bit mode is not supported when using the parallel
CMOS output interface.
Frame Format
Frame timing is indicated by means of two signals:
frame_valid and line_valid.
Sequencer
Internal State
FOT
ROT
black
ROT
line Ys
ROT
line Ys+1
ROT
line Ye
FOT
ROT
black
data channels
frame_valid
line_valid
Figure 37. V2−SN/SE: Frame Timing Indication
starting at position y0_start. When the line at position
y1_start is reached, a number of lines containing data of
‘ROI 0’ and ‘ROI 1’ are sent out, until the line position of
y0_end is reached. Then, only data of ‘ROI 1’ appears on the
data output until line position y1_end is reached. The
line_valid strobe is not shown in Figure 38.
The frame format is explained with an example of the
readout of two (overlapping) windows as shown in
Figure 38 (a).
The readout of a frame occurs on a line-by-line basis. The
read pointer goes from left to right, bottom to top. Figure 38
(a) and (b) indicate that, after the FOT is finished, a number
of lines which include information of ‘ROI 0’ are sent out,
www.onsemi.com
47
NOIV1SN1300A, NOIV2SN1300A
1280 pixels
1024 pixels
y1_end
ROI1
y0_end
y1_start
ROI0
y0_start
x0_start
x0_end
x1_start
x1_end
(a)
Reset
Exposure Time N
N
Readout Frame N -1
Integration Time
Handling
Readout
Handling
FOT
ROI1
ROI0
Reset
Exposure Time N +1
N+1
Readout Frame N
FOT
FOT
ROI0
ROI1
FOT
FOT
Frame valid
(b)
Figure 38. V2−SN/SE: Frame Format to Read Out Image Data
Black Lines: Black pixel data is also sent through the data
channels. To distinguish these pixels from the regular image
data, it is possible to ‘mute’ the frame and/or line valid
indications for the black lines.
Table 36. BLACK LINE FRAME_VALID AND LINE_VALID SETTINGS
bl_frame_valid_enable
bl_line_valid_enable
0x1
0x1
The black lines are handled similar to normal image lines. The frame valid indication is asserted
before the first black line and the line valid indication is asserted for every valid (black) pixel.
0x1
0x0
The frame valid indication is asserted before the first black line, but the line valid indication is not
asserted for the black lines. The line valid indication indicates the valid image pixels only. This
mode is useful when one does not use the black pixels and when the frame valid indication needs
to be asserted some time before the first image lines (for example, to precondition ISP pipelines).
0x0
0x1
In this mode, the black pixel data is clearly unambiguously indicated by the line valid indication,
while the decoding of the real image data is simplified.
0x0
0x0
Black lines are not indicated and frame and line valid strobes remain de-asserted. Note however
that the data channels contains the black pixel data and CRC codes (Training patterns are interrupted).
Description
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48
NOIV1SN1300A, NOIV2SN1300A
• V2-SN/SE: No Subsampling
Data Order
To read out the image data through the parallel CMOS
output, the pixel array is divided in kernels. The kernel size
is eight pixels in x-direction by one pixel in y-direction.
Figure 33 on page 45 indicates how the kernels are
organized.
The data order of this image data on the data output
channels depends on the subsampling mode.
kernel 12
kernel 13
The image data is read out in kernels of eight pixels in
x-direction by one pixel in y-direction.
Figure 39 shows the pixel sequence of a kernel which is
read out over the single CMOS output channel. The pixel
order is different for even and odd kernel positions.
kernel 14
kernel 15
time
pixel # (even kernel)
0
2
4
6
1
3
pixel # (odd kernel)
5
7
7
5
3
1
6
4
2
0
time
Figure 39. V2−SN/SE: Data Output Order without Subsampling
• V2−SN/SE: Subsampling On Monochrome Sensor
pixel positions inside that kernel are read out. Figure 40
shows the data order
Note that there is no difference in data order for even/odd
kernel numbers, as opposed to the ‘no-subsampling’
readout.
To read out the image data with subsampling enabled on
a monochrome sensor, two neighboring kernels are
combined to a single kernel of 16 pixels in the x-direction
and one pixel in the y-direction. Only the pixels at the even
kernel 12
kernel 13
kernel 14
kernel 15
time
pixel #
0
2
4
6
14
12
10
8
time
Figure 40. V2−SN/SE: Data Output Order with Subsampling on a Monochrome Sensor
• V2−SN/SE: Subsampling On Color Sensor
the y-direction. Only the pixels 0, 1, 4, 5, 8, 9, 12, and 13 are
read out. Figure 41 shows the data order.
Note that there is no difference in data order for even/odd
kernel numbers, as opposed to the ‘no-subsampling’
readout.
To read out the image data with subsampling enabled on
a color sensor, two neighboring kernels are combined to a
single kernel of 16 pixels in the x-direction and one pixel in
kernel 12
kernel 13
kernel 14
kernel 15
time
pixel #
0
13
4
9
1
12
5
8
time
Figure 41. V2−SN/SE: Data Output Order with Subsampling on a Color Sensor
www.onsemi.com
49
NOIV1SN1300A, NOIV2SN1300A
REGISTER MAP
Table 37. REGISTER MAP
Address
Offset
Address
Default
(Hex)
Default
(Dec)
chip_id
0x560D
22029
id
0x560D
22029
reserved
0x0000
0
reserved
0x0000
0
chip_configuration
0x0000
0
0x0
0
soft_reset_pll
0x099
153
[3:0]
pll_soft_reset
0x9
9
PLL Reset
0x9: Soft Reset State
others: Operational
[7:4]
pll_lock_soft_reset
0x9
9
PLL Lock Detect Reset
0x9: Soft Reset State
others: Operational
soft_reset_cgen
0x09
9
cgen_soft_reset
0x9
9
0x0999
2457
Bit Field
Register Name
Description
Type
Chip ID [Block Offset: 0]
0
0
[15:0]
1
1
[3:0]
2
2
[1:0]
RO
Chip ID
RO
Reserved
RW
Configure as per part #:
NOIV1SN1300A-QDC: 0x0
NOIV1SE1300A-QDC: 0x1
NOIV2SN1300A-QDC: 0x2
NOIV2SE1300A-QDC: 0x3
Reset Generator [Block Offset: 8]
0
1
8
9
[3:0]
2
10
soft_reset_analog
RW
RW
Clock Generator Reset
0x9: Soft Reset State
others: Operational
RW
[3:0]
mux_soft_reset
0x9
9
Column MUX Reset
0x9: Soft Reset State
others: Operational
[7:4]
afe_soft_reset
0x9
9
AFE Reset
0x9: Soft Reset State
others: Operational
[11:8]
ser_soft_reset
0x9
9
Serializer Reset
0x9: Soft Reset State
others: Operational
0x0004
4
PLL [Block Offset: 16]
0
1
16
17
power_down
RW
[0]
pwd_n
0x0
0
PLL Power Down
‘0’ = Power Down,
‘1’ = Operational
[1]
enable
0x0
0
PLL Enable
‘0’ = disabled,
‘1’ = enabled
[2]
bypass
0x1
1
PLL Bypass
‘0’ = PLL Active,
‘1’ PLL Bypassed
0x2113
8467
reserved
www.onsemi.com
50
RW
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
Address
Bit Field
[15:0]
Default
(Hex)
Default
(Dec)
reserved
0x2113
8467
config
0x0000
0
clock_in_pwd_n
0x0
0
Power down clock Input
reserved
0x0
0
Reserved
pll_lock
0x0000
0
0x0
0
reserved
0x2182
8578
reserved
0x2182
8578
Reserved
reserved
0x3D2D
15661
Reserved
reserved
0x3D2D
15661
Reserved
config
0x0004
4
Register Name
Description
Type
Reserved
I/O [Block Offset: 20]
0
20
[0]
[10:8]
RW
PLL lock detector [Block Offset: 24]
0
24
[0]
2
26
[14:0]
3
27
[15:0]
lock
RO
PLL Lock Indication
RW
RW
Clock Generator [Block Offset: 32]
0
32
RW
[0]
enable_analog
0x0
0
Enable analog clocks
‘0’ = disabled,
‘1’ = enabled
[1]
enable_log
0x0
0
Enable logic clock
‘0’ = disabled,
‘1’ = enabled
[2]
select_pll
0x1
1
Input Clock Selection
‘0’ = Select LVDS clock input,
‘1’ = Select PLL clock input
[3]
adc_mode
0x0
0
Set operation mode
‘0’ = 10-bit mode,
‘1’ = 8-bit mode
[11:8]
reserved
0x0
0
Reserved
[14:12]
reserved
0x0
0
Reserved
config
0x0000
0
enable
0x0
0
0x0000
0
General Logic [Block Offset: 34]
0
34
[0]
RW
Logic General Enable Configuration
‘0’ = Disable
‘1’ = Enable
Image Core [Block Offset: 40]
0
40
image_core_config
RW
[0]
imc_pwd_n
0x0
0
Image Core Power Down
‘0’ = powered down,
‘1’ = powered up
[1]
mux_pwd_n
0x0
0
Column Multiplexer Power
Down
‘0’ = powered down,
‘1’ = powered up
[2]
colbias_enable
0x0
0
Bias Enable
‘0’ = disabled
‘1’ = enabled
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51
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
Address
1
41
Bit Field
Register Name
Default
(Hex)
Default
(Dec)
image_core_config
0x1B5A
7002
Description
Type
RW
[3:0]
dac_ds
0xA
10
Double Slope Reset Level
[7:4]
dac_ts
0x5
5
Triple Slope Reset Level
[10:8]
reserved
0x3
3
Reserved
[12:11]
reserved
0x3
3
Reserved
[13]
reserved
0x0
0
Reserved
[14]
reserved
0x0
0
Reserved
[15]
reserved
0x0
0
Reserved
0x0000
0
0x0
0
0x0000
0
0x0
0
AFE [Block Offset:48]
0
48
power_down
[0]
pwd_n
RW
Power down for AFEs (8 columns)
‘0’ = powered down,
‘1’ = powered up
Bias [Block Offset: 64]
0
64
power_down
[0]
1
65
configuration
0x888B
34955
0x1
1
External Resistor Selection
‘0’ = internal resistor,
‘1’ = external resistor
[3:1]
reserved
0x5
5
Reserved
[7:4]
imc_colpc_ibias
0x8
8
Column Precharge ibias Configuration
[11:8]
imc_colbias_ibias
0x8
8
Column Bias ibias Configuration
cp_ibias
0x8
8
Charge Pump Bias
afe_bias
0x53C8
21448
[15:12]
3
4
6
Power down bandgap
‘0’ = powered down,
‘1’ = powered up
extres
[0]
2
pwd_n
RW
66
RW
RW
[3:0]
afe_ibias
0x8
8
AFE ibias Configuration
[7:4]
afe_adc_iref
0xC
12
ADC iref Configuration
[14:8]
afe_pga_iref
0x53
83
PGA iref Configuration
0x8888
34952
67
mux_bias
RW
[3:0]
mux_25u_stage1
0x8
8
Column Multiplexer Stage 1 Bias
Configuration
[7:4]
mux_25u_stage2
0x8
8
Column Multiplexer Stage 2 Bias
Configuration
[15:8]
reserved
0x88
72
Reserved
lvds_bias
0x0088
136
[3:0]
lvds_ibias
0x8
8
LVDS Ibias
[7:4]
lvds_iref
0x8
8
LVDS Iref
reserved
0x8888
34952
[11:0]
reserved
0x888
2184
[15:2]
afe_ref_bias
0x8
8
68
70
www.onsemi.com
52
RW
RW
Reserved
AFE_reference
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
Address
Bit Field
Register Name
Default
(Hex)
Default
(Dec)
0x1200
4608
Description
Type
Charge Pump [Block Offset: 72]
0
72
config
RW
[0]
respd_trans_pwd_n
0x0
0
PD Trans Charge Pump Enable
‘0’ = disabled, ‘1’ = enabled
[1]
resfd_pwd_n
0x0
0
FD Charge Pump Enable
‘0’ = disabled, ‘1’ = enabled
[10:8]
respd_trans_trim
0x2
2
PD Trans Charge Pump Trim
[14:12]
resfd_trim
0x1
1
FD Charge Pump Trim
reserved
0x0000
0
reserved
0x000
0
reserved
0x0000
0
reserved
0x0000
0
sensor enable
0x0000
0
0x0
0
0x0000
0
0x00
0
0x0000
0
Reserved [Block Offset: 80]
0
80
[9:0]
1
81
[15:0]
RW
Reserved
RW
Reserved
Temperature Sensor [Block Offset: 96]
0
96
[0]
1
97
reg_tempd_enable
sensor output
[7:0]
tempd_reg_temp
RW
Temperature Diode Enable
‘0’ = disabled
‘1’ = enabled
RO
Temperature Readout
Serializer/LVDS [Block Offset: 112]
0
112
power_down
RW
[0]
clock_out_pwd_n
0x0
0
Power down for clock output.
‘0’ =powered down,
‘1’ = powered up
[1]
sync_pwd_n
0x0
0
Power down for sync channel
‘0’ = powered down,
‘1’ = powered up
[2]
data_pwd_n
0x0
0
Power down for data channels
(4 channels)
‘0’ = powered down,
‘1’ = powered up
Data Block [Block Offset: 128]
0
1
128
129
0x4008
16392
[7:0]
blackcal
black_offset
0x08
8
Desired black level at output
[10:8]
black_samples
0x0
0
Black pixels taken into account
for black calibration.
Total samples = 2**black_samples
[14:11]
reserved
0x8
8
Reserved
[15]
crc_seed
0x0
0
CRC Seed
‘0’ = All-0
‘1’ = All-1
0xC001
49153
general_configuration
www.onsemi.com
53
RW
RW
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
2
3
Address
Bit Field
Register Name
Default
(Hex)
Default
(Dec)
[0]
auto_blackcal_enable
0x1
1
Automatic black calibration is
enabled when 1, bypassed
when 0
[9:1]
blackcal_offset
0x00
0
Black calibration offset used
when auto_black_cal_en = ‘0’.
[10]
blackcal_offset_dec
0x0
0
blackcal_offset is added when 0,
subtracted when 1
[11]
reserved
0x0
0
Reserved
[12]
reserved
0x0
0
Reserved
[13]
8bit_mode
0x0
0
8bit mode select
‘0’ = 10-bit mode, ‘1’ = 8-bit
mode
[14]
bl_frame_valid_
enable
0x1
1
Assert frame_valid for black
lines when ‘1’, gate frame_valid
for black lines when ‘0’.
V2-SN/SE only
[15]
bl_line_valid_enable
0x1
1
Assert line_valid for black lines
when ‘1’, gate line_valid for
black lines when ‘0’.
V2-SN/SE only
trainingpattern
0x03A6
934
[9:0]
trainingpattern
0x3A6
934
[10]
reserved
0x0
0
sync_code0
0x002A
42
frame_sync
0x02A
42
sync_code1
0x0015
21
bl
0x015
21
sync_code2
0x0035
53
img
0x035
53
sync_code3
0x0059
89
crc
0x059
89
sync_code4
0x03A6
934
tr
0x3A6
934
blackcal_error0
0x0000
0
blackcal_error[7:0]
0x0000
0
reserved
0x0000
0
130
131
[6:0]
4
132
[9:0]
5
133
[9:0]
6
134
[9:0]
7
135
[9:0]
8
136
[7:0]
9
137
www.onsemi.com
54
Description
Type
RW
Training pattern sent on data
channels during idle mode. This
data is used to perform word
alignment on the LVDS data
channels.
Reserved
RW
Frame Sync LSBs.
Note The tenth bit indicates
frame/line sync code, ninth bit
indicates start, eighth bit indicates end.
RW
Black Pixel Identification Sync
Code
RW
Valid Pixel Identification Sync
Code
RW
CRC Value Identification Sync
Code
RW
Training Value Identification
Sync Code
RO
Black Calibration Error. This flag
is set when not enough black
samples are available. Black
Calibration is not valid.
Channels 0-7.
RO
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
Address
Bit Field
[15:0]
10
138
[15:0]
11
139
12
140
[15:0]
[15:0]
13
141
[15:0]
Default
(Hex)
Default
(Dec)
reserved
0x0000
0
reserved
0x0000
0
reserved
0x0000
0
reserved
0x0000
0
reserved
0x0000
0
reserved
0x0000
0
reserved
0x0000
0
reserved
0xFFFF
65535
reserved
0xFFFF
65535
test_configuration
Register Name
Description
Type
Reserved
RO
Reserved
RO
Reserved
RW
Reserved
RW
Reserved
Datablock - Test
16
144
17
145
18
146
0x0000
0
[0]
testpattern_en
0x0
0
Insert synthesized testpattern
when ‘1’
[1]
inc_testpattern
0x0
0
Incrementing testpattern when
‘1’, constant testpattern when ‘0’
[2]
prbs_en
0x0
0
Insert PRBS when ‘1’
[3]
frame_testpattern
0x0
0
Frame test patterns when ‘1’,
unframed testpatterns when ‘0’
[4]
reserved
0x0
0
Reserved
reserved
0x0000
0
0x0100
256
[15:0]
19
20
21
22
0
test_configuration0
RW
Reserved
RW
[7:0]
testpattern0_lsb
0x00
0
Testpattern used on datapath #0
when testpattern_en = ‘1’.
Note Most significant bits are
configured in register 150.
[15:8]
testpattern1_lsb
0x01
1
Testpattern used on datapath #1
when testpattern_en = ‘1’.
Note Most significant bits are
configured in register 150.
0x0302
770
147
test_configuration1
RW
[7:0]
testpattern2_lsb
0x02
2
Testpattern used on datapath #2
when testpattern_en = ‘1’.
Note Most significant bits are
configured in register 150.
[15:8]
testpattern3_lsb
0x03
3
Testpattern used on datapath #3
when testpattern_en = ‘1’.
Note Most significant bits are
configured in register 150.
reserved
0x0504
1284
[7:0]
reserved
0x04
4
Reserved
[15:8]
reserved
0x05
5
Reserved
0x0706
1798
148
149
150
reserved
RW
test_configuration3
RW
RW
[7:0]
reserved
0x06
6
Reserved
[15:8]
reserved
0x07
7
Reserved
0x0000
0
test_configuration16
www.onsemi.com
55
RW
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
26
Address
Bit Field
Default
(Hex)
Default
(Dec)
Description
[1:0]
testpattern0_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
[3:2]
testpattern1_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
[5:4]
testpattern2_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
[7:6]
testpattern3_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
[9:8]
reserved
0x0
0
Reserved
[11:10]
reserved
0x0
0
Reserved
[13:12]
reserved
0x0
0
Reserved
[15:14]
reserved
0x0
0
Reserved
reserved
0x0000
0
reserved
0x0000
0
reserved
0x0000
0
reserved
0x0000
0
configuration
0x0010
16
154
[15:0]
27
Register Name
155
[15:0]
Type
RW
Reserved
RW
Reserved
AEC[Block Offset: 160]
0
1
160
[0]
enable
0x0
0
AEC Enable
[1]
restart_filter
0x0
0
Restart AEC filter
[2]
freeze
0x0
0
Freeze AEC filter and enforcer
gains
[3]
pixel_valid
0x0
0
Use every pixel from channel
when 0, every 4th pixel when 1
[4]
amp_pri
0x1
1
Stage 1 amplifier gets higher priority than Stage 2 gain distribution if 1. Vice versa if 0
intensity
0x60B8
24760
desired_intensity
0xB8
184
Target average intensity
reserved
0x018
24
Reserved
red_scale_factor
0x0080
128
red_scale_factor
0x80
128
green1_scale_factor
0x0080
128
green1_scale_factor
0x80
128
green2_scale_factor
0x0080
128
green2_scale_factor
0x80
128
blue_scale_factor
0x0080
128
blue_scale_factor
0x80
128
0x03FF
1023
161
[9:0]
[13:10]
2
162
[9:0]
3
163
[9:0]
4
164
[9:0]
5
165
[9:0]
6
166
RW
reserved
www.onsemi.com
56
RW
RW
Red scale factor for AEC statistics
3.7 unsigned
RW
Green1 scale factor for AEC statistics
3.7 unsigned
RW
Green2 scale factor for AEC statistics
3.7 unsigned
RW
Blue scale factor for AEC statistics
3.7 unsigned
RW
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
Address
Bit Field
[15:0]
7
167
[15:0]
8
168
9
169
[15:0]
10
12
13
14
min_exposure
0x0001
1
min_gain
0x0800
2048
RW
Minimum exposure time
RW
128
max_exposure
0x03FF
1023
max_exposure
0x03FF
1023
max_gain
0x100D
4109
Minimum digital gain
5.7 unsigned
RW
Maximum exposure time
RW
[1:0]
max_gain_stage1
0x1
1
Maximum gain stage 1
[3:2]
max_gain_stage2
0x3
3
Maximum gain stage 2
[15:4]
max_digital_gain
0x100
256
Maximum digital gain
5.7 unsigned
reserved
0x0083
131
[7:0]
reserved
0x83
131
Reserved
[13:8]
reserved
0x00
0
Reserved
[15:14]
reserved
0x0
0
Reserved
reserved
0x2824
10276
[7:0]
reserved
0x024
36
Reserved
[15:8]
reserved
0x028
40
Reserved
reserved
0x2A96
10902
reserved
0x2A96
10902
reserved
0x0080
128
reserved
0x080
128
reserved
0x0100
256
reserved
0x100
256
reserved
0x0100
256
reserved
0x100
256
reserved
0x0080
128
reserved
0x080
128
reserved
0x00AA
170
reserved
0x0AA
170
reserved
0x0100
256
reserved
0x100
256
reserved
0x0155
341
reserved
0x155
341
total_pixels0
0x0000
0
178
[9:0]
181
[9:0]
184
1
0x080
[9:0]
24
0x0001
min_digital_gain
[9:0]
21
min_exposure
Reserved
[15:4]
[9:0]
180
2048
Minimum gain stage 2
[9:0]
20
0x0800
0
175
179
reserved
RW
0x0
174
19
2048
min_gain_stage2
[9:0]
18
0x0800
[3:2]
173
177
reserved
www.onsemi.com
57
Type
Reserved
Minimum gain stage 1
172
17
1023
0
171
176
0x03FF
0x0
170
16
reserved
Description
min_gain_stage1
[15:0]
15
Default
(Dec)
[1:0]
[15:0]
11
Default
(Hex)
Register Name
RW
RW
RW
Reserved
RW
Reserved
RW
Reserved
RW
Reserved
RW
Reserved
RW
Reserved
RW
Reserved
RW
Reserved
RO
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
Address
Bit Field
[15:0]
25
185
[2:0]
26
27
186
29
Default
(Dec)
total_pixels[15:0]
0x0000
0
total_pixels1
0x0000
0
0x0
0
total_pixels[18:16]
Description
RO
Total number of pixels sampled
for Average, MSB
average_status
0x0000
0
average
0x000
0
AEC Average Status
[12]
locked
0x0
0
AEC Filter Lock Status
exposure_status
0x0000
0
exposure
0x0000
0
gain_status
0x00
0
[1:0]
gain_stage1
0x0
0
Gain Stage 1 Status
[3:2]
gain_stage2
0x0
0
Gain Stage 2 Status
[15:4]
digital_gain
0x000
0
AEC Digital Gain Status
5.7 unsigned
reserved
0x0000
0
reserved
0x000
0
general_configuration
0x00
0
[0]
enable
0x0
0
Enable sequencer
‘0’ = Idle,
‘1’ = enabled
[1]
rolling_shutter_enable
0x0
0
Operation Selection
‘0’ = Global Shutter,
‘1’ = Rolling Shutter
[2]
reserved
0x0
0
Reserved
[3]
reserved
0x0
0
Reserved
[4]
triggered_mode
0x0
0
Triggered Mode Selection (Global Shutter only)
‘0’ = Normal Mode,
‘1’ = Triggered Mode
[5]
slave_mode
0x0
0
Master/Slave Selection (Global
Shutter only)
‘0’ = master,
‘1’ = slave
[6]
xsm_delay_enable
0x0
0
Insert delay between end of
ROT and start of readout if ‘1’.
ROT delay is defined by register
xsm_delay
[7]
subsampling
0x0
0
Subsampling mode selection
‘0’ = no subsampling,
‘1’ = subsampling
[8]
binning
0x0
0
Binning mode selection
‘0’ = no binning,
‘1’ = binning
187
188
189
[12:0]
Type
Total number of pixels sampled
for Average, LSB
[9:0]
[15:0]
28
Default
(Hex)
Register Name
RO
RO
AEC Exposure Status
RO
RO
Reserved
Sequencer [Block Offset: 192]
0
192
www.onsemi.com
58
RW
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
Address
Bit Field
2
3
0
Enable windowing for AEC Statistics.
‘0’ = Subsample all windows
‘1’ = Subsample configured window
[13:11]
monitor_select
0x0
0
Control of the monitor pins
reserved
0x0
0
Reserved
0x0000
0
[7:0]
delay_configuration
rs_x_length
0x00
0
X-Readout duration in rolling
shutter mode (extends lines with
dummy pixels).
[15:8]
xsm_delay
0x00
0
Delay between ROT end and
X-readout (only when xsm_delay_enable = ‘1’)
integration_control
0x0004
4
[0]
dual_slope_enable
0x0
0
Enable Dual Slope (Global
mode only)
[1]
triple_slope_enable
0x0
0
Enable Triple Slope (Global
mode only)
[2]
fr_mode
0x1
1
Representation of fr_length.
‘0’: reset length
‘1’: frame length
[9:3]
reserved
0x00
0
Reserved
0x0001
1
0x01
1
reserved
0x0000
0
reserved
0x0000
0
black_lines
0x0102
258
black_lines
0x02
2
Number of black lines. Minimum
is 1.
Range 1 to 255
gate_first_line
0x1
1
Blank out first line
‘0’: No blank-out
‘1’: Blank-out
dummy_lines
0x0000
0
dummy_lines
0x000
0
mult_timer
0x0001
1
mult_timer
0x0001
1
fr_length
0x0000
0
195
roi_active0
[7:0]
5
197
[15:0]
[7:0]
[8]
6
198
[11:0]
7
199
[15:0]
8
200
Description
0x0
194
196
Default
(Dec)
roi_aec_enable
193
4
Default
(Hex)
[10]
[14]
1
Register Name
roi_active[7:0]
www.onsemi.com
59
Type
RW
RW
RW
Active ROI’s selection
RW
Reserved
RW
RW
Number of Dummy lines (Rolling
Shutter only)
Range 0 to 4095
RW
Mult Timer (Global Shutter only)
Defines granularity (unit =
1/System Clock) of exposure
and reset_length
RW
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
Address
Bit Field
[15:0]
9
201
[15:0]
10
202
[15:0]
11
203
[15:0]
12
204
13
205
14
206
Default
(Hex)
Default
(Dec)
fr_length
0x0000
0
exposure
0x0000
0
exposure
0x0000
0
exposure
0x0000
0
exposure_ds
0x0000
0
exposure
0x0000
0
exposure_ts
0x0000
0
gain_configuration
0x01E2
482
Register Name
Description
Frame/Reset length (Global
Shutter only)
Reset length when fr_mode =
‘0’, Frame Length when fr_mode
= ‘1’
Granularity defined by
mult_timer
RW
Exposure Time
Rolling Shutter:
granularity lines
Global Shutter:
granularity defined by mult_timer
RW
Exposure Time (Dual Slope)
Rolling Shutter: N/A
Global Shutter:
granularity defined by mult_timer
RW
Exposure Time (Triple Slope)
Rolling Shutter: N/A
Global Shutter:
granularity defined by mult_timer
RW
[1:0]
gain_stage1
0x02
2
Gain Stage 1
[8:5]
gain_stage2
0xF
15
Gain Stage 2
[13]
gain_lat_comp
0x0
0
Postpone gain update by 1
frame when ‘1’ to compensate
for exposure time updates latency.
Gain is applied at start of next
frame if ‘0’
0x0080
128
digital_gain_configuration
[11:0]
db_gain
RW
0x080
128
sync_configuration
0x033F
831
[0]
sync_rs_x_length
0x1
1
Update of rs_x_length are not
synchronized at start of frame
when ‘0’
[1]
sync_black_lines
0x1
1
Update of black_lines are not
synchronized at start of frame
when ‘0’
[2]
sync_dummy_lines
0x1
1
Update of dummy_lines are not
synchronized at start of frame
when ‘0’
[3]
sync_exposure
0x1
1
Update of exposure are not synchronized at start of frame when
‘0’
[4]
sync_gain
0x1
1
Update of gain settings
(gain_sw, afe_gain) are not synchronized at start of frame when
‘0’
www.onsemi.com
60
Type
Digital Gain
RW
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
16
Address
Bit Field
1
Update of roi updates (active_roi) are not synchronized at
start of frame when ‘0’
[8]
blank_roi_switch
0x1
1
Blank first frame after ROI
switching
[9]
blank_subsampling_ss
0x1
1
Blank first frame after subsampling/binning mode switching in global shutter mode (always blanked out in rolling shutter mode)
[10]
exposure_sync_mode
0x0
0
When ‘0’, exposure configurations are sync’ed at the start of
FOT. When ‘1’, exposure configurations sync is disabled
(continuously syncing). This
mode is only relevant for Triggered Global - master mode,
where the exposure configurations are sync’ed at the start of
exposure rather than the start of
FOT. For all other modes it
should be set to ‘0’.
Note Sync is still postponed if
sync_exposure = ‘0’.
mult_timer_status
0x0000
0
mult_timer
0x0000
0
reset_length_status
0x0000
0
reset_length
0x0000
0
exposure_status
0x0000
0
exposure
0x0000
0
exposure_ds_status
0x0000
0
exposure_ds
0x0000
0
exposure_ts_status
0x0000
0
exposure_ts
0x0000
0
gain_status
0x0000
0
[1:0]
gain_stage1
0x00
0
Current Stage 1 Gain
[8:5]
gain_stage2
0x00
0
Current Stage 2 Gain
digital_gain_status
0x0000
0
db_gain
208
209
210
211
[15:0]
20
212
[15:0]
21
22
213
214
[11:0]
24
Current Reset Length (not in
Slave mode)
RO
Current Exposure Time (not in
Slave mode)
RO
Current Exposure Time (not in
Slave mode)
RO
Current Exposure Time (not in
Slave mode)
RO
RO
0
Current Digital Gain
0x0
0
Dual Slope Enabled
[13]
triple_slope
0x0
0
Triple Slope Enabled
reserved
0x7F00
32512
reserved
0x7F00
32512
reserved
0x261E
9758
reserved
0x261E
9758
reserved
0x160B
5643
217
218
RO
0x000
[14:0]
26
Mult Timer Status (Master Global Shutter only)
dual_slope
216
www.onsemi.com
61
Type
RO
[12]
[14:0]
25
Description
0x1
[15:0]
19
Default
(Dec)
sync_roi
[15:0]
18
Default
(Hex)
[5]
[15:0]
17
Register Name
RW
Reserved
RW
Reserved
RW
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
Address
Default
(Hex)
Default
(Dec)
reserved
0x160B
5643
reserved
0x3E2E
15918
reserved
0x3E2E
15918
reserved
0x6368
25448
reserved
0x6368
25448
reserved
0x3E01
15873
[3:0]
reserved
0x1
1
Reserved
[7:4]
reserved
0x0
0
Reserved
[13:8]
reserved
0x3E
62
Reserved
reserved
0x5EF1
24305
reserved
0x5EF1
24305
reserved
0x6000
24576
reserved
0x6000
24576
reserved
0x0000
0
reserved
0x0000
0
reserved
0xFFFF
65535
reserved
0xFFFF
65535
reserved
0x0422
1058
[4:0]
reserved
0x02
2
Reserved
[9:5]
reserved
0x01
1
Reserved
[14:10]
reserved
0x01
1
Reserved
reserved
0x30F
783
[7:0]
reserved
0xF
15
Reserved
[15:8]
reserved
0x3
3
Reserved
reserved
0x0601
1537
[7:0]
reserved
0x1
1
Reserved
[15:8]
reserved
0x6
6
Reserved
0x0000
0
Bit Field
[14:0]
27
219
[14:0]
28
220
32
224
[14:0]
33
225
34
226
[15:0]
[15:0]
35
227
[15:0]
36
228
58
250
[15:0]
59
60
61
62
251
252
253
roi_aec_configuration0
RW
Reserved
RW
Reserved
RW
RW
Reserved
RW
Reserved
RW
Reserved
RW
Reserved
RW
RW
RW
RW
0x00
0
AEC ROI X Start
Configuration (used for AEC statistics when roi_aec_enable =
‘1’)
[15:8]
x_end
0x0
0
AEC ROI X End
Configuration (used for AEC statistics when roi_aec_enable =
‘1’)
roi_aec_configuration1
0x0000
0
y_start
0x000
0
roi_aec_configuration2
0x0000
0
www.onsemi.com
62
Type
Reserved
x_start
254
255
Description
[7:0]
[9:0]
63
Register Name
RW
AEC ROI Y Start
Configuration (used for AEC statistics when roi_aec_enable =
‘1’)
RW
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
Address
Bit Field
[9:0]
Register Name
y_end
Default
(Hex)
Default
(Dec)
0x0
0
0x9F00
40704
Description
Type
AEC ROI Y End
Configuration (used for AEC statistics when roi_aec_enable =
‘1’)
Sequencer ROI [Block Offset: 256]
0
1
256
roi0_configuration0
[7:0]
x_start
0x00
0
ROI 0 X Start
Configuration
[15:8]
x_end
0x9F
159
ROI 0 X End
Configuration
roi0_configuration1
0x0000
0
y_start
0x000
0
roi0_configuration2
0x03FF
1023
y_end
0x3FF
1023
roi1_configuration0
0x9F00
40704
257
[9:0]
2
258
[9:0]
3
4
259
7
10
RW
ROI 1 X Start
Configuration
[15:8]
x_end
0x9F
159
ROI 1 X End
Configuration
roi1_configuration1
0x0000
0
y_start
0x000
0
roi1_configuration2
0x03FF
1023
y_end
0x3FF
1023
roi2_configuration0
0x9F00
40704
260
261
262
RW
ROI 1 Y Start
Configuration
RW
ROI 1 Y End
Configuration
RW
[7:0]
x_start
0x00
0
ROI 2 X Start
Configuration
[15:8]
x_end
0x9F
159
ROI 2 X End
Configuration
roi2_configuration1
0x0000
0
y_start
0x000
0
roi2_configuration2
0x03FF
1023
y_end
0x3FF
1023
roi3_configuration0
0x9F00
40704
263
264
265
266
ROI 0 Y End
Configuration
0
[9:0]
9
RW
0x00
[9:0]
8
ROI 0 Y Start
Configuration
x_start
[9:0]
6
RW
[7:0]
[9:0]
5
RW
RW
ROI 2 Y Start
Configuration
RW
ROI 2 Y End
Configuration
RW
[7:0]
x_start
0x00
0
ROI 3 X Start
Configuration
[15:8]
x_end
0x9F
159
ROI 3 X End
Configuration
0x0000
0
roi3_configuration1
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63
RW
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
Address
Bit Field
[9:0]
11
267
[9:0]
12
13
268
16
19
22
y_end
0x3FF
1023
roi4_configuration0
RW
ROI 3 Y End
Configuration
ROI 4 X Start
Configuration
[15:8]
x_end
0x9F
159
ROI 4 X End
Configuration
roi4_configuration1
0x0000
0
y_start
0x000
0
roi4_configuration2
0x03FF
1023
y_end
0x3FF
1023
roi5_configuration0
0x9F00
40704
269
270
271
RW
RW
ROI 4 Y Start
Configuration
RW
ROI 4 Y End
Configuration
RW
[7:0]
x_start
0x00
0
ROI 5 X Start
Configuration
[15:8]
x_end
0x9F
159
ROI 5 X End
Configuration
roi5_configuration1
0x0000
0
y_start
0x000
0
roi5_configuration2
0x03FF
1023
y_end
0x3FF
1023
roi6_configuration0
0x9F00
40704
272
273
274
RW
ROI 5 Y Start
Configuration
RW
ROI 5 Y End
Configuration
RW
[7:0]
x_start
0x00
0
ROI 6 X Start
Configuration
[15:8]
x_end
0x9F
159
ROI 6 X End
Configuration
roi6_configuration1
0x0000
0
y_start
0x000
0
roi6_configuration2
0x03FF
1023
y_end
0x3FF
1023
roi7_configuration0
275
276
277
278
1023
0
[9:0]
21
0x03FF
40704
[9:0]
20
roi3_configuration2
RW
ROI 6 Y Start
Configuration
RW
ROI 6 Y End
Configuration
0x9F00
40704
[7:0]
x_start
0x00
0
ROI 7 X Start
Configuration
[15:8]
x_end
0x9F
159
ROI 7 X End
Configuration
0x0000
0
roi7_configuration1
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64
Type
ROI 3 Y Start
Configuration
0x00
[9:0]
18
0
0x9F00
[9:0]
17
0x000
y_start
Description
x_start
[9:0]
15
Default
(Dec)
[7:0]
[9:0]
14
Default
(Hex)
Register Name
RW
RW
NOIV1SN1300A, NOIV2SN1300A
Table 37. REGISTER MAP
Address
Offset
Address
[9:0]
23
Default
(Hex)
Default
(Dec)
0x000
0
roi7_configuration2
0x03FF
1023
y_end
0x3FF
1023
Bit Field
279
[9:0]
Register Name
y_start
Description
Type
ROI 7 Y Start
Configuration
RW
ROI 7 Y End
Configuration
Reserved [Block Offset: 384]
0
384
reserved
[15:0]
…
…
RW
reserved
Reserved
RW
…
…
127
511
…
reserved
[15:0]
RW
reserved
Reserved
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65
NOIV1SN1300A, NOIV2SN1300A
PACKAGE INFORMATION
Pin List
TIA/EIA-644-A Standard and the CMOS I/Os have a 3.3 V
signal level. Table 38 and Table 39 show the pin list for both
versions.
VITA 1300 has two output versions; V1-SN/SE (LVDS)
and V2-SN/SE (CMOS). The LVDS I/Os comply to the
Table 38. PIN LIST FOR V1-SN/SE LVDS INTERFACE
Pack Pin
No.
Pin Name
I/O Type
Direction
Description
1
vdd_33
Supply
3.3 V Supply
2
mosi
CMOS
Input
SPI Master Out - Slave In
3
miso
CMOS
Output
SPI Master In - Slave Out
4
sck
CMOS
Input
5
gnd_18
Supply
1.8 V Ground
6
vdd_18
Supply
1.8 V Supply
7
clock_outn
LVDS
Output
LVDS Clock Output (Negative)
8
clock_outp
LVDS
Output
LVDS Clock Output (Positive)
9
doutn0
LVDS
Output
LVDS Data Output Channel #0 (Negative)
10
doutp0
LVDS
Output
LVDS Data Output Channel #0 (Positive)
11
doutn1
LVDS
Output
LVDS Data Output Channel #1 (Negative)
12
doutp1
LVDS
Output
LVDS Data Output Channel #1 (Positive)
13
doutn2
LVDS
Output
LVDS Data Output Channel #2 (Negative)
14
doutp2
LVDS
Output
LVDS Data Output Channel #2 (Positive)
15
doutn3
LVDS
Output
LVDS Data Output Channel #3 (Negative)
16
doutp3
LVDS
Output
LVDS Data Output Channel #3 (Positive)
17
syncn
LVDS
Output
LVDS Sync Channel Output (Negative)
18
syncp
LVDS
Output
LVDS Sync Channel Output (Positive)
19
vdd_33
Supply
3.3 V Supply
20
gnd_33
Supply
3.3 V Ground
21
gnd_18
Supply
1.8 V Ground
22
vdd_18
Supply
1.8 V Supply
23
lvds_clock_inn
LVDS
Input
LVDS Clock Input (Negative)
24
lvds_clock_inp
LVDS
Input
LVDS Clock Input (Positive)
25
clk_pll
CMOS
Input
Reference Clock Input for PLL
26
vdd_18
Supply
1.8 V Supply
27
gnd_18
Supply
1.8 V Ground
28
ibias_master
Analog
29
vdd_33
Supply
3.3 V Supply
30
gnd_33
Supply
3.3 V Ground
31
vdd_pix
Supply
Pixel Array Supply
32
gnd_colpc
Supply
Pixel Array Ground
33
vdd_pix
Supply
Pixel Array Supply
34
gnd_colpc
Supply
Pixel Array Ground
35
gnd_33
Supply
3.3 V Ground
36
vdd_33
Supply
3.3 V Supply
37
gnd_colpc
Supply
Pixel Array Ground
I/O
SPI Clock
Master Bias Reference. Connect with 47k to gnd_33.
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66
NOIV1SN1300A, NOIV2SN1300A
Table 38. PIN LIST FOR V1-SN/SE LVDS INTERFACE
Pack Pin
No.
Pin Name
I/O Type
Direction
Description
38
vdd_pix
Supply
Pixel Array Supply
39
gnd_colpc
Supply
Pixel Array Ground
40
vdd_pix
Supply
Pixel Array Supply
41
trigger0
CMOS
Input
Trigger Input #0
42
trigger1
CMOS
Input
Trigger Input #1
43
trigger2
CMOS
Input
Trigger Input #2
44
monitor0
CMOS
Output
Monitor Output #0
45
monitor1
CMOS
Output
Monitor Output #1
46
reset_n
CMOS
Input
Sensor Reset (Active Low)
47
ss_n
CMOS
Input
SPI Slave Select (Active Low)
48
gnd_33
Supply
3.3 V Ground
Table 39. PIN LIST FOR V2-SN/SE CMOS INTERFACE
Pack Pin
No.
Pin Name
I/O Type
Direction
Description
1
vdd_33
Supply
3.3 V Supply
2
mosi
CMOS
Input
SPI Master Out - Slave In
3
miso
CMOS
Output
SPI Master In - Slave Out
4
sck
CMOS
Input
5
gnd_18
Supply
1.8 V Ground
6
vdd_18
Supply
1.8 V Supply
7
dout9
CMOS
Output
Data Output Bit #9
8
dout8
CMOS
Output
Data Output Bit #8
9
dout7
CMOS
Output
Data Output Bit #7
10
dout6
CMOS
Output
Data Output Bit #6
11
dout5
CMOS
Output
Data Output Bit #5
12
dout4
CMOS
Output
Data Output Bit #4
13
dout3
CMOS
Output
Data Output Bit #3
14
dout2
CMOS
Output
Data Output Bit #2
15
dout1
CMOS
Output
Data Output Bit #1
16
dout0
CMOS
Output
Data Output Bit #0
17
frame_valid
CMOS
Output
Frame Valid Output
18
line_valid
CMOS
Output
Line Valid Output
19
vdd_33
Supply
3.3 V Supply
20
gnd_33
Supply
3.3 V Ground
21
clk_out
CMOS
Clock output
22
vdd_18
Supply
23
lvds_clock_inn
LVDS
Input
LVDS Clock Input (Negative)
24
lvds_clock_inp
LVDS
Input
LVDS Clock Input (Positive)
25
clk_pll
CMOS
Input
CMOS Clock Input
26
vdd_18
Supply
1.8 V Supply
27
gnd_18
Supply
1.8 V Ground
SPI Clock
1.8 V Supply
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67
NOIV1SN1300A, NOIV2SN1300A
Table 39. PIN LIST FOR V2-SN/SE CMOS INTERFACE
Pack Pin
No.
Pin Name
I/O Type
Direction
I/O
Description
28
ibias_master
Analog
Master Bias Reference. Connect with 47k to gnd_33.
29
vdd_33
Supply
3.3 V Supply
30
gnd_33
Supply
3.3 V Ground
31
vdd_pix
Supply
Pixel Array Supply
32
gnd_colpc
Supply
Pixel Array Ground
33
vdd_pix
Supply
Pixel Array Supply
34
gnd_colpc
Supply
Pixel Array Ground
35
gnd_33
Supply
3.3 V Ground
36
vdd_33
Supply
3.3 V Supply
37
gnd_colpc
Supply
Pixel Array Ground
38
vdd_pix
Supply
Pixel Array Supply
39
gnd_colpc
Supply
Pixel Array Ground
40
vdd_pix
Supply
Pixel Array Supply
41
trigger0
CMOS
Input
Trigger Input #0
42
trigger1
CMOS
Input
Trigger Input #1
43
trigger2
CMOS
Input
Trigger Input #2
44
monitor0
CMOS
Output
Monitor Output #0
45
monitor1
CMOS
Output
Monitor Output #1
46
reset_n
CMOS
Input
Sensor Reset (Active Low)
47
ss_n
CMOS
Input
SPI Slave Select (Active Low)
48
gnd_33
Supply
3.3 V Ground
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68
NOIV1SN1300A, NOIV2SN1300A
Mechanical Specification
Parameter
Die
(Refer to Figure 43
showing Pin 1 reference as left center)
Glass Lid
Specification
Description
Die thickness
Min
Typ
Max
NA
740
NA
Die Size
Units
mm
mm2
8.65 X 7.95
Die center, X offset to the center of package
-50
0
50
mm
Die center, Y offset to the center of the package
-50
0
50
mm
Die position, tilt to the Die Attach Plane
-1
0
1
deg
Die rotation accuracy (referenced to die scribe and lead fingers on package on all four sides)
-1
0
1
deg
Optical center referenced from the die/package center (X-dir)
-179.3
mm
Optical center referenced from the die/package center (Y-dir)
1367.1
mm
Distance from PCB plane to top of the die surface
1.06
1.26
1.46
mm
Distance from top of the die surface to top of the glass lid
0.75
0.95
1.15
mm
(-10%)
13.6 X 13.6
(+10%)
mm2
Thickness
0.5
0.55
0.6
mm
Spectral response range
400
1000
nm
92
%
2000
G
2000
Hz
260
°C
XY size
Transmission of glass lid (refer to Figure 44)
Mechanical Shock
JESD22-B104C; Condition G
Vibration
JESD22-B103B; Condition 1
Mounting Profile
Reflow profile according to J-STD-020D.1
Recommended
Socket
Andon Electronics Corporation
http://www.andonelect.com
20
680-48-SM-G10-R14-X
Package Drawing
GLASS
Figure 42. Package Drawing for the 48−pin LCC Package
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69
NOIV1SN1300A, NOIV2SN1300A
• Active Area outer dimensions
Optical Center Information
The center of the die (CD) is the center of the cavity
The center of the die (CD) is exactly at 50% between the
outsides of the two outer seal rings
The center of the cavity is exactly at 50% between the
insides of the finger pads.
• Die outer dimensions:
♦ D4 is the reference for the Die (0,0) in mm
♦ D3 is at (7950,0) mm
♦ D2 is at (7950,8650) mm
♦ D3 is at (0,8650) mm
A1 is the at (706.9, 3217.7) mm
A2 is at (6884.5, 3217.7) mm
♦ A3 is at (6884.5, 8166.5) mm
♦ A4 is at (706.9, 8166.5) mm
Center of the Active Area
♦ AA is at (3795.7, 5692.1) mm
Center of the Die
♦ CD is at (3975, 4325) mm
♦
♦
•
•
Figure 43. Graphical Representation of the Optical Center
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70
NOIV1SN1300A, NOIV2SN1300A
Glass Lid
As shown in Figure 44, no infrared attenuating color filter
glass is used. A filter must be provided in the optical path
when
color
devices
are
used
(source:
http://www.pgo-online.com).
The VITA 1300 image sensor uses a glass lid without any
coatings. Figure 44 shows the transmission characteristics
of the glass lid.
Figure 44. Transmission Characteristics of the Glass Lid
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71
NOIV1SN1300A, NOIV2SN1300A
ADDITIONAL REFERENCES AND RESOURCES
Application Notes and other resources can be found
linked to the product web page at www.onsemi.com.
Additional information on this device may also be available
in the Image Sensor Portal, accessible within the MyON
section of www.onsemi.com. A signed NDA is required to
access the Image Sensor Portal – please see your
ON Semiconductor sales representative for more
information.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions document
from www.onsemi.com.
For information on Return Material Authorization
procedures, please refer to the RMA Policy Procedure
document from www.onsemi.com.
The Product Acceptance Criteria document, which lists
criteria to which this device is tested prior to shipment, is
available upon request.
For information on ESD and cover glass care and
cleanliness, please download the Application Note Image
Sensor Handling and Best Practices (AN52561/D) from
www.onsemi.com.
www.onsemi.com
72
NOIV1SN1300A, NOIV2SN1300A
SILICON ERRATA
VITA 1300 Qualification Status
This section describes the erratum for the VITA 1300
family.
Details include erratum trigger conditions, scope of
impact, available workaround, and silicon revision
applicability.
Items
[1]. Higher Standby current than rated in data sheet
Production Silicon
VITA 1300 Errata Summary
This table defines how the errata applies to the
VITA 1300.
Part Number
Silicon revision
VITA 1300 family
Production Silicon
(same as “ES2”)
• PROBLEM DEFINITION
Maintain the device in ‘power-off’, ‘idle’ or ‘running’
modes.
• FIX STATUS
The cause of this problem and its solution have been
identified. Silicon fix is planned to correct the deficiency.
• COMPLETION DATE
Production silicon with Stand-by current fix is planned.
In all states except for ‘idle’ and ‘running’ (including
‘reset’) there can be abnormal high power consumption on
vdd_33, up to 300mW.
• PARAMETERS AFFECTED
Power
• TRIGGER CONDITION(S)
Entering an affected state (reset, low-power standby,
standby(1), standby(2)).
• SCOPE OF IMPACT
High power consumption, not influencing performance
when grabbing images.
[2]. Rolling shutter mode has first line
brighter than the remainder rows in
uniform illumination
Silicon fix planned
• WORKAROUND
Higher Standby Current
Items
Fix Status
Part Number
Silicon revision
VITA 1300 family
Production Silicon
(same as “ES2”)
• SCOPE OF IMPACT
Rolling Shutter Mode: First row is brighter in uniform
illumination
Fix Status
No silicon fix planned
First 1 to 5 rows may show the blooming effect. Refer to
the VITA 1300 Acceptance Criteria Specification for
production test criteria.
• WORKAROUND
Maximum resolution of actual image is 1280 x 1019.
• FIX STATUS
The cause of this problem has been identified. No silicon
fix is planned to correct the deficiency.
• COMPLETION DATE
Not applicable.
• PROBLEM DEFINITION
The first line(s) are brighter than the remainder rows in
uniform illumination due to blooming.
• PARAMETERS AFFECTED
Image artifact: Brighter row(s)
• TRIGGER CONDITION(S)
Artifact observed in rolling shutter mode only.
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73
NOIV1SN1300A, NOIV2SN1300A
ACRONYMS
Acronym
Description
Acronym
Description
ADC
Analog-to-Digital Converter
IP
Intellectual Property
AFE
Analog Front End
LE
Line End
BL
Black pixel data
LS
Line Start
CDM
Charged Device Model
LSB
least significant bit
CDS
Correlated Double Sampling
LVDS
Low-Voltage Differential Signaling
CMOS
Complementary Metal Oxide Semiconductor
MSB
most significant bit
CRC
Cyclic Redundancy Check
PGA
Programmable Gain Amplifier
DAC
Digital-to-Analog Converter
PLS
Parasitic Light Sensitivity
DDR
Double Data Rate
PRBS
Pseudo-Random Binary Sequence
DNL
Differential Non-Llinearity
PRNU
Photo Response Non-Uniformity
DS
Double Sampling
QE
Quantum Efficiency
DSNU
Dark Signal Non-Uniformity
RGB
Red-Green-Blue
EIA
Electronic Industries Alliance
RMA
Return Material Authorization
ESD
Electrostatic Discharge
rms
Root Mean Square
FE
Frame End
ROI
Region of Interest
FF
Fill Factor
ROT
Row Overhead Time
FOT
Frame Overhead Time
S/H
Sample and Hold
FPGA
Field Programmable Gate Array
SNR
Signal-to-Noise Ratio
FPN
Fixed Pattern Noise
SPI
Serial Peripheral Interface
FPS
Frame per Second
TIA
Telecommunications Industry Association
FS
Frame Start
TJ
Junction temperature
HBM
Human Body Model
TR
Training pattern
IMG
Image data (regular pixel data)
% RH
Percent Relative Humidity
INL
Integral Non-Linearity
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74
NOIV1SN1300A, NOIV2SN1300A
GLOSSARY
conversion gain
A constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel.
Conversion gain = q/C where q is the charge of an electron (1.602E 19 Coulomb) and C is the capacitance
of the photodiode or sense node.
CDS
Correlated double sampling. This is a method for sampling a pixel where the pixel voltage after reset is
sampled and subtracted from the voltage after exposure to light.
CFA
Color filter array. The materials deposited on top of pixels that selectively transmit color.
DNL
Differential non-linearity (for ADCs)
DSNU
Dark signal non-uniformity. This parameter characterizes the degree of non-uniformity in dark leakage
currents, which can be a major source of fixed pattern noise.
fill-factor
A parameter that characterizes the optically active percentage of a pixel. In theory, it is the ratio of the
actual QE of a pixel divided by the QE of a photodiode of equal area. In practice, it is never measured.
INL
Integral nonlinearity (for ADCs)
IR
Infrared. IR light has wavelengths in the approximate range 750 nm to 1 mm.
Lux
Photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m2 = 1/683 W/m2)
pixel noise
Variation of pixel signals within a region of interest (ROI). The ROI typically is a rectangular portion of the
pixel array and may be limited to a single color plane.
photometric units
Units for light measurement that take into account human physiology.
PLS
Parasitic light sensitivity. Parasitic discharge of sampled information in pixels that have storage nodes.
PRNU
Photo-response non-uniformity. This parameter characterizes the spread in response of pixels, which is a
source of FPN under illumination.
QE
Quantum efficiency. This parameter characterizes the effectiveness of a pixel in capturing photons and
converting them into electrons. It is photon wavelength and pixel color dependent.
read noise
Noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode
into an output signal.
reset
The process by which a pixel photodiode or sense node is cleared of electrons. ”Soft” reset occurs when
the reset transistor is operated below the threshold. ”Hard” reset occurs when the reset transistor is operated above threshold.
reset noise
Noise due to variation in the reset level of a pixel. In 3T pixel designs, this noise has a component (in units
of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). In 4T pixel
designs, reset noise can be removed with CDS.
responsivity
The standard measure of photodiode performance (regardless of whether it is in an imager or not). Units
are typically A/W and are dependent on the incident light wavelength. Note that responsivity and sensitivity
are used interchangeably in image sensor characterization literature so it is best to check the units.
ROI
Region of interest. The area within a pixel array chosen to characterize noise, signal, crosstalk, and so on.
The ROI can be the entire array or a small subsection; it can be confined to a single color plane.
sense node
In 4T pixel designs, a capacitor used to convert charge into voltage. In 3T pixel designs it is the photodiode itself.
sensitivity
A measure of pixel performance that characterizes the rise of the photodiode or sense node signal in Volts
upon illumination with light. Units are typically V/(W/m2)/sec and are dependent on the incident light wavelength. Sensitivity measurements are often taken with 550 nm incident light. At this wavelength, 1 683 lux
is equal to 1 W/m2; the units of sensitivity are quoted in V/lux/sec. Note that responsivity and sensitivity are
used interchangeably in image sensor characterization literature so it is best to check the units.
spectral response
The photon wavelength dependence of sensitivity or responsivity.
SNR
Signal-to-noise ratio. This number characterizes the ratio of the fundamental signal to the noise spectrum
up to half the Nyquist frequency.
temporal noise
Noise that varies from frame to frame. In a video stream, temporal noise is visible as twinkling pixels.
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75
NOIV1SN1300A, NOIV2SN1300A
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
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