Ordering Orderingnumber number::ENA2011A ENA2011A LA4425PV Monolithic Linear IC 5W Power Amplifier with Very Few External Parts for Car Radio and Car Stereo http://onsemi.com Overview The LA4425PV is a 5W power amplifier with very few external parts. Encapsulated in a surface mount package [SSOP44K (275 mil)], it is designed for operation without a heat sink. Only two external parts (Only IN/OUT coupling capacitors). Almost no evaluation, adjustment and check of its functions as a power IC required, enabling control to be simplified and set patterns to be further miniaturized. Functions • Wide operation supply range → 5 to 16V • On-chip protection: - Over-voltage protection - Thermal protection - Output D.C. short protection . • On-chip pop noise reducing circuit Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Surge maximum supply voltage Symbol VCC max VCC surge Conditions Ratings Unit Rg = 0Ω 18 V Giant pulse 200ms 50 V Rise time 1ms Maximum output current IO peak Allowable power dissipation Pd max When mounted on the specified PCB 3.3 A 5.15 W Operating temperature Topr -40 to +85 °C Storage temperature Tstg -40 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Semiconductor Components Industries, LLC, 2013 June, 2013 31412 SY/22912 SY 20110916 S00002 No.A2011-1/8 LA4425PV Operating Conditions at Ta = 25°C, Parameter Symbol Recommended supply voltage VCC Recommended load resistance RL Operating voltage range Conditions Ratings VCC op Operating load resistance range RL op Under conditions where maximum ratings are Unit 13.2 V 4 Ω 5 to 16 V 2 to 8 Ω not exceeded Electrical Characteristics at Ta = 25°C, VCC = 13.2V, RL = 4Ω, f = 1 kHz, Rg = 600Ω, Specified board/specified circuit Ratings Parameter Symbol Conditions Unit min Quiescent current typ ICCO 65 130 mA 43 45 47 dB 13.2 V / 4Ω, THD = 10% 4 5 14.4 V / 4Ω, THD = 10% 5 6 Voltage gain VG VO = 0dBm Output power PO1 PO2 THD VO = 2Vrms Total harmonic distortion max Output noise voltage VNO Rg = 0Ω, BPF = 20 Hz to 20 kHz Ripple rejection ratio SVRR1 Rg = 0Ω, BPF = 20 Hz to 20 kHz 30 W W 0.1 1.0 % 0.15 0.5 mV 40 dB 47 dB 21.5 V VR = 0dBm, fR = 100Hz SVRR2 Rg = 0Ω, BPF = 20 Hz to 20 kHz VR = 0dBm, fR = 1kHz Over-voltage attack VCCX Starting time Rg = 0Ω tS Input resistance Roll-off frequency 0.35 s RIN 50 kΩ fL 40 Hz fH 90 kHz Package Dimensions unit : mm (typ) 3333 TOP VIEW SIDE VIEW BOTTOM VIEW 15.0 44 23 (3.5) 0.5 5.6 7.6 (4.7) 0.22 22 0.2 1.7MAX 0.65 SIDE VIEW 0.1 (1.5) 1 (0.68) SANYO : SSOP44K(275mil) No.A2011-2/8 LA4425PV Pd max -- Ta Maximum power dissipation, Pd max -- W 6.0 5.15 5.0 Board specifications of the Pdmax - Ta measurement (LA4425PV specified PCB) Size: 70mm × 70mm × 1.6mm3 (Four layer boards) Copper foil thickness: L1/L4=18µm, L2/L3=35µm Materials: FR-4 (Glass cloth matrix epoxy resin) 4.0 3.0 2.68 2.0 1.0 0 -40 -20 0 20 40 60 80 100 Ambient temperature, Ta -- C L1: Figure of copper wiring pattern L2: Figure of copper wiring pattern L3: Figure of copper wiring pattern L4: Figure of copper wiring pattern Notes: The data for the case with the exposed die-pad substrate mounted shows the values when 95% or more of the Exposed Die-Pad is wet. 1. For the set design, employ the derating design with sufficient margin. 2. Stresses to be derated include the voltage, current, junction temperature, power loss, and mechanical stresses such as vibration, impact, and tension. Accordingly, the design must ensure these stresses to be as low or small as possible. The guideline for ordinary derating is shown below: (1) Maximum value 80% or less for the voltage ratings (2) Maximum value 80% or less for the current ratings (3) Maximum value 80% or less for the temperature ratings 3. After the set has been designed, be sure to verify the design with the actual product. Confirm the solder joint state and verify also the reliability of solder joint for the Exposed Die-Pad, etc. Any void or deterioration, if observed in the solder joint of these parts, causes deteriorated thermal conduction, possibly resulting in thermal destruction of IC. No.A2011-3/8 LA4425PV 35 34 33 32 POWERGND 36 31 30 29 28 27 26 25 24 23 14 15 16 17 18 19 20 21 22 PREGND 37 38 POWERGND 39 PREGND 40 41 OUT 42 OUT 43 VCC 44 VCC Pin Assignment LV4425PV 2 3 5 4 6 7 8 9 10 11 12 IN 1 13 • Connect exposed die pad on the back side to GND with a large pattern. • Pins whose names are not given next to the pin numbers are all “NC pins” that are not connected to the chip inside the package, and they must not be used as relay pins. Application Circuit Example VCC IN 36 37 + + 10 LA4425PV 33 + 34 OUT 14 15 PREGND 30 31 POWERGND • On-chip overvoltage protection • On-chip thermal protection • On-chip pop noise reducing circuit • On-chip output D.C. short protection Pin Voltage at VCC = 13.2V Characteristics Input Pre GND Power GND Output Pin No. 10 14, 15 30, 31 33, 34 Pin voltage (reference value) (≈ 2VBE) 0V 0V (≈ 1/2VCC) 1.4V 6.5V VCC 36, 37 (VCC) 13.2V No.A2011-4/8 LA4425PV IC Usage Notes • Maximum ratings If the IC is used in the vicinity of the maximum ratings, even a slight variation in conditions may cause the maximum ratings to be exceeded, thereby leading to a breakdown. • Printed circuit board When drawing the printed circuit pattern, refer to the sample printed circuit pattern. Be careful not to form a feedback loop between input and output. Always use both pins of the Pre GND, Power GND, OUT and VCC when designing the layout. • Exposed Die-Pad The exposed die pad on the back side of the IC must be connected to GND with a large pattern surface area. • Load Resistance and Misoperation It should be noted that when RL < 2Ω and VCC is high, and the switch is turned “ON” when setting is for a signal (THD = 10%), the ground detector (current × voltage Schmitt circuit) operates momentarily. • Starting Time (ts) This is set at 0.35sec/typ, but it can be made shorter by making input capacitor Ci smaller, or longer by making it larger. • Pop noise The pop noise prevention circuit operates to reduce pop until Rg reaches 50kΩ. However, if Rg is left open, the charging route of input capacitor Ci is lost, so the pop noise reduction circuit stops operating and click noises become louder. • VG/OSC The voltage gain is fixed at 45dB inside the IC. It is impossible to change it externally. Phase compensation capacitors (350pF/total) are connected between individual stages inside the IC, and the open loop gain is low. In addition, the upper and lower drives are made equivalent so that final stage current gain is adjusted, providing a measure against unwanted high-frequency parasitic oscillation peculiar to power IC’s. • BTL Connection Connection is impossible with IC alone. PS No.A2011-5/8 LA4425PV ICCO -- VCC VN -- VCC 12 10 80 Output pin voltage, VN -- V Quiescent current, ICCO -- mA 100 60 40 20 0 0 8 6 4 2 2 4 6 8 10 12 14 16 18 20 22 0 0 24 2 4 Supply voltage, VCC -- V 10 Total harmonic distortion, THD -- % 3 2 0.1 7 5 3 2 1.0 18 20 22 24 5 7 10 7 10k 2 3 3 2 1.0 7 5 3 2 0.1 7 2 3 5 7 2 10 3 5 7 5 5 100 7 0.1 2 3 0 2 Total harmonic distortion, THD -- % 3 -1 -2 fL -4 fH -5 -6 -7 -8 -9 2 3 5 2 3 100 5 1k 2 3 2 1.0 3 5 10k 2 3 1.0 7 5 3 2 0.1 7 5 3 3 5 100k 5 7 100 Frequency, f -- Hz 2 3 5 7 1k 2 3 5 Frequency, f -- Hz THD -- VCC 5 7 THD -- f 1 -3 5 Output power, PO -- W f Response Response -- dB 16 5 Input voltage, VIN -- mV PO -- VCC 12 3 10 2 Output power, PO -- W Total harmonic distortion, THD -- % 14 7 1.0 7 5 -10 10 12 THD -- PO 10 3 2 Output power, PO -- W 8 Supply voltage, VCC -- V PO -- VIN 10 7 5 6 1.0 7 5 3 2 6 4 2 0.1 7 5 6 8 8 10 12 14 16 Supply voltage, VCC -- V 18 20 0 8 10 12 14 16 18 20 Supply voltage, VCC -- V PS No.A2011-6/8 LA4425PV ICC, Pd -- PO 700 7 ICC, Pd -- PO 1200 ICC 6 VCC=16V 400 300 VCC=13.2V 4 3 200 2 100 1 0 7 2 0.1 3 5 7 2 1.0 3 5 7 Current drain, ICC -- mA 5 500 1000 Power dissipation, Pd -- W Current drain, ICC -- mA 600 10 800 8 VCC=16V 600 400 VCC=13.2V 200 2 3 5 Output power, PO -- W 7 1.0 2 3 5 7 10 0 2 Output power, PO -- W VNO -- Rg 1.0 4 2 0 7 0.1 0 10 6 Power dissipation, Pd -- W ICC SVRR -- VCC 50 Ripple rejection ratio, SVRR -- dB Output noise voltage, VNO -- mV 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 7 1k 2 3 5 7 10k 2 3 5 7 100k 40 30 20 10 0 8 2 9 10 11 12 13 14 15 16 17 18 19 Supply voltage, VCC -- V SVRR -- VR Ripple rejection ratio, SVRR -- dB 40 30 20 10 0 0 200 400 600 800 SVRR -- fR 50 1000 1200 40 30 20 10 0 0 Power supply ripple, VR -- mVrms 5 7 100 2 3 5 7 1k 2 Ripple frequency, fR -- Hz 2V/div ts 2V/div Ripple rejection ratio, SVRR -- dB 50 GND GND 0.2s/div 0.2s/div PS No.A2011-7/8 LA4425PV ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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