Ramtron FM25CL64B-DGTR 64kb serial 3v f-ram memory Datasheet

Preliminary
FM25CL64B
64Kb Serial 3V F-RAM Memory
Features
64K bit Ferroelectric Nonvolatile RAM
• Organized as 8,192 x 8 bits
• High Endurance 100 Trillion (1014) Read/Writes
• 38 Year Data Retention (@ +75ºC)
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Very Fast Serial Peripheral Interface - SPI
• Up to 20 MHz Frequency
• Direct Hardware Replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Description
The FM25CL64B is a 64-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 38 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
The FM25CL64B performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array immediately after each byte has
been successfully transferred to the device. The next
bus cycle may commence immediately without the
need for data polling. In addition, the product offers
substantial write endurance compared with other
nonvolatile memories. The FM25CL64B is capable
of supporting 1014 read/write cycles, or 100 million
times more write cycles than EEPROM.
Sophisticated Write Protection Scheme
• Hardware Protection
• Software Protection
Low Power Consumption
• Low Voltage Operation 2.7-3.65V
• 200 µA Active Current (1 MHz)
• 3 µA (typ.) Standby Current
Industry Standard Configuration
• Industrial Temperature -40°C to +85°C
• 8-pin “Green”/RoHS SOIC and TDFN Packages
Pin Configuration
CS
1
8
VDD
SO
WP
2
7
3
6
HOLD
SCK
VSS
4
5
SI
Top View
/CS
SO
/WP
VSS
1
8
2
7
3
6
4
5
VDD
/HOLD
SCK
SI
These capabilities make the FM25CL64B ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss.
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
The FM25CL64B provides substantial benefits to
users of serial EEPROM as a hardware drop-in
replacement. The FM25CL64B uses the high-speed
SPI bus, which enhances the high-speed write
capability
of
F-RAM
technology.
Device
specifications are guaranteed over an industrial
temperature range of -40°C to +85°C.
Ordering Information
FM25CL64B-G
“Green” 8-pin SOIC
FM25CL64B-GTR
“Green” 8-pin SOIC,
Tape & Reel
FM25CL64B-DG
“Green”/RoHS 8-pin TDFN
FM25CL64B-DGTR
“Green”/RoHS 8-pin TDFN,
Tape & Reel
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 1.2
Feb. 2011
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage
Ground
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 14
FM25CL64B - 64Kb 3V SPI F-RAM
WP
Instruction Decode
Clock Generator
Control Logic
Write Protect
CS
HOLD
SCK
1,024 x 64
FRAM Array
Instruction Register
Address Register
Counter
SI
13
8
Data I/O Register
SO
3
Nonvolatile Status
Register
Figure 1. Block Diagram
Pin Descriptions
Pin Name
/CS
I/O
Input
SCK
Input
/HOLD
Input
/WP
Input
SI
Input
SO
Output
VDD
VSS
Supply
Supply
Rev. 1.2
Feb. 2011
Description
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 20 MHz and may be interrupted at
any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is low.
Write Protect: This active low pin prevents write operations to the Status Register.
This is critical since other write protection features are controlled through the Status
Register. A complete explanation of write protection is provided on pages 6 & 7.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet IDD specifications.
* SI may be connected to SO for a single pin data interface.
Serial Output: This is the data output pin. It is driven during a read and remains tristated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* SO may be connected to SI for a single pin data interface.
Power Supply (2.7V to 3.65V)
Ground
Page 2 of 14
FM25CL64B - 64Kb 3V SPI F-RAM
Overview
The FM25CL64B is a serial F-RAM memory. The
memory array is logically organized as 8,192 x 8 and
is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the F-RAM is similar to serial EEPROMs. The
major difference between the FM25CL64B and a
serial EEPROM with the same pinout is the FRAM’s superior write performance.
Memory Architecture
When accessing the FM25CL64B, the user addresses
8,192 locations of 8 data bits each. These data bits
are shifted serially. The addresses are accessed using
the SPI protocol, which includes a chip select (to
permit multiple devices on the bus), an op-code, and
a two-byte address. The upper 3 bits of the address
range are ‘don’t care’ values. The complete address
of 13-bits specifies each byte address uniquely.
Most functions of the FM25CL64B either are
controlled by the SPI interface or are handled
automatically by on-board circuitry. The access time
for memory operation is essentially zero, beyond the
time needed for the serial protocol. That is, the
memory is read or written at the speed of the SPI bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. So, by the time a new bus transaction can be
shifted into the device, a write operation will be
complete. This is explained in more detail in the
interface section.
Users expect several obvious system benefits from
the FM25CL64B due to its fast write cycle and high
endurance as compared with EEPROM. In addition
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Note: The FM25CL64B contains no power
management circuits other than a simple internal
power-on reset circuit. It is the user’s
responsibility to ensure that VDD is within
datasheet tolerances to prevent incorrect
operation. It is recommended that the part is not
powered down with chip enable active.
Serial Peripheral Interface – SPI Bus
The FM25CL64B employs a Serial Peripheral
Interface (SPI) bus. It is specified to operate at speeds
up to 20 MHz. This high-speed serial bus provides
Rev. 1.2
Feb. 2011
high performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25CL64B operates in SPI Mode 0 and 3.
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses one or more FM25CL64B devices
with a microcontroller that has a dedicated SPI port,
as Figure 2 illustrates. Note that the clock, data-in,
and data-out pins are common among all devices.
The Chip Select and Hold pins must be driven
separately for each FM25CL64B device.
For a microcontroller that has no dedicated SPI bus, a
general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins (SI, SO) together and tie
off (high) the /HOLD pin. Figure 3 shows a
configuration that uses only three pins.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data pins. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25CL64B will begin
monitoring the clock and data lines. The relationship
between the falling edge of /CS, the clock and data is
dictated by the SPI mode. The device will make a
determination of the SPI mode on the falling edge of
each chip select. While there are four such modes, the
FM25CL64B supports Modes 0 and 3. Figure 4
shows the required signal relationships for Modes 0
and 3. For both modes, data is clocked into the
FM25CL64B on the rising edge of SCK and data is
expected on the first rising edge after /CS goes
active. If the clock begins from a high state, it will
fall prior to beginning data transfer in order to create
the first rising edge.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the device. After
/CS is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred. Note that the
WREN and WRDI op-codes are commands with no
subsequent data transfer.
Important: The /CS pin must go inactive after an
operation is complete and before a new op-code
can be issued. There is one valid op-code only per
active chip select.
Page 3 of 14
FM25CL64B - 64Kb 3V SPI F-RAM
SCK
MOSI
MISO
SO
SPI
Microcontroller
SI
SCK
SO
FM25CL64B
CS
SI
SCK
FM25CL64B
HOLD
CS
HOLD
SS1
SS2
HOLD1
HOLD2
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS : Slave Select
Figure 2. System Configuration with SPI port
Figure 3. System Configuration without SPI port
SPI Mode 0: CPOL=0, CPHA=0
7
6
5
4
3
2
1
0
SPI Mode 3: CPOL=1, CPHA=1
7
6
5
4
3
2
1
0
Figure 4. SPI Modes 0 & 3
Rev. 1.2
Feb. 2011
Page 4 of 14
FM25CL64B - 64Kb 3V SPI F-RAM
Data Transfer
All data transfers to and from the FM25CL64B occur
in 8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
WREN - Set Write Enable Latch
The FM25CL64B will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for write
operations. These include writing the Status Register
(WRSR) and writing the memory (WRITE).
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25CL64B. They
are listed in the table below. These op-codes control
the functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the Status
Register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Sending the WREN op-code causes the internal Write
Enable Latch to be set. A flag bit in the Status
Register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the Status
Register has no effect on the state of this bit – only
the WREN op-code can set this bit. The WEL bit will
be automatically cleared on the rising edge of /S
following a WRDI, a WRSR, or a WRITE operation.
This prevents further writes to the Status Register or
the F-RAM array without another WREN command.
Figure 5 below illustrates the WREN command bus
configuration.
Table 1. Op-code Commands
Name
Description
Set Write Enable Latch
WREN
Write Disable
WRDI
Read Status Register
RDSR
Write Status Register
WRSR
Read Memory Data
READ
WRITE Write Memory Data
Op-code
0000
0000
0000
0000
0000
0000
0110b
0100b
0101b
0001b
0011b
0010b
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in the
Status Register and verifying that WEL=0. Figure 6
illustrates the WRDI command bus configuration.
Figure 5. WREN Bus Configuration
Figure 6. WRDI Bus Configuration
Rev. 1.2
Feb. 2011
Page 5 of 14
FM25CL64B - 64Kb 3V SPI F-RAM
RDSR - Read Status Register
The RDSR command allows the bus master to verify
the contents of the Status Register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR opcode, the FM25CL64B will return one byte with the
contents of the Status Register. The Status Register is
described in detail in a later section.
WRSR – Write Status Register
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status Register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive. Note
that on the FM25CL64B, /WP only prevents writing
to the Status Register, not the memory array. Prior to
sending the WRSR command, the user must send a
WREN command to enable writes. Note that
executing a WRSR command is a write operation and
therefore clears the Write Enable Latch.
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration (WREN not shown)
Status Register & Write Protection
The write protection features of the FM25CL64B are
multi-tiered. First, a WREN op-code must be issued
prior to any write operation. Assuming that writes are
enabled using WREN, writes to memory are
controlled by the Status Register. As described
above, writes to the Status Register are performed
using the WRSR command and subject to the /WP
pin. The Status Register is organized as follows.
Table 2. Status Register
Bit
Name
7
WPEN
6
0
5
0
4
0
3
BP1
2
BP0
1
WEL
0
0
Bits 0 and 4-6 are fixed at 0 and cannot be modified.
Note that bit 0 (“Ready” in EEPROMs) is
unnecessary as the F-RAM writes in real-time and is
never busy. The WPEN, BP1 and BP0 control write
protection features. They are nonvolatile (shaded
Rev. 1.2
Feb. 2011
yellow). The WEL flag indicates the state of the
Write Enable Latch. Attempting to directly write the
WEL bit in the Status Register has no effect on its
state. This bit is internally set and cleared via the
WREN and WRDI commands, respectively.
BP1 and BP0 are memory block write protection bits.
They specify portions of memory that are writeprotected as shown in the following table.
Table 3. Block Memory Write Protection
BP1
BP0 Protected Address Range
0
0
None
0
1
1800h to 1FFFh (upper ¼)
1
0
1000h to 1FFFh (upper ½)
1
1
0000h to 1FFFh (all)
Page 6 of 14
FM25CL64B - 64Kb 3V SPI F-RAM
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
The WPEN bit controls the effect of the hardware
/WP pin. When WPEN is low, the /WP pin is
ignored. When WPEN is high, the /WP pin controls
write access to the Status Register. Thus the Status
Register is write protected if WPEN=1 and /WP=0.
Table 4. Write Protection
WEL
WPEN
/WP
0
X
X
1
0
X
1
1
0
1
1
1
Protected Blocks
Protected
Protected
Protected
Protected
Memory Operation
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the F-RAM technology. Unlike SPI-bus
EEPROMs, the FM25CL64B can perform sequential
writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Write Operation
All writes to the memory begin with a WREN opcode with /CS being asserted and deasserted. The
next op-code is WRITE. The WRITE op-code is
followed by a two-byte address value. The upper 3bits of the address are ignored. In total, the 13-bits
specify the address of the first data byte of the write
operation. This is the starting address of the first data
byte of the write operation. Subsequent bytes are data
bytes, which are written sequentially. Addresses are
incremented internally as long as the bus master
continues to issue clocks and keeps /CS low. If the
last address of 1FFFh is reached, the counter will roll
over to 0000h. Data is written MSB first. The rising
edge of /CS terminates a WRITE operation. A write
operation is shown in Figure 9.
EEPROMs use page buffers to increase their write
throughput. This compensates for the technology’s
inherently slow write operations. F-RAM memories
do not have page buffers because each byte is written
to the F-RAM array immediately after it is clocked in
Rev. 1.2
Feb. 2011
This scheme provides a write protection mechanism,
which can prevent software from writing the memory
under any circumstances. This occurs if the BP1 and
BP0 are set to 1, the WPEN bit is set to 1, and /WP is
set to 0. This occurs because the block protect bits
prevent writing memory and the /WP signal in
hardware prevents altering the block protect bits (if
WPEN is high). Therefore in this condition, hardware
must be involved in allowing a write operation. The
following table summarizes the write protection
conditions.
Unprotected Blocks
Protected
Unprotected
Unprotected
Unprotected
Status Register
Protected
Unprotected
Protected
Unprotected
(after the 8th clock). This allows any number of bytes
to be written without page buffer delays.
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Following the READ command is
a two-byte address value. The upper 3-bits of the
address are ignored. In total, the 13-bits specify the
address of the first byte of the read operation. This is
the starting address of the first byte of the read
operation. After the op-code and address are issued,
the device drives out the read data on the next 8
clocks. The SI input is ignored during read data
bytes. Subsequent bytes are data bytes, which are
read out sequentially. Addresses are incremented
internally as long as the bus master continues to issue
clocks and /CS is low. If the last address of 1FFFh is
reached, the counter will roll over to 0000h. Data is
read MSB first. The rising edge of /CS terminates a
READ operation. A read operation is shown in
Figure 10.
Hold
The /HOLD pin can be used to interrupt a serial
operation without aborting it. If the bus master pulls
the /HOLD pin low while SCK is low, the current
operation will pause. Taking the /HOLD pin high
while SCK is low will resume an operation. The
transitions of /HOLD must occur while SCK is low,
but the SCK pin can toggle during a hold state.
Page 7 of 14
FM25CL64B - 64Kb 3V SPI F-RAM
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
X
X
13-bit Address
X 12 11 10
3
4
5
6
7
0
1
2
3
4
5
6
7
4
3
2
1
0
7
6
Data
5 4
3
2
1
0
SCK
op-code
0
SI
0
0
0
0
0
1
0
MSB
SO
LSB MSB
LSB
Figure 9. Memory Write (WREN not shown)
CS
0
1
2
3
4
5
6
7
0
1
2
X
X
X
3
4
5
3
4
5
6
7
4
3
2
1
0
0
1
2
3
4
5
Data
4 3
5
6
7
SCK
op-code
SI
0
0
0
0
0
0
1
1
13-bit Address
12 11 10
LSB MSB
MSB
SO
7
6
LSB
2
1
0
Figure 10. Memory Read
Endurance
The FM25CL64B devices are capable of being
accessed at least 1014 times, reads or writes. An FRAM memory operates with a read and restore
mechanism. Therefore, an endurance cycle is applied
on a row basis for each access (read or write) to the
memory array. The F-RAM architecture is based on
an array of rows and columns. Rows are defined by
A12-A3 and column addresses by A2-A0. See Block
Diagram (pg 2) which shows the array as 1K rows of
64-bits each. The entire row is internally accessed
once whether a single byte or all eight bytes are read
or written. Each byte in the row is counted only once
in an endurance calculation. The table below shows
endurance calculations for 64-byte repeating loop,
which includes an op-code, a starting address, and a
sequential 64-byte data stream. This causes each byte
to experience one endurance cycle through the loop.
F-RAM read and write endurance is virtually
unlimited even at 20MHz clock rate.
Table 5. Time to Reach Endurance Limit for Repeating 64-byte Loop
SCK Freq
Endurance
Endurance
Years to Reach
(MHz)
Cycles/sec.
Cycles/year
Limit
20
37,310
1.18 x 1012
85.1
10
18,660
5.88 x 1011
170.2
5
9,330
2.94 x 1011
340.3
Rev. 1.2
Feb. 2011
Page 8 of 14
FM25CL64B - 64Kb 3V SPI F-RAM
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
VDD
Power Supply Voltage with respect to VSS
VIN
Voltage on any pin with respect to VSS
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
Package Moisture Sensitivity Level
Ratings
-1.0V to +5.0V
-1.0V to +5.0V
and VIN < VDD+1.0V
-55°C to + 125°C
260° C
4kV
1.25kV
300V
MSL-1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40° C to + 85° C, VDD = 2.7V to 3.65V unless otherwise specified)
Symbol Parameter
Min
Typ
Max
Units
VDD
Power Supply Voltage
2.7
3.3
3.65
V
IDD
VDD Supply Current
@ SCK = 1.0 MHz
0.2
mA
@ SCK = 20.0 MHz
3.0
mA
ISB
Standby Current
3
6
µA
ILI
Input Leakage Current
±1
µA
ILO
Output Leakage Current
±1
µA
VIH
Input High Voltage
0.7 VDD
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.3 VDD
V
VOH
Output High Voltage
V
VDD – 0.8
@ IOH = -2 mA
VOL
Output Low Voltage
0.4
V
@ IOL = 2 mA
VHYS
Input Hysteresis
0.05 VDD
V
Notes
1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2. SCK = SI = /CS=VDD. All inputs VSS or VDD.
3. VSS ≤ VIN ≤ VDD and VSS ≤ VOUT ≤ VDD.
4. Characterized but not 100% tested in production. Applies only to /CS and SCK pins.
Rev. 1.2
Feb. 2011
Notes
1
2
3
3
4
Page 9 of 14
FM25CL64B - 64Kb 3V SPI F-RAM
AC Parameters (TA = -40° C to + 85° C, CL = 30pF, VDD = 2.7V to 3.65V unless otherwise specified)
Symbol
Parameter
Min
Max
Units
Notes
fCK
SCK Clock Frequency
0
20
MHz
tCH
Clock High Time
22
ns
1
tCL
Clock Low Time
22
ns
1
tCSU
Chip Select Setup
10
ns
tCSH
Chip Select Hold
10
ns
tOD
Output Disable Time
20
ns
2
tODV
Output Data Valid Time
20
ns
tOH
Output Hold Time
0
ns
tD
Deselect Time
60
ns
tR
Data In Rise Time
50
ns
2,3
tF
Data In Fall Time
50
ns
2,3
tSU
Data Setup Time
5
ns
tH
Data Hold Time
5
ns
tHS
/HOLD Setup Time
10
ns
tHH
/HOLD Hold Time
10
ns
tHZ
/HOLD Low to Hi-Z
20
ns
2
tLZ
/HOLD High to Data Active
20
ns
2
Notes
1.
2.
3.
tCH + tCL = 1/fCK.
Characterized but not 100% tested in production.
Rise and fall times measured between 10% and 90% of waveform.
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V)
Symbol Parameter
CO
Output Capacitance (SO)
CI
Input Capacitance
Notes
1.
Min
-
Max
8
6
Units
pF
pF
Notes
1
1
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
Output Load Capacitance
Data Retention
Symbol
Parameter
TDR
@ +85ºC
@ +80ºC
@ +75ºC
Rev. 1.2
Feb. 2011
10% and 90% of VDD
5 ns
0.5 VDD
30 pF
Min
10
19
38
Max
-
Units
Years
Years
Years
Notes
Page 10 of 14
FM25CL64B - 64Kb 3V SPI F-RAM
Serial Data Bus Timing
/Hold Timing
Power Cycle Timing
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.65V unless otherwise specified)
Symbol
Parameter
Min
Max
Units
tPU
VDD(min) to First Access Start
10
ms
tPD
Last Access Complete to VDD(min)
0
µs
tVR
VDD Rise Time
30
µs/V
tVF
VDD Fall Time
100
µs/V
Notes
1. Slope measured at any point on VDD waveform.
Rev. 1.2
Feb. 2011
Notes
1
1
Page 11 of 14
FM25CL64B - 64Kb 3V SPI F-RAM
Mechanical Drawing
8-pin SOIC (JEDEC MS-012 variation AA)
Recommended PCB Footprint
7.70
3.90 ±0.10
3.70
6.00 ±0.20
2.00
Pin 1
0.65
1.27
4.90 ±0.10
1.27
0.33
0.51
0.25
0.50
1.35
1.75
0.10
0.25
0.10 mm
0°- 8°
0.19
0.25
45 °
0.40
1.27
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
XXXXXXXP
RLLLLLLL
RICYYWW
Legend:
XXXXXXX= part number, P= package type (G=SOIC)
R=rev code, LLLLLLL= lot code
RIC=Ramtron Int’l Corp, YY=year, WW=work week
Example: FM25CL64B, “Green” SOIC package, Year 2010, Work Week 47
FM25CL64BG
A00002G1
RIC1047
Rev. 1.2
Feb. 2011
Page 12 of 14
FM25CL64B - 64Kb 3V SPI F-RAM
8-pin TDFN (4.0mm x 4.5mm body, 0.95mm pitch)
4.00 ±0.1
4.50 ±0.1
3.60 ±0.10
2.60 ±0.10
Exposed metal pad
should be left floating.
Pin 1
Pin 1 ID
0.30 ±0.1
2.85 REF
0.0 - 0.05
0.75 ±0.05
0.20 REF.
Recommended PCB Footprint
0.95
0.40 ±0.05
4.30
0.60
0.45
0.95
Note: All dimensions in millimeters. The exposed pad should be left floating.
TDFN Package Marking Scheme for Body Size 4.0mm x 4.5mm
RGXXXX
LLLL
YYWW
Legend:
R=Ramtron, G=”green” TDFN package, XXXX=base part number
LLLL= lot code
YY=year, WW=work week
Example: “Green”/RoHS TDFN package, FM25L64B, Lot 0003,
Year 2011, Work Week 07
R5L64B
0003
1107
Rev. 1.2
Feb. 2011
Page 13 of 14
FM25CL64B - 64Kb 3V SPI F-RAM
Revision History
Revision
1.0
1.1
1.2
Rev. 1.2
Feb. 2011
Date
11/15/2010
12/15/2010
2/15/2011
Summary
Initial Release
Added 4x4.5mm DFN package. Fixed endurance section on pg 8.
Added ESD ratings. Updated DFN package marking. Changed tPU and tVF
timing parameters.
Page 14 of 14