TI DS90UB904Q Ds90ub903q/ds90ub904q 10 - 43mhz 18 bit color fpd-link iii serializer and deserializer with bidirectional control channel Datasheet

DS90UB903Q, DS90UB904Q
www.ti.com
SNLS332E – JUNE 2010 – REVISED APRIL 2013
DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and
Deserializer with Bidirectional Control Channel
Check for Samples: DS90UB903Q, DS90UB904Q
FEATURES
DESCRIPTION
•
•
•
•
The DS90UB903Q/DS90UB904Q chipset offers a
FPD-Link III interface with a high-speed forward
channel and a bidirectional control channel for data
transmission over a single differential pair. The
DS90UB903Q/904Q
incorporates
differential
signaling on both the high-speed forward channel and
bidirectional control channel data paths. The
Serializer/ Deserializer pair is targeted for direct
connections between graphics host controller and
displays modules. This chipset is ideally suited for
driving video data to displays requiring 18-bit color
depth (RGB666 + HS, VS, and DE) along with
bidirectional control channel bus. The primary
transport converts 21 bit data over a single highspeed serial stream, along with a separate low
latency bidirectional control channel transport that
accepts control information from an I2C port. Using
TI’s embedded clock technology allows transparent
full-duplex communication over a single differential
pair, carrying asymmetrical bidirectional control
channel information in both directions. This single
serial stream simplifies transferring a wide data bus
over PCB traces and cable by eliminating the skew
problems between parallel data and clock paths. This
significantly saves system cost by narrowing data
paths that in turn reduce PCB layers, cable width,
and connector size and pins.
1
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
10 MHz to 43 MHz Input PCLK Support
210 Mbps to 903 Mbps Data Throughput
Single Differential Pair Interconnect
Bidirectional Control Interface Channel with
I2C Support
Embedded Clock with DC Balanced Coding to
Support AC-Coupled Interconnects
Capable to Drive up to 10 Meters Shielded
Twisted-Pair
I2C Compatible Serial Interface
Single Hardware Device Addressing Pin
Up to 4 General Purpose Input (GPI)/ Output
(GPO)
LOCK Output Reporting Pin and AT-SPEED
BIST Diagnosis Feature to Validate Link
Integrity
Integrated Termination Resistors
1.8V- or 3.3V-Compatible Parallel Bus Interface
Single Power Supply at 1.8V
ISO 10605 ESD and IEC 61000-4-2 ESD
Compliant
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
Temperature Range −40°C to +105°C
No Reference Clock Required on Deserializer
Programmable Receive Equalization
EMI/EMC Mitigation
– DES Programmable Spread Spectrum
(SSCG) Outputs
– DES Receiver Staggered Outputs
In addition, the Deserializer inputs provide
equalization control to compensate for loss from the
media over longer distances. Internal DC balanced
encoding/decoding is used to support AC-Coupled
interconnects.
The Serializer is offered in a 40-pin lead in WQFN
and Deserializer is offered in a 48-pin WQFN
packages.
APPLICATIONS
•
Automotive Display Systems
– Central Information Displays
– Navigation Displays
– Rear Seat Entertainment
– Touch Screen Displays
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
DS90UB903Q, DS90UB904Q
SNLS332E – JUNE 2010 – REVISED APRIL 2013
www.ti.com
Typical Application Diagram
FPD-Link III
Parallel
Data In
18+3
Graphics
Controller
-Video
Processor
Parallel
Data Out
18+3
4
Display
Module,
Touch Panel
4
DS90UB903Q
DS90UB904Q
GPO
GPI
Bidirectional
Control Channel
2
Bidirectional
Control Bus
2
Bidirectional
Control Bus
Deserializer
Serializer
Figure 1. Typical Application Circuit
DOUT+
DOUT-
RIN+
RT
RT
Output Latch
RT
Decoder
Serializer
4
RT
Deserializer
GPO[3:0]
Encoder
R/G/B[5:0], 21
HS,VS,DE
Input Latch
Block Diagrams
21 R/G/B[5:0],
HS,VS,DE
4
GPI[3:0]
RINPCLK
PDB
BISTEN
MODE
LOCK
PASS
I2C Controller
Decoder
Encoder
FIFO
Encoder
Timing
and
Control
Decoder
ID[x]
I2C Controller
SCL
Clock
Gen
CDR
Timing
and
Control
PDB
MODE
SDA
Clock
Gen
PLL
FIFO
PCLK
SDA
SCL
ID[x]
DS90UB904Q - DESERIALIZER
DS90UB903Q - SERIALIZER
Figure 2. Block Diagram
DS90UB903Q
Serializer
Graphics
Controller
--Video
Processor
DS90UB904Q
Deserializer
FPD-Link III
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
PLL
PDB
MODE
Config.
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
Config.
PDB
MODE
BISTEN
GPI[3:0]
Timing
Controller
LCD
Display
--Touch Panel
GPO[3:0]
PC
SDA
SCL
2
I C
2
I C
SDA
SCL
PC
Figure 3. Application Block Diagram
2
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SNLS332E – JUNE 2010 – REVISED APRIL 2013
VDDIO
31
DIN[8]
32
DIN[9]
33
VDDD
34
DIN[7]
DIN[6]
DIN[5]
DIN[4]
DIN[3]
DIN[2]
DIN[1]
DIN[0]
GPO[3]
GPO[2]
30
29
28
27
26
25
24
23
22
21
DS90UB903Q Pin Diagram
DAP = GND
DS9UB903Q
Serializer
40-Pin WQFN
(Top View)
20
GPO[1]
19
GPO[0]
18
VDDCML
17
DOUT+
16
DOUT-
15
VDDT
11
RES
RES
DIN[16]
10
40
9
DIN[15]
ID[x]
MODE
8
12
SDA
39
7
DIN[14]
SCL
PDB
6
13
PCLK
38
5
DIN[13]
DIN[20]
VDDPLL
4
14
DIN[19]
37
3
DIN[12]
DIN[18]
36
2
DIN[11]
DIN[17]
35
1
DIN[10]
Serializer - DS90UB903Q
40 Pin WQFN (Top View)
See Package Number RTA0040A
DS90UB903Q SERIALIZER PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
DIN[20:0]
PCLK
5, 4, 3, 2, 1,
40, 39, 38, 37,
36, 35, 33, 32,
30, 29, 28, 27,
26, 25, 24, 23
6
Inputs,
LVCMOS
w/ pull down
Parallel data inputs.
Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.
w/ pull down
GENERAL PURPOSE OUTPUT (GPO)
GPO[3:0]
22, 21, 20, 19
Output,
LVCMOS
General-purpose output pins can be used to control and respond to various
commands.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
SCL
7
Input/Output,
Open Drain
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA
8
Input/Output,
Open Drain
Data line for the bidirectional control bus communication
SDA requires an external pull-up resistor to VDDIO.
MODE
12
ID[x]
9
I2C Mode select
MODE = L, Master mode (default); Device generates and drives the SCL clock line.
Device is connected to slave peripheral on the bus. (Serializer initially starts up in
Input, LVCMOS
Standby mode and is enabled through remote wakeup by Deserializer)
w/ pull down
MODE = H, Slave mode; Device accepts SCL clock input and attached to an I2C
controller master on the bus. Slave mode does not generate the SCL clock, but uses
the clock generated by the Master for the data transfers.
Input, analog
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 3
CONTROL AND CONFIGURATION
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Product Folder Links: DS90UB903Q DS90UB904Q
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DS90UB903Q SERIALIZER PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
PDB
13
RES
10, 11
I/O, Type
Description
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
Input, LVCMOS
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,
w/ pull down
the PLL is shutdown, and IDD is minimized. Programmed control register data are
NOT retained and reset to default values
Input, LVCMOS Reserved.
w/ pull down
This pin MUST be tied LOW.
FPD-LINK III INTERFACE
Input/Output,
CML
Non-inverting differential output, bidirectional control channel input. The interconnect
must be AC Coupled with a 100 nF capacitor.
16
Input/Output,
CML
Inverting differential output, bidirectional control channel input. The interconnect must
be AC Coupled with a 100 nF capacitor.
VDDPLL
14
Power, Analog
PLL Power, 1.8V ±5%
VDDT
15
Power, Analog
Tx Analog Power, 1.8V ±5%
VDDCML
18
Power, Analog
CML & Bidirectional Channel Driver Power, 1.8V ±5%
VDDD
34
Power, Digital
Digital Power, 1.8V ±5%
Power, Digital
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO.
VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
16 vias.
DOUT+
17
DOUTPOWER AND GROUND
VDDIO
VSS
4
31
DAP
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SNLS332E – JUNE 2010 – REVISED APRIL 2013
PASS
37
GPI[3]
VDDIO1
ROUT[0]
ROUT[1]
ROUT[2]
ROUT[3]
31
30
29
28
27
26
25
33
GPI[1]
GPI[0]
34
GPI[2]
LOCK
35
32
VDDR
PDB
36
DS90UB904Q Pin Diagram
DAP = GND
24
ROUT[4]
RES/CMLOUTP
38
23
ROUT[5]
RES/CMLOUTN
39
22
ROUT[6]
VDDCML
40
21
ROUT[7]
RIN+
41
20
VDDIO2
RIN-
42
19
ROUT[8]
DS90UB904Q
Deserializer
48-Pin WQFN
(Top View)
8
9
10
11
12
ROUT[16]
ROUT[15]
ROUT[14]
ROUT[13]
ROUT[17]
13
ROUT[18]
48
7
ROUT[12]
6
14
VDDIO3
47
ID[x]
5
MODE
ROUT[19]
ROUT[11]
ROUT[20]
ROUT[10]
15
4
16
46
3
45
RES
PCLK
VDDPLL
VDDSSCG
VDDD
2
ROUT[9]
17
1
18
44
SCL
43
SDA
RES
BISTEN
Deserializer - DS90UB904Q
48 Pin WQFN (Top View)
See Package Number RHS0048A
DS90UB904Q DESERIALIZER PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[20:0]
PCLK
5, 6, 8, 9, 10,
11, 12, 13, 14,
15, 16, 18, 19,
21, 22, 23, 24,
25, 26, 27, 28
4
Outputs,
LVCMOS
Parallel data outputs.
Output,
LVCMOS
Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
GENERAL PURPOSE INPUT (GPI)
GPI[3:0]
30, 31, 32, 33
Input, LVCMOS
General-purpose input pins can be used to control and respond to various
commands.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
SCL
2
Input/Output,
Open Drain
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA
1
Input/Output,
Open Drain
Data line for bidirectional control bus communication
SDA requires an external pull-up resistor to VDDIO.
MODE
47
ID[x]
48
I2C Mode select
MODE = L, Master mode; Device generates and drives the SCL clock line, where
Input, LVCMOS required such as Read. Device is connected to slave peripheral on the bus.
w/ pull up
MODE = H, Slave mode (default); Device accepts SCL clock input and attached to an
I2C controller master on the bus. Slave mode does not generate the SCL clock, but
uses the clock generated by the Master for the data transfers.
Input, analog
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 4.
CONTROL AND CONFIGURATION
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Product Folder Links: DS90UB903Q DS90UB904Q
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DS90UB904Q DESERIALIZER PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
PDB
35
LOCK
34
RES
I/O, Type
Description
Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
Input, LVCMOS
PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power
w/ pull down
Down. Programmed control register data are NOT retained and reset to default
values.
Output,
LVCMOS
38, 39, 43, 46
-
LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as Link Status.
Reserved.
Pins 38, 39: Route to test point or leave open if unused. See also FPD-LINK III
INTERFACE pin description section.
Pin 46: This pin MUST be tied LOW.
Pin 43: Leave pin open.
BIST MODE
BISTEN
44
PASS
37
BIST Enable Pin.
Input, LVCMOS
BISTEN = H, BIST Mode is enabled.
w/ pull down
BISTEN = L, BIST Mode is disabled.
Output,
LVCOMS
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
FPD-LINK III INTERFACE
RIN+
41
Input/Output,
CML
Non-inverting differential input, bidirectional control channel output. The interconnect
must be AC Coupled with a 100 nF capacitor.
RIN-
42
Input/Output,
CML
Inverting differential input, bidirectional control channel output. The interconnect must
be AC Coupled with a 100 nF capacitor.
CMLOUTP
38
Output, CML
Non-inverting CML Output
Monitor point for equalized differential signal. Test port is enabled via control
registers.
CMLOUTN
39
Output, CML
Inverting CML Output
Monitor point for equalized differential signal. Test port is enabled via control
registers.
VDDSSCG
3
Power, Digital
SSCG Power, 1.8V ±5%
Power supply must be connected regardless if SSCG function is in operation.
VDDIO1/2/3
29, 20, 7
Power, Digital
LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered
from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
POWER AND GROUND
VDDD
17
Power, Digital
Digital Core Power, 1.8V ±5%
VDDR
36
Power, Analog
Rx Analog Power, 1.8V ±5%
VDDCML
40
Power, Analog
Bidirectional Channel Driver Power, 1.8V ±5%
VDDPLL
45
Power, Analog
PLL Power, 1.8V ±5%
DAP
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
16 vias.
VSS
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6
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SNLS332E – JUNE 2010 – REVISED APRIL 2013
Absolute Maximum Ratings (1) (2) (3)
−0.3V to +2.5V
Supply Voltage – VDDn (1.8V)
−0.3V to +4.0V
Supply Voltage – VDDIO
−0.3V to + (VDDIO + 0.3V)
LVCMOS Input Voltage I/O Voltage
−0.3V to +(VDD + 0.3V)
CML Driver I/O Voltage (VDD)
−0.3V to (VDD + 0.3V)
CML Receiver I/O Voltage (VDD)
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Maximum Package Power Dissipation Capacity
1/θJA °C/W above +25°
Package Derating
θJA(based on 16 thermal vias)
40 Lead WQFN
48 Lead WQFN
30.7 °C/W
θJC(based on 16 thermal vias)
6.8 °C/W
θJA(based on 16 thermal vias)
26.9 °C/W
θJC(based on 16 thermal vias)
4.4 °C/W
ESD Rating (IEC 61000-4-2)
RD = 330Ω, CS = 150pF
≥±25 kV
Air Discharge (DOUT+, DOUT-, RIN+, RIN-)
≥±10 kV
Contact Discharge (DOUT+, DOUT-, RIN+, RIN-)
ESD Rating (ISO10605)
RD = 330Ω, CS = 150/330pF
ESD Rating (ISO10605)
RD = 2KΩ, CS = 150/330pF
Air Discharge (DOUT+, DOUT-, RIN+, RIN-)
≥±15 kV
Contact Discharge (DOUT+, DOUT-, RIN+, RIN-)
≥±10 kV
≥±8 kV
ESD Rating (HBM)
≥±1 kV
ESD Rating (CDM)
≥±250 V
ESD Rating (MM)
(1)
(2)
(3)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions.
For soldering specifications: see product folder at www.ti.com
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Recommended Operating Conditions (1)
Min
Nom
Max
Units
Supply Voltage (VDDn)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO)
OR
1.71
1.8
1.89
V
3.0
3.3
LVCMOS Supply Voltage (VDDIO)
Supply Noise
3.6
V
VDDn (1.8V)
25
mVp-p
VDDIO (1.8V)
25
mVp-p
VDDIO (3.3V)
50
mVp-p
+105
°C
43
MHz
Operating Free Air Temperature (TA)
-40
PCLK Clock Frequency
10
(1)
+25
Supply noise testing was done with minimum capacitors (as shown on Figure 37 and Figure 38) on the PCB. A sinusoidal signal is AC
coupled to the VDDn (1.8V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the
Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on the
other hand shows no error when the noise frequency is less than 750 kHz.
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Electrical Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input
Voltage
VIN = 3.0V to 3.6V
2.0
VIN
V
VIL
Low Level Input
Voltage
VIN = 3.0V to 3.6V
GND
0.8
V
IIN
Input Current
VIN = 0V or 3.6V, VIN = 3.0V to 3.6V
-20
+20
µA
VOH
High Level Output
Voltage
VDDIO = 3.0V to 3.6V, IOH = −4 mA
2.4
VDDIO
V
VOL
Low Level Output
Voltage
VDDIO = 3.0V to 3.6V, IOL = +4 mA
GND
0.4
V
IOS
IOZ
Output Short Circuit
Current
VOUT = 0V
TRI-STATE Output
Current
PDB = 0V,
VOUT = 0V or VDD
±1
Serializer GPO
Outputs
-24
Deserializer LVCMOS
Outputs
-39
LVCMOS Outputs
mA
-20
±1
+20
µA
LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input
Voltage
VIN = 1.71V to 1.89V
0.65 VIN
VIN +0.3
VIL
Low Level Input
Voltage
VIN = 1.71V to 1.89V
GND
0.35 VIN
IIN
Input Current
VIN = 0V or 1.89V, VIN = 1.71V to 1.89V
VOH
High Level Output
Voltage
VDDIO = 1.71V to 1.89V, IOH = −4 mA
VOL
Low Level Output
Voltage
VDDIO = 1.71V to 1.89V
IOL = +4 mA
V
IOS
IOZ
Output Short Circuit
Current
VOUT = 0V
TRI-STATE Output
Current
PDB = 0V,
VOUT = 0V or VDD
Deserializer LVCMOS
Outputs
-20
±1
+20
µA
VDDIO 0.45
VDDIO
V
GND
0.45
V
Serializer GPO
Outputs
-11
Deserializer LVCMOS
Outputs
-20
LVCMOS Outputs
mA
-20
±1
+20
µA
268
340
412
mV
1
50
mV
VDD - VOD
VDD (MAX) VOD (MIN)
V
1
50
mV
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
|VOD|
Output Differential
Voltage
RT = 100Ω (Figure 8)
ΔVOD
Output Differential
Voltage Unbalance
RL = 100Ω
VOS
Output Differential
Offset Voltage
RL = 100Ω (Figure 8)
ΔVOS
Offset Voltage
Unbalance
RL = 100Ω
IOS
Output Short Circuit
Current
DOUT+/- = 0V
RT
Differential Internal
Termination
Resistance
Differential across DOUT+ and DOUT-
VDD (MIN) VOD (MAX)
-27
80
100
mA
120
Ω
CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)
(1)
(2)
(3)
8
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
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Electrical Characteristics(1)(2)(3)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Differential Threshold
High Voltage
VTH
Conditions
Min
Typ
Max
Units
+90
(Figure 10)
mV
VTL
Differential Threshold
Low Voltage
VIN
Differential Input
Voltage Range
RIN+ - RIN-
180
IIN
Input Current
VIN = VDD or 0V, VDD = 1.89V
-20
±1
+20
µA
RT
Differential Internal
Termination
Resistance
Differential across RIN+ and RIN-
80
100
120
Ω
62
90
-90
mV
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD
IDDT
RT = 100Ω
Serializer (Tx)
WORST CASE pattern
VDDn Supply Current (Figure 5)
(includes load
RT = 100Ω
current)
RANDOM PRBS-7 pattern
VDDn = 1.89V
PCLK = 43 MHz
Default Registers
IDDIOT
Serializer (Tx)
RT = 100Ω
VDDIO Supply
WORST CASE pattern
Current (includes load
(Figure 5)
current)
IDDTZ
IDDIOTZ
IDDR
Serializer (Tx) Supply PDB = 0V; All other
Current Power-down LVCMOS Inputs = 0V
VDDn = 1.89V, CL = 8 pF
Deserializer (Rx)
WORST CASE Pattern
VDDn Supply Current (Figure 5)
(includes load
VDDn = 1.89V, CL = 8 pF
current)
RANDOM PRBS-7 Pattern
IDDIOR
IDDRZ
IDDIORZ
VDDIO = 1.89V, CL = 8 pF
Deserializer (Rx)
WORST CASE Pattern
VDDIO Supply
(Figure 5)
Current (includes load
VDDIO = 3.6V, CL = 8 pF
current)
WORST CASE Pattern
Deserializer (Rx)
Supply Current
Power-down
PDB = 0V; All other
LVCMOS Inputs = 0V
mA
55
VDDIO = 1.89V
PCLK = 43 MHz
Default Registers
2
VDDIO = 3.6V
PCLK = 43 MHz
Default Registers
7
15
VDDn = 1.89V
370
775
VDDIO = 1.89V
55
125
VDDIO = 3.6V
65
135
PCLK = 43 MHz
SSCG[3:0] = ON
Default Registers
60
96
PCLK = 43 MHz
Default Registers
53
PCLK = 43 MHz
Default Registers
21
32
PCLK = 43 MHz
Default Registers
49
83
VDDn = 1.89V
42
400
VDDIO = 1.89V
8
40
VDDIO = 3.6V
350
800
5
mA
µA
mA
µA
Recommended Serializer Timing for PCLK (1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Min
Typ
Max
Units
tTCP
Symbol
Transmit Clock Period
23.3
T
100
ns
tTCIH
Transmit Clock Input High
Time
0.4T
0.5T
0.6T
ns
tTCIL
Transmit Clock Input Low
Time
0.4T
0.5T
0.6T
ns
tCLKT
PCLK Input Transition Time
(Figure 11)
3
ns
fOSC
Internal oscillator clock
source
(1)
Parameter
Conditions
10 MHz – 43 MHz
0.5
25
MHz
Recommended Input Timing Requirements are input specifications and not tested in production.
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Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tLHT
CML Low-to-High Transition
Time
RL = 100Ω (Figure 6)
150
330
ps
tHLT
CML High-to-Low Transition
Time
RL = 100Ω (Figure 6)
150
330
ps
tDIS
Data Input Setup to PCLK
tDIH
Data Input Hold from PCLK
tPLD
Serializer PLL Lock Time
RL = 100Ω (1) (2)
Serializer Delay
RT = 100Ω, PCLK = 10–43 MHz
Register 0x03h b[0] (TRFB = 1)
(Figure 14)
Serializer Output
Deterministic Jitter
Serializer output intrinsic deterministic
jitter . Measured (cycle-cycle) with
PRBS-7 test pattern
PCLK = 43 MHz (3) (4)
0.13
UI
Serializer Output Random
Jitter
Serializer output intrinsic random jitter
(cycle-cycle). Alternating-1,0 pattern.
PCLK = 43 MHz (3) (4)
0.04
UI
Peak-to-peak Serializer
Output Jitter
Serializer output peak-to-peak jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measured (cycle-cycle) with
PRBS-7 test pattern.
PCLK = 43 MHz (3) (4)
0.396
UI
λSTXBW
Serializer Jitter Transfer
Function -3 dB Bandwidth
PCLK = 43 MHz, Default Registers
(Figure 20) (3)
1.90
MHz
δSTX
Serializer Jitter Transfer
Function (Peaking)
PCLK = 43 MHz, Default Registers
(Figure 20) (3)
0.944
dB
δSTXf
Serializer Jitter Transfer
Function (Peaking
Frequency)
PCLK = 43 MHz, Default Registers
(Figure 20) (3)
500
kHz
tSD
tJIND
tJINR
tJINT
(1)
(2)
(3)
(4)
Serializer Data Inputs (Figure 12)
2.0
ns
2.0
ns
6.386T
+5
1
2
ms
6.386T
+ 12
6.386T
+ 19.7
ns
tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
Specification is ensured by design.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Min
Typ
Max
Units
tRCP
Symbol
Receiver Output Clock Period
tRCP = tTCP
PCLK
23.3
T
100
ns
tPDC
PCLK Duty Cycle
Default Registers
SSCG[3:0] = OFF
PCLK
45
50
55
%
tCLH
LVCMOS Low-to-High Transition
Time
1.3
2.0
2.8
1.3
2.0
2.8
1.6
2.4
3.3
1.6
2.4
3.3
0.38T
0.5T
0.38T
0.5T
tCHL
Parameter
Conditions
LVCMOS High-to-Low Transition
Time
LVCMOS Low-to-High Transition
Time
tCLH
tCHL
LVCMOS High-to-Low Transition
Time
tROS
ROUT Setup Data to PCLK
tROH
(1)
10
ROUT Hold Data to PCLK
Pin/Freq.
VDDIO: 1.71V to 1.89V or
3.0 to 3.6V,
CL = 8 pF (lumped load)
Default Registers
(Figure 16) (1)
PCLK
VDDIO: 1.71V to 1.89V or
3.0 to 3.6V,
CL = 8 pF (lumped load)
Default Registers
(Figure 16) (1)
Deserializer ROUTn
Data Outputs
VDDIO: 1.71V to 1.89V or
3.0V to 3.6V,
CL = 8 pF (lumped load)
Default Registers
Deserializer ROUTn
Data Outputs
ns
ns
ns
Specification is ensured by characterization and is not tested in production.
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SNLS332E – JUNE 2010 – REVISED APRIL 2013
Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
4.571T
+8
4.571T
+ 12
4.571T
+ 16
ns
10
ms
tDD
Deserializer Delay
Default Registers
Register 0x03h b[0]
(RRFB = 1) (Figure 17)
10 MHz–43 MHz
tDDLT
Deserializer Data Lock Time
(Figure 15) (2)
10 MHz–43 MHz
tRJIT
Receiver Input Jitter Tolerance
(Figure 19,
Figure 21) (3) (4)
43 MHz
0.53
Receiver Clock Jitter
PCLK
SSCG[3:0] = OFF (1) (5)
10 MHz
300
550
43 MHz
120
250
Deserializer Period Jitter
PCLK
SSCG[3:0] = OFF (1) (6)
10 MHz
425
600
43 MHz
320
480
Deserializer Cycle-to-Cycle Clock
Jitter
PCLK
SSCG[3:0] = OFF (1) (7)
10 MHz
320
500
43 MHz
300
500
LVCMOS Output Bus
SSC[3:0] = ON
(Figure 22)
20 MHz–43 MHz
±0.5% to
±2.0%
%
20 MHz–43 MHz
9 kHz to
66 kHz
kHz
tRCJ
tDPJ
tDCCJ
fdev
Spread Spectrum Clocking
Deviation Frequency
fmod
Spread Spectrum Clocking
Modulation Frequency
(2)
(3)
(4)
(5)
(6)
(7)
UI
ps
ps
ps
tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
tDCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
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Bidirectional Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant
Over recommended supply and temperature ranges unless otherwise specified. See Figure 4.
Symbol
Parameter
Conditions
RECOMMENDED INPUT TIMING REQUIREMENTS
Min
Typ
Max
Units
100
kHz
(1)
fSCL
SCL Clock Frequency
>0
tLOW
SCL Low Period
4.7
µs
tHIGH
SCL High Period
4.0
µs
tHD:STA
Hold time for a start or a repeated start
condition
4.0
µs
tSU:STA
Set Up time for a start or a repeated
start condition
4.7
µs
tHD:DAT
Data Hold Time
tSU:DAT
Data Set Up Time
250
ns
tSU:STO
Set Up Time for STOP Condition
4.0
µs
tr
SCL & SDA Rise Time
1000
tf
SCL & SDA Fall Time
300
ns
Cb
Capacitive load for bus
400
pF
fSCL = 100 kHz
0
3.45
µs
ns
SWITCHING CHARACTERISTICS (2)
fSCL
SCL Clock Frequency
tLOW
Serializer MODE = 0 – R/W
Register 0x05 = 0x40'h
100
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
100
kHz
Serializer MODE = 0 – R/W
Register 0x05 = 0x40'h
SCL Low Period
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Serializer MODE = 0 – R/W
Register 0x05 = 0x40'h
4.7
µs
4.0
µs
tHIGH
SCL High Period
tHD:STA
Hold time for a start or a repeated start
condition
Serializer MODE = 0
Register 0x05 = 0x40'h
4.0
µs
tSU:STA
Set Up time for a start or a repeated
start condition
Serializer MODE = 0
Register 0x05 = 0x40'h
4.7
µs
tHD:DAT
Data Hold Time
tSU:DAT
Data Set Up Time
tSU:STO
Set Up Time for STOP Condition
tf
SCL & SDA Fall Time
tBUF
Bus free time between a stop and start
condition
tTIMEOUT
NACK Time out
(1)
(2)
12
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
0
Serializer MODE = 0
3.45
250
ns
4.0
µs
300
Serializer MODE = 0
µs
4.7
ns
µs
Serializer MODE = 1
1
Deserializer MODE = 1
Register 0x06 b[2:0]=111'b
25
ms
Recommended Input Timing Requirements are input specifications and not tested in production.
Specification is ensured by design.
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SNLS332E – JUNE 2010 – REVISED APRIL 2013
SDA
tf
tHD;STA
tLOW
tBUF
tr
tf
tr
SCL
tSU;STA
tHD;STA
tHIGH
tSU;STO
tSU;DAT
tHD;DAT
START
STOP
REPEATED
START
START
Figure 4. Bidirectional Control Bus Timing
Bidirectional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
Over recommended supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Max
Units
SDA and SCL
0.7 x
VDDIO
VDDIO
V
Input Low Level Voltage
SDA and SCL
GND
0.3 x
VDDIO
V
VHY
Input Hysteresis
SDA and SCL
IOZ
TRI-STATE Output Current
PDB = 0V, VOUT = 0V or VDD
-20
±1
+20
µA
IIN
Input Current
SDA or SCL, Vin = VDDIO or GND
-20
±1
+20
µA
CIN
Input Pin Capacitance
VIH
Input High Level
VIL
Conditions
Min
Typ
>50
mV
<5
VOL
Low Level Output Voltage
pF
SCL and SDA, VDDIO = 3.0V
IOL = 1.5 mA
0.36
V
SCL and SDA, VDDIO = 1.71V
IOL = 1 mA
0.36
V
AC Timing Diagrams and Test Circuits
Device Pin Name
Signal Pattern
T
PCLK
(RFB = H)
DIN/ROUT
Figure 5. “Worst Case” Test Pattern
Vdiff
80%
80%
20%
Vdiff = 0V
20%
tLHT
tHLT
Vdiff = (DOUT+) - (DOUT-)
Figure 6. Serializer CML Output Load and Transition Times
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100 nF
DOUT+
50:
ZDiff = 100:
SCOPE
BW 8 4.0 GHz
100:
50:
DOUT-
100 nF
21
DIN
PARALLEL-TO-SERIAL
Figure 7. Serializer CML Output Load and Transition Times
DOUT+
RL
DOUT-
PCLK
Figure 8. Serializer VOD DC Diagram
DOUT-
Single Ended
V
V
OD
V
OD+
ODV
DOUT+
|
OS
0V
Differential
V
OD+
0V
(DOUT+)-(DOUT-)
V
OD-
Figure 9. Serializer VOD DC Diagram
RIN+
RIN+
VTH
VCM
VID
VTL
VIN
VID
VIN
RIN-
RIN-
GND
Figure 10. Differential VTH/VTL Definition Diagram
80%
VDD
80%
PCLK
20%
20%
0V
tCLKT
tCLKT
Figure 11. Serializer Input Clock Transition Times
14
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SNLS332E – JUNE 2010 – REVISED APRIL 2013
tTCP
PCLK
VDDIO/2
tDIS
VDDIO/2
VDDIO/2
tDIH
VDDIO
DINn VDDIO/2
Setup
Hold
VDDIO/2
0V
Figure 12. Serializer Setup/Hold Times
PDB
VDDIO/2
PCLK
tPLD
TRI-STATE
DOUT±
TRI-STATE
Output Active
SYMBOL N+2
| |
SYMBOL N+1
| |
SYMBOL N
| |
DIN
| |
Figure 13. Serializer Data Lock Time
SYMBOL N+3
tSD
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
| |
| |
| |
SYMBOL N
0V
| |
SYMBOL N-4
| |
|
|
|
DOUT+-
|
PCLK
VDDIO/2
Figure 14. Serializer Delay
PDB
VDDIO/2
| |
tDDLT
RIN±
LOCK
TRI-STATE
|
VDDIO/2
Figure 15. Deserializer Data Lock Time
80%
80%
Deserializer
8 pF
lumped
20%
20%
tCLH
tCHL
Figure 16. Deserializer LVCMOS Output Load and Transition Times
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DS90UB903Q, DS90UB904Q
SYMBOL N + 3
SYMBOL N + 3
| |
SYMBOL N + 2
| |
0V
| |
SYMBOL N + 1
| |
SYMBOL N
RIN±
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| |
SNLS332E – JUNE 2010 – REVISED APRIL 2013
tDD
PCLK
SYMBOL N - 1
| ||
SYMBOL N - 2
| ||
SYMBOL N - 3
| ||
| ||
| ||
ROUTn
VDDIO/2
SYMBOL N
SYMBOL N+1
Figure 17. Deserializer Delay
tRCP
PCLK
VDDIO
1/2 VDDIO
1/2 VDDIO
0V
VDDIO
ROUT[n],
VS, HS
1/2 VDDIO
1/2 VDDIO
0V
tROS
tROH
Figure 18. Deserializer Output Setup/Hold Times
Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
RxIN_TOL
Left
VTH
0V
VTL
RxIN_TOL
Right
Ideal Center Position (tBIT/2)
tBIT (1 UI)
tRJIT = RxIN_TOL (Left + Right)
Sampling Window = 1 UI
- tRJIT
Figure 19. Receiver Input Jitter Tolerance
2
JITTER TRANSFER (dB)
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
1.0E+04
1.0E+05
1.0E+06
1.0E+07
MODULATION FREQUENCY (Hz)
Figure 20. Typical Serializer Jitter Transfer Function Curve at 43 MHz
16
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SNLS332E – JUNE 2010 – REVISED APRIL 2013
0.62
JITTER AMPLITUDE (UI)
0.61
0.60
0.59
0.58
0.57
0.56
0.55
0.54
0.53
0.52
1.0E+04
1.0E+05
1.0E+06
1.0E+07
JITTER FREQUENCY (Hz)
Figure 21. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz
Frequency
FPCLK+
fdev
fdev (max)
FPCLK
FPCLK-
fdev (min)
Time
1 / fmod
Figure 22. Spread Spectrum Clock Output Profile
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Table 1. DS90UB903Q Control Registers
Addr
(Hex)
0
Name
R/W
7:1
DEVICE ID
0
SER ID SEL
7:3
RESERVED
RW
Default
0xB0'h
0x00'h
Description
7-bit address of Serializer; 0x58'h
(1011_000X'b) default
0: Device ID is from ID[x]
1: Register I2C Device ID overrides ID[x]
Reserved
Standby mode control. Retains control register data.
Supported only when MODE = 0
0: Enabled. Low-current Standby mode with wake-up
capability. Suspends all clocks and functions.
1: Disabled. Standby and wake-up disabled
2
STANDBY
RW
0
1
DIGITAL
RESET0
RW
0
self clear
1: Resets the device to default register values. Does not
affect device I2C Bus or Device ID
0
DIGITAL RESET1
RW
0
self clear
1: Digital Reset, retains all register values
Reset
2
18
Field
I2C Device ID
1
3
Bits
Reserved
7:0
RESERVED
0x20'h
Reserved
Reserved
7:6
RESERVED
11'b
Reserved
VDDIO Control
5
VDDIO CONTOL
RW
1
Auto VDDIO detect
Allows manual setting of VDDIO by register.
0: Disable
1: Enable (auto detect mode)
VDDIO Mode
4
VDDIO MODE
RW
1
VDDIO voltage set
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
I2C Pass-Through
3
I2C PASSTHROUGH
RW
1
I2C Pass-Through
0: Disabled
1: Enabled
RESERVED
2
RESERVED
0
Reserved
PCLK_AUTO
1
PCLK_AUTO
1
Switch over to internal 25 MHz Oscillator clock in the
absence of PCLK
0: Disable
1: Enable
1
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
TRFB
0
4
RESERVED
7:0
5
2
I C Bus Rate
6
DES ID
TRFB
RW
RESERVED
2
7:0
I C BUS RATE
7:1
DES DEV ID
0
RESERVED
7:1
RW
SLAVE DEV ID
0x80'h
Reserved
RW
0x40'h
I2C SCL frequency is determined by the following:
fSCL = 6.25 MHz / Register value (in decimal)
0x40'h = ~100 kHz SCL (default)
Note: Register values <0x32'h are NOT supported.
RW
0xC0'h
Deserializer Device ID = 0x60'h
(1100_000X'b) default
Reserved
RW
0x00'h
Slave Device ID. Sets remote slave I2C address.
7
Slave ID
0
RESERVED
8
Reserved
7:0
RESERVED
0x00'h
Reserved
Reserved
9
Reserved
7:0
RESERVED
0x01'h
Reserved
A
Reserved
7:0
RESERVED
0x00'h
Reserved
B
Reserved
7:0
RESERVED
0x00'h
Reserved
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SNLS332E – JUNE 2010 – REVISED APRIL 2013
Table 1. DS90UB903Q Control Registers (continued)
Addr
(Hex)
Name
Bits
Field
Reserved
7:3
RESERVED
PCLK Detect
2
PCLK DETECT
C
R/W
R
Default
Description
0x00'h
Reserved
0
1: Valid PCLK detected
0: Valid PCLK not detected
0
Reserved
0
0: Cable link not detected
1: Cable link detected
Reserved
3
RESERVED
Cable Link Detect
Status
0
LINK DETECT
D
Reserved
7:0
RESERVED
0x11'h
Reserved
E
Reserved
7:0
RESERVED
0x01'h
Reserved
F
Reserved
7:0
RESERVED
0x03'h
Reserved
10
Reserved
7:0
RESERVED
0x03'h
Reserved
11
Reserved
7:0
RESERVED
0x03'h
Reserved
12
Reserved
7:0
RESERVED
0x03'h
Reserved
R
GPCR[7]
0: LOW
GPCR[6]
1: HIGH
GPCR[5]
13
General Purpose
Control Reg
7:0
GPCR[4]
GPCR[3]
RW
0x00'h
GPCR[2]
GPCR[1]
GPCR[0]
Table 2. DS90UB904Q Control Registers
Addr
(Hex)
0
1
Name
Bits
Field
7:1
DEVICE ID
0
DES ID SEL
7:3
RESERVED
R/W
Default
Description
RW
0xC0'h
7-bit address of Deserializer; 0x60h
(1100_000X) default
2
I C Device ID
0: Device ID is from ID[x]
1: Register I2C Device ID overrides ID[x]
0x00'h
Reserved
2
REM_WAKEUP
RW
0
Remote Wake-up Select
1: Enable
Generate remote wakeup signal automatically wake-up
the Serializer in Standby mode
0: Disable
Puts the Serializer in Standby mode
1
DIGITALRESET0
RW
0
self clear
1: Resets the device to default register values. Does not
affect device I2C Bus or Device ID
0
DIGITALRESET1
RW
0
self clear
1: Digital Reset, retains all register values
Reset
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Table 2. DS90UB904Q Control Registers (continued)
Addr
(Hex)
Name
Bits
Field
R/W
Default
RESERVED
7:6
RESERVED
Auto Clock
5
AUTO_CLOCK
RW
0
1: Output PCLK or Internal 25 MHz Oscillator clock
0: Only PCLK when valid PCLK present
OSS Select
4
OSS_SEL
RW
0
Output Sleep State Select
0: Outputs = TRI-STATE, when LOCK = L
1: Outputs = LOW , when LOCK = L
00'b
2
3
20
Reserved
SSCG Select
0000: Normal Operation, SSCG OFF (default)
0001: fmod (kHz) PCLK/2168, fdev ±0.50%
0010: fmod (kHz) PCLK/2168, fdev ±1.00%
0011: fmod (kHz) PCLK/2168, fdev ±1.50%
0100: fmod (kHz) PCLK/2168, fdev ±2.00%
0101: fmod (kHz) PCLK/1300, fdev ±0.50%
0110: fmod (kHz) PCLK/1300, fdev ±1.00%
0111: fmod (kHz) PCLK/1300, fdev ±1.50%
1000: fmod (kHz) PCLK/1300, fdev ±2.00%
1001: fmod (kHz) PCLK/868, fdev ±0.50%
1010: fmod (kHz) PCLK/868, fdev ±1.00%
1011: fmod (kHz) PCLK/868, fdev ±1.50%
1100: fmod (kHz) PCLK/868, fdev ±2.00%
1101: fmod (kHz) PCLK/650, fdev ±0.50%
1110: fmod (kHz) PCLK/650, fdev ±1.00%
1111: fmod (kHz) PCLK/650, fdev ±1.50%
SSCG
3:0
SSCG
RESERVED
7:6
RESERVED
VDDIO Control
5
VDDIO CONTROL
RW
1
Auto voltage control
0: Disable
1: Enable (auto detect mode)
VDDIO Mode
4
VDDIO MODE
RW
0
VDDIO voltage set
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
I2C Pass-Through
3
I2C PASSTHROUGH
RW
1
I2C Pass-Through Mode
0: Disabled
1: Enabled
Auto ACK
2
AUTO ACK
RW
0
0: Disable
1: Enable
RESERVED
1
RESERVED
0
Reserved
1
Pixel Clock Edge Select
0: Parallel Interface Data is strobed on the Falling Clock
Edge
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
RRFB
0
RRFB
4
EQ Control
7:0
EQ
5
RESERVED
7:0
RESERVED
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0000'b
Description
11'b
RW
RW
Reserved
0x00'h
EQ Gain
00'h = ~0.0 dB
01'h = ~4.5 dB
03'h = ~6.5 dB
07'h = ~7.5 dB
0F'h = ~8.0 dB
1F'h = ~11.0 dB
3F'h = ~12.5 dB
FF'h = ~14.0 dB
0x00'h
Reserved
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Table 2. DS90UB904Q Control Registers (continued)
Addr
(Hex)
Name
Bits
RESERVED
7
SCL Prescale
6
Remote NACK
Remote NACK
7
8
9
SER ID
ID[0] Index
ID[1] Index
A
ID[2] Index
B
ID[3] Index
C
ID[4] Index
D
ID[5] Index
E
ID[6] Index
F
ID[7] Index
10
ID[0] Match
11
ID[1] Match
12
ID[2] Match
13
14
ID[3] Match
ID[4] Match
6:4
3
Field
R/W
RESERVED
SCL_PRESCALE
REM_NACK_TIME
R
2:0
NACK_TIMEOUT
7:1
SER DEV ID
0
RESERVED
7:1
ID[0] INDEX
0
RESERVED
7:1
ID[1] INDEX
0
RESERVED
7:1
ID[2] INDEX
0
RESERVED
7:1
ID[3] INDEX
0
RESERVED
7:1
ID[4] INDEX
0
RESERVED
7:1
ID[5] INDEX
0
RESERVED
7:1
ID[6] INDEX
0
RESERVED
7:1
ID[7] INDEX
0
RESERVED
7:1
ID[0] MATCH
0
RESERVED
7:1
ID[1] MATCH
0
RESERVED
7:1
ID[2] MATCH
0
RESERVED
7:1
ID[3] MATCH
0
RESERVED
7:1
ID[4] MATCH
0
RESERVED
Default
0
RW
RW
000'b
1
RW
111'b
RW
0xB0'h
Description
Reserved
Prescales the SCL clock line when reading data byte
from a slave device (MODE = 0)
000 : ~100 kHz SCL (default)
001 : ~125 kHz SCL
101 : ~11 kHz SCL
110 : ~33 kHz SCL
111 : ~50 kHz SCL
Other values are NOT supported.
Remote NACK Timer Enable
In slave mode (MODE = 1) if bit is set the I2C core will
automatically timeout when no acknowledge condition
was detected.
1: Enable
0: Disable
Remote NACK Timeout.
000: 2.0 ms
001: 5.2 ms
010: 8.6 ms
011: 11.8 ms
100: 14.4 ms
101: 18.4 ms
110: 21.6 ms
111: 25.0 ms
Serializer Device ID = 0x58'h
(1011_000X'b) default
Reserved
RW
0x00'h
Target slave Device ID slv_id0 [7:1]
Reserved
RW
0x00'h
RW
0x00'h
RW
0x00'h
RW
0x00'h
RW
0x00'h
RW
0x00'h
RW
0x00'h
RW
0x00'h
RW
0x00'h
RW
0x00'h
RW
0x00'h
RW
0x00'h
Target slave Device ID slv_id1 [7:1]
Reserved
Target slave Device ID slv_id2 [7:1]
Reserved
Target slave Device ID slv_id3 [7:1]
Reserved
Target slave Device ID slv_id4 [7:1]
Reserved
Target slave Device ID slv_id5 [7:1]
Reserved
Target slave Device ID slv_id6 [7:1]
Reserved
Target slave Device ID slv_id7 [7:1]
Reserved
Alias to match Device ID slv_id0 [7:1]
Reserved
Alias to match Device ID slv_id1 [7:1]
Reserved
Alias to match Device ID slv_id2 [7:1]
Reserved
Alias to match Device ID slv_id3 [7:1]
Reserved
Alias to match Device ID slv_id4 [7:1]
Reserved
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Table 2. DS90UB904Q Control Registers (continued)
Addr
(Hex)
Name
15
ID[5] Match
16
ID[6] Match
Bits
7:1
ID[5] MATCH
0
RESERVED
7:1
ID[6] MATCH
0
RESERVED
7:1
ID[7] MATCH
0
RESERVED
R/W
Default
RW
0x00'h
RW
0x00'h
RW
0x00'h
Description
Alias to match Device ID slv_id5 [7:1]
Reserved
Alias to match Device ID slv_id6 [7:1]
Reserved
Alias to match Device ID slv_id [7:1]
17
ID[7] Match
18
RESERVED
7:0
RESERVED
0x00'h
Reserved
19
RESERVED
7:0
RESERVED
0x01'h
Reserved
1A
RESERVED
7:0
RESERVED
0x00'h
Reserved
1B
RESERVED
7:0
RESERVED
0x00'h
Reserved
RESERVED
7:3
RESERVED
0x00'h
Reserved
RESERVED
2
RESERVED
0
Reserved
Signal Detect
Status
1
R
0
0: Active signal not detected
1: Active signal detected
LOCK Pin Status
0
R
0
0: CDR/PLL Unlocked
1: CDR/PLL Locked
1D
Reserved
7:0
RESERVED
0x17'h
Reserved
1E
Reserved
7:0
RESERVED
0x07'h
Reserved
1F
Reserved
7:0
RESERVED
0x01'h
Reserved
20
Reserved
7:0
RESERVED
0x01'h
Reserved
21
Reserved
7:0
RESERVED
0x01'h
Reserved
22
Reserved
7:0
RESERVED
0x01'h
Reserved
RW
0x00'h
RW
0
R
0x00'h
00'b
1C
Reserved
23
General Purpose
Control Reg
7:0
GPCR[7]
GPCR[6]
GPCR[5]
GPCR[4]
GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0]
24
BIST
0
BIST_EN
25
BIST_ERR
7:0
BIST_ERR
26
Remote Wake
Enable
7:6
REM_WAKEUP_
EN
RW
5:0
RESERVED
RW
0
7:6
BCC
RW
00'b
5:0
RESERVED
0
Reserved
7:5
RESERVED
0
Reserved
1
1: Disabled (Default)
0: Enabled
0
Reserved
27
3F
BCC
CMLOUT Config
4
3:0
22
Field
CMLOUT P/N
Enable
RESERVED
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0: LOW
1: HIGH
RW
BIST Enable
0: Normal operation
1: Bist Enable
Bist Error Counter
11: Enable remote wake up mode
00: Normal operation mode
Other values are NOT supported
Reserved
11: Normal operation mode
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FUNCTIONAL DESCRIPTION
The DS90UB903Q/904Q FPD-Link III chipset is intended for video display applications. The Serializer/
Deserializer chipset operates from a 10 MHz to 43 MHz pixel clock frequency. The DS90UB903Q transforms a
21-bit wide parallel LVCMOS data bus along with a bidirectional control bus into a single high-speed differential
pair. The high-speed serial bit stream contains an embedded clock and DC-balance information which enhances
signal quality to support AC coupling. The DS90UB904Q receives the single serial data stream and converts it
back into a 21-bit wide parallel data bus together with the bidirectional control channel data bus.
The control channel function of the DS90UB903Q/904Q provides bidirectional communication between the host
processor and display. The integrated control channel transfers data simultaneously over the same differential
pair used for video data interface. This interface offers advantages over other chipsets by eliminating the need
for additional wires for programming and control. The control supports I2C port. The bidirectional control channel
offers asymmetrical communication and is not dependent on video blanking intervals.
DISPLAY APPLICATION
The DS90UB903Q/904Q chipset is intended for interface between a host (graphics processor) and a Display. It
supports a 21 bit parallel video bus for 18-bit color depth (RGB666) display format. In a RGB666 configuration,
18 color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported
across the serial link.
The DS90UB903Q Serializer accepts a 21-bit parallel data bus along with a bidirectional control bus. The parallel
data and bidirectional control channel information is converted into a single differential link. The integrated
bidirectional control channel bus supports I2C compatible operation for controlling auxiliary data transport to and
from host processor and display module. The DS90UB904Q Deserializer extracts the clock/control information
from the incoming data stream and reconstructs the 21-bit data with control channel data.
DS90UB903Q
Serializer
FPD-Link III
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
Graphics
Controller
--Video
Processor
PC
SDA
SCL
DS90UB904Q
Deserializer
2
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
2
I C
I C
SDA
SCL
Timing
Controller
LCD Display
-Touch Panel
PC
Figure 23. Typical Display System Diagram
SERIAL FRAME FORMAT
The DS90UB903Q/904Q chipset will transmit and receive a pixel of data in the following format:
I2C
CLK0
CLK1
Bit 0 to Bit 20
Figure 24. Serial Bitstream for 28-bit Symbol
The High Speed Forward Channel is a 28-bit symbol composed of 21 bits of data containing video data & control
information transmitted from Serializer to Deserializer. CLK1 and CLK0 represent the embedded clock in the
serial stream. CLK1 is always HIGH and CLK0 is always LOW. This data payload is optimized for signal
transmission over an AC coupled link. Data is randomized, balanced and scrambled.
The bidirectional control channel data is transferred along with the high-speed forward data over the same serial
link. This architecture provides a full duplex low speed forward channel across the serial link together with a high
speed forward channel without the dependence of the video blanking phase.
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DESCRIPTION OF BIDIRECTIONAL CONTROL BUS AND I2C MODES
The I2C compatible interface allows programming of the DS90UB903Q, DS90UB904Q, or an external remote
device (such as a display) through the bidirectional control channel. Register programming transactions to/from
the DS90UB903Q/904Q chipset are employed through the clock (SCL) and data (SDA) lines. These two signals
have open-drain I/Os and both lines must be pulled-up to VDDIO by external resistor. Figure 4 shows the timing
relationships of the clock (SCL) and data (SDA) signals. Pull-up resistors or current sources are required on the
SCL and SDA busses to pull them high when they are not being driven low. A logic zero is transmitted by driving
the output low. A logic high is transmitted by releasing the output and allowing it to be pulled-up externally. The
appropriate pull-up resistor values will depend upon the total bus capacitance and operating speed. The
DS90UB903Q/904Q I2C bus data rate supports up to 100 kbps according to I2C specification.
Bus Activity:
Master
SDA Line
Register
Address
Slave
Address
7-bit Address
S
Stop
Start
To start any data transfer, the DS90UB903Q/904Q must be configured in the proper I2C mode. Each device can
function as an I2C slave proxy or master proxy depending on the mode determined by MODE pin. The Ser/Des
interface acts as a virtual bridge between Master Controller Unit (MCU) and the remote device. When the MODE
pin is set to High, the device is treated as a slave proxy; acts as a slave on behalf of the remote slave. When
addressing a remote peripheral or Serializer/Deserializer (not wired directly to the MCU), the slave proxy will
forward any byte transactions sent by the Master controller to the target device. When MODE pin is set to Low,
the device will function as a master proxy device; acts as a master on behalf of the I2C master controller. Note
that the devices must have complementary settings for the MODE configuration. For example, if the Serializer
MODE pin is set to High then the Deserializer MODE pin must be set to Low and vice-versa.
Data
P
0
A
C
K
A
C
K
A
C
K
Bus Activity:
Slave
S
Register
Address
Slave
Address
7-bit Address
A
C
K
Bus Activity:
Slave
Slave
Address
S
0
N
A
C
K
7-bit Address
A
C
K
Stop
SDA Line
Start
Bus Activity:
Master
Start
Figure 25. Write Byte
P
1
A
C
K
Data
Figure 26. Read Byte
SDA
1
2
6
MSB
R/W
Direction
Bit
Acknowledge
from the Device
7-bit Slave Address
SCL
ACK
LSB
MSB
7
8
9
LSB
N/ACK
Data Byte
*Acknowledge
or Not-ACK
1
2
8
Repeated for the Lower Data Byte
and Additional Data Transfers
START
9
STOP
Figure 27. Basic Operation
24
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SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 28. START and STOP Conditions
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SLAVE CLOCK STRETCHING
In order to communicate and synchronize with remote devices on the I2C bus through the bidirectional control
channel, slave clock stretching must be supported by the I2C master controller/MCU. The chipset utilizes bus
clock stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line low
prior to the 9th clock of every I2C data transfer (before the ACK signal). The slave device will not control the
clock and only stretches it until the remote peripheral has responded.
Any remote access involves the clock stretching period following the transmitted byte, prior to completion of the
acknowledge bit. Since each byte transferred to the I2C slave must be acknowledged separately, the clock
stretching will be done for each byte sent by the host controller. For remote accesses, the “Response Delay”
shown is on the order of 12 µs (typical). See Application Note AN-2173 (SNLA131) for more details.
ID[X] ADDRESS DECODER
The ID[x] pin is used to decode and set the physical slave address of the Serializer/Deserializer (I2C only) to
allow up to six devices on the bus using only a single pin. The pin sets one of six possible addresses for each
Serializer/Deserializer device. The pin must be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor and a
pull down resistor (RID) of the recommended value to set the physical device address. The recommended
maximum resistor tolerance is 0.1% worst case (0.2% total tolerance).
1.8V
10k
VDDIO
ID[x]
RPU
RPU
RID
HOST
SCL
SCL
SDA
SDA
SER
or
DES
To other
Devices
Figure 29. Bidirectional Control Bus Connection
Table 3. ID[x] Resistor Value – DS90UB903Q
ID[x] Resistor Value - DS90UB903Q Ser
(1)
26
Resistor RID Ω (±0.1%)
Address 7'b (1)
Address 8'b 0 appended (WRITE)
0, GND
7b' 101 1000 (h'58)
8b' 1011 0000 (h'B0)
2.0k
7b' 101 1001 (h'59)
8b' 1011 0010 (h'B2)
4.7k
7b' 101 1010 (h'5A)
8b' 1011 0100 (h'B4)
8.2k
7b' 101 1011 (h'5B)
8b' 1011 0110 (h'B6)
12.1k
7b' 101 1100 (h'5C)
8b' 1011 1000 (h'B8)
39.0k
7b' 101 1110 (h'5E)
8b' 1011 1100 (h'BC)
Specification is ensured by design.
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Table 4. ID[x] Resistor Value – DS90UB904Q
ID[x] Resistor Value - DS90UB904Q Des
(1)
Resistor RID Ω (±0.1%)
Address 7'b (1)
Address 8'b 0 appended (WRITE)
0, GND
7b' 110 0000 (h'60)
8b' 1100 0000 (h'C0)
2.0k
7b' 110 0001 (h'61)
8b' 1100 0010 (h'C2)
4.7k
7b' 110 0010 (h'62)
8b' 1100 0100 (h'C4)
8.2k
7b' 110 0011 (h'63)
8b' 1101 0110 (h'C6)
12.1k
7b' 110 0100 (h'64)
8b' 1101 1000 (h'C8)
39.0k
7b' 110 0110 (h'66)
8b' 1100 1100 (h'CC)
Specification is ensured by design.
CAMERA MODE OPERATION
In Camera mode, I2C transactions originate from the Deserializer from the Master controller (Figure 30). The I2C
slave core in the Deserializer will detect if a transaction is intended for the Serializer or a slave at the Serializer.
Commands are sent over the bidirectional control channel to initiate the transactions. The Serializer will receive
the command and generate an I2C transaction on its local I2C bus. At the same time, the Serializer will capture
the response on the I2C bus and return the response as a command on the forward channel link. The
Deserializer parses the response and passes the appropriate response to the Deserializer I2C bus.
To configure the devices for camera mode operation, set the Serializer MODE pin to Low and the Deserializer
MODE pin to High. Before initiating any I2C commands, the Deserializer needs to be programmed with the target
slave device addresses and Serializer device address. SER_DEV_ID Register 0x07h sets the Serializer device
address and SLAVE_x_MATCH/SLAVE_x_INDEX registers 0x08h~0x17h set the remote target slave addresses.
The slave address match registers must also be set. In slave mode the address register is compared with the
address byte sent by the I2C master. If the addresses are equal to any of registers values, the I2C slave will
acknowledge the transaction to the I2C master allowing reads or writes to target device.
DS90UB903Q
Serializer
CMOS
Image
Sensor
DS90UB904Q
Deserializer
DIN[20:0]
PCLK
ROUT[20:0]
PCLK
Host
-FPGA
-Video
Processor
µC
SDA
SCL
2
IC
2
IC
SDA
SCL
Figure 30. Typical Camera System Diagram
DISPLAY MODE OPERATION
In Display mode, I2C transactions originate from the controller attached to the Serializer. The I2C slave core in
the Serializer will detect if a transaction targets (local) registers within the Serialier or the (remote) registers within
the Deserializer or a remote slave connected to the I2C master interface of the Deserializer. Commands are sent
over the forward channel link to initiate the transactions. The Deserializer will receive the command and generate
an I2C transaction on its local I2C bus. At the same time, the Deserializer will capture the response on the I2C
bus and return the response as a command on the bidirectional control channel. The Serializer parses the
response and passes the appropriate response to the Serializer I2C bus.
The physical device ID of the I2C slave in the Serializer is determined by the analog voltage on the ID[x] input. It
can be reprogrammed by using the SER_DEV_ID register and setting the bit . The device ID of the logical I2C
slave in the Deserializer is determined by programming the DES ID in the Serializer. The state of the ID[x] input
on the Deserializer is used to set the device ID. The I2C transactions between Ser/Des will be bridged between
the host to the remote slave.
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To configure the devices for display mode operation, set the Serializer MODE pin to High and the Deserializer
MODE pin to Low. Before initiating any I2C commands, the Serializer needs to be programmed with the target
slave device address and Serializer device address. DES_DEV_ID Register 0x06h sets the Deserializer device
address and SLAVE_DEV_ID register 0x7h sets the remote target slave address. If the I2C slave address
matches any of registers values, the I2C slave will acknowledge the transaction allowing read or write to target
device. Note: In Display mode operation, registers 0x08h~0x17h on Deserializer must be reset to 0x00.
PROGRAMMABLE CONTROLLER
An integrated I2C slave controller is embedded in each of the DS90UB903Q Serializer and DS90UB904Q
Deserializer. It must be used to access and program the extra features embedded within the configuration
registers. Refer to Table 1 and Table 2 for details of control registers.
I2C PASS THROUGH
I2C pass-through provides an alternative means to independently address slave devices. The mode enables or
disables I2C bidirectional control channel communication to the remote I2C bus. This option is used to determine
whether or not an I2C instruction is to be transferred over to the remote I2C device. When enabled, the I2C bus
traffic will continue to pass through and will be received by I2C devices downstream. If disabled, I2C commands
will be excluded to the remote I2C device. The pass through function also provides access and communication to
only specific devices on the remote bus. The feature is effective for both Camera mode and Display mode.
SYNCHRONIZING MULTIPLE LINKS
For applications requiring synchronization across multiple links, it is recommended to utilize the General Purpose
Input/Output (GPI/GPO) pins to transmit control signals to synchronize slave peripherals together. To
synchronize the peripherals properly, the system controller needs to provide a sync signal output. Note this form
of synchronization timing relationship has a non-deterministic latency. After the control data is reconstructed from
the birectional control channel, there will be a time variation of the GPI/GPO signals arriving at the different target
devices (between the parallel links). The maximum latency delta (t1) of the GPI/GPO data transmitted across
multiple links is 25 us.
Note: The user must verify that the timing variations between the different links are within their system and timing
specifications.
The maximum time (t1) between the rising edge of GPI/GPO (i.e. sync signal) arriving at SER A and SER B is 25
us.
DES A
GPI[n] Input
SER B
GPO[n] Output
|
SER A
GPO[n] Output
|
DES B
GPI[n] Input
t1
Figure 31. GPI/GPO Delta Latency
GENERAL PURPOSE I/O (GPI/GPO)
The DS90UB903Q/904Q has up to 4 GPO and 4 GPI on the Serializer and Deserializer respectively. The
GPI/GPO maximum switching rate is up to 66 kHz for communication between Deserializer GPI to Serializer
GPO.
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AT-SPEED BIST (BISTEN, PASS)
An optional AT SPEED Built in Self Test (BIST) feature supports at speed testing of the high-speed serial and
the bidirectional control channel link. Control pins at the Deserializer are used to enable the BIST test mode and
allow the system to initiate the test and set the duration. A HIGH on PASS pin indicates that all payloads
received during the test were error free during the BIST duration test. A LOW on this pin at the conclusion of the
test indicates that one or more payloads were detected with errors.
The BIST duration is defined by the width of BISTEN. BIST starts when Deserializer LOCK goes HIGH and
BISTEN is set HIGH. BIST ends when BISTEN goes LOW. Any errors detected after the BIST Duration are not
included in PASS logic.
Note: AT-SPEED BIST is only available in the Camera mode and not the Display mode
The following diagram shows how to perform system AT SPEED BIST:
Serializer MODE = 0 and Deserializer MODE = 1
Apply power for Serializer and Deserializer
Normal
Step 1: Enable AT SPEED BIST by placing the
Deserializer in BIST by mode setting BISTEN = H
BIST Wait
Step 2: Deserializer will setup Serializer and enable BIST
mode through Bidirectional control channel
communication and then reacquire forward channel clock
Step 4: Place System in
Normal Operating Mode
BISTEN = L
BIST Start
Step 3: Stop AT SPEED BIST by turning off BIST
mode with BISTEN = L at the Deserializer.
BIST Stop
Figure 32. AT-SPEED BIST System Flow Diagram
Step 1: Place the Deserializer in BIST Mode.
Serializer and Deserializer power supply must be supplied. Enable the AT SPEED BIST mode on the
Deserializer by setting the BISTEN pin High. The 904 GPI[1:0] pins are used to select the PCLK frequency of the
on-chip oscillator for the BIST test on high speed data path.
Table 5. BIST Oscillator Frequency Select
Des GPI[1:0]
Oscillator Source
min (MHz)
typ (MHz)
00
External PCLK
10
01
Internal
10
Internal
25
11
Internal
12.5
max (MHz)
43
50
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The Deserializer GPI[1:0] set to 00 will bypass the on-chip oscillator and an external oscillator to Serializer PCLK
input is required. This allows the user to operate BIST under different frequencies other than the predefined
ranges.
Step 2: Enable AT SPEED BIST by placing the Serializer into BIST mode.
Deserializer will communicate through the bidirectional control channel to configure Serializer into BIST mode.
Once the BIST mode is set, the Serializer will initiate BIST transmission to the Deserializer.
Wait 10 ms for Deserializer to acquire lock and then monitor the LOCK pin transition from LOW to HIGH. At this
point, AT SPEED BIST is operational and the BIST process has begun. The Serializer will start transfer of an
internally generated PRBS data pattern through the high speed serial link. This pattern traverses across the
interconnecting link to the Deserializer. Check the status of the PASS pin; a HIGH indicates a pass, a LOW
indicates a fail. A fail will stay LOW for ½ a clock cycle. If two or more bits in the serial frame fail, the PASS pin
will toggle ½ clock cycle HIGH and ½ clock cycle low. The user can use the PASS pin to count the number of
fails on the high speed link. In addition, there is a defined SER and DES register that will keep track of the
accumulated error count. The Serializer 903 GPO[0] pin will be assigned as a PASS flag error indicator for the
bidirectional control channel link.
Recovered
Pixel Clock
Case 1: No bit errors
Start Pixel
BISTEN
Recovered
Pixel Data
PASS
Previous
³%,67´ 6WDWH
³%,67´ 6WDWH
Case 2: Bit error(s)
Recovered
Pixel Data
PASS
B
B
B
B
Previous
³%,67´ 6WDWH
³%,67´ 6WDWH
E
E
E
E
Case 3: Bit error(s) AFTER BIST
Duration
Recovered
Pixel Data
PASS
B
Previous
³%,67´ 6WDWH
B = Bad Pixel
PE = Payload Error
³%,67´ 6WDWH
BIST Duration
(when BISTEN=H)
BIST Status
(when BISTEN=L)
Figure 33. BIST Timing Diagram
Step 3: Stop at SPEED BIST by turning off BIST mode in the Deserializer to determine Pass/Fail.
To end BIST, the system must pull BISTEN pin of the Deserializer LOW. The BIST duration is fully defined by
the BISTEN width and Deserializer LOCK is HIGH; thus the Bit Error Rate is determined by how long the system
holds BISTEN HIGH.
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fpixel (MHz)
BIST Duration (s)
x Total Pixels Transmitted = Total Bits Transmitted
= BIST Duration (s) x
Pixel
1 Pixel period (ns) x Total Bits
Bit (Pixel) Error Rate
-1
= [Total Bits Transmitted]
(for passing BIST)
=
[Total Bits Transmitted x Bits/Pixel] -1
Figure 34. BIST BER Calculation
Step 4: Place system in Normal Operating Mode by disabling BIST at the Serializer.
Once Step 3 is complete, AT SPEED BIST is over and the Deserializer is out of BIST mode. To fully return to
Normal mode, apply Normal input data into the Serializer.
Any PASS result will remain unless it is changed by a new BIST session or cleared by asserting and releasing
PDB. The default state of PASS after a PDB toggle is HIGH.
It is important to note that AT SPEED BIST will only determine if there is an issue on the link that is not related to
the clock and data recovery of the link (whose status is flagged with LOCK pin).
LVCMOS VDDIO OPTION
1.8V or 3.3V SER Inputs and DES Outputs are user seletable to provide compatibility with 1.8V and 3.3V system
interfaces.
REMOTE WAKE UP (Camera Mode)
After initial power up, the Serializer is in a low-power Standby mode. The Deserializer (controlled by ECU/MCU)
'Remote Wake-up' register allows the Deserializer side to generate a signal across the link to remotely wake-up
the Serializer. Once the Serializer detects the wake-up signal Serializer switches from Standby mode to active
mode. In active mode, the Serializer locks onto PCLK input (if present), otherwise the on-chip oscillator is used
as the input clock source. Note the MCU controller should monitor the Deserializer LOCK pin and confirm LOCK
= H before performing any I2C communication across the link.
For Remote Wake-up to function properly:
• The chipset needs to be configured in Camera mode: Serializer MODE = 0 and Deserializer MODE = 1
• Serializer expects remote wake-up by default at power on.
• Configure the control channel driver of the Deserializer to be in remote wake-up mode by setting Deserializer
Register 0x26h = 0xC0h
• Perform remote wake-up on Serializer by setting Deserializer Register 0x01 b[2] = 1
• Return the control channel driver of the Deserializer to the normal operation mode by setting Deserializer
Register 0x26h = 0x00h
• Configure the control channel driver of the Deserializer to be in normal operation mode by setting Deserializer
Register 0x27h = 0xC0h.
Serializer can also be put into standby mode by programming the Deserializer remote wake-up control register
0x01 b[2] REM_WAKEUP to 0.
POWERDOWN
The SER has a PDB input pin to ENABLE or Powerdown the device. The modes can be controlled by the host
and is used to disable the Link to save power when the remote device is not operational. An auto mode is also
available. In this mode, the PDB pin is tied High and the SER switches over to an internal oscillator when the
PCLK stops or not present. When a PCLK starts again, the SER will then lock to the valid input PCLK and
transmits the data to the DES. In powerdown mode, the high-speed driver outputs are static (High).
The DES has a PDB input pin to ENABLE or Powerdown the device. This pin can be controlled by the system
and is used to disable the DES to save power. An auto mode is also available. In this mode, the PDB pin is tied
High and the DES will enter powerdown when the serial stream stops. When the serial stream starts up again,
the DES will lock to the input stream and assert the LOCK pin and output valid data. In powerdown mode, the
Data and PCLK outputs are set by the OSS_SEL control register.
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POWER UP REQUIREMENTS AND PDB PIN
It is required to delay and release the PDB input signal after VDD (VDDn and VDDIO) power supplies have
settled to the recommended operating voltages. A external RC network can be connected to the PDB pin to
ensure PDB arrives after all the VDD have stabilized.
SIGNAL QUALITY ENHANCERS
Des - Receiver Input Equalization (EQ)
The receiver inputs provided input equalization filter in order to compensate for loss from the media. The level of
equalization is controlled via register setting. Note this function can be observed at the CMLOUTP/N test port
enabled via the control registers.
EMI REDUCTION
Des - Receiver Staggered Output
The Receiver staggered outputs allows for outputs to switch in a random distribution of transitions within a
defined window. Outputs transitions are distributed randomly. This minimizes the number of outputs switching
simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall
EMI.
Des Spread Spectrum Clocking
The DS90UB904Q parallel data and clock outputs have programmable SSCG ranges from 9 kHz–66 kHz and
±0.5%–±2% from 20 MHz to 43 MHz. The modulation rate and modulation frequency variation of output spread is
controlled through the SSC control registers.
PIXEL CLOCK EDGE SELECT (TRFB/RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register
is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the
data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,
data is strobed on the Falling edge of the PCLK.
PCLK
DIN/
ROUT
TRFB/RRFB: 0
TRFB/RRFB: 1
Figure 35. Programmable PCLK Strobe Select
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APPLICATIONS INFORMATION
AC COUPLING
The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme.
External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in
Figure 36.
DOUT+
RIN+
DOUT-
RIN-
D
R
Figure 36. AC-Coupled Connection
For high-speed FPD-Link III transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 100
nF AC coupling capacitors to the line.
TYPICAL APPLICATION CONNECTION
Figure 37 shows a typical connection of the DS90UB903Q Serializer.
DS90UB903Q (SER)
VDDIO
VDDIO
C12
FB1
C8
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
LVCMOS
Parallel
Bus
DIN14
DIN15
DIN16
DIN17
DIN18
DIN19
DIN20
FB2
C10
C5
FB3
C11
C6
FB4
C7
FB5
MODE
PDB
GPO
Control
Interface
GPO[0]
GPO[1]
GPO[2]
GPO[3]
VDDD
C1
C2
1.8V
10 k:
ID[X]
RID
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C9 = 0.1 PF
C10 - C13 = 4.7 PF
C14 - C15 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB7: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
SCL
SDA
C14
Optional
C15
Serial
FPD-Link III
Interface
DOUT+
DOUT-
RPU
FB6
C13
VDDCML
VDDIO
RPU
C9
VDDPLL
PCLK
LVCMOS
Control
Interface
FB7
C4
C3
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
I2C
Bus
Interface
1.8V
VDDT
RES
DAP (GND)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Optional
Figure 37. DS90UB903Q Typical Connection Diagram — Pin Control
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Figure 38 shows a typical connection of the DS90UB904Q Deserializer.
DS90UB904Q (DES)
1.8V
VDDD
C13
C11
FB1
C3
FB2
C4
FB3
C5
C8
VDDR
C6
FB5
C16
C7
VDDCML
C1
Serial
FPD-Link III
Interface
RIN+
RINC2
TP_A
RES_PIN38
RES_PIN39
TP_B
LVCMOS
Control
Interface
MODE
PDB
I2C
Bus
Interface
C14
VDDIO2
VDDIO3
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
LVCMOS
Parallel
Bus
ROUT14
ROUT15
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
PCLK
GPI[0]
GPI[1]
GPI[2]
GPI[3]
VDDIO
RPU
C12
C10
VDDPLL
C15
FB6
C9
VDDSSCG
FB4
VDDIO
VDDIO1
RPU
GPI
Control
Interface
SCL
FB7
SDA
FB8
C17
LOCK
PASS
1.8V
C18
Optional
Optional
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C12 = 0.1 PF
C13 - C16 = 4.7 PF
C17 - C18 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB8: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
10 k:
ID[X]
RES_PIN46
DAP (GND)
RID
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 38. DS90UB904Q Typical Connection Diagram — Pin Control
TRANSMISSION MEDIA
The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and
signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment.
The interconnect for FPD-Link III interface should present a differential impedance of 100 Ohms. Use of cables
and connectors that have matched differential impedance will minimize impedance discontinuities. Shielded or
un-shielded cables may be used depending upon the noise environment and application requirements. The
chipset's optimum cable drive performance is achieved at 43 MHz at 10 meters length. The maximum signaling
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rate increases as the cable length decreases. Therefore, the chipset supports 50 MHz at shorter distances. Other
cable parameters that may limit the cable's performance boundaries are: cable attenuation, near-end crosstalk
and pair-to-pair skew. The maximum length of cable that can be used is dependant on the quality of the cable
(gauge, impedance), connector, board (discontinuities, power plane), the electrical environment (e.g. power
stability, ground noise, input clock jitter, PCLK frequency, etc.) and the application environment.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the CMLOUT P/N output. A differential probe should be used to measure across the
termination resistor at the CMLOUT P/N pins.
For obtaining optimal performance, we recommend:
• Use Shielded Twisted Pair (STP) cable
• 100Ω differential impedance and 24 AWG (or lower AWG) cable
• Low skew, impedance matched
• Ground and/or terminate unused conductors
70
1960
60
1680
50
1400
40
1120
30
840
DS90UB903Q/904Q
20
560
10
280
0
0
5
15
20
10
CABLE LENGTH (m)
MAX RAW SERIAL RATE (Mbps)
PCLK FREQUENCY (MHz)
Figure 39 shows the Typical Performance Characteristics demonstrating various lengths and data rates using
Rosenberger HSD and Leoni DACAR 538 Cable.
0
25
*Note: Equalization is enabled for cable lengths greater than 7 meters
Figure 39. Rosenberger HSD & Leoni DACAR 538 Cable Performance
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
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Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In
some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the
differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential
lines of 100 Ohms are typically recommended for differential interconnect. The closely coupled lines help to
ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled
lines will also radiate less.
Information on the WQFN style package is provided in Application Note: AN-1187 “Leadless Leadframe Package
(LLP) Application Report” (literature number SNOA401).
INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas
Instruments web site at: www.ti.com/lvds
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Revision History
04/16/2012
• Added CMLOUT P/N in DS90UB904Q Deserializer Pin Descriptions
• Added ESD CDM and ESD MM values
• Added 3.3V I/O VOH conditions: IOH = -4 mA
• Corrected 3.3V I/O VOL conditions: IOL = +4 mA
• Changed NSID DS90UB903/904QSQX to qty 2500
• Added “Only used when VDDIOCONTROL = 0” note for UB904 Register 0x03 bit[4] description
• Added Register 0x27 BCC in UB904 Register table
• Added Register 0x3F CML Output in UB904 Register table
• Updated SLAVE CLOCK STRETCHING in Functional Description section
• Updated REMOTE WAKE UP (Camera Mode) procedure in Functional Description section
• Updated Des - Receiver Input Equalization (EQ) in Functional Description section
• Updated TRANSMISSION MEDIA in Applications Information section
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
•
38
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 37
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PACKAGE OPTION ADDENDUM
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16-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
DS90UB903QSQ/NOPB
ACTIVE
WQFN
RTA
40
1000
Green (RoHS
& no Sb/Br)
SN
Level-3-260C-168 HR
-40 to 105
UB903QSQ
DS90UB903QSQE/NOPB
ACTIVE
WQFN
RTA
40
250
Green (RoHS
& no Sb/Br)
SN
Level-3-260C-168 HR
-40 to 105
UB903QSQ
DS90UB903QSQX/NOPB
ACTIVE
WQFN
RTA
40
2500
Green (RoHS
& no Sb/Br)
SN
Level-3-260C-168 HR
-40 to 105
UB903QSQ
DS90UB904QSQ/NOPB
ACTIVE
WQFN
RHS
48
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB904QSQ
DS90UB904QSQE/NOPB
ACTIVE
WQFN
RHS
48
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB904QSQ
DS90UB904QSQX/NOPB
ACTIVE
WQFN
RHS
48
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB904QSQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DS90UB903QSQ/NOPB
WQFN
RTA
40
DS90UB903QSQE/NOPB
WQFN
RTA
DS90UB903QSQX/NOPB
WQFN
RTA
DS90UB904QSQ/NOPB
WQFN
DS90UB904QSQE/NOPB
DS90UB904QSQX/NOPB
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
40
250
178.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
40
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
RHS
48
1000
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
WQFN
RHS
48
250
178.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
WQFN
RHS
48
2500
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90UB903QSQ/NOPB
WQFN
RTA
40
1000
367.0
367.0
38.0
DS90UB903QSQE/NOPB
WQFN
RTA
40
250
213.0
191.0
55.0
DS90UB903QSQX/NOPB
WQFN
RTA
40
2500
367.0
367.0
38.0
DS90UB904QSQ/NOPB
WQFN
RHS
48
1000
367.0
367.0
38.0
DS90UB904QSQE/NOPB
WQFN
RHS
48
250
213.0
191.0
55.0
DS90UB904QSQX/NOPB
WQFN
RHS
48
2500
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
RTA0040A
SQA40A (Rev B)
www.ti.com
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