NCV7344 High Speed Low Power CAN, CAN FD Transceiver Description The NCV7344 CAN transceiver is the interface between a controller area network (CAN) protocol controller and the physical bus. The transceiver provides differential transmit capability to the bus and differential receive capability to the CAN controller. The NCV7344 is an addition to the CAN high−speed transceiver family complementing NCV734x CAN stand−alone transceivers and previous generations such as AMIS42665, AMIS3066x, etc. The NCV7344 guarantees additional timing parameters to ensure robust communication at data rates beyond 1 Mbps to cope with CAN flexible data rate requirements (CAN FD). These features make the NCV7344 an excellent choice for all types of HS−CAN networks, in nodes that require a low−power mode with wake−up capability via the CAN bus. Features • Compatible with ISO 11898−2:2016 • Specification for Loop Delay Symmetry up to 5 Mbps • VIO pin on NCV7344−3 Version Allowing Direct Interfacing with • • • • • • • • • • • 3 V to 5 V Microcontrollers Very Low Current Standby Mode with Wake−up via the Bus Low Electromagnetic Emission (EME) and High Electromagnetic Immunity Very Low EME without Common−mode (CM) Choke No Disturbance of the Bus Lines with an Un−powered Node Transmit Data (TxD) Dominant Timeout Function Under All Supply Conditions the Chip Behaves Predictably Very High ESD Robustness of Bus Pins, >8 kV System ESD Pulses Thermal Protection Bus Pins Short Circuit Proof to Supply Voltage and Ground Bus Pins Protected Against Transients in an Automotive Environment These are Pb−free Devices www.onsemi.com MARKING DIAGRAM 1 1 1 1 Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable NV7344−x ALYWG G DFN8 MW SUFFIX CASE 506BW NV7344−x = Specific Device Code x = 0 or 3 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT TxD STB GND CANH VCC CANL RxD NC (−0) VIO (−3) NCV7344D1x (Top View) Quality • Wettable Flank Package for Enhanced Optical Inspection • NCV Prefix for Automotive and Other Applications Requiring NV7344−x ALYW G G SOIC−8 D SUFFIX CASE 751AZ TxD GND VCC RxD EP Flag NCV7344MWx (Top View) Typical Applications • Automotive • Industrial Networks STB CANH CANL NC (−0) VIO (−3) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. © Semiconductor Components Industries, LLC, 2017 February, 2017 − Rev. 1 1 Publication Order Number: NCV7344/D NCV7344 BLOCK DIAGRAM VCC NC 3 5 NCV7344−0 VCC TxD 1 Thermal shutdown 7 CANH Driver control 6 CANL 7 CANH 6 CANL Timer VCC STB RxD GND 8 Mode & Wake−up control 4 Wake−up Filter COMP 2 COMP Figure 1. NCV7344−0 Block Diagram VCC VIO 3 5 NCV7344−3 VIO TxD Thermal shutdown 1 Timer VIO STB RxD GND 8 4 Mode & Wake−up control Driver control Wake−up Filter COMP 2 COMP Figure 2. NCV7344−3 Block Diagram www.onsemi.com 2 NCV7344 TYPICAL APPLICATION VBAT IN 5V −reg OUT VCC NC VCC 5 STB 7 8 TxD NCV7344 Micro− controller 1 RxD 3 4 CAN BUS 6 2 GND RLT = 60 W CANH CANL RLT = 60 W GND Figure 3. Application Diagram NCV7344−0 VBAT IN 5V −reg OUT IN 3V −reg OUT VIO VCC 5 Micro− controller TxD RxD 8 1 4 NCV7344−3 STB 3 7 CAN BUS 6 2 GND RLT = 60 W CANH CANL RLT = 60 W GND Figure 4. Application Diagram NCV7344−3 Table 1. PIN FUNCTION DESCRIPTION Pin Name Description 1 TxD Transmit data input; low input Ù dominant driver; internal pull−up current 2 GND Ground 3 VCC Supply voltage 4 RxD Receive data output; dominant transmitter Ù low output 5 5 NC VIO Not connected. On NCV7344−0 only Digital Input / Output pins and other functions supply voltage. On NCV7344−3 only 6 CANL Low−level CAN bus line (low in dominant mode) 7 CANH High−level CAN bus line (high in dominant mode) 8 STB Standby mode control input; internal pull−up current www.onsemi.com 3 NCV7344 FUNCTIONAL DESCRIPTION Operating Modes Overtemperature Detection NCV7344 provides two modes of operation as illustrated in Table 2. These modes are selectable through pin STB. A thermal protection circuit protects the IC from damage by switching off the transmitter if the junction temperature exceeds a value of approximately 170°C. Because the transmitter dissipates most of the power, the power dissipation and temperature of the IC is reduced. All other IC functions continue to operate. The transmitter off−state resets when the temperature decreases below the shutdown threshold and pin TxD goes high. The thermal protection circuit is particularly needed when a bus line short circuits. Table 2. OPERATING MODES Pin STB Mode Pin RxD Low Normal Low when bus dominant High when bus recessive High Standby Follows the bus when wake−up detected High when no wake−up request detected TxD Dominant Timeout Function A TxD dominant timeout timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network communication) if pin TxD is forced permanently low by a hardware and/or software application failure. The timer is triggered by a negative edge on pin TxD. If the duration of the low−level on pin TxD exceeds the internal timer value tdom(TxD), the transmitter is disabled, driving the bus into a recessive state. The timer is reset by a positive edge on pin TxD. This TxD dominant timeout time tdom(TxD) defines the minimum possible bit rate to 12 kbps. Normal Mode In the normal mode, the transceiver is able to communicate via the bus lines. The signals are transmitted and received to the CAN controller via the pins TxD and RxD. The slopes on the bus lines outputs are optimized to give low EME. Standby Mode In standby mode both the transmitter and receiver are disabled and a very low−power differential receiver monitors the bus lines for CAN bus activity. The bus lines are biased to ground and supply current is reduced to a minimum, typically 10 mA. When a wake−up request is detected by the low−power differential receiver, the signal is first filtered and then verified as a valid wake signal after a time period of twake_filt, the RxD pin is driven low by the transceiver (following the bus) to inform the controller of the wake−up request. Fail Safe Features A current−limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. Undervoltage on VCC pin prevents the chip sending data on the bus when there is not enough VCC supply voltage. After supply is recovered TxD pin must be first released to high to allow sending dominant bits again. Recovery time from undervoltage detection is equal to td(stb−nm) time. The pins CANH and CANL are protected from automotive electrical transients (according to ISO 7637; see Figure 7). Pins TxD and STB are pulled high internally should the input become disconnected. Pins TxD, STB and RxD will be floating, preventing reverse supply should the VCC supply be removed. Wake−up When a valid wake−up pattern (phase in order dominant – recessive – dominant) is detected during the standby mode the RxD pin follows the bus. Minimum length of each phase is twake_filt – see Figure 5. Pattern must be received within twake_to to be recognized as valid wake−up otherwise internal logic is reset. twake_filt twake_filt twake_filt VIO Supply Pin The VIO pin (available only on NCV7344−3 version) should be connected to microcontroller supply pin. By using VIO supply pin shared with microcontroller the I/O levels between microcontroller and transceiver are properly adjusted. See Figure 4. Pin VIO also provides the internal supply voltage for low−power differential receiver of the transceiver. This allows detection of wake−up request even when there is no supply voltage on pin VCC. CANH CANL < twake_to t dwakerd t dwakedr RxDC Figure 5. NCV7344 Wake−up Behavior www.onsemi.com 4 NCV7344 ELECTRICAL CHARACTERISTICS Definitions All voltages are referenced to GND (pin 2). Positive currents flow into the IC. Sinking current means the current is flowing into the pin; sourcing current means the current is flowing out of the pin. ABSOLUTE MAXIMUM RATINGS Table 3. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Unit −0.3 +6 V 0 < VCC < 5.25 V; no time limit −42 +42 V 0 < VCC < 5.25 V; no time limit −42 +42 V DC voltage between CANH and CANL −42 +42 V DC voltage at pin TxD, RxD, STB −0.3 +6 V VSUP Supply voltage VCC, VIO VCANH DC voltage at pin CANH VCANL DC voltage at pin CANL VCANH−CANL VI/O Conditions VesdHBM Electrostatic discharge voltage at all pins, Component HBM (Note 1) −8 +8 kV VesdCDM Electrostatic discharge voltage at all pins, Component CDM (Note 2) −750 +750 V VesdIEC Electrostatic discharge voltage at pins CANH and CANL, System HBM (Note 4) (Note 3) −8 +8 kV Vschaff Voltage transients, pins CANH, CANL. According to ISO7637−3, Class C (Note 4) test pulses 1 −100 test pulses 2a +75 test pulses 3a Latch−up V Static latch−up at all pins −150 V V test pulses 3b +100 V (Note 5) 150 mA Tstg Storage temperature −55 +150 °C TJ Maximum junction temperature −40 +170 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF capacitor through a 1.5 kW resistor. 2. Standardized charged device model ESD pulses when tested according to AEC−Q100−011 3. System human body model electrostatic discharge (ESD) pulses in accordance to IEC 61000−4−2. Equivalent to discharging a 150 pF capacitor through a 330 W resistor referenced to GND. 4. Results were verified by external test house. 5. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78. Table 4. THERMAL CHARACTERISTICS Parameter Symbol Value Unit Thermal characteristics, SOIC−8 (Note 6) Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 7) Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 8) RqJA RqJA 131 81 °C/W °C/W Thermal characteristics, DFN8 (Note 6) Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 7) Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 8) RqJA RqJA 125 58 °C/W °C/W 6. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 7. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage. 8. Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage. www.onsemi.com 5 NCV7344 ELECTRICAL CHARACTERISTICS Table 5. ELECTRICAL CHARACTERISTICS VCC = 4.75 V to 5.25 V; VIO = 2.8 to 5.25 V; TJ = −40 to +150°C; RLT = 60 W, CLT = 100 pF, C1 not used unless specified otherwise. Parameter Symbol Conditions Min Typ Max Unit SUPPLY (Pin VCC) VCC Power supply voltage ICC Supply current ICCS Supply current in standby mode (Note 9) 4.75 5 5.25 V Dominant; VTxD = Low 20 45 70 mA Recessive; VTxD = High 2 5 10 mA TJ ≤ 100°C, (Note 10) − 10 15 mA VUVD(VCC)(stby) Standby undervoltage detection VCC pin 3.5 4 4.3 V VUVD(VCC)(swoff) Switch−off undervoltage detection VCC pin 2.0 2.3 2.6 V VIO SUPPLY VOLTAGE (Pin VIO) Only for NCV7344−3 version VIO Supply voltage on pin VIO 2.8 − 5.5 V IIOS Supply current on pin VIO in standby mode TJ ≤ 100°C, (Note 10) − − 11 mA ICCS Supply current on pin VCC in standby mode TJ ≤ 100°C, (Note 10) − 0 4.0 IIONM Supply current on pin VIO during normal mode Dominant; VTxD = Low 0.45 0.65 0.9 mA mA Recessive; VTxD = Low 0.32 0.43 0.58 2.0 2.3 2.6 V V VUVDVIO Undervoltage detection voltage on VIO pin TRANSMITTER DATA INPUT (Pin TxD) VIH High−level input voltage Output recessive 2.0 − − VIL Low−level input voltage Output dominant − − 0.8 V IIH High−level input current VTxD = VCC/VIO −5 0 +5 mA IIL Low−level input current VTxD = 0 V −300 −150 −75 mA Ci Input capacitance (Note 10) − 5 10 pF V TRANSMITTER MODE SELECT (Pin STB) VIH High−level input voltage Standby mode 2.0 − − VIL Low−level input voltage Normal mode − − 0.8 V IIH High−level input current VSTB = VCC/VIO −1 0 +1 mA IIL Low−level input current VSTB = 0 V −15 − −1 mA Ci Input capacitance (Note 10) − 5 10 pF RECEIVER DATA OUTPUT (Pin RxD) IOH High−level output current Normal mode VRxD = VCC/VIO – 0.4 V −8 −3 −1 mA IOL Low−level output current VRxD = 0.4 V 1 6 12 mA −27 V < VCANH, VCANL < +32 V; Normal mode −5 − +5 mA 0 W < R(VCC to GND) < 1 MW VCANL = VCANH = 5 V −5 0 +5 mA BUS LINES (Pins CANH and CANL) Io(rec) ILI Recessive output current at pins CANH and CANL Input leakage current Vo(rec) (CANH) Recessive output voltage at pin CANH Normal mode, VTxD = High 2.0 2.5 3.0 V Vo(rec) (CANL) Recessive output voltage at pin CANL Normal mode, VTxD = High 2.0 2.5 3.0 V Vo(off) (CANH) Recessive output voltage at pin CANH Standby mode −0.1 0 0.1 V Vo(off) (CANL) Recessive output voltage at pin CANL Standby mode −0.1 0 0.1 V Differential bus output voltage (VCANH − VCANL) Standby mode −0.2 0 0.2 V Vo(off (diff) Vo(dom) (CANH) Dominant output voltage at pin CANH VTxD = 0 V; t < tdom(TxD); 50 W < RLT < 65 W 2.75 3.5 4.5 V Vo(dom) (CANL) Dominant output voltage at pin CANL VTxD = 0 V; t < tdom(TxD); 50 W < RLT < 65 W 0.5 1.5 2.25 V VTxD = 0 V; dominant; 45 W < RLT < 65 W 1.5 2.25 3.0 V Vo(dom) (diff) Differential bus output voltage (VCANH − VCANL) 9. In the range of 4.5 V to 4.75V and from 5.25 V to 5.5 V the chip is fully functional; some parameters may be outside of the specification. 10. Values based on design and characterization, not tested in production www.onsemi.com 6 NCV7344 Table 5. ELECTRICAL CHARACTERISTICS VCC = 4.75 V to 5.25 V; VIO = 2.8 to 5.25 V; TJ = −40 to +150°C; RLT = 60 W, CLT = 100 pF, C1 not used unless specified otherwise. Symbol Parameter Conditions Min Typ Max Unit RLT = 2.24 kW (Note 10) 1.5 − 5.0 V Differential bus output voltage (VCANH − VCANL) VTxD = High; recessive; no load −50 0 +50 mV Vo(dom) (sym) Dominant output voltage driver symmetry (VCANH + VCANL) RLT = 60 W; C1 = 4.7 nF; TxD = square wave up to 1 MHz 0.9 1.0 1.1 VCC Io(sc) (CANH) Short circuit output current at pin CANH VCANH = −3 V; VTxD = Low −3 V < VCANH < +18 V −100 −115 −70 −40 115 mA Io(sc) (CANL) Short circuit output current at pin CANL VCANL = 36 V; VTxD = Low −3 V < VCANL < +18 V 40 −115 70 100 115 mA Vi(diff) (th)_NORM Differential receiver threshold voltage in normal mode −12 V < VCANL < +12 V; −12 V < VCANH < +12 V 0.5 − 0.9 V Vi(diff) (th)_STDBY Differential receiver threshold voltage in standby mode −12 V < VCANL < +12 V; −12 V < VCANH < +12 V 0.4 − 1.05 V BUS LINES (Pins CANH and CANL) Vo(dom) (diff)_arb Vo(rec) (diff) Differential bus output voltage during arbitration (VCANH + VCANL) Ri(cm) (CANH) Common−mode input resistance at pin CANH −2 V < VCANH < +7 V; −2 V < VCANL < +7 V 15 26 37 kW Ri(cm) (CANL) Common−mode input resistance at pin CANL −2 V < VCANH < +7 V; −2 V < VCANL < +7 V 15 26 37 kW Matching between pin CANH and pin CANL common mode input resistance VCANH = VCANL = +5 V −1 0 +1 % Ri(cm) (m) 25 50 75 kW Ci(CANH) Ri(diff) Input capacitance at pin CANH VTxD = High; (Note 10) − 7.5 20 pF Ci(CANL) Input capacitance at pin CANL VTxD = High; (Note 10) − 7.5 20 pF Differential input capacitance VTxD = High; (Note 10) − 3.75 10 pF Ci(diff) Differential input resistance TIMING CHARACTERISTICS (see Figures 6 and 8) td(TxD−BUSon) Delay TxD to bus active − 75 − ns td(TxD−BUSoff) Delay TxD to bus inactive − 85 − ns td(BUSon−RxD) Delay bus active to RxD − 24 − ns td(BUSoff−RxD) Delay bus inactive to RxD − 32 − ns tpd_dr Propagation delay TxD to RxD dominant to recessive transition 50 100 210 ns tpd_rd Propagation delay TxD to RxD recessive to dominant transition 50 120 210 ns td(stb−nm) Delay standby mode to normal mode twake_filt Filter time for wake−up via bus tdwakerd Delay to flag wake event (recessive to dominant transitions) tdwakedr Delay to flag wake event (dominant to recessive transitions) 5 11 20 ms 0.5 − 5 ms Valid bus wake−up event 0.5 2.6 6 ms Valid bus wake−up event 0.5 2.6 6 ms twake_to Bus time for wake−up timeout Standby mode 1 − 10 ms tdom(TxD) TxD dominant time for timeout VTxD = Low; Normal mode 1 − 10 ms tBit(RxD) Bit time on RxD pin tBit(TxD) = 500 ns 400 − 550 ns tBit(TxD) = 200 ns 120 − 220 ns tBit(TxD) = 500 ns 435 − 530 ns tBit(TxD) = 200 ns 155 − 210 ns tBit(TxD) = 500 ns −65 − +40 ns tBit(TxD) = 200 ns −45 − +15 ns Junction temperature rising 160 180 200 °C tBit(Vi(diff)) DtRec Bit time on bus (CANH – CANL pin) Receiver timing symmetry DtRec = tBit(RxD) − tBit(Vi(diff)) THERMAL SHUTDOWN TJ(sd) Shutdown junction temperature 9. In the range of 4.5 V to 4.75V and from 5.25 V to 5.5 V the chip is fully functional; some parameters may be outside of the specification. 10. Values based on design and characterization, not tested in production www.onsemi.com 7 NCV7344 MEASUREMENT SETUPS AND DEFINITIONS 0.7·VCC * TxD 0.3·VCC * 0.3·VCC * tpd_rd tbit(TxD) td(TxD−BUSon) 5·tbit(TxD) Vi(diff)= VCANH −VCANL td(BUSon−RxD) 900 mV 500 mV tbit(Vi(diff)) td(TxD−BUSoff) tpd_dr 0.7·VCC * RxD 0.3·VCC * *On NCV7344−3 VCC is replaced by VIO Edge length below 10 ns tbit(RxD) Figure 6. Transceiver Timing Diagram +5 V 100nF VIO TxD CANH 7 1 NCV7344 RxD VCC 3 5 4 8 15pF 1 nF Transient Generator 1 nF 6 CANL 2 STB GND Figure 7. Test Circuit for Automotive Transients +5 V 100 nF 3 5 RxD 7 1 NCV7344 TxD 4 8 15 pF VCC VIO RLT/2 CLT 6 2 STB CANH C1 RLT/2 CANL 100 pF 2x 30 W GND Figure 8. Test Circuit for Timing Characteristics www.onsemi.com 8 NCV7344 Table 6. ISO 11898−2:2016 Parameter Cross−Reference Table ISO 11898−2:2016 Specification Parameter NCV7344 Datasheet Notation Symbol Single ended voltage on CAN_H VCAN_H Vo(dom)(CANH) Single ended voltage on CAN_L VCAN_L Vo(dom)(CANL) Differential voltage on normal bus load VDiff Vo(dom)(diff) Differential voltage on effective resistance during arbitration VDiff Vo(dom)(diff)_arb Differential voltage on extended bus load range (optional) VDiff Vo(dom)(diff) VSYM Vo(dom)(sym) Absolute current on CAN_H ICAN_H Io(SC)(CANH) Absolute current on CAN_L ICAN_L Io(SC)(CANL) Single ended output voltage on CAN_H VCAN_H Vo(rec)(CANH) Single ended output voltage on CAN_L VCAN_L Vo(rec)(CANL) VDiff Vo(rec)(diff) Single ended output voltage on CAN_H VCAN_H Vo(off)(CANH) Single ended output voltage on CAN_L VCAN_L Vo(off)(CANL) VDiff Vo(off)(dif) Transmit dominant timeout, long tdom Tdom(TxD) Transmit dominant timeout, short tdom NA Recessive state differential input voltage range VDiff Vi(diff)(th)_NORM Dominant state differential input voltage range VDiff Vi(diff)(th)_NORM Recessive state differential input voltage range VDiff Vi(diff)(th)_STDBY Dominant state differential input voltage range VDiff Vi(diff)(th)_STDBY RDiff Ri(diff) RCAN_H RCAN_L Ri(cm)(CANH) Ri(cm)(CANL) mR Ri(cm)(m) tLoop tpd_rd tpd_dr Dominant output characteristics Driver symmetry Driver symmetry Driver output current Receiver output characteristics, bus biasing active Differential output voltage Receiver output characteristics, bus biasing inactive Differential output voltage Optional transmit dominant timeout Static receiver input characteristics, bus biasing active Static receiver input characteristics, bus biasing inactive Receiver input resistance Differential internal resistance Single ended internal resistance Receiver input resistance matching Matching a of internal resistance Implementation loop delay requirement Loop delay Optional implementation data signal timing requirements for use with bit rates above 1 Mbit/s and up to 2 Mbit/s Transmitted recessive bit width @ 2 Mbit/s tBit(Bus) tBit(Vi(diff)) Received recessive bit width @ 2 Mbit/s tBit(RXD) tBit(RxD) www.onsemi.com 9 NCV7344 Table 6. ISO 11898−2:2016 Parameter Cross−Reference Table Parameter Receiver timing symmetry @ 2 Mbit/s Notation Symbol DtRec DtRec Optional implementation data signal timing requirements for use with bit rates above 2 Mbit/s and up to 5 Mbit/s Transmitted recessive bit width @ 5 Mbit/s tBit(Bus) tBit(Vi(diff)) Transmitted recessive bit width @ 5 Mbit/s tBit(RXD) tBit(RxD) DtRec DtRec VDiff VCANH−CANL General maximum rating VCAN_H and VCAN_L VCAN_H VCAN_L VCANH VCANL Optional: Extended maximum rating VCAN_H and VCAN_L VCAN_H VCAN_L NA ICAN_H ICAN_L ILI CAN activity filter time, long tFilter twake_filt CAN activity filter time, short tFilter NA Wake−up timeout, short tWake twake_to Wake−up timeout, long tWake twake_to tSilence NA tBias NA Received recessive bit width @ 5 Mbit/s Maximum ratings of VCAN_H, VCAN_L and VDiff Maximum rating VDiff Maximum leakage currents on CAN_H and CAN_L, unpowered Leakage current on CAN_H, CAN_L Bus biasing control timings Timeout for bus inactivity (Required for selective wake−up implementation only) Bus Bias reaction time (Required for selective wake−up implementation only) DEVICE ORDERING INFORMATION Part Number NCV7344D10R2G Description Package Shipping† −40°C to +125°C SOIC 150 8 GREEN (Matte Sn, JEDEC MS−012) (Pb−Free) 3000 / Tape & Reel −40°C to +150°C DFN 8 Wettable Flank (Pb−Free) 3000 / Tape & Reel High Speed Low Power CAN, CANFD Transceiver NCV7344D13R2G High Speed Low Power CAN, CANFD Transceiver with VIO pin NCV7344MW0R2G High Speed Low Power CAN, CANFD Transceiver NCV7344MW3R2G Temperature Range High Speed Low Power CAN, CANFD Transceiver with VIO pin †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 10 NCV7344 PACKAGE DIMENSIONS SOIC−8 CASE 751AZ ISSUE B NOTES 4&5 0.10 C D 45 5 CHAMFER D h NOTE 6 D A 8 H 2X 5 0.10 C D E E1 NOTES 4&5 L2 1 0.20 C D 4 8X B NOTE 6 TOP VIEW b 0.25 M L C DETAIL A C A-B D NOTES 3&7 DETAIL A A2 NOTE 7 c 0.10 C A A1 NOTE 8 e SIDE VIEW SEATING PLANE C END VIEW SEATING PLANE RECOMMENDED SOLDERING FOOTPRINT* NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.004 mm IN EXCESS OF MAXIMUM MATERIAL CONDITION. 4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006 mm PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.010 mm PER SIDE. 5. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOT TOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTER MOST EXTREMES OF THE PLASTIC BODY AT DATUM H. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H. 7. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 FROM THE LEAD TIP. 8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. DIM A A1 A2 b c D E E1 e h L L2 MILLIMETERS MIN MAX --1.75 0.10 0.25 1.25 --0.31 0.51 0.10 0.25 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.25 0.41 0.40 1.27 0.25 BSC 8X 0.76 8X 1.52 7.00 1 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 11 NCV7344 PACKAGE DIMENSIONS DFN8, 3x3, 0.65P CASE 506BW ISSUE O A B D L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L1 PIN ONE REFERENCE 2X 0.10 C 2X DETAIL A ÉÉÉ ÉÉÉ ÉÉÉ 0.10 C OPTIONAL CONSTRUCTIONS E ÉÉ ÉÉ EXPOSED Cu TOP VIEW (A3) DETAIL B 0.05 C DIM A A1 A3 b D D2 E E2 e K L L1 MOLD CMPD DETAIL B A OPTIONAL CONSTRUCTIONS MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.25 0.35 3.00 BSC 2.30 2.50 3.00 BSC 1.55 1.75 0.65 BSC 0.20 −−− 0.35 0.45 0.00 0.15 0.05 C NOTE 4 SIDE VIEW C RECOMMENDED SOLDERING FOOTPRINT* SEATING PLANE D2 DETAIL A 1 8X A1 2.50 ÇÇÇÇÇÇ ÇÇÇÇÇÇ 4 L E2 8X K e/2 8 5 e BOTTOM VIEW 8X 8X 0.62 3.30 1.75 ÇÇÇÇÇÇ ÇÇÇÇÇÇ b 1 0.65 PITCH 0.10 C A B 0.05 C NOTE 3 8X 0.40 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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