TI OPA2313IDR 1-mhz, micro-power, low-noise, rrio,1.8-v cmos operational amplifier Datasheet

OPA313
OPA2313
OPA4313
www.ti.com
SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
1-MHz, Micro-Power, Low-Noise, RRIO,1.8-V CMOS
OPERATIONAL AMPLIFIER
Precision Value Line Series
Check for Samples: OPA313, OPA2313, OPA4313
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
The OPA313 family of single-, dual-, and quadchannel op amps represents a new generation of lowcost, general purpose, micro-power operational
amplifiers. Featuring rail-to-rail input and output
swings, and low quiescent current (50 μA, typ)
combined with a wide bandwidth of 1 MHz and very
low noise (25 nV/√Hz at 1 kHz) makes this family
very attractive for a variety of battery-powered
applications that require a good balance between
cost and performance. The low input bias current
supports those op amps to be used in applications
with megaohm source impedances.
1
2
Low IQ: 50 µA/ch
Wide Supply Range: 1.8 V to 5.5 V
Low Noise: 25 nV/√Hz at 1 kHz
Gain Bandwidth: 1 MHz
Low Input Bias Current: 0.2 pA
Low Offset Voltage: 0.5 mV
Unity-Gain Stable
Internal RF/EMI Filter
Extended Temperature Range:
–40°C to +125°C
APPLICATIONS
•
•
•
Battery-Powered Instruments:
– Consumer, Industrial, Medical
– Notebooks, Portable Media Players
Sensor Signal Conditioning:
– Loop-Powered
– Notebooks, Portable Media Players
Wireless Sensors:
– Home Security
– Remote Sensing
– Wireless Metering
The robust design of the OPA313 devices provides
ease-of-use to the circuit designer: unity-gain stability
with capacitive loads of up to 150 pF, integrated
RF/EMI rejection filter, no phase reversal in overdrive
conditions, and high electrostatic discharge (ESD)
protection (4-kV HBM).
These devices are optimized for operation at voltages
as low as +1.8 V (±0.9 V) and up to +5.5 V (±2.75 V),
and are specified over the extended temperature
range of –40°C to +125°C.
The OPA313 (single) is available in both SC70-5 and
SOT23-5 packages. The OPA2313 (dual) is offered in
SO-8, MSOP-8, and DFN-8 packages. The quadchannel OPA4313 is offered in a TSSOP-14 package.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
OPA313
OPA2313
OPA4313
SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE INFORMATION (1)
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE RANGE
PACKAGE MARKING
SC70-5
DCK
–40°C to +125°C
SIE
SOT23-5
DBV
–40°C to +125°C
SIF
SO-8
D
–40°C to +125°C
OP2313
OPA2313
MSOP-8
DGK
–40°C to +125°C
OUSS
DFN-8
DRG
–40°C to +125°C
SDY
OPA4313
TSSOP-14
PW
–40°C to +125°C
OPA4313
PRODUCT
OPA313
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage
UNIT
7
V
(V–) – 0.5 to (V+) + 0.5
V
±10
mA
Output short-circuit (3)
Continuous
mA
Operating temperature, TA
–40 to +150
°C
Storage temperature, Tstg
–65 to +150
°C
Junction temperature, TJ
+150
°C
Human body model (HBM)
4000
V
Charged device model (CDM)
1000
V
Machine model (MM)
200
V
Signal input terminals
ESD rating
(1)
(2)
(3)
2
Voltage
(2)
OPA313, OPA2313, OPA4313
Current (2)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: OPA313 OPA2313 OPA4313
OPA313
OPA2313
OPA4313
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SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
ELECTRICAL CHARACTERISTICS: +5.5 V (1)
At TA = +25 °C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
OPA313, OPA2313, OPA4313
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
2.5
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
vs Temperature
TA = –40°C to +125°C
PSRR
vs power supply
TA = –40°C to +125°C
Channel separation, dc
At dc
mV
μV/°C
2
74
90
dB
10
µV/V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
No phase reversal, rail-to-rail input
(V–) – 0.2
(V+) + 0.2
V
TA = –40°C to +125°C,
(VS–) – 0.2 V < VCM < (VS+) – 1.3 V
70
85
dB
TA = –40°C to +125°C,
VCM = –0.2 V to 5.7 V
64
80
dB
INPUT BIAS CURRENT
±0.2
IB
Input bias current
±10
pA
TA = –40°C to +85°C (2)
±50
pA
TA = –40°C to +125°C (2)
±600
pA
±10
pA
TA = –40°C to +85°C (2)
±50
pA
TA = –40°C to +125°C (2)
±600
pA
±0.2
IOS
Input offset current
NOISE
Input voltage noise (peak-topeak)
6
μVPP
f = 10 kHz
22
nV/√Hz
f = 1 kHz
25
nV/√Hz
f = 1 kHz
5
fA/√Hz
Differential
1
pF
Common-mode
5
pF
en
Input voltage noise density
in
Input current noise density
f = 0.1 Hz to 10 Hz
INPUT CAPACITANCE
CIN
OPEN-LOOP GAIN
0.05 V < VO < (V+) – 0.05 V, RL = 100 kΩ
AOL
Open-loop voltage gain
Phase margin
(1)
(2)
90
104
dB
TA = –40°C to +125°C, 0.1 V < VO < (V+) – 0.1 V
104
116
dB
0.3 V < VO < (V+) – 0.3 V, RL = 2 kΩ
100
110
dB
65
degrees
VS = 5.0 V, G = +1
Parameters with minimum or maximum specification limits are 100% production tested at +25ºC, unless otherwise noted. Over
temperature limits are based on characterization and statistical analysis.
Specified by design and characterization; not production tested.
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: OPA313 OPA2313 OPA4313
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OPA313
OPA2313
OPA4313
SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
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ELECTRICAL CHARACTERISTICS: +5.5 V(1) (continued)
At TA = +25 °C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
OPA313, OPA2313, OPA4313
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
VS = 5.0 V, CL = 10 pF
SR
Slew rate
VS = 5.0 V, G = +1
tS
MHz
V/μs
To 0.1%, VS = 5.0 V, 2-V step , G = +1
5
μs
To 0.01%, VS = 5.0 V, 2-V step , G = +1
6
μs
Overload recovery time
VS = 5.0 V, VIN × Gain > VS
3
μs
Total harmonic distortion +
noise (3)
VS = 5.0 V, VO = 1 VRMS, G = +1, f = 1 kHz
Settling time
THD+N
1
0.5
0.0045%
OUTPUT
RL = 100 kΩ (4)
VO
Voltage output swing from supply
rails
TA = –40°C to +125°C, RL = 100 kΩ
5
20
mV
30
mV
75
100
mV
125
mV
(4)
RL = 2 kΩ (4)
TA = –40°C to +125°C, RL = 2 kΩ
ISC
Short-circuit current
RO
Open-loop output impedance
TA = –40°C to +125°C
±15
mA
±12
mA
2300
Ω
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per amplifier
Power-on time
1.8 (±0.9)
IO = 0 mA, VS = 5.0 V
50
TA = –40°C to +125°C, VS = 5.0 V, IO = 0 mA
VS = 0 V to 5 V, to 90% IQ level
5.5 (±2.75)
V
60
µA
85
µA
10
µs
TEMPERATURE
(3)
(4)
4
Specified range
–40
+125
°C
Operating range
–40
+150
°C
Storage range
–65
+150
°C
Third-order filter; bandwidth = 80 kHz at –3 dB.
Specified by design and characterization; not production tested.
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Product Folder Links: OPA313 OPA2313 OPA4313
OPA313
OPA2313
OPA4313
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SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
ELECTRICAL CHARACTERISTICS: +1.8 V (1)
At TA = +25 °C, RL = 10 kΩ connected to VS / 2, VCM = VS+ – 1.3 V, and VOUT = VS / 2, unless otherwise noted.
OPA313, OPA2313, OPA4313
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
2.5
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
vs Temperature
TA = –40°C to +125°C
PSRR
vs power supply
TA = –40°C to +125°C
Channel separation, dc
At dc
mV
μV/°C
2
74
90
dB
10
µV/V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
No phase reversal, rail-to-rail input
(V–) – 0.2
(V+) + 0.2
TA = –40°C to +125°C,
(VS–) – 0.2 V < VCM < (VS+) – 1.3 V
70
85
VS = 1.8 V, VCM = –0.2 V to +1.8 V
58
73
TA = –40°C to +125°C, VCM = –0.2 V to 1.6 V
58
70
V
dB
dB
INPUT BIAS CURRENT
±0.2
IB
Input bias current
±10
pA
TA = –40°C to +85°C (2)
±50
pA
TA = –40°C to +125°C (2)
±600
pA
±10
pA
TA = –40°C to +85°C (2)
±50
pA
TA = –40°C to +125°C (2)
±600
pA
±0.2
IOS
Input offset current
NOISE
Input voltage noise (peak-topeak)
6
μVPP
f = 10 kHz
22
nV/√Hz
f = 1 kHz
25
nV/√Hz
f = 1 kHz
5
fA/√Hz
Differential
1
pF
Common-mode
5
pF
90
110
dB
100
110
dB
en
Input voltage noise density
in
Input current noise density
f = 0.1 Hz to 10 Hz
INPUT CAPACITANCE
CIN
OPEN-LOOP GAIN
AOL
(1)
(2)
Open-loop voltage gain
TA = –40°C to +125°C, 0.1 V < VO < (V+) – 0.1 V
0.05 V < VO < (V+) – 0.05 V, RL = 100 kΩ
Parameters with minimum or maximum specification limits are 100% production tested at +25ºC, unless otherwise noted. Over
temperature limits are based on characterization and statistical analysis.
Specified by design and characterization; not production tested.
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: OPA313 OPA2313 OPA4313
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OPA313
OPA2313
OPA4313
SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
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ELECTRICAL CHARACTERISTICS: +1.8 V(1) (continued)
At TA = +25 °C, RL = 10 kΩ connected to VS / 2, VCM = VS+ – 1.3 V, and VOUT = VS / 2, unless otherwise noted.
OPA313, OPA2313, OPA4313
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
CL = 10 pF
SR
Slew rate
G = +1
tS
MHz
V/μs
To 0.1%, VS = 5.0 V, 2-V step , G = +1
5
μs
To 0.01%, VS = 5.0 V, 2-V step , G = +1
6
μs
Overload recovery time
VS = 5.0 V, VIN × Gain > VS
3
μs
Total harmonic distortion +
noise (3)
VS = 5.0 V, VO = 1 VRMS, G = +1, f = 1 kHz
Settling time
THD+N
0.9
0.45
0.0045%
OUTPUT
RL = 100 kΩ (4)
VO
Voltage output swing from supply
rails
TA = –40°C to +125°C, RL = 100 kΩ
5
(4)
RL = 2 kΩ (4)
25
TA = –40°C to +125°C, RL = 2 kΩ
ISC
Short-circuit current
RO
Open-loop output impedance
15
mV
30
mV
50
mV
125
mV
±6
mA
Ω
2300
POWER SUPPLY
VS
Specified voltage range
IQ
Quiescent current per amplifier
IO = 0 mA
1.8 (±0.9)
50
Power-on time
VS = 0 V to 5 V, to 90% IQ level
10
5.5 (±2.75)
V
60
µA
µs
TEMPERATURE
(3)
(4)
6
Specified range
–40
+125
°C
Operating range
–40
+150
°C
Storage range
–65
+150
°C
Third-order filter; bandwidth = 80 kHz at –3 dB.
Specified by design and characterization; not production tested.
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Product Folder Links: OPA313 OPA2313 OPA4313
OPA313
OPA2313
OPA4313
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SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
THERMAL INFORMATION: OPA313
OPA313
THERMAL METRIC (1)
DBV (SOT23)
DCK (SC70)
5 PINS
5 PINS
θJA
Junction-to-ambient thermal resistance
228.5
281.4
θJC(top)
Junction-to-case(top) thermal resistance
99.1
91.6
θJB
Junction-to-board thermal resistance
54.6
59.6
ψJT
Junction-to-top characterization parameter
7.7
1.5
ψJB
Junction-to-board characterization parameter
53.8
58.8
θJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
N/A
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERMAL INFORMATION: OPA2313
OPA2313
THERMAL METRIC (1)
D (SO)
DGK (MSOP)
DRG (DFN)
8 PINS
8 PINS
8 PINS
θJA
Junction-to-ambient thermal resistance
138.4
191.2
53.8
θJC(top)
Junction-to-case(top) thermal resistance
89.5
61.9
69.2
θJB
Junction-to-board thermal resistance
78.6
111.9
20.1
ψJT
Junction-to-top characterization parameter
29.9
5.1
3.8
ψJB
Junction-to-board characterization parameter
78.1
110.2
20.0
θJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
N/A
11.6
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERMAL INFORMATION: OPA4313
OPA4313
THERMAL METRIC (1)
PW (TSSOP)
UNITS
14 PINS
θJA
Junction-to-ambient thermal resistance
121.0
θJC(top)
Junction-to-case(top) thermal resistance
49.4
θJB
Junction-to-board thermal resistance
62.8
ψJT
Junction-to-top characterization parameter
5.9
ψJB
Junction-to-board characterization parameter
62.2
θJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: OPA313 OPA2313 OPA4313
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OPA313
OPA2313
OPA4313
SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
www.ti.com
PIN CONFIGURATIONS
DCK PACKAGE
SC70-5
(TOP VIEW)
+IN
1
V-
2
-IN
3
D, DGK PACKAGES
SO-8, MSOP-8
(TOP VIEW)
5
V+
4
OUT
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
DBV PACKAGE
SOT23-5
(TOP VIEW)
OUT
1
V-
2
+IN
3
DRG PACKAGE(1)
DFN-8
(TOP VIEW)
5
V+
4
-IN
OUT A
1
-IN A
2
+IN A
3
V-
4
Exposed
Thermal
Die Pad
on
Underside(2)
8
V+
7
OUT B
6
-IN B
5
+IN B
PW PACKAGE
TSSOP-14
(TOP VIEW)
14
OUT D
13
-IN D
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
OUT A
1
-IN A
2
+IN A
A
B
D
C
(1) Pitch: 0,65 mm.
(2) Connect thermal pad to V–. Pad size: 1,8 mm × 1,5 mm.
8
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SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
TYPICAL CHARACTERISTICS
Table 1. Characteristic Performance Measurements
TITLE
FIGURE
Open-Loop Gain and Phase vs Frequency
Figure 1
Open-Loop Gain vs Temperature
Figure 2
Quiescent Current vs Supply Voltage
Figure 3
Quiescent Current vs Temperature
Figure 4
Offset Voltage Production Distribution
Figure 5
Offset Voltage Drift Distribution
Figure 6
Offset Voltage vs Common-Mode Voltage (Maximum Supply)
Figure 7
Offset Voltage vs Temperature
Figure 8
CMRR and PSRR vs Frequency (RTI)
Figure 9
CMRR and PSRR vs Temperature
Figure 10
0.1-Hz to 10-Hz Input Voltage Noise (5.5 V)
Figure 11
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V)
Figure 12
Input Voltage Noise vs Common-Mode Voltage (5.5 V)
Figure 13
Input Bias and Offset Current vs Temperature
Figure 14
Open-Loop Output Impedance vs Frequency
Figure 15
Maximum Output Voltage vs Frequency and Supply Voltage
Figure 16
Output Voltage Swing vs Output Current (over Temperature)
Figure 17
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (1.8 V)
Figure 18
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (5.5 V)
Figure 19
Small-Signal Overshoot vs Load Capacitance
Figure 20
Phase Margin vs Capacitive Load
Figure 21
Small-Signal Step Response, Noninverting (1.8 V)
Figure 22
Small-Signal Step Response, Noninverting ( 5.5 V)
Figure 23
Large-Signal Step Response, Noninverting (1.8 V)
Figure 24
Large-Signal Step Response, Noninverting ( 5.5 V)
Figure 25
Positive Overload Recovery
Figure 26
Negative Overload Recovery
Figure 27
No Phase Reversal
Figure 28
Channel Separation vs Frequency (Dual)
Figure 29
THD+N vs Amplitude (G = +1, 2 kΩ, 10 kΩ)
Figure 30
THD+N vs Amplitude (G = –1, 2 kΩ, 10 kΩ)
Figure 31
THD+N vs Frequency (0.5 VRMS, G = +1, 2 kΩ, 10 kΩ)
Figure 32
EMIRR IN+ vs Frequency
Figure 33
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OPA2313
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TYPICAL CHARACTERISTICS
At TA = +25 °C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
180
140
Gain
Phase
100 k , 5.5 V
135
100
135
CL=10pF
C
L = 10 pF
80
60
Phase (o)
Gain (dB)
140
90
40
20
45
C
L = 100 pF
CL=100pF
Open-Loop Gain (dB)
120
130
10 k , 5.5 V
125
120
2 k , 5.5 V
115
110
0
105
-20
1
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
0
100M
10 k , 1.8 V
100
-50
C001
Figure 1. OPEN-LOOP GAIN AND PHASE vs FREQUENCY
-25
0
25
50
Temperature (oC)
75
100
125
C002
Figure 2. OPEN-LOOP GAIN vs TEMPERATURE
65
60
Quiescent Current (µA/ch)
Quiescent Current (µA/ch)
58
56
54
52
50
48
46
44
60
VS = 5.5 V
55
50
45
VS = 1.8 V
40
42
40
35
1.5
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
-50
6
-25
0
C003
Figure 3. QUIESCENT CURRENT vs SUPPLY
25
50
Temperature (oC)
75
100
125
C004
Figure 4. QUIESCENT CURRENT vs TEMPERATURE
25
9
Percent of Amplifiers (%)
Percent of Amplifiers (%)
8
7
6
5
4
3
2
20
15
10
5
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2.5
2.75
2.25
2
1.75
1.5
1.25
1
0.75
2.5
2
1.5
0.5
Offset Voltage Drift (µV/oC)
C005
Figure 5. OFFSET VOLTAGE PRODUCTION DISTRIBUTION
10
0
0.25
Offset Voltage (mV)
1
0.5
0
-0.5
-1
-1.5
-2
0
-2.5
1
C006
Figure 6. OFFSET VOLTAGE DRIFT DISTRIBUTION
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SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
TYPICAL CHARACTERISTICS (continued)
At TA = +25 °C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
1500
1500
Typical Units
VS = 5.5 V
1200
900
Offset Voltage (µV)
Offset Voltage (µV)
900
600
300
0
-300
-600
600
300
0
-300
-600
-900
-900
-1200
-1200
-1500
-1500
0
0.5
1
1.5 2 2.5 3 3.5 4
Common-Mode Voltage (V)
4.5
5
5.5
-50
-25
0
C007
Figure 7. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
25
50
Temperature (oC)
75
100
125
C008
Figure 8. OFFSET VOLTAGE vs TEMPERATURE
110
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
120
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
Typical Units
VS = 5.5 V
1200
100
80
+PSRR
60
CMRR
40
20
-PSRR
105
PSRR
100
95
90
CMRR
85
80
75
70
65
VCM = ±0.2 V to 5.2 V
60
0
10
100
1k
10k
Frequency (Hz)
100k
-50
1M
-25
0
C009
Figure 9. CMRR AND PSRR vs FREQUENCY
(Referred-to-Input)
25
50
75
Temperature (oC)
100
125
C001
Figure 10. CMRR AND PSRR vs TEMPERATURE
1000
9ROWDJH 1RLVH Q9 ¥+]
Voltage Noise (1 µV/div)
VS = 1.8 V
100
10
VS = 5.5 V
1
Time (1 s/div)
1
10
C011
Figure 11. 0.1-Hz TO 10-Hz INPUT VOLTAGE NOISE
100
1k
Frequency (Hz)
10k
100k
C012
Figure 12. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY
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OPA2313
OPA4313
SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = +25 °C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
200
VS = 5.5 V
f = 1 kHz
35
150
Input Bias Current (pA)
9ROWDJH 1RLVH 'HQVLW\ Q9 ¥+]
40
30
25
20
IBN
100
IBP
50
0
15
IOS
-50
10
-100
0
0.5
1
1.5 2 2.5 3 3.5 4 4.5
Common-Mode Input Voltage (V)
5
5.5
-50
-25
0
25
50
Temperature (oC)
C013
75
125
C014
Figure 13. VOLTAGE NOISE vs COMMON-MODE VOLTAGE
Figure 14. INPUT BIAS AND OFFSET CURRENT vs
TEMPERATURE
100k
6
RL = 10 k
CL = 10 pF
5
VS = 5.5 V
Output Voltage (V)
Output Impedance ( )
100
VS = 1.8 V
10k
4
VS = 1.8 V
3
2
1
VS = 5.5 V
1000
1
10
100
1k
Frequency (Hz)
10k
0
1000
100k
Figure 15. OPEN-LOOP OUTPUT IMPEDANCE vs
FREQUENCY
100k
1M
Frequency (Hz)
C016
Figure 16. MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
AND SUPPLY VOLTAGE
3
40
G = +10 V/V
2
1
20
oC
+125
+125oC
0
+25oC
+25 oC
Gain (dB)
Output Voltage Swing (V)
10k
C015
-40 oC
-40oC
-1
G = +1 V/V
0
-2
G = -1 V/V
VS = 1.8 V
-3
-20
0
5
10
Output Current (mA)
15
20
Figure 17. OUTPUT VOLTAGE SWING vs OUTPUT
CURRENT (Over Temperature)
12
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10
100
C017
1k
10k
100k
Frequency (Hz)
1M
10M
100M
C018
Figure 18. CLOSED-LOOP GAIN vs FREQUENCY (Minimum
Supply)
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OPA2313
OPA4313
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SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
TYPICAL CHARACTERISTICS (continued)
At TA = +25 °C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
40
50
45
VS = 1.8V, VCM = 0.5V
40
G = +10 V/V
Overshoot (%)
Gain (dB)
20
G = +1 V/V
0
35
30
25
VS = 5.5V
20
15
10
G = -1 V/V
Gain = +1 V/V
RL = 10 kŸ
5
VS = 5.5V
0
±20
10
100
1k
10k
100k
1M
Frequency (Hz)
10M
100M
0
100
C000
Figure 19. CLOSED-LOOP GAIN vs FREQUENCY
(Maximum Supply)
200
Capacitive Load (pF)
300
400
C002
Figure 20. SMALL-SIGNAL OVERSHOOT vs
LOAD CAPACITANCE
90
80
Voltage (25 mV/div)
Phase Margin (o)
70
60
50
VS = 5.5V
40
30
G = +1 V/V
VS = 1.8V
VCM = 0.5V
RL = 10 kŸ
CL = 100 pF
VIN
CL = 10 pF
20
VS = 1.8V, VCM = 0.5V
10
0
0
100
200
Capacitive Load (pF)
300
400
Time (1 µs/div)
C003
Figure 21. PHASE MARGIN vs CAPACITIVE LOAD
G = +1 V/V
VS = 1.8 V
RL = 10 k
CL = 100 pF
VIN
Voltage (250 mV/div)
Voltage (25 mV/div)
G = +1 V/V
VS = 5.5 V
RL = 10 k
C004
Figure 22. SMALL-SIGNAL PULSE RESPONSE
(Minimum Supply)
CL = 10 pF
VOUT
VIN
Time (1 µs/div)
Time (2.5 µs/div)
C023
Figure 23. SMALL-SIGNAL PULSE RESPONSE
(Maximum Supply)
C024
Figure 24. LARGE-SIGNAL PULSE RESPONSE
(Minimum Supply)
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OPA313
OPA2313
OPA4313
SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
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TYPICAL CHARACTERISTICS (continued)
At TA = +25 °C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
Voltage (500 mV/div)
G = -10 V/V
VS = 5.5 V
Voltage (250 mV/div)
G = +1 V/V
VS = 5.5 V
RL = 10 k
VOUT
VIN
VOUT
VIN
Time (2.5 µs/div)
Time (2 µs/div)
C025
C026
Figure 26. POSITIVE OVERLOAD RECOVERY
Voltage (1 V/div)
Voltage (500 mV/div)
Figure 25. LARGE-SIGNAL PULSE RESPONSE
(Maximum Supply)
VIN
VOUT
VOUT
G = -10 V/V
VS = 5.5 V
VIN
Time (2 µs/div)
Time (125 µs/div)
C027
C028
Figure 27. NEGATIVE OVERLOAD RECOVERY
Figure 28. NO PHASE REVERSAL
-60
0.1
VS = 5.5 V
-100
THD + N (%)
Crosstalk (dB)
-80
chB to chA
-120
chA to chB
0.01
RL = 2 k
0.001
-140
RL = 10 k
-160
100
1k
10k
100k
Frequency (Hz)
1M
10M
Submit Documentation Feedback
0.1
1
Output Amplitude (VRMS)
C029
Figure 29. CHANNEL SEPARATION vs FREQUENCY
14
0.0001
0.01
VS = 1.8 V
f = 1 kHz
BW = 80 kHz
G = +1 V/V
10
C030
Figure 30. THD+N vs OUTPUT AMPLITUDE
(Minimum Supply)
Copyright © 2012–2013, Texas Instruments Incorporated
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OPA4313
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SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
TYPICAL CHARACTERISTICS (continued)
At TA = +25 °C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
0.1
0.1
0.01
THD + N (%)
THD + N (%)
VS = 5.5 V
VOUT= 0.5 VRMS
BW = 80 kHz
G = +1 V/V
RL = 2 k
0.001
VS = 5.5 V
f = 1 kHz
BW = 80 kHz
G = -1 V/V
0.0001
0.01
RL = 2 k
0.01
0.001
RL = 10 k
R L = 10 k
0.0001
0.1
1
Output Amplitude (VRMS)
10
10
100
1k
Frequency (Hz)
C031
Figure 31. THD+N vs OUTPUT AMPLITUDE
(Maximum Supply)
10k
100k
C032
Figure 32. THD+N vs FREQUENCY
120
PRF = -10 dBm
VSUPPLY = 5 V
VCM = 2.5 V
EMIRR IN+ (dB)
100
80
60
40
20
0
10
100
1000
Frequency (MHz)
10000
C033
Figure 33. EMIRR IN+ vs FREQUENCY
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OPA313
OPA2313
OPA4313
SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
www.ti.com
APPLICATION INFORMATION
The OPA313 is a family of low-power, rail-to-rail input and output operational amplifiers specifically designed for
portable applications. These devices operate from 1.8 V to 5.5 V, are unity-gain stable, and suitable for a wide
range of general-purpose applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected
to any point between V+ and ground. The input common-mode voltage range includes both rails, and allows the
OPA313 family to be used in virtually any single-supply application. Rail-to-rail input and output swing
significantly increases dynamic range, especially in low-supply applications, and makes them ideal for driving
sampling analog-to-digital converters (ADCs).
The OPA313 features 1-MHz bandwidth and 0.5-V/μs slew rate with only 50-μA supply current per channel,
providing good ac performance at very low power consumption. DC applications are also well served with a low
input noise voltage of 25 nV/√Hz at 1 kHz, low input bias current (0.2 pA), and an input offset voltage of 0.5 mV
(typical). The typical offset voltage drift is 2 μV/°C; over the full temperature range the input offset voltage
changes only 200 μV (0.5 mV to 0.7 mV).
OPERATING VOLTAGE
The OPA313 series op amps are fully specified and ensured for operation from +1.8 V to +5.5 V. In addition,
many specifications apply from –40°C to +125°C. Parameters that vary significantly with operating voltages or
temperature are shown in the Typical Characteristics graphs. Power-supply pins should be bypassed with 0.01μF ceramic capacitors.
RAIL-TO-RAIL INPUT
The input common-mode voltage range of the OPA313 series extends 200 mV beyond the supply rails. This
performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a
P-channel differential pair, as shown in Figure 34. The N-channel pair is active for input voltages close to the
positive rail, typically (V+) – 1.3 V to 200 mV above the positive supply, while the P-channel pair is on for inputs
from 200 mV below the negative supply to approximately (V+) – 1.3 V. There is a small transition region, typically
(V+) – 1.4 V to (V+) – 1.2 V, in which both pairs are on. This 200-mV transition region can vary up to 300 mV
with process variation. Thus, the transition region (both stages on) can range from (V+) – 1.7 V to (V+) – 1.5 V
on the low end, up to (V+) – 1.1 V to (V+) – 0.9 V on the high end. Within this transition region, PSRR, CMRR,
offset voltage, offset drift, and THD may be degraded compared to device operation outside this region.
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
Figure 34. Simplified Schematic
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SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
INPUT AND ESD PROTECTION
The OPA313 family incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case
of input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as long
as the current is limited to 10 mA as stated in the Absolute Maximum Ratings. Figure 35 shows how a series
input resistor may be added to the driven input to limit the input current. The added resistor contributes thermal
noise at the amplifier input and its value should be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
Device
VOUT
VIN
5 kW
Figure 35. Input Current Protection
COMMON-MODE REJECTION RATIO (CMRR)
CMRR for the OPA313 is specified in several ways so the best match for a given application may be used; see
the Electrical Characteristics. First, the CMRR of the device in the common-mode range below the transition
region [VCM < (V+) – 1.3 V] is given. This specification is the best indicator of the capability of the device when
the application requires use of one of the differential input pairs. Second, the CMRR over the entire commonmode range is specified at (VCM = –0.2 V to 5.7 V). This last value includes the variations seen through the
transition region (see Figure 7).
EMI SUSCEPTIBILITY AND INPUT FILTERING
Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If
conducted EMI enters the op amp, the dc offset observed at the amplifier output may shift from its nominal value
while EMI is present. This shift is a result of signal rectification associated with the internal semiconductor
junctions. While all op amp pin functions can be affected by EMI, the signal input pins are likely to be the most
susceptible. The OPA313 operational amplifier family incorporate an internal input low-pass filter that reduces the
amplifiers response to EMI. Both common-mode and differential mode filtering are provided by this filter. The
filter is designed for a cutoff frequency of approximately 35 MHz (–3 dB), with a roll-off of 20 dB per decade.
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR)
metric allows op amps to be directly compared by the EMI immunity. Figure 33 illustrates the results of this
testing on the OPA313 family. Detailed information can also be found in the application report, EMI Rejection
Ratio of Operational Amplifiers (SBOA128), available for download from www.ti.com.
RAIL-TO-RAIL OUTPUT
Designed as a micro-power, low-noise operational amplifier, the OPA313 delivers a robust output drive capability.
A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing capability.
For resistive loads up to 10 kΩ, the output swings typically to within 5 mV of either supply rail regardless of the
power-supply voltage applied. Different load conditions change the ability of the amplifier to swing close to the
rails; refer to the typical characteristic graph, Output Voltage Swing vs Output Current.
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OPA313
OPA2313
OPA4313
SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
www.ti.com
CAPACITIVE LOAD AND STABILITY
The OPA313 is designed to be used in applications where driving a capacitive load is required. As with all op
amps, there may be specific instances where the OPA313 can become unstable. The particular op amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether or
not an amplifier is stable in operation. An op amp in the unity-gain (+1-V/V) buffer configuration that drives a
capacitive load exhibits a greater tendency to be unstable than an amplifier operated at a higher noise gain. The
capacitive load, in conjunction with the op amp output resistance, creates a pole within the feedback loop that
degrades the phase margin. The degradation of the phase margin increases as the capacitive loading increases.
When operating in the unity-gain configuration, the OPA313 remains stable with a pure capacitive load up to
approximately 1 nF. The equivalent series resistance (ESR) of some very large capacitors (CL greater than 1 μF)
is sufficient to alter the phase characteristics in the feedback loop such that the amplifier remains stable.
Increasing the amplifier closed-loop gain allows the amplifier to drive increasingly larger capacitance. This
increased capability is evident when observing the overshoot response of the amplifier at higher voltage gains.
See the typical characteristic graph, Small-Signal Overshoot vs. Capacitive Load.
One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain
configuration is to insert a small resistor, typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 36.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique, however, is that a voltage divider is created with the added series resistor and any
resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output
that reduces the output swing.
V+
RS
VOUT
Device
VIN
10 W to
20 W
RL
CL
Figure 36. Improving Capacitive Load Drive
DFN PACKAGE
The OPA2313 (dual version) uses the DFN style package (also known as SON); this package is a QFN with
contacts on only two sides of the package bottom. This leadless package maximizes printed circuit board (PCB)
space and offers enhanced thermal and electrical characteristics through an exposed pad. One of the primary
advantages of the DFN package is its low, 0.9-mm height. DFN packages are physically small, have a smaller
routing area, improved thermal performance, reduced electrical parasitics, and use a pinout scheme that is
consistent with other commonly-used packages, such as SO and MSOP. Additionally, the absence of external
leads eliminates bent-lead issues.
The DFN package can easily be mounted using standard PCB assembly techniques. See Application Note,
QFN/SON PCB Attachment (SLUA271) and Application Report, Quad Flatpack No-Lead Logic Packages
(SCBA017), both available for download from www.ti.com.
NOTE
The exposed leadframe die pad on the bottom of the DFN package should be connected
to the most negative potential (V–).
18
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SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
APPLICATION EXAMPLES
GENERAL CONFIGURATIONS
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting terminal of the
amplifier, as Figure 37 shows.
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Figure 37. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task, as Figure 38 shows. For best results, the amplifier should have a bandwidth that is eight to 10 times the
filter frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier.
C1
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking factor
(Butterworth Q = 0.707)
R2
VIN
VOUT
C2
1
2pRC
f-3 dB =
RF
RF
RG =
RG
(
2-
1
Q
(
Figure 38. Two-Pole Low-Pass Sallen-Key Filter
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OPA313
OPA2313
OPA4313
SBOS649C – SEPTEMBER 2012 – REVISED MARCH 2013
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2012) to Revision C
Page
•
Changed first Open-Loop Gain, AOL typical specification in Electrical Characteristics: +5.5 V table ................................... 3
•
Updated Figure 10 .............................................................................................................................................................. 11
•
Updated Figure 19 through Figure 22 ................................................................................................................................ 12
Changes from Revision A (Sepetmber 2012) to Revision B
Page
•
Changed title of document .................................................................................................................................................... 1
•
Changed third paragraph of Description section .................................................................................................................. 1
•
Changed title of Electrical Characteristics: +5.5 V table ....................................................................................................... 3
•
Deleted middle two rows from Input Voltage Range, CMRR parameter in Electrical Characteristics: +5.5 V table ............ 3
•
Changed test conditions of Input Voltage Range, CMRR parameter in Electrical Characteristics: +5.5 V table ................. 3
•
Added footnote to Input Bias Current, IB and IOS parameters in Electrical Characteristics: +5.5 V table ............................. 3
•
Changed Open-Loop Gain, AOL parameter in Electrical Characteristics: +5.5 V table ......................................................... 3
•
Deleted first row from Frequency Response, GBW parameter in Electrical Characteristics: +5.5 V table .......................... 4
•
Deleted first row from Frequency Response, SR parameter in Electrical Characteristics: +5.5 V table .............................. 4
•
Changed Output, VO parameter in Electrical Characteristics: +5.5 V table .......................................................................... 4
•
Changed Output, ISC parameter in Electrical Characteristics: +5.5 V table .......................................................................... 4
•
Changed test conditions for the first row in the Power Supply, IQ parameter in Electrical Characteristics: +5.5 V table ..... 4
•
Changed Electrical Characteristics: +1.8 V table ................................................................................................................. 5
•
Changed conditions of Electrical Characteristics: +1.8 V table ............................................................................................ 5
•
Changed last row of Input Voltage Range, CMRR parameter in Electrical Characteristics: +1.8 V table ........................... 5
•
Changed footnote to Input Bias Current, IB and IOS parameters in Electrical Characteristics: +1.8 V table ......................... 5
•
Changed Open-Loop Gain, AOL parameter in Electrical Characteristics: +1.8 V table ......................................................... 5
•
Changed Frequency Response, GBW parameter test conditions in Electrical Characteristics: +1.8 V table ...................... 6
•
Changed Frequency Response, SR parameter test conditions in Electrical Characteristics: +1.8 V table ......................... 6
•
Changed Output, VO parameter test conditions in Electrical Characteristics: +1.8 V table .................................................. 6
•
Changed Output, ISC parameter in Electrical Characteristics: +1.8 V table .......................................................................... 6
•
Deleted last row from Power Supply, IQ parameter in Electrical Characteristics: +1.8 V table ............................................ 6
•
Updated Figure 2 ................................................................................................................................................................ 10
Changes from Original (September 2012) to Revision A
•
20
Page
Changed from product preview to production data ............................................................................................................... 1
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Feb-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU NIPDAU
(4)
OPA2313ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
-40 to 125
OP2313
OPA2313IDGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 125
OUSS
OPA2313IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 125
OUSS
OPA2313IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2313
OPA2313IDRGR
ACTIVE
SON
DRG
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SDY
OPA2313IDRGT
ACTIVE
SON
DRG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SDY
OPA313IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SIE
OPA313IDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SIE
OPA313IDCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SIF
OPA313IDCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SIF
OPA4313IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4313
OPA4313IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4313
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Feb-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Feb-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
OPA2313IDGKR
VSSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2313IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA2313IDRGR
SON
DRG
8
1000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA2313IDRGT
SON
DRG
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA313IDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Feb-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2313IDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA2313IDR
SOIC
D
8
2500
340.5
338.1
20.6
OPA2313IDRGR
SON
DRG
8
1000
367.0
367.0
35.0
OPA2313IDRGT
SON
DRG
8
250
210.0
185.0
35.0
OPA313IDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
Pack Materials-Page 2
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