ams AS1151-T Quad lvds receiver Datasheet

a u s t ri a m i c r o s y s t e m s
A S 11 5 0 , A S 11 5 1
Q u a d LV D S R e c e i v e r s
D a ta S he e t
1 General Description
2 Key Features
The AS1150 and AS1151 are quad flow-through LVDS
(low-voltage differential signaling) receivers which
accept LVDS differential inputs and convert them to
LVCMOS outputs. The receivers are perfect for lowpower low-noise applications requiring high signaling
rates and reduced EMI emissions.
The devices are guaranteed to receive data at speeds
up to 500Mbps (250MHz) over controlled impedance
media of approximately 100Ω. Supported transmission
media are PCB traces, backplanes, and cables.
The AS1150 uses high impedance inputs and requires
an external termination resistor when used in a point-topoint connection. The AS1151 features integrated parallel termination resistors (nominally 107Ω), which eliminate the requirement for discrete termination resistors,
and reduce stub lengths.
The integrated failsafe feature sets the output high if the
inputs are open, undriven and terminated, or undriven
and shorted. Enable inputs (EN and ENn – internally
pulled down to GND) control the high-impedance output
and are common to all four receivers. All inputs conform
to the ANSI TIA/EIA- 644 LVDS standards. Flow-through
pinout simplifies PC board layout and reduces crosstalk
by separating the LVDS inputs and LVCMOS outputs.
!
Flow-Through Pinout
!
Guaranteed 500Mbps Data Rate
!
300ps Pulse Skew (Max)
!
Conform to ANSI TIA/EIA-644 LVDS Standards
!
Single +3.3V Supply
!
Operating Temperature Range: -40 to +85ºC
!
Failsafe Circuit
!
Integrated Termination (AS1151)
!
16-pin TSSOP Package
3 Applications
The devices are ideal for digital copiers, laser printers,
cellular phone base stations, add/drop muxes, digital
cross-connects, dslams, network switches/routers,
backplane interconnect, clock distribution computers,
intelligent instruments, controllers, critical microprocessors and microcontrollers, power monitoring, and portable/battery-powered equipment.
The devices are available in a 16-pin TSSOP package.
Figure 1. Block Diagrams
VCC
IN1+
Rx
VCC
IN1+
OUT1
IN1-
IN2+
Rx
IN2+
OUT2
Rx
IN3+
OUT3
Rx
IN4+
OUT4
IN4-
EN
EN
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Rx
107Ω
Rx
107Ω
Rx
OUT2
OUT3
IN3-
IN4-
ENn
107Ω
OUT1
IN2-
IN3-
IN4+
Rx
IN1-
IN2-
IN3+
107Ω
ENn
AS1150
Revision 1.19
OUT4
AS1151
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Data Sheet
4 Absolute Maximum Ratings
Stresses beyond those listed in Table 1 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Section 5 Electrical
Characteristics on page 3 is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 1. Absolute Maximum Ratings
Parameter
Min
Max
Units
VCC to GND
-0.3
+5.0
V
INx+, INx- to GND
-0.3
+5.0
V
EN, ENn to GND
-0.3
VCC + 0.3
V
OUTx to GND
-0.3
VCC + 0.3
V
750
mW
+150
ºC
+150
ºC
Continuous Power Dissipation
(TAMB = +70ºC)
Storage Temperature Range
-65
Maximum Junction Temperature
Notes
Derate 9.4mW/°C Above +70°C
Operating Temperature Range
-40
+85
ºC
ESD Protection
-4
+4
kV
Human Body Model, INx+, INx-
ºC
The reflow peak soldering
temperature (body temperature)
specified is in compliance with
IPC/JEDEC J-STD-020C
“Moisture/ Reflow Sensitivity
Classification for Non-Hermetic
Solid State Surface Mount
Devices”.
Package Body Temperature
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Data Sheet
DC Electrical Characteristics
5 Electrical Characteristics
DC Electrical Characteristics
VCC = +3.0 to +3.6V, Differential Input Voltage |VID| = 0.1 to 1.0V, Common-Mode Voltage VCM = |VID/2| to
1
2.4V - |VID/2|,TAMB = -40 to +85ºC. Typical values are at VCC = +3.3V, TAMB = +25ºC (unless otherwise specified).
Table 2. DC Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
100
mV
LVDS Inputs (INx+, INx-)
Differential Input High
Threshold
VTH
Differential Input Low
Threshold
VTL
Input Current (AS1150)
IINx+,
IINx-
Power-Off Input Current
(AS1150)
IINOFF
-100
mV
0.1V ≤ |VID| ≤ 0.6V
-20
20
µA
0.6V ≤ |VID| ≤ 1.0V
-25
25
µA
0.1V ≤ |VID| ≤ 0.6V, VCC = 0
-20
20
µA
0.6V ≤ |VID| ≤ 1.0V, VCC = 0
-25
25
µA
1
35
kΩ
1
132
kΩ
kΩ
Input Resistor 1 (AS1150)
RIN1
VCC = 3.6V or 0, Figure 16 on page 9
Input Resistor 2 (AS1150)
RIN2
VCC = 3.6V or 0, Figure 16 on page 9
Common Mode Input
Resistance
RINCM
AS1151: Input = 0
150
Differential Input
Resistance
RDIFF
AS1151: VCC = 3.6V or 0, Figure 16 on
page 9
90
107
Open, undriven short, or
undriven 100Ω parallel
termination
2.7
3.2
VID = +100mV
2.7
3.2
Open or Undriven Short
2.7
3.2
VID = +100mV
2.7
132
Ω
LVCMOS/LVTTL Outputs (OUTx)
Output High Voltage
(Table 5)
IOH = -4.0mA
(AS1150)
VOH
IOH = -4.0mA
(AS1151)
Output Low Voltage
VOL
IOL = +4.0mA, VID = -100mV
Output Short-Circuit
2
Current
IOS
Enabled, VID = 0.1V, VOUTx = 0
Output High-Impedance
Current
IOZ
Disabled, VOUTx = 0 or VCC
V
3.2
0.1
0.25
V
15
160
mA
-10
10
µA
2.0
VCC
V
0
0.8
V
-15
15
µA
Logic Inputs (EN, ENn)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Current
IIN
VINx = VCC or 0
Supply
Supply Current
ICC
Disabled Supply Current
ICCZ
Enabled, Inputs Open
5
11
average value, |VID| = 200mV
8
15
Disabled, Inputs Open
300
500
mA
µA
Notes:
1. Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced
to ground except VTH, VTL, and VID.
2. Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
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Data Sheet
AC Electrical Characteristics
AC Electrical Characteristics
VCC = +3.0 to +3.6V, CLOAD = 15pF, Differential Input Voltage |VID| = 0.2 to 1.0V, Common-Mode Voltage VCM = |VID/2|
to 2.4V -|VID/2|, Input Rise and Fall Time = 1ns (20 to 80%), Input Frequency = 100MHz, TAMB = -40 to +85ºC. Typical
values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V, TAMB = +25ºC (unless otherwise specified).
Table 3. AC Electrical Characteristics
1, 2
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Differential Propagation Delay Highto-Low
tPHLD
Figure 18 on page 11 and Figure 19 on
page 12
1.6
2.0
3.1
ns
Differential Propagation Delay Lowto-High
tPLHD
Figure 18 on page 11 and Figure 19 on
page 12
1.6
2.0
3.1
ns
tSKD1
Figure 18 on page 11 and Figure 19 on
page 12
140
300
ps
page 12
400
ps
Differential Pulse Skew
(tPHLD - tPLHD)
3
Differential Channel-to-Channel
4
Skew
tSKD2
5
tSKD3
Figure 18 on page 11 and Figure 19 on
page 12
0.8
ns
6
tSKD4
Figure 18 on page 11 and Figure 19 on
page 12
1.5
ns
Rise Time
tTLH
Figure 18 on page 11 and Figure 19 on
page 12
0.5
1.0
ns
Fall Time
tTHL
Figure 18 on page 11 and Figure 19 on
page 12
0.5
1.0
ns
Disable Time High-to-Z
tPHZ
RLOAD = 2kΩ, Figure 20 on page 12
and Figure 21 on page 12
14
ns
Disable Time Low-to-Z
tPLZ
RLOAD = 2kΩ, Figure 20 on page 12
and Figure 21 on page 12
14
ns
Enable Time Z-to-High
tPZH
RLOAD = 2kΩ, Figure 20 on page 12
and Figure 21 on page 12
70
ns
Enable Time Z-to-Low
tPZL
RLOAD = 2kΩ, Figure 20 on page 12
and Figure 21 on page 12
70
ns
fMAX
All Channels Switching
Differential Part-to-Part Skew
Differential Part-to-Part Skew
Maximum Operating Frequency
7, 8
Figure 18 on page 11 and Figure 19 on
250
300
MHz
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
AC parameters are guaranteed by design and characterization.
CL includes scope probe and test jig capacitance.
tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = |tPHLD - tPLHD|.
tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the same device.
tSKD3 is the magnitude difference of any differential propagation delays between devices operating over rated
conditions at the same VCC and within 5ºC of each other.
tSKD4 is the magnitude difference of any differential propagation delays between devices operating over rated
conditions.
fMAX generator output conditions:
a. Rise time = fall time = 1ns (0 to 100%)
b. 50% duty cycle
c. VOH = +1.3V
d. VOL = +1.1V
Output criteria:
a. Duty cycle = 60% to 40%
b. VOL = 0.4V (max)
c. VOH = 2.7V (min)
d. Load = 15pF
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Data Sheet
AC Electrical Characteristics
6 Typical Operating Characteristics
VCC = +3.3V, VCM = +1.2V, |VID| = 0.2V, CLOAD = 15pF, TAMB = +25ºC, unless otherwise noted.
Figure 2. Supply Current vs. Frequency
Figure 3. Supply Current vs. Temperature
14
100
.
80
All Channels Switching
Supply Current (mA)
Supply Current (mA)
.
90
70
60
50
40
30
20
12
Outputs Low
10
8
Outputs High
6
4
2
10
One Channel Switching
0
0,01
0
0,1
1
10
100
-40
1000
-20
Figure 4. Diff. Threshold Voltage vs. VCC
20
40
60
80
100
Figure 5. Output Short-Circuit Current vs. VCC
120
Output Short-Circuit Current (mA)
.
.
70
Diff. Threshold Voltage (mV)
0
Tem perature (°C)
Frequency (MHz)
60
100
High to Low
50
80
40
Low to High
60
30
40
20
20
10
0
0
3
3,1
3,2
3,3
3,4
3,5
3
3,6
3,1
3,2
3,3
3,4
Supply Voltage (V)
Supply Voltage (V)
Figure 6. Output Low Voltage vs. VCC
Figure 7. Output High Voltage vs. VCC
3,6
3,5
3,6
3,7
Output High Voltage (V) .
Output Low Voltage (mV)
.
110
3,5
109
108
107
106
105
3,5
3,3
3,1
2,9
2,7
3
3,1
3,2
3,3
3,4
3,5
3,6
3
Supply Voltage (V)
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3,1
3,2
3,3
3,4
Supply Voltage (V)
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Data Sheet
AC Electrical Characteristics
Figure 8. Differential Propagation Delay vs. VCC
Figure 9. Differential Propagation Delay vs. Temperature
2,25
Diff. Propagation Delay (ns)
Diff. Propagation Delay (ns)
.
.
2,2
2,16
2,12
tPHLD
2,08
tPLHD
2,04
2,2
2,15
tPLHD
2,1
tPHLD
2,05
2
2
3
3,1
3,2
3,3
3,4
3,5
-45
3,6
-25
Figure 10. Differential Propagation Delay vs. VCM
15
35
55
75
95
Figure 11. Differential Propagation Delay vs. VID
2,3
Diff. Propagation Delay (ns)
.
.
2,5
Diff. Propagation Delay (ns)
-5
Tem perature (°C)
Supply Voltage (V)
2,4
2,3
2,2
tPHLD
2,1
tPLHD
2
1,9
-0,5
2,2
2,1
tPHLD
2
tPLHD
1,9
1,8
0
0,5
1
1,5
2
0,1
2,5
Figure 12. Differential Pulse Skew vs. VCC
1,3
1,7
2,1
2,5
.
400
380
Transition Time (ps)
.
Diff. Pulse Skew (ps)
70
0,9
Figure 13. Transition Time vs. VCC
80
75
0,5
Differential Input Voltage (V)
Common-Mode Voltage (V)
65
60
55
50
tTLH
360
tTHL
340
320
45
300
40
3
3,1
3,2
3,3
3,4
3,5
3
3,6
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3,1
3,2
3,3
3,4
3,5
3,6
Supply Voltage (V)
Supply Voltage (V)
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Data Sheet
AC Electrical Characteristics
Figure 14. Transition Time vs. Temperature
.
500
Transition Time (ps)
450
400
tTLH
350
tTHL
300
250
-45
-25
-5
15
35
55
75
95
Tem perature (°C)
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Data Sheet
Pin Assignments
7 Pinout
Pin Assignments
Figure 15. Pin Assignments (Top View)
IN1-
1
16 EN
IN1+
2
15 OUT1
IN2+
3
14 OUT2
IN2-
4
IN3-
5
IN3+
6
11 OUT3
IN4+
7
10 OUT4
IN4-
8
9 ENn
AS1150
AS1151
13 VCC
12 GND
Pin Descriptions
Table 4. Pin Descriptions
Pin Number
Pin Name
1
IN1-
Inverting Differential Receiver Input
2
IN1+
Noninverting Differential Receiver Input
3
IN2+
Noninverting Differential Receiver Input
4
IN2-
Inverting Differential Receiver Input
5
IN3-
Inverting Differential Receiver Input
6
IN3+
Noninverting Differential Receiver Input
7
IN4+
Noninverting Differential Receiver Input
8
IN4-
Inverting Differential Receiver Input
9
ENn
Receiver Enable Input. Internally pulled down to GND.
When EN = high and ENn = low or open, the receiver outputs are active. For other
combinations of EN and ENn, the outputs are disabled and in high impedance.
10
OUT4
LVCMOS/LVTTL Receiver Output
11
OUT3
LVCMOS/LVTTL Receiver Output
12
GND
Ground
13
VCC
Power-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic
capacitors.
14
OUT2
LVCMOS/LVTTL Receiver Output
15
OUT1
LVCMOS/LVTTL Receiver Output
16
EN
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Description
Receiver Enable Input. Internally pulled down to GND.
When EN = high and ENn = low or open, the receiver outputs are active. For other
combinations of EN and ENn, the outputs are disabled and in high impedance.
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Data Sheet
LVDS Interface
8 Detailed Description
The AS1150 and AS1151 are 500Mbps, four-channel LVDS receivers intended for high-speed, point-to-point, lowpower applications. Each independent channel accepts and converts an LVDS input to an LVTTL/LVCMOS output.
The devices are capable of detecting differential signals from 100mV to 1V within an input voltage range of 0 to 2.4V.
The 250 to 450mV differential output of an LVDS driver is nominally centered around 1.25V. Due to the receiver input
voltage range, a ±1V voltage shift in the signal relative to the receiver is allowed. Thus, a difference in ground references of the transmitter and the receiver, as well as the common mode effect of coupled noise, can be tolerated.
LVDS Interface
The LVDS Interface Standard is a signaling method defined for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, resulting in higher data rates, reduced power consumption
and EMI emissions, and less susceptibility to noise.
The devices fully comply with the LVDS standard input voltage range of 0 to +2.4V referenced to receiver ground.
The AS1151 has an integrated termination resistors connected internally across each receiver input. This internal termination saves board space, eases layout, and reduces stub length compared to an external termination resistor. In
other words, the transmission line is terminated on the IC.
Failsafe Circuit
The devices contain an integrated failsafe circuit to prevent noise at inputs that are open, undriven and terminated, or
undriven and shorted.
Open or undriven terminated input conditions can occur if there is a cable failure or when the LVDS driver outputs are
high impedance. A short condition also can occur because of a cable failure. The failsafe circuit of the AS1150/AS1151
automatically sets the output high if any of these conditions are true.
The failsafe input circuit (see Figure 16) samples the input common-mode voltage and compares it to VCC - 0.3V (nominal). If the input is driven to levels specified in the LVDS standards, the input common-mode voltage is less than VCC 0.3V and the failsafe circuit is not activated. If the inputs are open, undriven and shorted, or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the failsafe circuit pulls both inputs above VCC - 0.3V,
activating the failsafe circuit and thus forcing the device output high.
Figure 16. Failsafe Input Circuit
VCC
VCC
RIN2
RIN2
VCC - 0.3V
VCC - 0.3V
INx+
INx+
RIN1
RIN1
RDIFF
OUTx
RIN1
OUTx
RIN1
INx-
INx-
AS1150
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Data Sheet
9 Applications
Table 5. Function Table
Enable Pins
EN
Input
ENn
H
Output
INx+
L or Open
INx-
OUTx
VID ≥ +100mV
H
VID ≤ +100mV
L
AS1150 – Open, undriven short, or undriven
100Ω parallel termination
H
AS1151 – Open or undriven short
Other Combinations of Enable Pin Settings
Don’t Care
Z
Figure 17. Typical Application Circuit
LVDS
Signals
Tx
107Ω
Rx
Tx
107Ω
Rx
LVTTL/LVCMOS
Data Inputs
LVTTL/LVCMOS
Data Outputs
Tx
107Ω
Rx
Tx
107Ω
Rx
AS1151
AS1152
Quad LVDS Driver
100Ω Shielded Twisted Cable or Microstrip PC Board Traces
Power-Supply Bypassing
To bypass VCC, use high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the
device as possible, with the smaller valued capacitor closest to pin VCC.
Differential Traces
Input trace characteristics can adversely affect the performance of the AS1150 and AS1151.
!
Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor
must also be matched to this characteristic impedance.
!
Eliminate reflections and ensure that noise couples as common mode by running differential traces close together.
!
Reduce skew by using matched trace lengths. Tight skew control is required to minimize emissions and proper
data recovery of the devices.
!
Route each channel’s differential signals very close to each other for optimal cancellation of their respective external magnetic fields. Use a constant distance between the differential traces to avoid irregularities in differential
impedance.
!
Avoid 90° turns (use two 45° turns).
!
Minimize the number of vias to further prevent impedance irregularities.
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Data Sheet
Cables and Connectors
Supported transmission media include printed circuit board traces, backplanes, and cables.
!
Use cables and connectors with matched differential impedance (typically 100Ω) to minimize impedance mismatches.
!
Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic
field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
!
Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable.
Termination
Due to the high data rates of LVDS drivers, matched termination will prevent the generation of any signal reflections,
and reduce EMI.
!
The AS1151 has integrated termination resistors connected across the inputs of each receiver. The value of the
integrated resistor is specified in Table 2 on page 3.
!
The AS1150 requires an external termination resistor. The termination resistor should match the differential impedance of the transmission line and be placed as close to the receiver inputs as possible. Termination resistance values may range between 90 to 132Ω depending on the characteristic impedance of the transmission medium. Use
1% surface-mount resistors.
Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length.
!
Keep the LVDS and any other digital signals separated from each other to reduce crosstalk.
!
Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals.
!
Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent
coupling.
!
Separate the input LVDS signals from the output signals planes with the power and ground planes for best results.
Figure 18. Propagation Delay and Transition Time Test Circuit
INx+
Pulse
Generator**
OUT
INx50Ω
50Ω
CL
Receiver Enabled
1/4 AS1150, AS1151
* 50Ω required for pulse generator.
** When testing the AS1151, adjust the pulse generator output
to account for internal termination resistor.
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Data Sheet
Figure 19. Propagation Delay and Transition Time Waveforms
INxVID
VID = 0
VID = 0
INx+
tPLHD
tPHLD
VOH
VID = (VINx+) - (VINx-)
Note: VCM = (VIN- + VIN+)
2
80
80
50%
50%
20
20
OUTx
tTLH
VOL
tTHL
Figure 20. High Impedance Delay Test Circuit
VCC
INx+
Generator
INx-
EN
50Ω
S1
RL
Device
Under
Test
OUTx
CL
ENn
CL includes load and test JIG capacitance.
S1 = VCC for tPZL and tPLZ measurements.
S1 = GND for tPZH and tPHZ measurements.
Figure 21. High Impedance Delay Waveforms
3V
EN when ENn = GND or Open
1.5V
1.5V
0
3V
1.5V
1.5V
0
ENn when EN = VCC
tPZL
VCC
tPLZ
50%
Output when
VID = -100mV
Output when
VID = +100mV
0.5V
tPHZ
VOL
tPZH
VOH
0.5V
50%
GND
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Data Sheet
Board Layout
10 Package Drawings and Markings
Figure 22. 16-Pin TSSOP Package
1, 2
Symbol
A
A1
A2
L
R
R1
b
b1
c
c1
D
E1
E
0.65mm Lead Pitch
Min
Nom
Max
1.10
0.05
0.15
0.85
0.90
0.95
0.50
0.60
0.75
0.09
0.09
0.19
0.30
0.19
0.22
0.25
0.09
0.20
0.09
0.16
4.90
4.30
5.00
4.40
6.4 BSC
5.10
4.50
1, 2
Note
5
Symbol
θ1
L1
aaa
bbb
ccc
ddd
e
θ2
θ3
Variations
3, 8
e
4, 8
N
0.65mm Lead Pitch
Min
Nom
Max
0º
8º
1.0 Ref
0.10
0.10
0.05
0.20
0.65 BSC
12º Ref
12º Ref
0.65 BSC
16
Note
6
Notes:
1. All dimensions are in millimeters; angles in degrees.
2. Dimensions and tolerancing per ASME Y14.5M-1994.
3. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15mm per side.
4. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm
per side.
5. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm total in excess of
dimension b at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm for 0.5mm pitch packages.
6. Terminal numbers shown are for reference only.
7. Datums A and B to be determined at datum plane H.
8. Dimensions D and E1 to be determined at datum plane H.
9. This dimension applies only to variations with an even number of leads per side. For variations with an odd number
of leads per package, the center lead must be coincident with the package centerline, datum A.
10. Cross section A-A to be determined at 0.10 to 0.25mm from the leadtip.
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Revision 1.19
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austriam i c r o systems
AS1150, AS1151
Data Sheet
Board Layout
11 Ordering Information
Model
Description
Package Type
Delivery Form
AS1150
Quad low-voltage differential signaling receiver
16-pin TSSOP
Tubes
AS1150-T
Quad low-voltage differential signaling receiver
16-pin TSSOP
Tape and Reel
AS1151
Quad low-voltage differential signaling receiver with
integrated termination
16-pin TSSOP
Tubes
AS1151-T
Quad low-voltage differential signaling receiver with
integrated termination
16-pin TSSOP
Tape and Reel
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Revision 1.19
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austriam i c r o systems
AS1150, AS1151
Data Sheet
Board Layout
Copyrights
Copyright © 1997-2006, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information.
This product is intended for use in normal commercial applications. Applications requiring extended temperature
range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for
each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard
production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
A-8141 Schloss Premstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
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austriamicrosystems
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