ISSI IS93C56-3GI 2,048-bit serial electrically erasable prom Datasheet

ISSI
IS93C56-3
2,048-BIT SERIAL ELECTRICALLY
ERASABLE PROM
®
MARCH 2001
FEATURES
OVERVIEW
• State-of-the-art architecture
— Non-volatile data storage
— Low voltage operation:
3.0V (Vcc = 2.7V to 6.0V)
— Full TTL compatible inputs and outputs
— Auto increment for efficient data dump
• Low voltage read operation
— Down to 2.7V
• Hardware and software write protection
— Defaults to write-disabled state at power-up
— Software instructions for write-enable/disable
• Advanced low voltage CMOS E2PROM
technology
• Versatile, easy-to-use Interface
— Self-timed programming cycle
— Automatic erase-before-write
— Programming status indicator
— Word and chip erasable
— Stop SK anytime for power savings
• Durable and reliable
— 10-year data retention after 100K write cycles
— 100,000 write cycles
— Unlimited read cycles
The IS93C56-3 is a low cost 2,048-bit, non-volatile, serial
E2PROM. It is fabricated using ISSI’s advanced CMOS
E2PROM technology. The IS93C56-3 provides efficient
non-volatile read/write memory arranged as 128 registers
of 16 bits each. Seven 11-bit instructions control the
operation of the device, which includes read, write, and
mode enable functions. The data out pin (DOUT) indicates
the status of the device during in the self-timed nonvolatile programming cycle.
The self-timed write cycle includes an automatic erasebefore-write capability. To protect against inadvertent
writes, the WRITE instruction is accepted only while the
chip is in the write enabled state. Data is written in 16 bits
per write instruction into the selected register. If Chip
Select (CS) is brought HIGH after initiation of the write
cycle, the Data Output (DOUT) pin will indicate the READY/
BUSY status of the chip.
APPLICATIONS
The IS93C56-3 is ideal for high-volume applications
requiring low power and low density storage. This device
uses a low cost, space saving 8-pin package. Candidate
applications include robotics, alarm devices, electronic
locks, meters and instrumentation settings.
FUNCTIONAL BLOCK DIAGRAM
DATA
REGISTER
(16 BITS)
INSTRUCTION
REGISTER
(11 BITS)
DIN
CS
SK
DUMMY
BIT
DOUT
R/W
AMPS
INSTRUCTION
DECODE,
CONTROL,
AND
CLOCK
GENERATION
ADDRESS
REGISTER
1 OF 128
DECODER
EEPROM
ARRAY
(128 X 16)
WRITE
ENABLE
HIGH VOLTAGE
GENERATOR
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
04/26/01
1
ISSI
IS93C56-3
PIN CONFIGURATION
PIN CONFIGURATION
PIN CONFIGURATION
8-Pin DIP
8-Pin JEDEC Small Outline “G”
8-Pin JEDEC Small Outline “GR”
CS
1
8
VCC
NC
1
8
NC
CS
1
8
VCC
SK
2
7
NC
VCC
2
7
GND
SK
2
7
NC
DIN
3
6
NC
CS
3
6
DOUT
DIN
3
6
NC
DOUT
4
5
GND
SK
4
5
DIN
DOUT
4
5
GND
®
PIN DESCRIPTIONS
CS
Chip Select
SK
Serial Data Clock
DIN
Serial Data Input
DOUT
Serial Data Output
NC
Not Connected
Vcc
Power
GND
Ground
ENDURANCE AND DATA RETENTION
Low Voltage Read
The IS93C56-3 is designed for applications requiring up to
100,000 programming cycles (WRITE, WRALL, ERASE and
ERAL). It provides 10 years of secure data retention, without
power after the execution of 100,000 programming cycles.
The IS93C56-3 has been designed to ensure that data
read operations are reliable in low voltage environments.
The IS93C56-3 is guaranteed to provide accurate data
during read operations with Vcc as low as 2.7V.
DEVICE OPERATION
Auto Increment Read Operations
The IS93C56-3 is controlled by seven 9-bit instructions.
Instructions are clocked in (serially) on the DIN pin. Each
instruction begins with a logical “1” (the start bit). This is
followed by the opcode (2 bits), the address field (8 bits), and data,
if appropriate. The clock signal (SK) may be halted at any
time and the IS93C56-3 will remain in its last state. This allows
full static flexibility and maximum power conservation.
In the interest of memory transfer operation applications,
the IS93C56-3 has been designed to output a continuous
stream of memory content in response to a single read
operation instruction. To utilize this function, the system
asserts a read instruction specifying a start location address. Once the 16 bits of the addressed word have been
clocked out, the data in consecutively higher address
locations is output. The address will wrap around continuously with CS HIGH until the chip select (CS) control pin is
brought LOW. This allows for single instruction data dumps
to be executed with a minimum of firmware overhead.
Read (READ)
The READ instruction is the only instruction that outputs
serial data on the DOUT pin. After the read instruction and
address have been decoded, data is transferred from the
selected memory register into a 16-bit serial shift register.
(Please note that one logical “0” bit precedes the actual
16-bit output data string.) The output on DOUT changes
during the low-to-high transitions of SK (see Figure 3).
2
Write Enable (WEN)
The write enable (WEN) instruction must be executed
before any device programming (WRITE, WRALL, ERASE,
and ERAL) can be done. When Vcc is applied, this device
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
04/26/01
ISSI
IS93C56-3
powers up in the write disabled state. The device then
remains in a write disabled state until a WEN instruction
is executed. Thereafter, the device remains enabled until
a WDS instruction is executed or until Vcc is removed.
(NOTE: Neither the WEN nor the WDS instruction has any
effect on the READ instruction.) (See Figure 4.)
Write (WRITE)
The WRITE instruction includes 16 bits of data to be
written into the specified register. After the last data bit
has been applied to DIN, and before the next rising edge of
SK, CS must be brought LOW. The falling edge of CS
initiates the self-timed programming cycle.
After a minimum wait of 250 ns (5V operation) from the
falling edge of CS (tCS), if CS is brought HIGH, DOUT will
indicate the READY/BUSY status of the chip: logical “0”
means programming is still in progress; logical “1” means
the selected register has been written, and the part is
ready for another instruction (see Figure 5). (NOTE: The
combination of CS HIGH, DIN HIGH and the rising edge of
the SK clock, resets the READY/BUSY flag. Therefore, it
is important if you want to access the READY/BUSY flag
, not to reset it through this combination of control
signals.) Before a WRITE instruction can be executed, the
device must be write enabled (see WEN).
Write All (WRALL)
The write all (WRALL) instruction programs all registers
with the data pattern specified in the instruction. While the
®
WRALL instruction is being loaded, the address field
becomes a sequence of “Don’t Care” bits (see Figure 6).
As with the WRITE instruction, if CS is brought HIGH after
a minimum wait of 250 ns (tCS), the DOUT pin indicates the
READY/BUSY status of the chip (see Figure 6).
Write Disable (WDS)
The write disable (WDS) instruction disables all programming capabilities. This protects the entire part against
accidental modification of data until a WEN instruction is
executed. (When Vcc is applied, this part powers up in the
write disabled state.) To protect data, a WDS instruction
should be executed upon completion of each programming
operation. (NOTE: Neither the WEN nor the WDS instruction
has any effect on the READ instruction.) (See Figure 7.)
Erase Register (ERASE)
After the erase instruction is entered, CS must be brought
LOW. The falling edge of CS initiates the self-timed internal
programming cycle. Bringing CS HIGH after a minimum of
tCS, will cause DOUT to indicate the READ/BUSY status of
the chip: a logical “0” indicates programming is still in
progress; a logical “1” indicates the erase cycle is complete
and the part is ready for another instruction (see Figure 8).
Erase All (ERAL)
Full chip erase is provided for ease of programming.
Erasing the entire chip involves setting all bits in the entire
memory array to a logical “1” (see Figure 9).
INSTRUCTION SET
Instruction
Start Bit
OP Code
Address
Input Data
READ
1
10
X(A6-A0)
WEN
(Write Enable)
1
00
11XXXXXX
WRITE
1
01
X(A6-A0)
D15-D0(1)
WRALL
(Write All Registers)
1
00
01XXXXXX
D15-D0(1)
WDS
(Write Disable)
1
00
00XXXXXX
ERASE
1
11
X(A6-A0)
ERAL
(Erase All Registers)
1
00
10XXXXXX
Note: 1. If input data is not 16 bits exactly, the last 16 bits will be taken as input data (a word).
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
04/26/01
3
ISSI
IS93C56-3
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VGND
TBIAS
TBIAS
TSTG
Parameter
Voltage with Respect to GND
Temperature Under Bias (IS93C56-3)
Temperature Under Bias (IS93C56-3I)
Storage Temperature
Value
–0.3 tp +6.5
0 to +70
–40 to +85
–65 to +125
Unit
V
°C
°C
°C
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
2.7V to 6.0V
2.7V to 6.0V
CAPACITANCE
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
5
pF
VOUT = 0V
5
pF
FIGURE 1. AC TEST CONDITIONS
+2.08V
800Ω
DOUT
100 pF
Vcc = 5.0V
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
04/26/01
ISSI
IS93C56-3
®
DC ELECTRICAL CHARACTERISTICS
TA = 0°C to +70°C for IS93C56-3 and –40°C to +85°C for IS93C56-3I.
Symbol
Parameter
Test Conditions
VOL
Output LOW Voltage
IOL = 10 µA CMOS
VOL1
Output LOW Voltage
VOH
Vcc
Min.
Max.
Unit
2.7V to 3.3V
—
0.2
V
IOL = 2.1 mA TTL
4.5V to 5.5V
—
0.4
V
Output HIGH Voltage
IOH = –10 µA CMOS
2.7V to 3.3V
VCC – 0.2
—
V
VOH1
Output HIGH Voltage
IOH = –400 µA TTL
4.5V to 5.5V
2.4
—
V
VIH
Input HIGH Voltage
2.7V to 3.3V
4.5V to 5.5V
2.4
2
V CC
VCC
V
VIL
Input LOW Voltage
2.7V to 3.3V
4.5V to 5.5V
-0.1
–0.1
0.6
0.8
V
ILI
Input Leakage
VIN = 0V to VCC (CS, SK, DIN)
1
1
µA
ILO
Output Leakage
VOUT = 0V to VCC, CS = 0V
1
1
µA
POWER SUPPLY CHARACTERISTICS
TA = 0°C to +70°C for IS93C56-3 and –40°C to +85°C for IS93C56-3I.
IS93C56-3I
Min. Typ. Max.
Parameter
Test Conditions
ICC
Vcc Operating
Supply Current
CS = VIH, SK = 500 KHz
CMOS Input Levels
2.7V to 3.3V
—
0.5
2
—
0.5
2
mA
ICC
Vcc Operating
Supply Current
CS = VIH, SK = 1 MHz
CMOS Input Levels
4.5V to 5.5V
—
4
6
—
4
6
mA
ISB
Standby Current
CS = DIN = SK = 0V
2.7V to 3.3V
4.5V to 5.5V
—
—
2
10
10
50
—
—
2
10
10
50
µA
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
04/26/01
Vcc
IS93C56-3
Min. Typ. Max.
Symbol
Unit
5
ISSI
IS93C56-3
®
AC ELECTRICAL CHARACTERISTICS
TA = 0°C to +70°C for IS93C56-3 and –40°C to +85°C for IS93C56-3.
6
Test Conditions
IS93C56-3
Min. Max.
Vcc
IS93C56-3I
Min. Max.
Symbol
Parameter
Unit
fSK
SK Clock Frequency
2.7V to 6.0V
4.5V to 6.0V
0
0
0.5
1
0
0
0.5
1
MHz
MHz
tSKH
SK HIGH Time
2.7V to 6.0V
4.5V to 6.0V
500
250
—
—
500
250
—
—
ns
tSKL
SK LOW Time
2.7V to 6.0V
4.5V to 6.0V
1
250
—
—
1
250
—
—
µs
ns
tCS
Minimum CS LOW Time
2.7V to 6.0V
4.5V to 6.0V
500
250
—
—
500
250
—
—
ns
tCSS
CS Setup Time
Relative to SK
2.7V to 6.0V
4.5V to 6.0V
100
50
—
—
100
50
—
—
ns
ns
tDIS
DIN Setup Time
Relative to SK
2.7V to 6.0V
4.5V to 6.0V
200
100
—
—
200
100
—
—
ns
ns
tCSH
CS Hold Time
Relative to SK
2.7V to 6.0V
4.5V to 6.0V
0
0
—
—
0
0
—
—
ns
tDIH
DIN Hold Time
Relative to SK
2.7V to 6.0V
4.5V to 6.0V
400
100
—
—
400
100
—
—
ns
tPD1
Output Delay to “1”
AC Test
2.7V to 6.0V
4.5V to 6.0V
—
—
500
500
—
—
500
500
ns
tPD0
Output Delay to “0”
AC Test
2.7V to 6.0V
4.5V to 6.0V
—
—
500
500
—
—
500
500
ns
tSV
CS to Status Valid
AC Test, CL = 100 pF
2.7V to 6.0V
4.5V to 6.0V
—
—
500
500
—
—
500
500
ns
tDF
CS to DOUT in 3-state
CS = VIL
2.7V to 6.0V
4.5V to 6.0V
—
—
200
100
—
—
200
100
ns
tWP
Write Cycle Time
2.7V to 6.0V
4.5V to 6.0V
—
—
10
10
—
—
10
10
ms
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
04/26/01
ISSI
IS93C56-3
®
AC WAVEFORMS
FIGURE 2. SYNCHRONOUS DATA TIMING
CS
T
tCSS
tSKH
tSKL
tCSH
SK
tDIS
tDIH
DIN
tPD0
tPD1
tDF
DOUT
(READ)
tSV
tDF
DOUT
(WRITE)
(WRALL)
(ERASE)
(ERAL)
STATUS VALID
FIGURE 3. READ CYCLE TIMING
tCS
CS
SK
DIN
1
1
0
X
A6...A1
DOUT
A0
0
D15
D0
*
*Address Pointer Cycles to the Next Register
X is a don't care bit
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
04/26/01
7
ISSI
IS93C56-3
®
FIGURE 4. SYNCHRONOUS DATA TIMING
tCS
CS
SK
DIN
1
0
0
1
1
DOUT = 3-state
FIGURE 5. WRITE (WRITE) CYCLE TIMING
tCS
CS
SK
DIN
1
0
1
X
A6...A1
A0
D15
D0
tSV
DOUT
tDF
BUSY
READY
tWP
X is a don't care bit
FIGURE 6. WRITE ALL (WRALL) TIMING
tCS
CS
SK
DIN
1
0
0
0
1
D15
D0
tSV
DOUT
BUSY
READY
tWP
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
04/26/01
ISSI
IS93C56-3
®
FIGURE 7. WRITE DISABLE (WDS) CYCLE TIMING
tCS
CS
SK
DIN
1
0
0
0
0
DOUT = 3-STATE
FIGURE 8. ERASE (REGISTER ERASE) CYCLE TIMING
SK
tCS
CS
DIN
1
1
1
X
A6
A0
tSV
DOUT
tDF
BUSY
X is a don't care bit
READY
tWP
FIGURE 9. ERASE ALL (ERAL) CYCLE TIMING
SK
tCS
CS
DIN
1
0
0
1
0
tSV
DOUT
BUSY
tDF
READY
tWP
Note for Figures 8 and 9:
After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT
indicates BUSY status) then performs another instruction would cause device malfunction.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
04/26/01
9
ISSI
IS93C56-3
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (MHz) Order Part No.
1
1
1
IS93C56-3P
IS93C56-3G
IS93C56-3GR
Package
300-mil Plastic DIP
Small Outline (JEDEC)
Small Outline (JEDEC)
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (MHz) Order Part No.
1
1
1
IS93C56-3PI
IS93C56-3GI
IS93C56-3GRI
Package
300-mil Plastic DIP
Small Outline (JEDEC)
Small Outline (JEDEC)
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
04/26/01
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