LINER LTC3829 2-phase, high efficiency dc/dc controller for intel mobile cpus Datasheet

LTC3735
2-Phase, High Efficiency
DC/DC Controller for
Intel Mobile CPUs
DESCRIPTION
FEATURES
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Output Stages Operate Antiphase
±1% Output Voltage Accuracy
6-Bit IMVP-IV VID Code: VOUT = 0.7V to 1.708V
Intel Compatible Power Saving Mode (PSIB)
Stage Shedding Improves Low Current Efficiency
Power Good Output with Adaptive Masking
Lossless Voltage Positioning
Dual Input Supply Capability for Load Sharing
Resistor Programmable VOUT at Boot-Up and Deeper
Sleep State
Resistor Programmable Deep Sleep Offset
Programmable Fixed Frequency: 210kHz to 550kHz
Adjustable Soft-Start Current Ramping
Foldback Output Current Limit
Short-Circuit Shutdown Timer with Defeat Option
Overvoltage Protection
Available in 36-Lead SSOP (0.209 Wide) and 38-Lead
(5mm × 7mm) Packages
The LTC®3735 is a 2-phase synchronous step-down
switching regulator controller that drives all N-channel
power MOSFETs in a constant frequency architecture. The
output voltage is programmable by six VID bits during
normal operation and by external resistors during initial
boot-up and deeper sleep state. The LTC3735 drives its two
output stages out-of-phase at frequencies up to 550kHz
to minimize the RMS ripple currents in both input and
output capacitors. This antiphase technique also doubles
the apparent switching frequency, improving the transient
response while operating each phase at an optimum frequency for efficiency. Thermal design is further simplified
by cycle-by-cycle current sharing between the two phases.
An Intel compatible PSIB input is provided to select between
two modes of operation. Fully enhanced synchronous
mode achieves a very small output ripple and very fast
transient response while power saving mode realizes
very high efficiency. OPTI-LOOP® compensation allows
the transient response to be optimized for a wide range
of output capacitance and ESR values.
APPLICATIONS
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Mobile and Desktop Computers
Internet Servers
L, LT, LTC, LTM, OPTI-LOOP, PolyPhase, Linear Technology and the Linear logo are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
TYPICAL APPLICATION
MCH_PG
DPRSLPVR
STP_CPUB
PSIB
FREQSET
VID5-VID0
PGOOD
ITH
RC
4.74k
CC
470pF
100pF
232k
BG1
1µH
M2
0.002Ω
VIN
5V TO 24V
D1
PGND
SENSE1+
SENSE1–
RUN/SS
+
M3
TG2
1µH
SW2
0.1µF
SGND
VOA+
M1
TG1
SW1
M4
BG2
0.002Ω
COUT
330µF
2V
×5
VOUT
0.7V TO 1.708V
40A
CIN
10µF
35V
×4
D2
LTC3735
PVCC
4.5V TO 7V
SENSE2+
SENSE2–
4.7µF
RBOOT
BAT54A
0.47µF
0.47µF
SW2
SW1
BOOST1 RDPRSLP
BOOST2 RDPSLP
VOA+
OAOUT
VOA–
12.7k
13.3k
56.2k
1.27M
13.3k
549k
VOA+
3735 F01
Figure 1. High Current 2-Phase Step-Down Converter
3735fa
1
LTC3735
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage (PVCC)........................ 7V to – 0.3V
Topside Driver Voltages (BOOST1,2).......... 38V to –0.3V
Switch Voltage (SW1, 2)................................ 32V to –5V
Boosted Driver Voltages
(BOOST1-SW1, BOOST2-SW2)................ 7V to –0.3V
DPRSLPVR, STP_CPUB, MCH_PG, PGOOD,
RDPRSLP, RDPSLP, RBOOT Voltages .......... 5V to –0.3V
RUN/SS, PSIB, FREQSET Voltages ..............7V to – 0.3V
VID0-VID5 Voltages .....................................5V to – 0.3V
VFB, Voltage................................................. 2V to –0.3V
VOA+, VOA– ................................................ 3.6V to –0.3V
Peak Gate Drive Current <1µs
(TG1, TG2, BG1, BG2)..................................................5A
Operating Ambient Temperature Range
(Note 2) .................................................... –40°C to 85°C
Junction Temperature (Note 3).............................. 125°C
Storage Temperature Range
SSOP.................................................. –65°C to 150°C
QFN..................................................... –65°C to 125°C
QFN Reflow Peak Body Temperature..................... 260°C
Lead Temperature (Soldering, 10 sec)................... 300°C
PIN CONFIGURATION
TOP VIEW
MCH_PG
DPRSLPVR
TOP VIEW
35 PGOOD
3
34 BOOST1
PSIB
4
33 TG1
FREQSET 1
VOA+
5
32 SW1
PSIB 2
30 BOOST2
VOA–
6
31 BOOST2
VOA+ 3
29 TG2
OAOUT
7
30 TG2
VOA– 4
28 SW2
29 SW2
OAOUT 5
27 PVCC
28 PVCC
STP_CPUB 6
SENSE2+ 12
25 BG2
SENSE2– 13
24 VID5
RDPRSLP 14
23 VID4
RDPSLP 15
22 VID3
RUN/SS 16
21 VID2
ITH 17
20 VID1
RBOOT 18
19 VID0
24 BG2
SENSE1– 9
23 VID5
SENSE2+ 10
22 VID4
SENSE2– 11
21 VID3
20 VID2
RDPRSLP 12
13 14 15 16 17 18 19
VID1
26 PGND
VID0
11
25 PGND
SENSE1+ 8
RBOOT
27 BG1
ITH
10
SENSE1–
26 BG1
39
SGND 7
RUN/SS
9
SENSE1+
31 NC
NC
SGND
8
38 37 36 35 34 33 32
RDPSLP
STP_CPUB
SW1
2
FREQSET
TG1
DPRSLPVR
BOOST1
36 MCH_PG
PGOOD
1
VFB
VFB
UHF PACKAGE
38-LEAD (7mm × 5mm) PLASTIC QFN
G PACKAGE
36-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS SIGNAL GROUND, MUST BE CONNECTED TO PCB AND SGND
TJMAX = 125°C, θJA = 85°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3735EG#PBF
LTC3735EG#TRPBF
LTC3735
36-Lead Plastic SSOP
–40°C to 85°C
LTC3735EUHF#PBF
LTC3735EUHF#TRPBF
LTC3735
38-Lead (7mm × 5mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3735fa
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LTC3735
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VPVCC = 5V, VRUN/SS = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
Reference
Regulated Feedback Voltage
ITH Voltage = 0.5V; Measured at VFB (Note 4)
VSENSEMAX
Maximum Current Sense Threshold
ITH Voltage = Max; VCM = 1.7V
VLOADREG
Output Voltage Load Regulation
VREFLNREG
Reference Voltage Line Regulation
VPSIB
Forced Continuous Threshold
IPSIB
Forced Continuous Current
VPSIB = 0V
VOVL
Output Overvoltage Threshold
Measured with Respect to VFB = 0.6V
gm
Transconductance Amplifier gm
ITH = 1.2V, Sink/Source 25µA (Note 4)
gmOL
Transconductance Amplifier Gain
ITH = 1.2V, (gm • ZL; No Ext Load) (Note 4)
VACTIVE
Output Voltage in Active Mode
VID = 010110, ITH = 0.5V (0°C to 85°C)
VID = 010110, ITH = 0.5V (Note 2)
0.600
72
85
mV
(Note 4)
Measured in Servo Loop, ∆ITH Voltage: 1.2V to 0.7V l
l
Measured in Servo Loop, ∆ITH Voltage: 1.2V to 2V
0.1
–0.1
0.5
–0.5
%
%
VPVCC = 4.5V to 7V
0.02
0.1
%/V
l
59
V
0.57
0.64
l
4.5
0.6
0.63
V
–0.5
–1
µA
0.66
0.68
V
6
7.5
mmho
3
l
1.342
1.336
V/mV
1.356
1.356
1.370
1.376
2
20
3
100
V
V
Input DC Supply Current
Normal Mode
Shutdown
(Note 5)
UVR
Undervoltage RUN/SS Reset
PVCC Lowered Until the RUN/SS Pin is Pulled Low
3.2
3.7
4.2
V
IRUN/SS
Soft-Start Charge Current
VRUN/SS = 1.9V
–2.3
–1.5
–0.8
µA
VRUN/SS
RUN/SS Pin ON Threshold
VRUN/SS Rising
1.0
1.5
1.9
V
IQ
VRUN/SSARM RUN/SS Pin Latchoff Arming
VRUN/SS = 0V
mA
µA
VRUN/SS Rising from 3V
3.9
V
3.2
V
VRUN/SSLO
RUN/SS Pin Latchoff Threshold
VRUN/SS, Ramping Negative
ISCL
RUN/SS Discharge Current
Soft-Short Condition VFB = 0.375V, VRUN/SS = 4.5V
ISDLHO
Shutdown Latch Disable Current
VFB = 0.375V, VRUN/SS = 4.5V
ISENSE
Total Sense Pins Source Current
Each Channel: VSENSE1–, 2– = VSENSE1+, 2+ = 0V
–85
–60
µA
DFMAX
Maximum Duty Factor
In Dropout, VSENSEMAX ≤ 45mV
95
98.5
%
TG1, 2 tr
TG1, 2 tf
Top Gate Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
30
40
90
90
ns
ns
BG1, 2 tr
BG1, 2 tf
Bottom Gate Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
60
50
90
90
ns
ns
–5
–1.5
1.5
µA
5
µA
TG/BG t1D
Top Gate Off to Bottom Gate On Delay CLOAD = 3300pF Each Driver (Note 6)
Synchronous Switch-On Delay Time
50
ns
BG/TG t2D
Bottom Gate Off to Top Gate On Delay CLOAD = 3300pF Each Driver (Note 6)
Top Switch-On Delay Time
60
ns
tON(MIN)
Minimum On-Time
100
ns
Tested with a Square Wave (Note 7)
VID Parameters
RATTEN
VID Top Resistance
ATTENERR
Resistive Divider Error
VIDTHLOW
VID0 to VID5 Logic Threshold Low
VIDTHHIGH
VID0 to VID5 Logic Threshold High
VIDLEAK
VID0 to VID5 Leakage
5.33
(Note 8)
l
–0.25
kΩ
0.25
%
0.3
V
±1
µA
0.7
V
3735fa
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LTC3735
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VPVCC = 5V, VRUN/SS = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
IFREQSET
FREQSET Input Current
VFREQSET = 0V
MIN
TYP
MAX
UNITS
–2
–1
µA
Oscillator
fNOM
Nominal Frequency
VFREQSET = 1.2V
320
355
390
kHz
fLOW
Lowest Frequency
VFREQSET = 0V
190
210
240
kHz
fHIGH
Highest Frequency
VFREQSET ≥ 2.4V
490
550
610
kHz
0.1
0.3
V
±1
µA
PGOOD Output
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
VPG
PGOOD Trip Thresholds
VFB with Respect to Set Output Voltage
VFB Ramping Negative
VFB Ramping Positive
tMASK
PGOOD Mask Timer
tDELAY
MCH_PG Delay Time
–7
7
–10
11
–13
13
%
%
100
110
120
µs
15
cycles
Operational Amplifier
IB
Input Bias Current
VOS
Input Offset Voltage Magnitude
CM
Common Mode Input Voltage Range
VOA+ = VOA– 1.2V, IOUT = 1mA
15
200
nA
0.8
5
mV
PVCC – 1.4
0
46
70
dB
10
35
mA
IOUT = 1mA
30
V/mV
Gain-Bandwidth Product
IOUT = 1mA
2
MHz
Slew Rate
RL = 2k
5
V/µs
Maximum High Output Voltage
IOUT = 1mA
CMRR
Common Mode Rejection Ratio
ICL
Output Source Current
AVOL
Open-Loop DC Gain
GBP
SR
VO(MAX)
IOUT = 1mA
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3735E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
LTC3735EG: TJ = TA + (PD • 85°C/W)
LTC3735EUHF: TJ = TA + (PD • 34°C/W)
PVCC – 1.2 PVCC – 0.9
V
Note 4: The LTC3735 is tested in a feedback loop that servos VITH to a
specified voltage and measures the resultant VFB.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition corresponds to the on inductor
peak-to-peak ripple current ≥40% IMAX (see Minimum On-Time
Considerations in the Applications Information section).
Note 8: The ATTENERR specification is in addition to the output voltage
accuracy specified at VID code = 010110.
3735fa
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LTC3735
TYPICAL PERFORMANCE CHARACTERISTICS
Active Mode Efficiency
(Figure 14)
100
90
VID = 1.468V
PSI = 0
Efficiency vs Input Voltage
(Figure 14)
100
PSI = 0
VIN = 7.5V
80
VIN = 7.5V
80
EFFICIENCY (%)
VIN = 20V
VIN = 20V
70
70
60
0
5
10
15
20
LOAD CURRENT (A)
25
60
0.01
30
15
10
INPUT VOLTAGE (V)
5
20
3735 G03
Maximum Current Sense
Threshold vs Percent of Nominal
Output Voltage (Foldback)
75
80
70
ON
2000
60
1500
1000
50
VSENSE (mV)
VSENSE (mV)
SUPPLY CURRENT (µA)
50
10
0.1
1
LOAD CURRENT (A)
Maximum Current Sense
Threshold vs Duty Factor
2500
25
50
40
30
20
500
10
SHUTDOWN
0
7
6
5
PVCC VOLTAGE (V)
4
0
20
40
60
DUTY FACTOR (%)
80
Maximum Current Sense
Threshold vs VRUN/SS (Soft-Start)
80
0
100
50
100
0
25
75
PERCENT OF NOMINAL OUTPUT VOLTAGE (%)
3735 G05
3735 G04
3735 G06
Maximum Current Sense Threshold
vs Sense Common Mode Voltage
76
VSENSE(CM) = 1.25V
90
Current Sense Threshold
vs ITH Voltage
80
70
70
60
72
40
30
60
VSENSE (mV)
50
VSENSE (mV)
VSENSE (mV)
70
3735 G02
Supply Current vs PVCC Voltage
and Mode
68
50
40
30
20
10
20
64
0
–10
10
0
80
60
3735 G01
0
IOUT = 20A
VOUT = 1.6V
90
EFFICIENCY (%)
90
EFFICIENCY (%)
Deeper Sleep Mode Efficiency
(Figure 14)
–20
0
1
2
3
VRUN/SS (V)
4
5
3735 G07
60
0
1
3
4
2
COMMON MODE VOLTAGE (V)
5
3735 G08
–30
0
0.5
1
1.5
VITH (V)
2
2.5
3735 G09
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LTC3735
TYPICAL PERFORMANCE CHARACTERISTICS
Load Regulation (Without AVP)
SENSE Pins Total Source Current
100
VPSIB = 5V
VIN = 15V
FIGURE 1
50
–0.1
ISENSE (µA)
NORMALIZED VOUT (%)
0.0
–0.2
–50
–0.3
–0.4
0
0
5
15
10
LOAD CURRENT (A)
20
–100
25
2
0
4
6
VSENSE COMMON MODE VOLTAGE (V)
3735 G12
3735 G10
Maximum Current Sense
Threshold vs Temperature
Current Sense Pin Input Current
vs Temperature
RUN/SS Current vs Temperature
78
–12
CURRENT SENSE INPUT CURRENT (µA)
1.8
1.6
RUN/SS CURRENT (µA)
VSENSE (mV)
76
74
72
70
1.4
1.2
1.0
0.8
0.6
0.4
0.2
68
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
3735 G13
FREQUENCY (kHz)
VOUT(AC)
20mV/DIV
VFREQSET = 2.4V
VFREQSET = 1.2V
–8
–7
–50 –25
3735 G17
125
100
Start-Up Sequence (Figure 14)
PGOOD
2V/DIV
2µs/DIV
100
50
0
75
25
TEMPERATURE (°C)
3735 G18
VCC – CORE
500mV/DIV
VPSIB = 0V
VFREQSET = 0V
50
25
75
0
TEMPERATURE (°C)
–9
VRON
2V/DIV
IL2
1A/DIV
300
100
– 50 – 25
VIN = 15V, VOUT = 1.6V, ILOAD = 400mA
IL1
1A/DIV
500
200
–10
Constant Frequency Low Current
Mode (Figure 14)
700
400
–11
3735 G14
Oscillator Frequency
vs Temperature
600
125
VOUT = 1.6V
MCH –PGOOD
2V/DIV
C1 MAX
3.28V V
BOOT = 1.37V
VID = 1.228V
C2 MAX
1.37V
C3 MAX
3.24V
C4 MAX
3.20V
500µs/DIV
3735 G16
125
3735 G19
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LTC3735
TYPICAL PERFORMANCE CHARACTERISTICS
VRUN/SS Shutdown Latch
Thresholds vs Temperature
Load Step (Figure 14)
VID Transition (Figure 14)
SHUTDOWN LATCH THRESHOLDS (V)
4.5
VIDs
LATCH ARMING
4.0
3.0
IOUT
10A/DIV
LATCHOFF
THRESHOLD
2.5
0
1.356V
32A
3.5
VOUT
200mV
/DIV
7.2A
0.844V
1.364V
VOUT
100mV/DIV
1.230V
2.0
1.5
1
PGOOD
2V/DIV
1.0
0.5
0
–50
20s/DIV
–25
0
25
50
75
TEMPERATURE (°C)
100
3735 G22
50s/DIV
3735 G23
125
3735 G21
PIN FUNCTIONS
(G/UHF)
VFB (Pin 1/Pin 37): Input to the error amplifier that compares the feedback voltage to the internal 0.6V reference
voltage.
DPRSLPVR (Pin 2/Pin 38): Deeper Sleep State Input.
When the signal to this pin is high, the voltage regulator
enters deeper sleep state and its output is determined
by the parallel resistor value of RDPRSLP and RDPSLP.
When the signal is low, the voltage regulator exits deeper
sleep state.
FREQSET (Pin 3/Pin 1): Frequency Set Pin. Apply a DC
voltage between 0V and 5V to set the operating frequency
of the internal oscillator. This frequency is the switching
frequency of each phase.
PSIB (Pin 4/Pin 2): Power Status Indicator Input. When
the signal to this pin is high, both channels operate in fully
synchronous switching mode for fastest transient and
lowest ripple. When the signal is low, controller enters
power saving mode, providing high efficiency at light load.
VOA+, VOA– (Pins 5, 6/Pins 3, 4): Inputs to the Internal
Operational Amplifier.
OAOUT (Pin 7/Pin 5): Output of the Internal Operational
Amplifier.
STP_CPUB (Pin 8/Pin 6): Deep Sleep State Input. When the
signal to this pin is low, the voltage regulator enters deep
sleep state and its output voltage is a certain percentage
lower than the VID commands. This offset percentage is
set by the resistor connected to the RDPSLP pin. When
the signal to this pin is high, the voltage regulator exits
deep sleep state.
SGND (Pin 9/Pin 7): Signal Ground. This pin is common
to both controllers. Route separately to the PGND pin.
SENSE1+, SENSE2+ (Pins 10,12/Pins 8, 9): The (+) Input
to Each Differential Current Comparator. The ITH pin voltage
and built-in offsets between SENSE– and SENSE+ pins in
conjunction with RSENSE set the current trip threshold.
SENSE1–, SENSE2– (Pins 11,13/Pins 10, 11): The (–)
Input to Each Differential Current Comparator.
RDPRSLP (Pin 14/Pin 12): Deeper Sleep State Resistor
Pin. Connect a resistor from this pin to VOA+. This resistor in conjunction with RDPSLP resistor sets the output
voltage of the regulator in deeper sleep state.
RDPSLP (Pin 15/Pin 14): Deep Sleep Resistor Pin. Connect a resistor from this pin to VOA+. This resistor sets the
percentage offset of output voltage in deep sleep state.
3735fa
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LTC3735
PIN FUNCTIONS
(G/UHF)
RUN/SS (Pin 16/Pin 15): Combination of Soft-Start,
Run Control Input and Short-Circuit Detection Timer. A
capacitor to ground at this pin sets the ramp time to full
current output. Forcing this pin below 1V causes the IC to
shut down all internal circuitry. All functions are disabled
in shutdown.
ITH (Pin 17/Pin 16): Error Amplifier Output and Switching
Regulator Compensation Point. Both current comparator’s
thresholds increase with this control voltage. The normal
voltage range of this pin is from 0V to 2.4V
RBOOT (Pin 18/Pin 17): Boot-Up Resistor Pin. Connect a
resistor from this pin to VOA+. This resistor sets the output
voltage during the initial boot-up.
VID0–VID5 (Pins 19, 20, 21, 22, 23, 24/Pins 18, 19, 20,
21, 22, 23): VID Control Logic Input Pins.
BG2, BG1 (Pins 25, 27/Pins 24, 26): High Current Gate
Drives for Bottom N-Channel MOSFETs. Voltage swing at
these pins is from ground to PVCC.
PGND (Pin 26/Pin 25): Driver Power Ground. Connect
to sources of bottom N-channel MOSFETs and the (–)
terminals of CIN.
PVCC (Pin 28/Pin 27): Power Supply Pin. The internal
control circuits and on-chip gate drivers are powered from
this voltage source. Decouple to PGND with a minimum of
4.7µF X5R/X7R ceramic capacitor placed directly adjacent
to the IC.
SW2, SW1 (Pins 29, 32/Pins 28, 32): Switch Node Connections to Inductors. Voltage swing at these pins is from a
Schottky diode (external) voltage drop below ground to VIN.
TG2, TG1 (Pins 30, 33/Pins 29, 33): High Current Gate
Drives for Top N-Channel MOSFETs. These are the outputs
of floating drivers with a voltage swing equal to PVCC
superimposed on the switch node voltage SW.
BOOST2, BOOST1 (Pins 31, 34/Pins 30, 34): Bootstrapped
Supplies to the Topside Floating Drivers. External capacitors are connected between the BOOST and SW pins, and
Schottky diodes are connected between the BOOST and
PVCC pins.
PGOOD (Pin 35/Pin 35): Power Good Indicator Output.
This pin is open drain when output is within ±10% of its
set point. When output is not within the ±10% window,
this pin is pulled to ground. An internal timer watches
over VID, state transitions overvoltage or undervoltage
conditions, then masks PGOOD from going low for 110µs.
MCH_PG (Pin 36/Pin 36): MCH Power Good Input. Output
voltage remains VBOOT for 15 clock cycles after the assertion of MCH_PG. This delay is only sensitive to the rising
edge of the MCH_PG logic signal.
SGND (Exposed Pad Pin 39, UHF Only): Signal Ground.
Connect to Pins 7 and 25. The Exposed Pad must be
soldered to the PCB.
NC (Pins 13, 31, UHF Only): No Connect.
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8
LTC3735
FUNCTIONAL DIAGRAM
R3
R4
MCH_PG
R6
RDPSLP
STP_CPUB
R5
DPRSLPVR
RDPRSLP
MD
DELAY
FREQSET
CLK1
OSCILLATOR
CLK2
TO SECOND
CHANNEL
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
BOOST
DROP
OUT
DET
–
0.66V
+
RUN
VFB
–
+
VOA+
S
Q
R
Q
BOT
DB
CB
+
D1
PSI
TOP ON
SWITCH
LOGIC
PVCC
BOT
0.54V
BG
COUT
+
DPRSLPVR
A1
SHDN
I1
OAOUT
–
+
–
++
–
–
0.5µA
PVCC
I2
+
36k SENSE
+
–
36k SENSE
SLOPE
COMP
PSIB
+
–
54k
54k
VFB
2.4V
PSI
–
EA
+
VREF
0.60V
VOUT
RSENSE
L
5.33(VFB)
3V
CIN
SW
–
VOA–
OV
5V
TG
TOP
VIN
PGND
+
R1
PVCC
COMPOSITE PG
DPRSLPVR
STP_CPUB
VID CHANGE
PGOOD
110µs BLANKING
R2
RBOOT
PVCC
0.60V
+
–
+
VFB
0.66V
ITH
CC
1.5µA
SGND
SHDN
RST
5.33(VFB)
6V
DPRSLPVR
MD
VID CHANGE
RATTEN
5.33k
RUN
SOFTSTART
CC2
RC
RUN/SS
RUN
6-BIT VID DECODER
CSS
+
–
1.5V
RVID
VID0
VID1
VID2
VID3
VID4
VID5
3735 FD
3735fa
9
LTC3735
OPERATION
(Refer to Functional Diagram)
Main Control Loop
The LTC3735 uses a constant frequency, current mode stepdown architecture with the two output stages operating
180 degrees out of phase. During normal operation, each
top MOSFET is turned on when the clock for that channel
sets the RS latch, and turned off when the main current
comparator, I1, resets the RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by
the voltage on the ITH pin, which is the output of error
amplifier EA. The VOA+ pin receives the voltage feedback
signal, which is compared to the internal reference voltage
by the EA. When the load current increases, it causes a
slight decrease in EA inverting input node relative to the
0.6V reference, which in turn causes the ITH voltage to
increase until the average inductor current matches the
new load current. After the top MOSFET has turned off,
the bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle.
The top MOSFET drivers are biased from floating bootstrap
capacitor CB, which normally is recharged during each off
cycle through an external diode when the top MOSFET
turns off. As VIN decreases to a voltage close to VOUT,
the loop may enter dropout and attempt to turn on the
top MOSFET continuously. The dropout detector detects
this and forces the top MOSFET off for about 500ns every
sixth cycle to allow CB to recharge.
The main control loop is shut down by pulling the RUN/
SS pin low. Releasing RUN/SS allows an internal 1.5µA
current source to charge soft-start capacitor CSS. When
CSS reaches 1.5V, the main control loop is enabled with
the internal ITH voltage clamped at approximately 30%
of its maximum value. As CSS continues to charge, the
internal ITH voltage is gradually released allowing normal,
full-current operation.
Frequency Programming and Antiphase Operation
The switching frequency of the LTC3735 is determined by
the DC voltage at the FREQSET pin. A DC voltage ranging
from 0V to 2.4V moves the internal oscillator frequency
from 210kHz to 550kHz.
This frequency is the actual switching frequency of either
channel. Because the two channels operate 180°C out of
phase, the apparent frequency at both VIN and VOUT is
twice the actual switching frequency, minimizing ripple
voltages and speeding up transient responses.
Low Current Operation (PSIB)
The PSIB pin selects between two modes of operation.
When PSIB is above 0.6V, both channels operate in full
synchronous switching mode. Both bottom drivers (BG1,
BG2) are kept on once they are turned on until their respective oscillator sets the RS latch. The inductor current
can therefore go from output back to input power supply
and could potentially boost the input supply to dangerous
voltage levels—BEWARE! This mode of operation is also
of lower efficiency, given both channels are fully enabled
and much current can circulate between input and output.
However, this mode provides faster transient response,
lower input noise and minimum output ripple.
When PSIB is below 0.6V, the bottom drivers (BG1, BG2)
are turned off if the inductor current starts to reverse. This
mode of operation prevents current going from output
back to input and eliminates the conduction power loss
related to circulating current. If the DPRSLPVR signal
goes high in this mode, Channel 2 will be shut off and
only Channel 1 will be active in supplying load current.
This further eliminates power MOSFET gate driving and
transition losses of Channel 2. Since DPRSLPVR indicates
the entry to deeper sleep state, this “channel shedding”
technique optimizes the voltage regulator efficiency at
light loads. Table 1 summarizes the operation modes for
different pin configurations.
Table 1. Low Current Operation Modes
PSIB
DPRSLPVR
OPERATION MODE
High
High or Low Both Channels ON, Fully Synchronous
Switching, Inductor Current is Allowed to
Reverse
Low
Low
Both Channels ON; Reverse Current is
Prevented
Low
High
Channel 2 is Shut Off, Reverse Current is
Prevented
3735fa
10
LTC3735
OPERATION
(Refer to Functional Diagram)
Output Voltage at Start-Up and at Deeper Sleep State
Power Good
Under normal conditions, the output voltage of the regulator is commanded by six VID bits, except at start-up and
at deeper sleep state. At start-up, the RUN/SS capacitor
starts to charge up and its voltage limits the inrush current
from the input power source. This linearly rising current
limit provides a controlled output voltage rise. During
start-up, the VID command is ignored and the output set
point is determined by the value of the resistor connected
to the RBOOT pin. The VID bits continue to be ignored for
15 switching cycles after the completion of the following
two conditions: 1) output voltage has risen up and has
regulated 2) MCH_PG signal has asserted. After 15 switching cycles, output voltage is fully commanded by VID bits.
The PGOOD pin is connected to the drain of an internal
N‑channel MOSFET. The MOSFET turns on when the output voltage is not within ±10% of its nominal set point.
When the output voltage is within ±10% of its nominal set
point, the MOSFET turns off and PGOOD is high impedance. PGOOD monitors the VBOOT voltage when MCH_PG
is not asserted. During VID, deep sleep or deeper sleep
transitions, PGOOD is masked from going low for 110µs,
preventing the system from resetting during CPU mode
changes. When VID bits, STP_CPUB or DPRSLPVR signals
change again after a previous transition, but before the
timer expires, the internal timer resets.
In deeper sleep state, the VID command and STP_CPUB
signal are ignored and the output set point is determined
by the parallel value of the resistors at the RDPRSLP pin
and RDPSLP pin.
Operational Amplifier and Deep Sleep Offset
The internal operational amplifier provides a programmable
output offset at deep sleep state (when the STP_CPUB
signal is low). The offset percentage is programmed by
the resistor from RDPSLP to VOA+ and the resistor from
output to VOA+. The amplifier has an output slew rate of
5V/µs and is capable of driving capacitive loads with an
output RMS current typically up to 40mA. The open-loop
gain of the amplifier is >120dB and the unity-gain bandwidth is 2MHz.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious conditions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Short-Circuit Detection
The RUN/SS capacitor is used initially to limit the inrush current from the input power source. Once the
controllers have been given time, as determined by the
capacitor on the RUN/SS pin, to charge up the output
capacitors and provide full-load current, the RUN/SS
capacitor is then used as a short-circuit timeout circuit.
If the output voltage falls to less than 70% of its nominal
output voltage the RUN/SS capacitor begins discharging assuming that the output is in a severe overcurrent
and/or short-circuit condition. If the condition lasts for
a long enough period as determined by the size of the
RUN/SS capacitor, the controller will be shut down until the
RUN/SS pin voltage is recycled. This built-in latchoff can
be overidden by providing a current >5µA to the RUN/SS
pin. This current shortens the soft-start period but also
prevents net discharge of the RUN/SS capacitor during a
severe overcurrent and/or short-circuit condition. Foldback
current limiting is activated when the output voltage falls
below 70% of its nominal level whether or not the shortcircuit latchoff circuit is enabled.
3735fa
11
LTC3735
APPLICATIONS INFORMATION
biased with a resistor divider to prevent noise getting
into the system.
A graph for the voltage applied to the FREQSET pin vs frequency is given in Figure 2. As the operating frequency is
increased the gate drive and switching losses will be higher,
reducing efficiency (see Efficiency Considerations). The
maximum switching frequency is approximately 550kHz.
600
550
OPERATING FREQUENCY (kHz)
The basic LTC3735 application circuit is shown in
Figure 1 on the first page of this data sheet. External component selection begins with the selection of the inductors
based on ripple current requirements and continues with
the current sensing resistors using the calculated peak
inductor current and/or maximum current limit. Next, the
power MOSFETs, D1 and D2 are selected. The operating
frequency and the inductor are chosen based mainly on
the amount of ripple current. Finally, CIN is selected for its
ability to handle the input ripple current (that PolyPhase®
operation minimizes) and COUT is chosen with low enough
ESR to meet the output ripple voltage and load step
specifications (also minimized with PolyPhase). Current
mode architecture provides inherent current sharing between output stages. The circuit shown in Figure 1 can
be configured for operation up to an input voltage of 28V
(limited by the external MOSFETs). Current mode control
allows the ability to connect the two output stages to two
different input power supply rails. A heavy output load
can take some power from each input supply according
to the selection of the RSENSE resistors.
500
450
400
350
300
250
200
150
100
0
0.5
1.0
1.5
2.0
2.5
FREQSET PIN VOLTAGE (V)
3.0
3735 F02
Figure 2. Operating Frequency vs VFREQSET
RSENSE Selection For Output Current
Inductor Value Calculation and Output Ripple Current
RSENSE1,2 are chosen based on the required peak output
current. The LTC3735 current comparator has a maximum
threshold of 72mV/RSENSE and an input common mode
range of SGND to PVCC. The current comparator threshold
sets the peak inductor current, yielding a maximum average output current IMAX equal to the peak value less half
the peak-to-peak ripple current, ∆IL.
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
MOSFET gate charge and transition losses increase
directly with frequency. In addition to this basic tradeoff,
the effect of inductor value on ripple current and low current operation must also be considered. The PolyPhase
approach reduces both input and output ripple currents
while optimizing individual output stages to run at a lower
fundamental frequency, enhancing efficiency.
Assuming a common input power source for each output stage and allowing a margin for variations in the
LTC3735 and external component values yields:
RSENSE = 2(40mV/IMAX)
Operating Frequency
The LTC3735 uses a constant frequency architecture with
the frequency determined by an internal capacitor. This
capacitor is charged by a fixed current plus an additional
current which is proportional to the DC voltage applied
to the FREQSET pin. The FREQSET voltage is internally
set to 1.2V. It is recommended that this pin is actively
The inductor value has a direct effect on ripple current.
The inductor ripple current ∆IL, decreases with higher
inductance or frequency and increases with higher VIN:
∆IL =
VOUT  VOUT 
1−
fL 
VIN 
where f is the individual output stage operating frequency.
3735fa
12
LTC3735
APPLICATIONS INFORMATION
In a 2-phase converter, the net ripple current seen by
the output capacitor is much smaller than the individual
inductor ripple currents due to ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Linear Technology Application Note 77.
Figure 3 shows the net ripple current seen by the output
capacitors for 1- and 2-phase configurations. The output
ripple current is plotted for a fixed output voltage as the
duty factor is varied between 10% and 90% on the x‑axis.
The graph can be used in place of tedious calculations,
simplifying the design process.
Accepting larger values of ∆IL allows the use of low inductances, but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is
∆IL = 0.4(IOUT)/2, where IOUT is the total load current.
Remember, the maximum ∆IL occurs at the maximum
input voltage. The individual inductor ripple currents
are determined by the frequency, inductance, input and
output voltages.
1.0
1-PHASE
2-PHASE
0.9
0.8
0.6
VO/fL
∆IO(P-P)
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
A variety of inductors designed for high current, low voltage applications are available from manufacturers such
as Sumida, Coilcraft, Coiltronics, Toko and Panasonic.
Power MOSFET, D1 and D2 Selection
Two external power MOSFETs must be selected for each
output stage with the LTC3735: one N-channel MOSFET
for the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the PVCC voltage. This voltage typically ranges from 4.5V to 7V. Consequently, logic-level threshold MOSFETs must be used
in most applications. Pay close attention to the BVDSS
specification for the MOSFETs as well; most of the logiclevel MOSFETs are limited to 30V or less.
0.7
0.5
0.4
0.3
0.2
0.1
0
is very dependent on inductor type selected. As inductance
increases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore copper losses will increase.
0.1
0.2
0.3 0.4 0.5 0.6 0.7
DUTY FACTOR (VOUT/VIN)
0.8
0.9
3735 F03
Figure 3. Normalized Output Ripple Current
vs Duty Factor [IRMS ≈ 0.3 (∆IO(P-P)]
Inductor Core Selection
Once the values for L1 and L2 are known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy, or Kool Mµ cores. Actual core loss
is independent of core size for a fixed inductor value, but it
Selection criteria for the power MOSFETs include the “ON”
resistance RDS(ON), gate charge QG, reverse transfer capacitance CRSS, breakdown voltage BVDSS and maximum
continuous drain current ID(MAX).
When the LTC3735 is operating at continuous mode in a
step-down configuration, the duty cycles for the top and
bottom MOSFETs of each power stage are approximately:
Top MOSFET Duty Cycle =
VOUT
VIN
Bottom MOSFET Duty Cycle =
VIN – VOUT
VIN
(1)
(2)
3735fa
13
LTC3735
APPLICATIONS INFORMATION
The conduction losses of the top and bottom MOSFETs
are therefore:
PCONTOP =
VOUT
VIN
2
I 
•  OUT  • (1+ δ • ∆T ) •RDS(ON)(3)
 2 
V –V
PCONBOT = IN OUT
VIN
2
I 
•  OUT  • (1+ δ • ∆T )
 2 
(4)
• RDS(ON)
where IOUT is the total output current at full load, ∆T is the
difference between MOSFET operating temperature and
room temperature, and δ is the temperature dependency
of RDS(ON). δ is roughly 0.004/°C ~ 0.006/°C for low voltage MOSFETs.
The power losses of driving the top and bottom MOSFETs
are simply:
PDRTOP = QG • PVCC • f
(5)
PDRBOT = QG • PVCC • f
(6)
Use QG data at VGS = PVCC in MOSFET data sheets. f is
the switching frequency as described previously. Please
notice that the above gate driving losses are usually not
dissipated by the MOSFETs. Instead they are mainly dissipated on the internal drivers of the LTC3735, if there are
no resistors connected between the drive pins (TG, BG)
and the gates of the MOSFETs.
The calculation of MOSFET switching loss is complicated
by several factors including the wide distribution of power
MOSFET threshold voltage, the nonlinearity of current rising/falling characteristic and the Miller Effect. Given the
data in a typical power MOSFET data sheet, the switching losses of the top and bottom MOSFETs can only be
estimated as follows:
V 2 •I
PSWTOP = IN OUT • f • CRSS •RDR •
4
per Phase

1 
1
+


 VDR – VTH(MIN) VTH(MIN) 
PSWBOT ≈ 0
(7)
(8)
where RDR is the effective driver resistance (of approximately 2Ω), VDR is the driving voltage (= PVCC) and VTH(MIN)
is the minimum gate threshold voltage of the MOSFET.
Please notice that the switching loss of the bottom MOSFET
is effectively negligible because the current conduction of
the antiparalleling diode. This effect is often referred as
zero-voltage-transition (ZVT). Similarly when the LTC3735
converter works under fully synchronous mode at light
load, the reverse inductor current can also go through
the body diode of the top MOSFET and make the turn-on
loss to be negligible. However, equations 7 and 8 have to
be used in calculating the worst-case power loss, which
happens at highest load level.
The selection criteria of power MOSFETs start with the
stress check:
VIN < BVDSS
IMAX < ID(MAX)
and
PCONTOP + PSWTOP < top MOSFET maximum power
dissipation specification
PCONBOT + PSWBOT < bottom MOSFET maximum power
dissipation specification
The maximum power dissipation allowed for each MOSFET
depends heavily on MOSFET manufacturing and packaging, PCB layout and power supply cooling method.
Maximum power dissipation data are usually specified
in MOSFET data sheets under different PCB mounting
conditions.
The next step of selecting power MOSFETs is to minimize
the overall power loss:
POVL = PTOP + PBOT
= (PCONTOP + PDRTOP + PSWTOP) + (PCONBOT + PDRBOT + PSWBOT)
For typical mobile CPU applications where the ratio between
input and output voltages is higher than 2:1, the bottom
MOSFET conducts load current most of the time while
the main losses of the top MOSFET are for switching and
driving. Therefore a low RDS(ON) part (or multiple parts in
parallel) would minimize the conduction loss of the bottom
3735fa
14
LTC3735
APPLICATIONS INFORMATION
CIN and COUT Selection
In continuous mode, the source current of each top
N‑channel MOSFET is a square wave of duty cycle VOUT/
VIN. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a closed form
equation can be found in Linear Technology Application
Note 77. Figure 4 shows the input capacitor ripple current
for a 2-phase configuration with the output voltage fixed
and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be
used in place of tedious calculations. The minimum input
ripple current can be achieved when the input voltage is
twice the output voltage.
In the graph of Figure 4, the 2-phase local maximum input
RMS capacitor currents are reached when:
VOUT 2k − 1
=
VIN
4
where k = 1, 2
These worst-case conditions are commonly used for
design, considering input/output variations and long
term reliability. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor,
0.6
1-PHASE
2-PHASE
0.5
DC LOAD CURRENT
The Schottky diodes, D1 and D2 in Figure 1 conduct during the dead-time between the conduction of the top and
bottom MOSFETs. This helps reduce the current flowing
through the body diode of the bottom MOSFET. A body
diode usually has a forward conduction voltage higher than
that of a Schottky and is thus detrimental to efficiency. The
charge storage and reverse recovery of a body diode also
cause high frequency rings at the switching nodes (the
conjunction nodes between the top and bottom MOSFETs),
which are again not desired for efficiency or EMI. Some
power MOSFET manufacturers integrate a Schottky diode
with a power MOSFET, eliminating the need to parallel an
external Schottky. These integrated Schottky-MOSFETs,
however, have smaller MOSFET die sizes than conventional
parts and are thus not suitable for high current applications.
or to choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled to meet size or height requirements in the design.
Always consult the capacitor manufacturer if there is any
question.
RMS INPUT RIPPLE CURRNET
MOSFET while a higher RDS(ON) but lower QG and CRSS
part would be desirable for the top MOSFET.
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3 0.4 0.5 0.6 0.7
DUTY FACTOR (VOUT/VIN)
0.8
0.9
3735 F04
Figure 4. Normalized RMS Input Ripple Current
vs Duty Factor for 1 and 2 Output Stages
It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a
2‑phase implementation results in 75% less power loss
when compared to a single phase design. Battery/input
protection fuse resistance (if used), PC board trace and
connector resistance losses are also reduced by the reduction of the input ripple current in a 2-phase system. The
required amount of input capacitance is further reduced
by the factor, 2, due to the reduction in input RMS current.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically once the ESR requirement has been met, the RMS current rating generally far
exceeds the IRIPPLE(P-P) requirements. The steady state
output ripple (∆VOUT) is determined by:


1
∆VOUT ≈ ∆IRIPPLE  ESR +
16 • f • COUT 

where f = operating frequency of each stage, COUT =
output capacitance and ∆IRIPPLE = interleaved inductor
ripple currents.
∆IRIPPLE can be calculated from the duty factor and the
∆IL of each stage. A closed form equation can be found in
3735fa
15
LTC3735
APPLICATIONS INFORMATION
Linear Technology Application Note 77. Assuming inductors are selected to have same ripple percentage for both
1-phase and 2-phase configurations, Figure 5 shows the
reduction of output ripple current by 2-phase operation.
Not only the ripple amplitude is more than halved, but
the ripple frequency is also doubled. Compared with the
output voltage ripple for 1-phase:


1
∆VOUT ≈ ∆IRIPPLE  ESR +
8 • f • COUT 

∆VOUT of 2-phase is less than 50% of that of 1-phase, given
the same output capacitor ESRs. Or, to have same ∆VOUT
2-phase only need half the number of output capacitors
that are needed in 1-phase.
The output ripple varies with input voltage since ∆IL is a
function of input voltage. The output ripple will be less than
±25mV at max VIN with ∆IL = 0.4IOUT(MAX)/2 assuming:
COUT required ESR < 4(RSENSE) and
COUT > 1/(16f)(RSENSE)
The LTC3735 employs OPTI-LOOP technique to compensate the switching regulator loop with external components
(through ITH pin). OPTI-LOOP compensation speeds
up regulator’s transient response, minimizes output
capacitance and effectively removes constraints on output
capacitor ESR. It opens a much wider selection of output
capacitor types and a variety of capacitor manufactures are
available for high current, low voltage switching regulators.
∆IRIPPLE OF 2-PHASE
• 100%
∆IRIPPLE OF 1-PHASE
50
40
30
20
10
0
0.1
0.2
0.3 0.4 0.5 0.6 0.7
DUTY FACTOR (VOUT/VIN)
0.8 0.9
3735 F05
Manufacturers such as Nichicon, United Chemicon
and Sanyo should be considered for high performance
through-hole capacitors. The OS-CON semiconductor
dielectric capacitor available from Sanyo has the lowest
(ESR)(size) product of any aluminum electrolytic at a
somewhat higher price. An additional ceramic capacitor
in parallel with OS-CON type capacitors is recommended
to reduce the inductance effects.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer (SP)
surface mount capacitors from Panasonic offer very low
ESR also but have much lower capacitive density per unit
volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies.
Several excellent choices are the AVX TPS, AVX TPSV or the
KEMET T510 series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. Other capacitor
types include Sanyo OS-CON, POSCAPs, Kemet AO-CAPs,
Nichicon PL series and Sprague 595D series. Consult
the manufacturer for other specific recommendations. A
combination of capacitors will often result in maximizing
performance and minimizing overall cost and size.
PVCC Decoupling
The PVCC pin supplies power to the top and bottom gate
drivers and therefore must be bypassed to power ground
with a minimum of 4.7µF ceramic or tantalum capacitor.
Since the gate driving currents are of high amplitude and
high slew rate, this bypassing capacitor should be placed
very close to the PVCC and PGND pins to minimize the
parasitic inductance. Do NOT apply greater than 7V to
the PVCC pin.
The PVCC pin also supplies current to the internal control
circuitry of the LTC3735. This supply current is much
lower than that of the current for the external MOSFET
gate drive. Ceramic capacitors are very good for high
frequency filtering and a 0.1µF ~ 1µF ceramic capacitor
should be placed adjacent to the PVCC and SGND pins.
Figure 5. Output Ripple Current Reduction
of 2-Phase Over Single Phase
3735fa
16
LTC3735
APPLICATIONS INFORMATION
Topside MOSFET Driver Supply (CB,DB) (Refer to
Functional Diagram)
External bootstrap capacitors CB1 and CB2 connected to the
BOOST1 and BOOST2 pins supply the gate drive voltages
for the topside MOSFETs. Capacitor CB in the Functional
Diagram is charged though diode DB from PVCC when the
SW pin is low. When the topside MOSFET turns on, the
driver places the CB voltage across the gate-source of the
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin rises to VIN + PVCC. The value of
the boost capacitor CB needs to be 30 to 100 times that of
the total input capacitance of the topside MOSFET(s). The
reverse breakdown of DB must be greater than PVCC(MAX).
VID Output Voltage Programming
After 27µs ~ 71µs tBOOT delay, the output voltage of the
regulator is digitally programmed as defined in Table 2
using the VID0 to VID5 logic input pins. The VID logic
inputs program a precision, 0.25% internal feedback resistive divider. The LTC3735 has an output voltage range
of 0.700V to 1.708V in 16mV steps.
Refering to the Functional Diagram, there is a resistor,
RVID, from VFB to ground. The value of RVID is controlled
by the six VID input pins. Another internal resistor, 5.33k
(RATTEN), completes the resistive divider. The output voltage
is thus set by the ratio of (RVID + 5.33k) to RVID.
Each VID digital pin is a high impedance input. Therefore they must be actively pulled high or pulled low. The
logic low threshold of the VID pins is 0.3V; the logic high
threshold is 0.7V.
An internal 1.5µA current source charges up the soft-start
capacitor, CSS. When the voltage on RUN/SS reaches 1.5V,
the controller is permitted to start operating. As the voltage on RUN/SS increases from 1.5V to 3.0V, the internal
current limit is increased from 25mV/RSENSE to 72mV/
RSENSE. The output current thus ramps up slowly, eliminating the starting surge current required from the input
power supply. If RUN/SS has been pulled all the way to
ground there is a delay before starting of approximately:
1.5V
tDELAY =
C = (1s/µF ) CSS
1.5µA SS
The time for the output current to ramp up is then:
3V − 1.5V
tIRAMP =
C = (1s/µF ) CSS
1.5µA SS
By pulling the RUN/SS pin below 1V the LTC3735 is put
into low current shutdown (IQ < 100µA). The RUN/SS pin
can be driven directly from logic as shown in Figure 6.
Diode D1 in Figure 6 reduces the start delay but allows
CSS to ramp up slowly providing the soft-start function.
The RUN/SS pin has an internal 6V zener clamp (see
Functional Diagram).
PVCC
3.3V OR 5V
D1
RUN/SS
RSS*
CSS
RUN/SS
CSS
3735 F06
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
Figure 6. RUN/SS Pin Interfacing
Soft-Start/Run Function
Start-Up Sequence (Refer to the Functional Diagram)
The RUN/SS pin provides three functions: 1) run/shutdown,
2) soft-start and 3) an optional short-circuit latchoff timer.
Soft-start reduces the input power sources’ surge currents
by gradually increasing the controller’s current limit. The
latchoff timer prevents very short, extreme load transients
from tripping the overcurrent latch. A small pull-up current (>5µA) supplied to the RUN/SS pin will prevent the
overcurrent latch from operating. The following paragraph
describes how the functions operate.
After soft-start, the output voltage of the regulator settles
at a voltage level equal to VBOOT.
VBOOT = 0.6V •
R2 • (R3 +R5)
R5 • (R1+R2)
By using different R5 resistors, VBOOT can be programmed.
3735fa
17
LTC3735
APPLICATIONS INFORMATION
Table 2. VID Output Voltage Programming
VID5
VID4
VID3
VID2
VID1
VID0
LTC3735
VID5
VID4
VID3
VID2
VID1
VID0
LTC3735
0
0
0
0
0
0
1.708V
1
0
0
0
0
0
1.196V
0
0
0
0
0
1
1.692V
1
0
0
0
0
1
1.180V
0
0
0
0
1
0
1.676V
1
0
0
0
1
0
1.164V
0
0
0
0
1
1
1.660V
1
0
0
0
1
1
1.148V
0
0
0
1
0
0
1.644V
1
0
0
1
0
0
1.132V
0
0
0
1
0
1
1.628V
1
0
0
1
0
1
1.116V
0
0
0
1
1
0
1.612V
1
0
0
1
1
0
1.100V
0
0
0
1
1
1
1.596V
1
0
0
1
1
1
1.084V
0
0
1
0
0
0
1.580V
1
0
1
0
0
0
1.068V
0
0
1
0
0
1
1.564V
1
0
1
0
0
1
1.052V
0
0
1
0
1
0
1.548V
1
0
1
0
1
0
1.036V
0
0
1
0
1
1
1.532V
1
0
1
0
1
1
1.020V
0
0
1
1
0
0
1.516V
1
0
1
1
0
0
1.004V
0
0
1
1
0
1
1.500V
1
0
1
1
0
1
0.988V
0
0
1
1
1
0
1.484V
1
0
1
1
1
0
0.972V
0
0
1
1
1
1
1.468V
1
0
1
1
1
1
0.956V
0
1
0
0
0
0
1.452V
1
1
0
0
0
0
0.940V
0
1
0
0
0
1
1.436V
1
1
0
0
0
1
0.924V
0
1
0
0
1
0
1.420V
1
1
0
0
1
0
0.908V
0
1
0
0
1
1
1.404V
1
1
0
0
1
1
0.892V
0
1
0
1
0
0
1.388V
1
1
0
1
0
0
0.876V
0
1
0
1
0
1
1.372V
1
1
0
1
0
1
0.860V
0
1
0
1
1
0
1.356V
1
1
0
1
1
0
0.844V
0
1
0
1
1
1
1.340V
1
1
0
1
1
1
0.828V
0
1
1
0
0
0
1.324V
1
1
1
0
0
0
0.812V
0
1
1
0
0
1
1.308V
1
1
1
0
0
1
0.796V
0
1
1
0
1
0
1.292V
1
1
1
0
1
0
0.780V
0
1
1
0
1
1
1.276V
1
1
1
0
1
1
0.764V
0
1
1
1
0
0
1.260V
1
1
1
1
0
0
0.748V
0
1
1
1
0
1
1.244V
1
1
1
1
0
1
0.732V
0
1
1
1
1
0
1.228V
1
1
1
1
1
0
0.716V
0
1
1
1
1
1
1.212V
1
1
1
1
1
1
0.700V
3735fa
18
LTC3735
APPLICATIONS INFORMATION
After the output voltage enters the ±10% regulation window
centered at VBOOT, the internal power good comparator
issues a logic high signal. Refer to the timing diagram in
Figure 7. This signal then enters a logic AND gate, with
MCH_PG being the other input, and the output of the gate
is PG shown in Figure 7. This composite PG signal is then
delayed by tBOOT amount of time and then becomes MD.
As soon as MD is asserted, the output voltage changes
from VBOOT to VVID, a voltage level totally controlled by
the six VID bits. In the LTC3735, the time tBOOT is set to
be 15 switching cycles:
1
tBOOT = 15
fS
Output Voltage Set in Deep Sleep and Deeper Sleep
States (Refer to the Functional Diagram)
If fS is set at 210kHz, tBOOT = 71µs
The output voltage could also be set by external resistors
R6 and R4 when DPRSLPVR input is high. This state is
defined to be the deeper sleep state. The output voltage
is set to VDPRSLPVR, regardless of the VID setting:
If fS is set at 550kHz, tBOOT = 27µs
RUN/SS
STP% = –
R3
• 100%
R3 +R4
By using different R4 resistors, STP_CPUB offset can be
programmed.
VDPRSLPVR = 0.6V •
1.5V
VVID
VBOOT
R2 • (R3 +R6||R4)
(R6||R4) • (R1+R2)
By using different value R6 resistors, VDPRSLPVR can be
programmed.
VOUT
90% VBOOT
(The digital input threshold voltage is set to 1.8V for
STP_CPUB, DPRSLPVR and MCH_PG inputs.)
INTERNAL PG
(OUTPUT OF
INTERNAL
POWER GOOD
COMPARATOR)
Power Good Masking
The PGOOD output monitors VOUT. When VOUT is not
within ±10% of the set point, PGOOD is pulled low with
an internal MOSFET. When VOUT is within the regulation
window, PGOOD is high impedance. PGOOD should be
pulled up by an external resistor.
MCH_PG
COMPOSITE PG
(=(INTERNAL PG)
AND (MCH_PG))
tBOOT
MD
VID BITS
The output voltage can be offset by the STP_CPUB signal.
When STP_CPUB becomes low, the output voltage will be
a certain percentage lower than that set by the VID bits in
Table 2. This state is defined to be the deep sleep state.
Referring to the Functional Diagram, we can caluculate
the STP_CPUB offset to be:
VALID
INVALID
TIME
3735 F07
During VID changes, deep sleep and deeper sleep transitions, the output voltage can initially be out of the ±10%
window of the newly set regulation point. To avoid nuisance indications from PGOOD, a timer masks PGOOD for
110µs. If VOUT is still out of regulation after this blanking
time, PGOOD goes low. Any overvoltage or undervoltage
condition is also masked for 110µs before it is reported
by PGOOD.
Figure 7. Start-Up Timing Diagram
3735fa
19
LTC3735
APPLICATIONS INFORMATION
The masking circuitry also adaptively tracks VID and state
changes. If a new change in VID or state happens before
the 110µs masking timer expires, the timer resets and
starts a fresh count of 110µs. This prevents the system
from rebooting under frequent output voltage transitions.
Refer to Figure 8 for the PGOOD timing diagram.
During start-up, PGOOD is actively pulled low until the RUN/
SS pin voltage reaches its arming voltage, which is 4.2V
typically, only then is the PGOOD pull-low signal released.
When RUN/SS goes low, PGOOD goes low simultaneously.
begins discharging on the assumption that the output is in
an overcurrent condition. If the condition lasts for a long
enough period as determined by the size of the CSS, the
controller will be shut down until the RUN/SS pin voltage
is recycled. If the overload occurs during start-up, the
time can be approximated by:
tLO1 ≈ (CSS • 0.7V)/(1.5µA) = 4.6 • 105 (CSS)
If the overload occurs after start-up, the voltage on CSS
will continue charging and will provide additional time
before latching off:
tLO2 ≈ (CSS • 2V)/(1.5µA) = 1.3 • 106 (CSS)
VID BITS
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor, RSS, to the RUN/SS pin as
shown in Figure 6. This resistance shortens the softstart period and prevents the discharge of the RUN/SS
capacitor during a severe overcurrent and/or short-circuit
condition. When deriving the 5µA current from PVCC as in
the figure, current latchoff is always defeated.
VOUT
INTERNAL PG
(OUTPUT OF
INTERNAL
POWER GOOD
COMPARATOR)
PGOOD
MASKING
110µs
110µs
PGOOD
TIME
3735 F08
Figure 8. PGOOD Timing Diagram
Fault Conditions: Overcurrent Latchoff
The RUN/SS pin also provides the ability to latch off the
controller when an overcurrent condition is detected. The
RUN/SS capacitor, CSS, is used initially to limit the inrush
current. After the controller has been started and been
given adequate time to charge up the output capacitors
and provide full load current, the RUN/SS capacitor is used
for a short-circuit timer. If the output voltage falls to less
than 70% of its nominal value after CSS reaches 4.2V, CSS
Why should you defeat current latchoff? During the prototyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. A decision can be made after the design is complete
whether to rely solely on foldback current limiting or to
enable the latchoff feature by removing the pull-up resistor.
The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capacitance is given by:
CSS > (COUT )(VOUT)(10-4)(RSENSE)
A recommended soft-start capacitor of CSS = 0.1µF will
be sufficient for most applications.
3735fa
20
LTC3735
APPLICATIONS INFORMATION
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3735 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON (MIN ) <
VOUT
VIN ( f )
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3735 will begin to skip
cycles resulting in variable frequency operation. The output
voltage will continue to be regulated, but the ripple current
and ripple voltage will increase.
The minimum on-time for the LTC3735 is generally less
than 150ns. However, as the peak sense voltage decreases,
the minimum on-time gradually increases. This is of particular concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger ripple current and ripple voltage.
AVP ≅ –35.5 •
Active voltage positioning can be used to minimize peak-topeak output voltage excursion under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifications. Active voltage positioning can easily be
added to the LTC3735. Figure 9 shows the equivalent circuit
for implementing AVP. The load line slope is estimated to be:
(9)
V
if gm •R3 > 10 • OUT
0.6V
where RSENSE is the current sense resistor, m is the number
of phases, (m = 2 for LTC3735) R3 and RAVP are defined
in Figure 9. gm is the transconductance gain for the error
amplifier, it is about 4.5mmho for LTC3735. Rewriting
Equation 9 we can estimate the AVP resistor to be:
R AVP ≅
35.5 •R3 •RSENSE
m•| AVP|
(10)
VOUT+
R3
RAVP
VOA+
R2
+
VOA–
OAOUT
–
R1
If an application can operate close to the minimum
on-time limit, an inductor must be chosen that has a low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement. As a general
rule, keep the inductor ripple current of each phase equal
to or greater than 15% of IOUT(MAX) at VIN(MAX).
Active Voltage Positioning
RSENSE R3
•
,
m
R AVP
FB
–
VID
0.6V
ITH
+
3735 F09
Figure 9. Simplified Schematic Diagram
for AVP Design in LTC3735
We also adopt the current sense resistors as part of
voltage positioning slopes. So the total load line slope is
estimated to be:
AVP ≅ –35.5 •
RSENSE R3 RSENSE
•
–
,
m
R AVP
m
V
if gm •R3 >> OUT
0.6V
(11)
3735fa
21
LTC3735
APPLICATIONS INFORMATION
Rewriting this equation, we can estimate the RAVP value
to be:
R AVP≅
35.5 •R3
m •| AVP|
–1
RSENSE
(12)
Typically the calculation results based on these equations
have ±10% tolerance. So the resistor values need to be
fine tuned.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3735 circuits: 1) I2R losses, 2) Topside
MOSFET transition losses, 3) PVCC supply current and
4) CIN loss.
1) I2R losses are predicted from the DC resistances of
the fuse (if used), MOSFET, inductor, and current sense
resistor. In continuous mode the average output current
flows through L and RSENSE, but is “chopped” between the
topside MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same RDS(ON), then the
resistance of one MOSFET can simply be summed with
the resistances of L, RSENSE and ESR to obtain I2R losses.
For example, if each RDS(ON) = 10mΩ, RL = 10mΩ, and
RSENSE = ­5mΩ, then the total resistance is 25mΩ. This
results in losses ranging from 2% to 8% as the output
current increases from 3A to 15A per output stage for a 5V
output, or a 3% to 12% loss per output stage for a 3.3V
output. Efficiency varies as the inverse square of VOUT for
the same external components and output power level.
The combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
2) Transition losses apply only to the topside MOSFET(s),
and are significant only when operating at high input voltages (typically 12V or greater). Transition losses can be
estimated from:
Transition Loss =
per Phase
2
VIN
•IOUT
4
• f • CRSS • R DR •


1
1
+


 VDR – VTH(MIN) VTH(MIN) 
3) PVCC drives both top and bottom MOSFETs. The MOSFET
driver current results from switching the gate capacitance
of the power MOSFETs. Each time a MOSFET gate is
switched from low to high to low again, a packet of charge
dQ moves from PVCC to ground. The resulting dQ/dt is a
current out of PVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG =
(QT + QB)f, where QT and QB are the gate charges of the
topside and bottom side MOSFETs and f is the switching
frequency.
4) The input capacitor has the difficult job of filtering
the large RMS input current to the regulator. It must
have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
The LTC3735 2-phase architecture typically halves the
input and output capacitor requirements over 1-phase
solutions.
Other losses, including COUT ESR loss, Schottky diode
conduction loss during dead time, inductor core loss and
internal control circuitry supply current generally account
for less than 2% additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at the load transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
3735fa
22
LTC3735
APPLICATIONS INFORMATION
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD(ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the ITH pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time, and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The ITH external components shown
in the Figure 1 circuit will provide an adequate starting
point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon first because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of <1µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. The initial output voltage step resulting from the step change in output current may not be
within the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why
it is better to look at the ITH pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased
by increasing RC and the bandwidth of the loop will be
increased by decreasing CC. If RC is increased by the
same factor that CC is decreased, the zero frequency will
be kept the same, thereby keeping the phase the same in
the most critical frequency range of the feedback loop.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging into
the supply from hell. The main battery line in an automobile
is the source of a number of nasty potential transients,
including load-dump, reverse-battery and double-battery.
Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 10 is the most straightforward approach to protect a DC/DC converter from the
ravages of an automotive power line. The series diode
prevents current from flowing during reverse-battery,
while the transient suppressor clamps the input voltage
during load-dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of
the converter. Although the LT3735 has a maximum input
voltage of 32V, most applications will be limited to 30V
by the MOSFET BVDSS.
VBAT
12V
PVCC
+
PVCC
LTC3735
3735 F10
Figure 10. Automotive Application Protection
3735fa
23
LTC3735
APPLICATIONS INFORMATION
Design Example
2
As a design example, assume VIN = 12V (nominal), VIN
= 21V (max), VOUT = 1.5V, IMAX = 35A, and f = 350kHz
(each phase).
1.5V  35A 
PTOP =
•
• 1+ 0.005 • ( 85°C – 25°C) •
21V  2 
0.008Ω +
The inductance value is chosen first based on a 40% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. The minimum
inductance for 40% ripple current is:
L≥
VOUT  VOUT 
1.5V
=
•  1–
•

f • ∆I 
VIN  350kHz • ( 40% • 17.5A )
 1.5V 
 1– 21V  = 0.57µH
The minimum on-time also occurs at maximum input
voltage:
tON(MIN) =
VOUT
1.5V
=
= 204ns
VIN • f 21V • 350kHz
which is larger than 150ns, the typical minimum on time
of the LTC3735.
RSENSE1 and RSENSE2 can be calculated by using a conservative maximum sense voltage threshold of 40mV and
taking into account of the peak current:
RSENSE =
40mV
= 0.002Ω
21A
The power loss dissipated by the top MOSFET can be calculated with equations 3 and 7. Using a Fairchild FDS7760
as an example: RDS(ON) = 8mΩ, QG = 55nC at 5V VGS, CRSS
= 307pF, VTH(MIN) = 1V. At maximum input voltage with
TJ(estimated) = 85°C at an elevated ambient temperature:
)
21V 2 • 17.5A
• 350kHz • 307pF •
2
1
 1
2Ω • 
+  = 1.26W
 5V – 1V 1V 
Equation 4 gives the worst-case power loss dissipated
by the bottom MOSFET (assuming FDS7760 and TJ =
85°C again):
2
PBOT =
Using L = 0.6µH, a common “off-the-shelf” value results
in 38%ripple current. The peak inductor current will be
the maximum DC current plus one half of the ripple current, or 21A.
Tie the FREQSET pin to 1.2V, resistively divided down from
PVCC to have 350kHz operation for each phase.
(
21V – 1.5V  35A 
•
•
 2 
21V
(1+ 0.005 • (85°C – 25°C)) • 0.008Ω
= 2.95W
Therefore it is necessary to have two FDS7760s in parallel
to split the power loss.
A short-circuit to ground will result in a folded back current of about:
25mV 1  200ns • 21V 
ISC =
+ •
= 16A
0.002Ω 2  0.6µH 
The worst-case power dissipation by the bottom MOSFET
under short-circuit conditions is:
1
– 200ns
2
350kHz
PBOT =
• (16A ) •
1
350kHz
(1+ 0.005 • (85°C – 25°C)) • 0.008Ω
= 2.48W
which is less than normal, full load conditions.
The nominal duty cycle of this application is equation 1:
DC =
1.5V
= 12.5%
12V
3735fa
24
LTC3735
APPLICATIONS INFORMATION
Using Figure 4, the RMS input ripple current will be:
IINRMS = 35A • 0.22 = 7.7A
An input capacitor(s) with a 8A RMS current rating is
required.
The output capacitor ripple current is calculated by using
the inductor ripple current and multiplying by the factor
obtained from Figure 3. The output ripple will be highest
at the maximum input voltage since the duty cycle is less
than 50%. The maximum output current ripple is:
∆IOUT(MAX) =
1.5V
• 0.77 = 5.5AP-P
350kHz • 0.6µH
Assuming the ESR of output capacitor(s) is 5mΩ, the
output ripple voltage is:


1
∆VOUT ≈ 5.5AP-P  5mΩ +
16 • 350kHz • ( 4 • 270µF ) 

= 28.4mVP-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3735. Check the following in your layout:
1) Are the signal and power grounds segregated? Keep
the SGND at one end of a PC board to prevent MOSFET
currents from traveling under the IC. The IC signal ground
pin should be used to hook up all control circuitry on one
side of the IC, routing the copper through SGND, under
the IC covering the “shadow” of the package, connecting
to the PGND pin and then continuing on to the (–) plate
of COUT.
2) Is the PVCC decoupling capacitor connected immediately adjacent to the PVCC and PGND pins? A 1µF ceramic
capacitor of the X7R or X5R material is small enough to
fit very close to the IC to minimize the ill effects of the
large current pulses drawn to drive the power MOSFETs.
An additional 4.7µF ~ 10µF of ceramic, tantalum or other
low ESR capacitor is recommended in order to keep PVCC
stable. The power ground returns to the sources of the bottom N-channel MOSFETs, anodes of the Schottky diodes,
and (–) plates of CIN, which should have the shortest trace
length possible.
3) Are the SENSE – and SENSE+ leads routed together
with minimum PC trace spacing? The filter capacitors
between SENSE+ and SENSE – pin pairs should be as
close as possible to the LTC3735. Ensure accurate current sensing with Kelvin connections at the current sense
resistor. See Figure 11.
4) Does the (+) plate of CIN connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the AC current to the MOSFETs. Keep the input
current path formed by the input capacitor, top and bottom MOSFETs, and the Schottky diode on the same side
of the PC board in a tight loop to minimize conducted and
radiated EMI.
5) Keep the “noisy” nodes, SW, BOOST, TG and BG away
from sensitive small-signal nodes. Ideally the switch
nodes should be placed at the furthest point from the
LTC3735.
The diagram in Figure 12 illustrates all branch currents in
a 2-phase switching regulator. It becomes very clear after
studying the current waveforms why it is critical to keep
the high-switching-current paths to a small physical size.
High electric and magnetic fields will radiate from these
“loops” just as radio stations transmit signals. The output
capacitor ground should return to the negative terminal of
the input capacitor and not share a common ground path
with any switched current paths. The left half of the circuit
gives rise to the “noise” generated by a switching regulator.
PADS OF SENSE RESISTOR
TRACE TO OUTPUT CAP (+)
TRACE TO INDUCTOR
3735 F11
SENSE +
SENSE –
Figure 11. Proper Current Sense Connections
3735fa
25
LTC3735
APPLICATIONS INFORMATION
SW1
L1
RSENSE1
D1
VIN
VOUT
RIN
CIN
+
+
SW2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
L2
COUT
RL
RSENSE2
D2
3735 F12
Figure 12. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator
The ground terminations of the sychronous MOSFETs and
Schottky diodes should return to the negative plate(s) of
the input capacitor(s) with a short isolated PC trace since
very high switched currents are present. A separate isolated
path from the negative plate(s) of the input capacitor(s)
should be used to tie in the IC power ground pin (PGND)
and the signal ground pin (SGND). This technique keeps
inherent signals generated by high current pulses from
taking alternate current paths that have finite impedances
during the total period of the switching regulator. External
OPTI-LOOP compensation allows overcompensation for
PC layouts which are not optimized but this is not the
recommended design procedure.
Simplified Visual Explanation of How a 2-Phase
Controller Reduces Both Input and Output RMS Ripple
Current
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors. The RMS input ripple current is divided by,
and the effective ripple frequency is multiplied up by the
number of phases used (assuming that the input voltage
is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced
by, and the effective ripple frequency is increased by the
number of phases used. Figure 13 graphically illustrates
the principle.
3735fa
26
LTC3735
APPLICATIONS INFORMATION
SINGLE PHASE
SW V
ICIN
Figure 4 illustrates the RMS input current drawn from
the input capacitance vs the duty cycle as determined
by the ratio of input and output voltage. The peak input
RMS current level of the single phase system is reduced
by 50% in a 2-phase solution due to the current splitting
between the two stages.
DUAL PHASE
SW1 V
SW2 V
IL1
ICOUT
An interesting result of the 2-phase solution is that the
VIN which produces worst-case ripple current for the
input capacitor, VOUT = VIN/2, in the single phase design
produces zero input current ripple in the 2-phase design.
IL2
ICIN
ICOUT
RIPPLE
3735 F13
Figure 13. Single and 2-Phase Current Waveforms
The worst-case RMS ripple current for a single stage design peaks at an input voltage of twice the output voltage.
The worst-case RMS ripple current for a two stage design
results in peak outputs of 1/4 and 3/4 of input voltage.
When the RMS current is calculated, higher effective duty
factor results and the peak current levels are divided as
long as the currents in each stage are balanced. Refer
to Linear Technology Application Note 19 for a detailed
description of how to calculate RMS current for the single
stage switching regulator. Figures 3 and 4 illustrate how
the input and output currents are reduced by using an
additional phase. The input current peaks drop in half and
the frequency is doubled for this 2-phase converter. The
input capacity requirement is thus reduced theoretically
by a factor of four! Ceramic input capacitors with their
low ESR characteristics can be used.
The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the VOUT/L discharge current
term from the stage that has its bottom MOSFET on subtracts current from the (VIN – VOUT)/L charging current
resulting from the stage which has its top MOSFET on.
The output ripple current is:
∆IRIPPLE =
2VOUT
fL
 1– 2D (1– D) 


 1– 2D + 1 
where D is duty factor.
The input and output ripple frequency is increased by
the number of stages used, reducing the output capacity
requirements. When VIN is approximately equal to 2(VOUT)
as illustrated in Figures 3 and 4, very low input and output
ripple currents result.
3735fa
27
LTC3735
TYPICAL APPLICATION
Figure 14 shows a typical application using the LTC3735
to power the mobile CPU core. The input can vary from
5V to 24V; the output voltage can be programmed from
0.7V to 1.708V with a maximum current of 32A. By only
modifying the external MOSFET and inductor selection,
higher load current capability (up to 40A) can be achieved.
1.708V. When the STP_CPUB signal is low, a deep sleep
state is indicated and the output voltage is decreased by
about 1.04%. When the DPRSLPVR signal is high, a deeper
sleep state is indicated and the output voltage becomes
0.748V regardless of the states of the VID bits. Active
voltage positioning is accomplished with a resistor from
the ITH to the VOA+ pin. Lower resistance yields a steeper
AVP slope while higher resistance provides a flatter slope.
Finally, the PGOOD output is masked for 110µs during VID
change or state transition.
The power supply in Figure 14 receives a VRON signal for
ON/OFF control. After soft-start, the output voltage is set
at 1.2V until the assertion of the MCH_PG signal. After
about a 50µs delay, the VID5-VID0 bits gain the control
over the output voltage and program it between 0.7V and
VCCP_PG/MCH_PG
3.3V
DPRSLPVR
STP_CPUB
2k
PGOOD
PSIB
5V
Si1034X
VID0
100k
VID1
VID2
VID3
VRON
VOA+
VID4
VID5
232k
100pF
470pF
2
8
4
3
19
20
21
22
23
24
35
17
1000pF
3.3k
1M
VOUT
1µF
X5R
5V
36
47pF
16
470pF 9
1
28
34
31
4.7µF
X5R
SW2
SW1
BAT54
0.1µF
0.1µF
MCH_PG
TG1
DPRSLPVR
SW1
STP_CPUB
BG1
PGND
PSIB
FREQSET SENSE1+
SENSE1–
VID0
VID1
VID2
LTC3735
TG2
VID3
SW2
VID4
BG2
VID5
PGOOD
SENSE2+
ITH
SENSE2–
RUN/SS
SGND
VFB
PVCC
RBOOT
RDPRSLP
RDPSLP
VOA+
BOOST1
OAOUT
BOOST2
VOA–
33
Q1
32
27
Q2
26
1µF L1
0.8µH
0.002Ω
S1+
D1
10Ω
C1
10µF ×4
35V X5R
10Ω
10
11
1nF
30
Q3
29
25
Q4
13
1nF
14
100Ω
1.27M
5
6
13.3k
56.2k
15
7
10Ω
12.7k
13.3k
VOA+
1M 1%
549k
C5
×3
C5: PANSONIC SP CAPS EEFSX0D181R
OR SANYO POSCAP 2R5TPE220M9
D1, D2: B340A
L1, L2: CDEP 104-OR8MC-L
Q1, Q3: IRF7811W OR Si7860DP
Q2, Q4: IRF7811W ¥2 OR Si7856DP
10Ω
18
VOUT
0.7V ~ 1.708V
AT 32A
0.002Ω
S2+
D2
12
+
2.2µF
1µF L2
0.8µH
VIN
5V ~ 24V
100Ω
S1+
PSIB
S2+
3.3V CLK_EN# 3.3V
3.3V
2k
1M
1.9k
2N7002
249k
MMBT3904
4.12k
43.2k
IMVP4_PG
MMBT3904
1µF
80.6k
PGOOD
BAT54C
3735 F14
VRON
Figure 14. 5V to 24V Input, 0.7V to 1.708V Output, 32A IMVP-IV Compatible Power Supply
3735fa
28
LTC3735
PACKAGE DESCRIPTION
G Package
36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
12.50 – 13.10*
(.492 – .516)
1.25 ±0.12
7.8 – 8.2
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
5.3 – 5.7
0.42 ±0.03
7.40 – 8.20
(.291 – .323)
0.65 BSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
RECOMMENDED SOLDER PAD LAYOUT
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
0.65
(.0256)
BSC
0.22 – 0.38
(.009 – .015)
TYP
0.05
(.002)
MIN
G36 SSOP 0204
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3735fa
29
LTC3735
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 ± 0.05
5.50 ± 0.05
5.15 ± 0.05
4.10 ± 0.05
3.00 REF
3.15 ± 0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
5.5 REF
6.10 ± 0.05
7.50 ± 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ± 0.10
0.75 ± 0.05
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
3.00 REF
37
0.00 – 0.05
38
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ± 0.10
5.50 REF
7.00 ± 0.10
3.15 ± 0.10
(UH) QFN REF C 1107
0.200 REF 0.25 ± 0.05
0.50 BSC
R = 0.125
TYP
R = 0.10
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
30
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3735fa
LTC3735
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
4/11
Updated Figure 14
28
Updated Related Parts
32
3735fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC3735
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3816
Single Phase DC/DC Controller for Intel IMVP-6/6+/6.5 CPUs
7-Bit IMVP-6 VID: 0.00V ≤ VOUT ≤ 1.50V,
4.5V ≤ VIN ≤ 36V, Very Low Duty Cycle Capable
LTC3732
3-Phase, 5-Bit VID, 600kHz, Synchronous Controller
5-Bit VRM 9/9.1: 1.10V ≤ VOUT ≤ 1.85V
LTC3734
Single Phase DC/DC Controller for IMVP-4
6-Bit IMVP-4 VID: 0.70V ≤ VOUT ≤ 1.708V,
4.5V ≤ VIN ≤ 30V, Lossless Voltage Positioning
LTC3869/LTC3869-2 Dual, 2-Phase Synchronous Step-Down DC/DC Controllers with
Excellent Current Share when Paralleled
Phase-Lockable Fixed 250kHz to 780kHz Frequency,
4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 12.5V
LTC3856
Phase-Lockable Fixed 250kHz to 770kHz Frequency,
4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5V
2-Phase, Single Output Synchronous Step-Down DC/DC Controller
with Diff Amp and DCR Temperature Compensation
LTC3850/LTC3850-1 Dual 2-Phase, High Efficiency Synchronous Step-Down DC/DC
LTC3850-2
Controller, RSENSE or DCR Current Sensing and Tracking
Phase-Lockable Fixed 250kHz to 780kHz Frequency,
4V ≤ VIN ≤ 30V, 0.8V ≤ VOUT ≤ 5.25V
LTC3860
Dual, Multiphase, Synchronous Step-Down DC/DC Controller with
Diff Amp and Three-State Output Drive
Operates with Power Blocks, DRMOS Devices or External
Drivers/MOSFETs, 3V ≤ VIN ≤ 24V, tON(MIN) = 20ns
LTC3855
Dual, Multiphase, Synchronous Step-Down DC/DC Controller with
Diff Amp and DCR Temperature Compensation
Phase-Lockable Fixed Frequency 250kHz to 770kHz,
4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 12V
LTC3829
3-Phase, Single Output Synchronous Step-Down Controller with Diff
Amp and DCR Temperature Compensation
Phase-Lockable Fixed 250kHz to 770kHz Frequency,
4.5V ≤ VIN ≤ 38V, 0.8V≤ VOUT ≤ 5V
LTC3853
Triple Output, Multiphase Synchronous Step-Down DC/DC Controller, Phase-Lockable Fixed 250kHz to 750kHz Frequency,
4V ≤ VIN ≤ 24V, VOUT3 Up to 13.5V
RSENSE or DCR Current Sensing and Tracking
3735fa
32 Linear Technology Corporation
LT 0411 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
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 LINEAR TECHNOLOGY CORPORATION 2002