TI1 ADS1000A0QDBVRQ1 Low-power 12-bit analog-to-digital converter with i2câ ¢ interface Datasheet

ADS1000-Q1
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LOW-POWER 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH I2C™ INTERFACE
Check for Samples: ADS1000-Q1
FEATURES
APPLICATIONS
•
•
•
•
1
23
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Complete 12-Bit Data Acquisition System in a
Tiny SOT-23 Package
Low Current Consumption: Only 90 mA
Integral Nonlinearity: 1 LSB Max
Single-Cycle Conversion
Programmable Gain Amplifier
Gain = 1, 2, 4, or 8
128-SPS Data Rate
I2C Interface with Two Available Addresses
Power Supply: 2.7 V to 5.5 V
Pin- and Software-Compatible with 16-Bit
ADS1100
Voltage Monitors
Battery Management
VIN- VDD SDA
6
5
VIN- VDD SDA
4
6
BSKQ
1
2
5
4
BTMQ
3
1
2
3
VIN+ GND SCL
VIN+ GND SCL
I C address: 1001000
I C address: 1001001
2
2
NOTE: Marking text direction indicates pin 1.
2
Marking text depends on I C address; see Package Option Addendum.
DESCRIPTION
The ADS1000 is an I2C-compatible serial interface analog-to-digital (A/D) converter with differential inputs and 12
bits of resolution in a tiny SOT23-6 package. Conversions are performed ratiometrically, using the power supply
as the reference voltage. The ADS1000 operates from a single power supply ranging from 2.7V to 5.5V.
The ADS1000 performs conversions at a rate of 128 samples per second (SPS). The onboard programmable
gain amplifier (PGA), which offers gains of up to 8, allows smaller signals to be measured with high resolution. In
single-conversion mode, the ADS1000 automatically powers down after a conversion, greatly reducing current
consumption during idle periods.
The ADS1000 is designed for applications where space and power consumption are major considerations.
Typical applications include portable instrumentation, consumer goods, and voltage monitoring.
VDD
A = 1, 2, 4, or 8
VIN+
PGA
VIN-
A/D
Converter
2
IC
Interface
SCL
SDA
Clock
Oscillator
ADS1000
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I C is a trademark of NXP Semiconductors, Inc.
All other trademarks are the property of their respective owners.
2
2
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
SOT-23 – DBV
Reel of 3000
ORDERABLE PART NUMBER
TOP-SIDE MARKING
ADS1000A0QDBVRQ1
BSKQ
ADS1000A1QDBVRQ1
BTMQ
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
ADS1000
VDD to GND
UNIT
–0.3 to 6
V
Input current (momentary)
100
mA
Input current (continuous)
10
mA
Voltage to GND, VIN+, VIN–
–0.3 to VDD to 0.3
V
Voltage to GND, SDA, SCL
–0.5 to 6
V
+150
°C
Operating temperature
–40 to 125
°C
Storage temperature
–60 to 150
°C
Maximum junction temperature, TJ
(1)
2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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ELECTRICAL CHARACTERISTICS
All specifications at –40°C to 125°C, VDD = 5V, GND = 0V, and all PGAs (unless otherwise noted)
ADS1000
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Input
Full-scale input voltage
Analog input voltage
±VDD/PGA (1)
(VIN+) – (VIN–)
VIN+, VIN– to GND
GND – 0.2
Differential input impedance
Common-mode input impedance
V
VDD + 0.2
V
2.4/PGA
MΩ
8
MΩ
System Performance
Resolution
No missing codes
12
Data rate
104
Bits
128
184
SPS
±0.1
1
LSB
1
±2
LSB
0.01
0.1
%
0.7 VDD
6
V
GND – 0.5
0.3 VDD
V
GND
0.4
V
10
mA
Integral nonlinearity (INL)
Offset error
Gain error
Digital Input/Output
Logic level
VIH
VIL
VOL
IOL = 3 mA
Input leakage
IIH
VIH = 5.5 V
IIL
VIL = GND
– 10
VDD
2.7
mA
Power-Supply Requirements
Power-supply voltage
Supply current
Power-down
Active
5.5
V
0.05
2
mA
90
150
mA
Power dissipation
(1)
mA
VDD = 5.0 V
450
VDD = 3.0 V
210
750
mW
mW
Each input, VIN+ and VIN–, must meet the absolute input voltage specifications.
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TYPICAL CHARACTERISTICS
At TA = 25°C and VDD = 5V, unless otherwise indicated.
SUPPLY CURRENT vs I2C BUS FREQUENCY
SUPPLY CURRENT vs TEMPERATURE
120
250
225
VDD = 5V
200
IVDD (µA)
I VDD (µA)
100
80
25_C
175
125_C
150
125
60
100
−40_C
VDD = 2.7V
75
40
50
−60 −40 −20
0
20
40
60
80
100 120
10
140
100
1k
I2C Bus Frequency (kHz)
Temperature (_C)
Figure 1.
10k
Figure 2.
OFFSET ERROR vs TEMPERATURE
GAIN ERROR vs TEMPERATURE
0.04
2.0
0.03
PGA = 8
PGA = 4
PGA = 2
PGA = 1
Gain Error (%)
Offset Error (mV)
PGA = 8
0.02
1.0
0.0
PGA = 4
PGA = 1
0.01
0.00
-0.01
-1.0
-0.02
PGA = 2
-0.03
-2.0
-60
-40
-20
0
20
40
60
80
-0.04
-60 -40
100 120 140
-20
0
Temperature (°C)
20
40
60
80
100 120 140
Temperature (°C)
Figure 3.
Figure 4.
DATA RATE vs TEMPERATURE
160
VDD = 2.7V
Data Rate (SPS)
144
128
VDD = 5V
112
96
−60 −40 −20
0
20
40
60
80
100 120
140
Temperature (_C)
Figure 5.
4
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THEORY OF OPERATION
The ADS1000 is a fully differential, 12-bit A/D converter. The ADS1000 allows users to obtain precise
measurements with a minimum of effort, and the device is extremely easy to design with and configure.
The ADS1000 consists of an A/D converter core with adjustable gain, a clock generator, and an I2C interface.
Each of these blocks are described in detail in the sections that follow.
ANALOG-TO-DIGITAL CONVERTER
The ADS1000 uses a switched-capacitor input stage. To external circuitry, it looks roughly like a resistance. The
resistance value depends on the capacitor values and the rate at which they are switched. The switching clock is
generated by the onboard clock generator, so its frequency, nominally 275kHz, is dependent on supply voltage
and temperature. The capacitor values depend on the PGA setting.
The common-mode and differential input impedances are different. For a gain setting of PGA, the differential
input impedance is typically 2.4MΩ/PGA.
The common-mode impedance is typically 8MΩ.
OUTPUT CODE CALCULATION
The ADS1000 outputs codes in binary two’s complement format. The output code is confined to the range of
numbers: –2048 to 2047, and is given by:
Output Code + 2048(PGA)
ǒV
Ǔ
*V IN−
V DD
IN)
CLOCK GENERATOR
The ADS1000 features an onboard clock generator. The Typical Characteristics show variations in data rate over
supply voltage and temperature. It is not possible to operate the ADS1000 with an external clock.
USING THE ADS1000
OPERATING MODES
The ADS1000 operates in one of two modes: continuous conversion and single conversion.
In continuous conversion mode, the ADS1000 continuously performs conversions. Once a conversion has been
completed, the ADS1000 places the result in the output register, and immediately begins another conversion.
When the ADS1000 is in continuous conversion mode, the ST/BSY bit in the configuration register always reads
1.
In single conversion mode, the ADS1000 waits until the ST/BSY bit in the conversion register is set to 1. When
this happens, the ADS1000 powers up and performs a single conversion. After the conversion completes, the
ADS1000 places the result in the output register, resets the ST/BSY bit to 0 and powers down. Writing a 1 to
ST/BSY while a conversion is in progress has no effect.
When switching from continuous conversion mode to single conversion mode, the ADS1000 will complete the
current conversion, reset the ST/BSY bit to 0 and power-down the device.
RESET AND POWER-UP
When the ADS1000 powers up, it automatically performs a reset. As part of the reset, the ADS1000 sets all of
the bits in the configuration register to their respective default settings.
The ADS1000 responds to the I2C General Call Reset command. When the ADS1000 receives a General Call
Reset, it performs an internal reset, exactly as though it had just been powered on.
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I2C INTERFACE
The ADS1000 communicates through an I2C (Inter-Integrated Circuit) interface. The I2C interface is a two-wire,
open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive
the bus lines low, by connecting them to ground; they never drive the bus lines high. Instead, the bus wires are
pulled high by pullup resistors, so the bus wires are high when no device is driving them low. This way, two
devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.
Communication on the I2C bus always takes place between two devices, one acting as the master and the other
acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of
the master. Some I2C devices can act as masters or slaves, but the ADS1000 can only act as a slave device.
An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted
across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the bit level
while SCL is low (a Low on SDA indicates the bit is 0; a High indicates the bit is 1). Once the SDA line has
settled, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the receiver shift
register.
The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads
from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. The
master always drives the clock line. The ADS1000 never drives SCL, because it cannot act as a master. On the
ADS1000, SCL is an input only.
Most of the time the bus is idle, no communication takes place, and both lines are high. When communication
takes place, the bus is active. Only master devices can start a communication. They do this by causing a start
condition on the bus. Normally, the data line is only allowed to change state while the clock line is low. If the data
line changes state while the clock line is high, it is either a start condition or its counterpart, a stop condition. A
start condition is when the clock line is high and the data line goes from high to low. A stop condition is when the
clock line is high and the data line goes from low to high.
After the master issues a start condition, it sends a byte that indicates with which slave device it wants to
communicate. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to
which it responds. (Slaves can also have 10-bit addresses; see the I2C specification for details.) The master
sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to
the slave device.
Every byte transmitted on the I2C bus, whether it be address or data, is acknowledged with an acknowledge bit.
When a master has finished sending a byte, eight data bits, to a slave, it stops driving SDA and waits for the
slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a
clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA low
to acknowledge to the slave that it has finished reading the byte. It then sends a clock pulse to clock the bit.
(Remember that the master always drives the clock line.)
A not-acknowledge is performed by simply leaving SDA high during an acknowledge cycle. If a device is not
present on the bus, and the master attempts to address it, it will receive a not-acknowledge because no device is
present at that address to pull the line low.
When a master has finished communicating with a slave, it may issue a stop condition. When a stop condition is
issued, the bus becomes idle again. A master may also issue another start condition. When a start condition is
issued while the bus is active, it is called a repeated start condition.
A timing diagram for an ADS1000 I2C transaction is shown in Figure 6. Table 1 gives the parameters for this
diagram.
6
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t(LOW)
tR
t(HDSTA)
tF
SCL
t(HDSTA)
t(HIGH)
t(HDDAT)
t(SUSTO)
t(SUSTA)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 6. I2C Timing Diagram
Table 1. Timing Diagram Definitions
FAST MODE
PARAMETER
SCLK operating frequency
Bus free time between STOP and START
conditions
MIN
f(SCLK)
HIGH-SPEED MODE
MAX
MIN
0.4
MAX
UNITS
3.4
MHz
t(BUF)
600
160
ns
t(HDSTA)
600
160
ns
Repeated START condition setup time
t(SUSTA)
600
160
ns
STOP condition setup time
t(SUSTO)
600
160
ns
Data hold time
t(HDDAT)
0
0
ns
Data setup time
t(SUDAT)
100
10
ns
SCLK clock low period
t(LOW)
1300
160
ns
SCLK clock high period
t(HIGH)
600
60
Hold time after repeated START condition
After this period, the first clock is generated.
ns
Clock/data fall time
tF
300
160
ns
Clock/data rise time
tR
300
160
ns
ADS1000 I2C ADDRESSES
The ADS1000 I2C address is either 1001000 or 1001001, set at the factory. The address is identified with an A0
or an A1 within the orderable name.
The two different I2C variants are also marked differently. Devices with an I2C address of 1001000 have
packages marked BD0, while devices with an I2C address of 1001001 are marked with BD1.
I2C GENERAL CALL
The ADS1000 responds to General Call Reset, which is an address byte of 00h followed by a data byte of 06h.
The ADS1000 acknowledges both bytes.
On receiving a General Call Reset, the ADS1000 performs a full internal reset, just as though it had been
powered off and then on. If a conversion is in process, it is interrupted; the output register is set to zero, and the
configuration register returns to its default setting.
The ADS1000 always acknowledges the General Call address byte of 00h, but it does not acknowledge any
General Call data bytes other than 04h or 06h.
I2C DATA RATES
The I2C bus operates in one of three speed modes: Standard, which allows a clock frequency of up to 100kHz;
Fast, which allows a clock frequency of up to 400kHz; and High-speed mode (also called Hs mode), which allows
a clock frequency of up to 3.4MHz. The ADS1000 is fully compatible with all three modes.
No special action needs to be taken to use the ADS1000 in Standard or Fast modes, but High-speed mode must
be activated. To activate High-speed mode, send a special address byte of 00001XXX following the start
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condition, where the XXX bits are unique to the Hs-capable master. This byte is called the Hs master code. (Note
that this is different from normal address bytes; the low bit does not indicate read/write status.) The ADS1000 will
not acknowledge this byte; the I2C specification prohibits acknowledgment of the Hs master code. On receiving a
master code, the ADS1000 will switch on its High-speed mode filters, and will communicate at up to 3.4MHz. The
ADS1000 switches out of Hs mode with the next stop condition.
For more information on High-speed mode, consult the I2C specification.
REGISTERS
The ADS1000 has two registers that are accessible via its I2C port. The output register contains the result of the
last conversion; the configuration register allows users to change the ADS1000 operating mode and query the
status of the device.
OUTPUT REGISTER
The 16-bit output register contains the result of the last conversion in binary two’s complement format. Since the
port yields 12 bits of data, the ADS1000 outputs right-justified and sign-extended codes. This output format
makes it possible to perform averaging using a 16-bit accumulator.
Following reset or power-up, the output register is cleared to 0; it remains zero until the first conversion is
completed. Therefore, if a user reads the ADS1000 just after reset or power-up, the output register will read 0.
The output register format is shown in Table 2.
Table 2. OUTPUT REGISTER
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
D15 (1)
D14 (1)
D13 (1)
D12 (1)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(1)
D15–D12 are sign extensions of 12-bit data.
CONFIGURATION REGISTER
A user controls the ADS1000 operating mode and PGA settings via the 8-bit configuration register. The
configuration register format is shown in Table 3. The default setting is 80H.
Table 3. CONFIGURATION REGISTER
7
6
5
4
3
2
1
0
ST/BSY
0
0
SC
0
0
PGA1
PGA0
Bit 7: ST/BSY
The meaning of the ST/BSY bit depends on whether it is being written to or read from.
In single conversion mode, writing a 1 to the ST/BSY bit causes a conversion to start, and writing a 0 has no
effect. In continuous conversion mode, the ADS1000 ignores the value written to ST/BSY.
When read in single conversion mode, ST/BSY indicates whether the A/D converter is busy taking a conversion.
If ST/BSY is read as 1, the A/D converter is busy, and a conversion is taking place; if 0, no conversion is taking
place, and the result of the last conversion is available in the output register.
In continuous mode, ST/BSY is always read as 1.
Bits 6 - 5: Reserved
Bits 6 and 5 must be set to zero.
Bit 4: SC
SC controls whether the ADS1000 is in continuous conversion or single conversion mode. When SC is 1, the
ADS1000 is in single conversion mode; when SC is 0, the ADS1000 is in continuous conversion mode. The
default setting is 0.
Bits 3 - 2: Reserved
Bits 3 and 2 must be set to zero.
8
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Bits 1 - 0: PGA
Bits 1 and 0 control the ADS1000 gain setting; see Table 4.
Table 4. PGA Bits
PGA1
PGA0
GAIN
0(1)
0(1)
1(1)
0
1
2
1
0
4
1
1
8
(1) Default setting
READING FROM THE ADS1000
A user can read the output register and the contents of the configuration register from the ADS1000. To do this,
address the ADS1000 for reading, and read three bytes from the device. The first two bytes are the output
register contents; the third byte is the configuration register contents.
A user does not always have to read three bytes from the ADS1000. If only the contents of the output register
are needed, read only two bytes.
Reading more than three bytes from the ADS1000 has no effect. All of the bytes beginning with the fourth byte
will be FFh. See Figure 7 for a timing diagram of an ADS1000 read operation.
WRITING TO THE ADS1000
A user can write new contents into the configuration register (the contents of the output register cannot change).
To do this, address the ADS1000 for writing, and write one byte to it. This byte is written into the configuration
register.
Writing more than one byte to the ADS1000 has no effect. The ADS1000 ignores any bytes sent to it after the
first one, and will only acknowledge the first byte. See Figure 8 for a timing diagram of an ADS1000 write
operation.
9
1
9
1
···
SCL
SDA
1
0
0
1
A2
A1
A0
R/W
Start By
Master
D15
D14
ACK By
ADS1000
2
SDA
(Continued)
···
D7
9
D6
D5
D4
D3
D2
D1
D11 D10
D9
···
D8
ACK By
Master
Frame 2: Output Register Upper Byte
1
···
D12
From
ADS1000
Frame 1: I C Slave Address Byte
SCL
(Continued)
D13
D0
From
ADS1000
Frame 3: Output Register Lower Byte
1
ST/
BSY
9
0
0
ACK By
Master
SC
0
0
PGA1 PGA0
From
ADS1000
ACK By
Master
Stop By
Master
Frame 4: Configuration Register
(Optional)
Figure 7. Timing Diagram for Reading from the ADS1000
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1
9
1
9
SCL
SDA
1
0
0
1
A2
A1
A0
Start By
Master
R/W
ST/
BSY
0
0
SC
0
0
PGA1 PGA0
ACK By
ADS1000
2
Frame 1: I C Slave Address Byte
ACK By
ADS1000
Stop By
Master
Frame 2: Configuration Register
Figure 8. Timing Diagram for Writing to the ADS1000
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APPLICATION INFORMATION
BASIC CONNECTIONS
For many applications, connecting the ADS1000 is extremely simple. A basic connection diagram for the
ADS1000 is shown in Figure 9.
The fully differential voltage input of the ADS1000 is ideal for connection to differential sources with moderately
low source impedance, such as bridge sensors and thermistors. Although the ADS1000 can read bipolar
differential signals, it cannot accept negative voltages on either input. It may be helpful to think of the ADS1000
positive voltage input as noninverting, and of the negative input as inverting.
When the ADS1000 is converting, it draws current in short spikes. The 0.1mF bypass capacitor supplies the
momentary bursts of extra current needed from the supply.
The ADS1000 interfaces directly to standard mode, fast mode, and high-speed mode I2C controllers. Any
microcontroller I2C peripheral, including master-only and non-multiple-master I2C peripherals, will work with the
ADS1000. The ADS1000 does not perform clock-stretching (that is, it never pulls the clock line low), so it is not
necessary to provide for this unless other devices are on the same I2C bus.
Pull-up resistors are necessary on both the SDA and SCL lines because I2C bus drivers are open-drain. The size
of these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value resistors
consume less power, but increase the transition times on the bus, limiting the bus speed. Lower-value resistors
allow higher speed at the expense of higher power consumption. Long bus lines have higher capacitance and
require smaller pullup resistors to compensate. The resistors should not be too small; if they are, the bus drivers
may not be able to pull the bus lines low.
Positive Input
(0V to 5V)
Negative Input
(0V to 5V)
2
I C Pull-Up Resistors
1kW to 10kW (typ.)
VDD
ADS1000
Microcontroller or
Microprocessor
2
with I C Port
SCL
VDD
1
VIN+
VIN-
6
2
GND
VDD
5
3
SCL
SDA
4
4.7mF (typ.)
SDA
Figure 9. Typical Connections of the ADS1000
CONNECTING MULTIPLE DEVICES
Connecting two ADS1000s to a single bus is almost trivial. An example showing two ADS1000 devices and one
ADS1100 connected on a single bus is shown in Figure 10. Multiple devices can be connected to a single bus
(provided that their addresses are different).
Note that only one set of pullup resistors is needed per bus. A user might find that he or she needs to lower the
pullup resistor values slightly to compensate for the additional bus capacitance presented by multiple devices
and increased line length.
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2
I C Pull-Up Resistors
1kW to 10kW (typ.)
VDD
ADS1000A0
Microcontroller or
Microprocessor
1
VIN+
VIN-
6
with I C Port
2
GND
VDD
5
SCL
3
SCL
SDA
4
2
SDA
ADS1000A1
1
VIN+
VIN-
6
2
GND
VDD
5
3
SCL
SDA
4
ADS1100A2
NOTE: ADS1000 power
and input connections
omitted for clarity.
1
VIN+
VIN-
6
2
GND
VDD
5
3
SCL
SDA
4
Figure 10. Connecting Multiple ADS1000s
USING GPIO PORTS FOR I2C
Most microcontrollers have programmable input/output pins that can be set in software to act as inputs or
outputs. If an I2C controller is not available, the ADS1000 can be connected to GPIO pins, and the I2C bus
protocol simulated, or bit-banged, in software. An example of this for a single ADS1000 is shown in Figure 11.
VDD
ADS1000
Microcontroller or
Microprocessor
2
with I C Port
SCL
1
VIN+
VIN-
6
2
GND
VDD
5
3
SCL
SDA
4
SDA
NOTE: ADS1000 power
and input connections
omitted for clarity.
Figure 11. Using GPIO with a Single ADS1000
Bit-banging I2C with GPIO pins can be done by setting the GPIO line to zero and toggling it between input and
output modes to apply the proper bus states. To drive the line low, the pin is set to output a 0; to let the line go
high, the pin is set to input. When the pin is set to input, the state of the pin can be read; if another device is
pulling the line low, this device will read as a 0 in the port input register.
Note that no pullup resistor is shown on the SCL line. In this simple case, the resistor is not needed; the
microcontroller can simply leave the line on output, and set it to 1 or 0 as appropriate. It can do this because the
ADS1000 never drives its clock line low. This technique can also be used with multiple devices, and has the
advantage of lower current consumption resulting from the absence of a resistive pullup.
12
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ADS1000-Q1
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SBAS480A – SEPTEMBER 2009 – REVISED AUGUST 2010
If there are any devices on the bus that may drive their clock lines low, the above method should not be used;
the SCL line should be high-Z or zero and a pullup resistor provided as usual. Note also that this cannot be done
on the SDA line in any case, because the ADS1000 does drive the SDA line low from time to time, as all I2C
devices do.
Some microcontrollers have selectable strong pullup circuits built into the GPIO ports. In some cases, these can
be switched on and used in place of an external pullup resistor. Weak pullups are also provided on some
microcontrollers, but usually these are too weak for I2C communication. If there is any doubt about the matter,
test the circuit before committing it to production.
SINGLE-ENDED INPUTS
Although the ADS1000 has a fully differential input, it can easily measure single-ended signals. A simple
single-ended connection scheme is shown in Figure 12. The ADS1000 is configured for single-ended
measurement by grounding either of its input pins, usually VIN–, and applying the input signal to VIN+. The
single-ended signal can range from –0.2V to VDD + 0.3V. The ADS1000 loses no linearity anywhere in its input
range. Negative voltages cannot be applied to this circuit because the ADS1000 inputs can only accept positive
voltages.
VDD
0V - VDD
Single-Ended
Filter Capacitor
33pF to 100pF
(typ.)
ADS1000
1
VIN+
VIN-
6
2
GND
VDD
5
3
SCL
SDA
4
Output
Codes
0 - 2048
Figure 12. Measuring Single-Ended Inputs
The ADS1000 input range is bipolar differential with respect to the reference, that is, ±VDD. The single-ended
circuit shown in Figure 12 covers only half the ADS1000 input scale because it does not produce differentially
negative inputs; therefore, one bit of resolution is lost. The DRV134 balanced line driver can be employed to
regain this bit for single-ended signals.
Negative input voltages must be level-shifted. A good candidate for this function is the THS4130 differential
amplifier, which can output fully differential signals. This device can also help recover the lost bit noted previously
for single-ended positive signals. Level-shifting can also be performed using the DRV134.
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Product Folder Link(s): ADS1000-Q1
13
ADS1000-Q1
SBAS480A – SEPTEMBER 2009 – REVISED AUGUST 2010
www.ti.com
LOW-SIDE CURRENT MONITOR
Figure 13 shows a circuit for a low-side shunt-type current monitor. The circuit reads the voltage across a shunt
resistor, which is sized as small as possible while still giving a readable output voltage. This voltage is amplified
by an OPA335 low-drift op-amp, and the result is read by the ADS1000.
11.5kW
5V
V
5V
FS = 0.63V
Load
OPA335
(1)
RS
(2)
R3
49.9kW
1kW
G = 12.5
-5V
2
ADS1000
IC
(PGA Gain = 8)
5V FS
NOTES: (1) Pull-down resistor to allow accurate swing to 0V.
(2) RS is sized for a 50mV drop at full-scale current.
Figure 13. Low-Side Current Measurement
It is recommended that the ADS1000 be operated at a gain of 8. The gain of the OPA335 can then be set lower.
For a gain of 8, the op amp should be configured to give a maximum output voltage of no greater than 0.75V. If
the shunt resistor is sized to provide a maximum voltage drop of 50mV at full-scale current, the full-scale input to
the ADS1000 is 0.63V.
ADDITIONAL RECOMMENDATIONS
The ADS1000 is fabricated in a small-geometry low-voltage process. The analog inputs feature protection diodes
to the supply rails. However, the current-handling ability of these diodes is limited, and the ADS1000 can be
permanently damaged by analog input voltages that remain more than approximately 300mV beyond the rails for
extended periods. One way to protect against overvoltage is to place current-limiting resistors on the input lines.
The ADS1000 analog inputs can withstand momentary currents of as large as 10mA.
The previous paragraph does not apply to the I2C ports, which can both be driven to 6V regardless of the supply.
If the ADS1000 is driven by an op amp with high voltage supplies, such as ±12V, protection should be provided,
even if the op amp is configured so that it will not output out-of-range voltages. Many op amps seek to one of the
supply rails immediately when power is applied, usually before the input has stabilized; this momentary spike can
damage the ADS1000. Sometimes this damage is incremental and results in slow, long-term failure—which can
be disastrous for permanently installed, low-maintenance systems.
If using an op amp or other front-end circuitry with the ADS1000, be sure to take the performance characteristics
of this circuitry into account; a chain is only as strong as its weakest link.
Any data converter is only as good as its reference. For the ADS1000, the reference is the power supply, and the
power supply must be clean enough to achieve the desired performance. If a power-supply filter capacitor is
used, it should be placed close to the VDD pin, with no vias placed between the capacitor and the pin. The trace
leading to the pin should be as wide as possible, even if it must be necked down at the device.
14
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS1000A0QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ADS1000A1QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS1000-Q1 :
• Catalog: ADS1000
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
ADS1000A0QDBVRQ1
SOT-23
DBV
6
3000
180.0
8.4
ADS1000A1QDBVRQ1
SOT-23
DBV
6
3000
180.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.2
3.1
1.39
4.0
8.0
Q3
3.2
3.1
1.39
4.0
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS1000A0QDBVRQ1
SOT-23
DBV
6
3000
210.0
185.0
35.0
ADS1000A1QDBVRQ1
SOT-23
DBV
6
3000
210.0
185.0
35.0
Pack Materials-Page 2
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