LS3956 MONOLITHIC DUAL N-CHANNEL JFET The LS3956 is a Low Noise, Low Drift, Monolithic Dual N-Channel JFET The LS3956 family are matched JFET pairs for differential amplifiers. The LS3956 family of general purpose JFETs is characterized for low and medium frequency differential amplifiers requiring low offset voltage, drift, noise and capacitance The LS3956 family exhibits low capacitance - 6pF max and a spot noise figure of - 0.5dB max. The part offers a superior tracking ability. The 8 Pin P-DIP and 8 Pin SOIC provide ease of manufacturing, and the symmetrical pinout prevents improper orientation. (See Packaging Information). LS3956 Applications: Wideband Differential Amps High Input Impedance Amplifiers FEATURES LOW DRIFT LOW LEAKAGE LOW NOISE ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted) |∆ VGS1‐2 /∆T|= 5µV/°C max. IG = 20pA TYP. en = 10nV/√Hz TYP. Maximum Temperatures Storage Temperature ‐65°C to +200°C Operating Junction Temperature +150°C Maximum Voltage and Current for Each Transistor – Note 1 ‐VGSS Gate Voltage to Drain or Source 60V ‐VDSO Drain to Source Voltage 60V ‐IG(f) Gate Forward Current 50mA Maximum Power Dissipation Device Dissipation @ Free Air – Total 400mW @ 25°C MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED SYMBOL CHARACTERISTICS VALUE UNITS CONDITIONS | V GS1‐2 / T| max. DRIFT VS. 50 µV/°C VDG=20V, ID=200µA TEMPERATURE TA=‐55°C to +125°C | V GS1‐2 | max. OFFSET VOLTAGE 15 mV VDG=20V, ID=200µA ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted) SYMBOL CHARACTERISTICS MIN. TYP. BVGSS Breakdown Voltage 60 ‐‐ BVGGO Gate‐To‐Gate Breakdown 60 ‐‐ TRANSCONDUCTANCE YfSS Full Conduction 1000 2000 YfS Typical Operation 500 700 |YFS1‐2 / Y FS| Mismatch ‐‐ 0.6 DRAIN CURRENT IDSS Full Conduction 0.5 2 |IDSS1‐2 / IDSS| Mismatch at Full Conduction ‐‐ 1 GATE VOLTAGE VGS(off) or Vp Pinchoff voltage 1 2 VGS(on) Operating Range 0.5 ‐‐ GATE CURRENT ‐IG Operating ‐‐ 20 ‐IG High Temperature ‐‐ ‐‐ ‐IG Reduced VDG ‐‐ 5 ‐IGSS At Full Conduction ‐‐ ‐‐ OUTPUT CONDUCTANCE YOSS Full Conduction ‐‐ ‐‐ YOS Operating ‐‐ 0.1 |YOS1‐2| Differential ‐‐ 0.01 COMMON MODE REJECTION CMR ‐20 log | VGS1‐2/ VDS| ‐‐ 100 CMR ‐20 log | VGS1‐2/ VDS| ‐‐ 75 NOISE NF Figure ‐‐ ‐‐ en Voltage ‐‐ ‐‐ CAPACITANCE CISS Input ‐‐ ‐‐ CRSS Reverse Transfer ‐‐ ‐‐ CDD Drain‐to‐Drain ‐‐ 0.1 MAX. ‐‐ ‐‐ UNITS V V CONDITIONS VDS = 0 ID=1µA I G= 1nA ID= 0 I S= 0 3000 1000 3 µmho µmho % VDG= 20V VDG= 20V 5 5 mA % VDG= 20V VGS= 0V 4.5 4 V V VDS= 20V VDS=20V ID= 1nA ID=200µA 50 50 ‐‐ 100 pA nA pA pA 5 1 0.1 µmho µmho µmho ‐‐ ‐‐ dB dB 0.5 15 dB nV/√Hz 6 2 ‐‐ pF pF pF VGS= 0V f = 1kHz ID= 200µA Click To Buy VDG= 20V TA= +125°C VDG= 10V VDG= 20V ID= 200µA ID= 200µA VDS= 0 VDG= 20V VDG= 20V VGS= 0V ID= 200µA ∆VDS = 10 to 20V ID=200µA ∆VDS = 5 to 10V ID=200µA VDS= 20V VGS= 0V RG= 10MΩ f= 100Hz NBW= 6Hz VDS=20V ID=200µA f=10Hz NBW=1Hz VDS= 20V VGS= 0V VDG= 20V f= 1MHz ID= 200µA Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired PDIP / SOIC (Top View) Micross Components Europe Available Packages: LS3956 in PDIP / SOIC LS3956 available as bare die Please contact Micross for full package and die dimensions Tel: +44 1603 788967 Email: [email protected] Web: http://www.micross.com/distribution Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.