CPC7556 Diode Bridge with Integrated Adjustable OVP Circuit Bridge Characteristics Parameter Description Rating Units Reverse Voltage 100 V Forward Current 240 mArms Thyristor Current 120 mA Features • Monolithic Construction • Surface Mount Package Applications • Telecommunications Protection Clamp • High Voltage Multiplexer/Switch • High Voltage ESD Clamp 100V Diode Bridge with an integrated Over-Voltage Protection (OVP) thyristor uses Clare's High Voltage SOI technology. The CPC7556N integrated diode bridge offers protection from high voltage transients by means of an adjustable voltage clamp. The clamp performs two actions, first to limit the voltage across the diode bridge rectified outputs to a value determined by external resistors and the gate voltage and second to fully discharge the V+ to V outputs when the Gate’s trigger threshold is exceeded during the voltage limiting function. The rectified outputs are discharged as a result of the voltage fold-back function of the OVP device. Voltage fold back of the OVP circuit will continue until the current through the protector falls below the hold current threshold. Terminating the gate to V will disable the clamp voltage feature up to the thyristor’s off state voltage. Ordering Information Pb e3 RoHS 2002/95/EC Part Description CPC7556N 8-Pin SOIC in Tubes (50/Tube) CPC7556NTR 8-Pin SOIC Tape & Reel (1000/Reel) CPC7556N Diagram A/B + A K B/A G - DS-CPC7556 - R02 www.clare.com 1 CPC7556 1 Specifications 1.2 Pin Description 1.1 Package Pinout 8 1 Pin# Name Description 1 Negative Bridge Output 2 G Thyristor Gate 3 N/C No Connection 4 + Positive Bridge Output - ~B G N/C N/C N/C 5 ~A Input A + ~A 6 N/C No Connection 7 N/C No Connection 8 ~B Input B 4 5 1.3 Absolute Maximum Ratings Unless Otherwise Specified all electrical ratings are at 25C Parameter Symbol Minimum Maximum Units VRRM - 120 V IF - 250 mArms Diode Forward Surge Current IFSM - 2 A Gate Voltage VGK -4 7 V Gate Current IGK - 20 mA Overvoltage Current IAK - 120 mA Thyristor Surge Current ITSM - 1.2 A 2 It - 0.02 A2s - - 3 kV TJ - +150 C TSTG -65 +150 C Reverse Voltage Diode Forward Current (Average) Fusing Current ESD, Human Body Model Junction Temperature 1 Storage Temperature 1 Derate package for PDISS 120C/W. Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. R02 www.clare.com 2 CPC7556 1.4 Recommended Operating Conditions Parameter Symbol Minimum Maximum Units Diode Forward Current (Average) IF - 240 mArms Reverse Voltage VR - 100 V Operating Temperature Range TA -40 +125 C Thermal Impedance JA 120 - C/W 1.5 General Conditions Typical values are characteristic of the device at 25C and are the result of engineering evaluations. They are provided for information purposes only and are not part of the manufacturing testing requirements. Unless otherwise noted, all electrical specifications are listed for TA=25C. 1.6 DC Electrical Characteristics Parameter Conditions Symbol Minimum Typical Maximum Units - IF - - 240 mArms 0.83 0.91 0.97 1 1.3 1.49 Diode Bridge Characteristics: Forward Current Diode Forward Voltage Drop IF = 40mA IF = 250mA VF V VR = 100V IR - - 1 A V+/ = VAK = 10V, IAK = 110mA IGT 0.5 1.2 1.8 mA VGK 2.5 2.8 3.2 V Trigger Current - IAKT - 25 40 mA Hold Current - IH 70 100 - mA VGK = 0V, IAK = 5 uA VDRM 110 - - V Reverse Voltage Leakage Current Thyrister Characteristics: Gate Trigger Current Gate Trigger Voltage Peak Off State Voltage 3 www.clare.com R02 CPC7556 1.7 AC Electrical Characteristics Parameter Input Zero Bias Capacitance Conditions Symbol Minimum Typical Maximum Units V+ V = 0V Measured from V~A to V~B C~A~B - 4.4 12 pF V~A = V~B Measured from V+ to V C+/ - 8.3 20 pF V+ V = 0V Measured from V~A to V+/- and V~B to V+/- C~A/+, C~A/, C~B/+, C~B/ - 8.5 12 pF EPP - - 300 mJ EAVE - - 14 mJ Output Zero Bias Capacitance Bridge Zero Bias Capacitance Thyristor Peak Pulse Discharge Energy Thyristor Repeated Discharge Energy Single Event Over-Voltage Discharge Energy Allowable Repeated Discharge Energy, Rectified 60Hz 2 Typical Performance Data Diode Forward Voltage (VF) vs. Temperature 1.2 1.0 0.8 IF=40mA 0.6 0.4 0.2 0 -40 -20 0 20 40 60 Temperature (ºC) 100 80 IF=250mA 2.6 2.4 2.2 2.0 IF=40mA 1.8 1.6 1.4 1.2 1.0 -40 -20 0 20 40 60 Temperature (ºC) 80 Gate Trigger Voltage (V) Gate Trigger Current (mA) 150 148 146 144 142 140 138 -40 -20 0 20 40 60 Temperature (ºC) 80 100 80 100 3.4 3.0 2.5 2.0 1.5 1.0 0.5 0 R02 100 152 Gate Trigger Voltage vs. Temperature Gate Trigger Current vs. Temperature -40 Reverse Breakdown Voltage (V) 2.8 IF=250mA 1.4 Diode Forward Voltage (V) Diode Forward Voltage (V) 1.6 Diode Reverse Breakdown Voltage (VRRM) vs. Temperature Bridge Forward Voltage (VF) vs. Temperature -20 0 20 40 60 Temperature (ºC) 80 100 3.2 3.0 2.8 2.6 2.4 2.2 2.0 -40 www.clare.com -20 0 20 40 60 Temperature (ºC) 4 CPC7556 3 Manufacturing Information 3.1 Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. Clare classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033. Device Moisture Sensitivity Level (MSL) Rating CPC7556N MSL 1 3.2 ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD-625. 3.3 Reflow Profile This product has a maximum body temperature and time rating as shown below. All other guidelines of J-STD-020 must be observed. Device Maximum Temperature x Time CPC7556N 260C for 30 seconds 3.4 Board Wash Clare recommends the use of no-clean flux formulations. However, board washing to remove flux residue is acceptable. The use of a short drying bake may be necessary if a wash is used after solder reflow processes. Chlorine-based or Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be used. Pb 5 RoHS 2002/95/EC e3 www.clare.com R02 CPC7556 3.5 8-Pin SOIC Package Dimensions 0.1905 / 0.2489 (0.0075 / 0.0098) 0.406 / 1.270 (0.016 / 0.050) 3.810 / 3.988 (0.150 / 0.157) 5.8014 / 6.1976 (0.2284 / 0.2440) PCB Land Pattern 1.50 (0.059) PIN 1 1.27 TYP (0.05 TYP) 0.356 / 0.457 (0.014 / 0.018) 5.30 (0.209) 1.372 / 1.575 (0.054 / 0.062) 4.801 / 4.978 (0.189 / 0.196) 0.60 (0.024) 1.27 (0.050) 0.1016 / 0.2489 (0.0040 / 0.0098) Dimensions mm MIN / mm MAX (inches MIN / inches MAX) 1.524 / 1.727 (0.060 / 0.068) 0.533 REF (0.021 REF) 3.6 Tape & Reel Dimensions 330.2 DIA. (13.00 DIA.) Top Cover Tape Thickness 0.102 MAX. (0.004 MAX.) W=12.00 (0.472) B0=5.30 (0.209) K0= 2.10 (0.083) A0=6.50 (0.256) P=8.00 (0.315) User Direction of Feed Embossed Carrier Embossment Dimensions mm (inches) NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2 For additional information please visit our website at: www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC7556 - R02 ©Copyright 2011, Clare, Inc. All rights reserved. Printed in USA. 8/17/2011 R02 www.clare.com 6