19-3385; Rev 0; 8/04 Multiple-Output Network Clock Generator Features ♦ 15 LVCMOS Outputs with 10 Independently Programmable Frequencies: 133MHz, 125MHz, 100MHz, 83MHz, 80MHz, 66MHz, 62.5MHz, 50MHz, 33MHz, and 25MHz ♦ 25MHz Crystal or Clock Input Reference ♦ Programmable Through I2C Interface ♦ Programmable Output Frequency Margin of ±5% or ±10% ♦ Pin-Selectable Power-Up Frequency for CLK1 Output: 100MHz, 125MHz, or 133MHz Applications ♦ Low Output Period Jitter: < 48psRMS ♦ Output-to-Output Skew < 200ps ♦ Available in 32-Lead, 5mm x 5mm x 0.8mm, Thin QFN Package ♦ Operates from +3.0V to +3.6V Power Supply ♦ Power Dissipation 450mW (typ) ♦ Extended Temperature Range: -40°C to +85°C Network Routers Ordering Information Telecom/Networking Equipment Storage Area Networks/Network Attached Storage PART MAX9489ETJ TEMP RANGE PIN-PACKAGE -40°C to +85°C 32 Thin QFN-EP* 5mm x 5mm x 0.8mm Pin Configuration CLK13 CLK14 CLK15 VDD GND SA0 VDD SA1 *EP = Exposed pad. TOP VIEW Typical Operating Circuit 32 31 30 29 28 27 26 25 GND 1 24 VDD SCL 2 23 CLK12 SDA 3 4 5 20 VDD X1 6 19 CLK9 X2 7 17 CLK7 X1 I 2C is a trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. VDD VDD 25MHz 10pF VDD X2 VDD CLK6 CLK5 CLK4 VDD THIN QFN-EP VDD 10pF 10 11 12 13 14 15 16 CLK3 CLK1 9 CLK2 8 VDD MAX9489 18 CLK8 EXPOSED PAD (GND) 0.1µF x 5 AVDD 21 CLK10 SEL +3.3V 0.1µF 22 CLK11 MAX9489 AVDD AGND +3.3V SERIAL INTERFACE CLK1 SDA CLOCK OUTPUTS SCL SA0 CLK15 SA1 SEL AGND GND ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9489 General Description The MAX9489 clock generator provides multiple clock outputs, ideal for network routers. The MAX9489 provides 15 buffered clock outputs, each independently programmable to any of 10 individual frequencies: 133MHz, 125MHz, 100MHz, 83MHz, 80MHz, 66MHz, 62.5MHz, 50MHz, 33MHz, or 25MHz. All of the outputs are single-ended LVCMOS. The MAX9489 is controlled through its I2C™ interface. At power-up, the frequency of output CLK1 is set by the tri-level input SEL to 100MHz, 125MHz, or 133MHz, while all other outputs are logic low. All outputs are then programmable to any available frequency through the I2C interface. Additionally, all output frequencies are adjustable up or down, by a margin of 5% or 10%, through the I2C interface. The MAX9489 requires a 25MHz reference that can be either a crystal or an external clock signal. The MAX9489 requires a +3.0V to +3.6V power supply and is available in a 32-pin thin QFN package with an exposed pad for heat removal. MAX9489 Multiple-Output Network Clock Generator ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................…….….-0.3V to +4.0V AGND to GND .............................................……...-0.3V to +0.3V All Other Pins to GND.................................-0.3V to (VDD + 0.3V) Short-Circuit Duration for all CLK_ Outputs ...............Continuous Continuous Power Dissipation (TA = +70°C) 32-Pin Thin QFN (derate 21.3mW/°C above +70°C) ....1702mW Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Operating Temperature Range ...........................-40°C to +85°C ESD Rating (Human Body Model) .......................................±2kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VDD = AVDD = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = AVDD = +3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.8 V +5 µA CLOCK INPUT (X1) Input High Level VIH1 Input Low Level VIL1 Input Current IIL1, IIH1 2.0 VX_ = 0 to VDD -5 V CLOCK OUTPUTS (CLK_) IOH = -100µA Output High Level VOH VDD 0.2 IOH = -4mA 2.4 IOH = -8mA 2.1 IOL = 100µA Output Low Level VOL V 0.2 IOL = 4mA 0.4 IOL = 8mA 0.75 V Output Short-Circuit Current IOS CLK_ = VDD or GND 45 mA Output Capacitance CO (Note 2) 5 pF 0.8 V 1.35 1.90 V -10 +10 µA TRI-LEVEL INPUTS (SEL, SA0, SA1) Input High Level VIH2 Input Low Level VIL2 Input Open Level VIO2 Input Current IIL2, IIH2 2.5 VIL2 = 0 or VIH2 = VDD V SERIAL INTERFACE (SCL, SDA) (Note 3) Input High Level VIH 0.7 x VDD VDD V Input Low Level VIL 0 0.3 x VDD V -1 +1 µA 0 0.4 V 10 pF Input leakage Current IIH, IIL Low-Level Output VOL Input Capacitance Ci 2 ISINK = 4mA (Note 2) _______________________________________________________________________________________ Multiple-Output Network Clock Generator (VDD = AVDD = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = AVDD = +3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS V POWER SUPPLIES Digital Power-Supply Voltage VDD 3.0 3.6 Analog Power-Supply Voltage AVDD 3.0 3.6 V Total Supply Current Total Power-Down Current IPD CL = 10pf (with all CLK_ outputs at 133MHz) 134 160 mA All clock registers = 0x00 38 47 mA AC ELECTRICAL CHARACTERISTICS (VDD = AVDD = +3.0V to +3.6V, CL = 10pF, unless otherwise noted. Typical values are at VDD = AVDD = +3.3V, TA = +25°C, with all CLK_ outputs at 133MHz.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS +50 ppm 200 ps OUTPUTS (CLK_) Crystal Frequency Tolerance ∆fA Output-to-Output Skew tSKO Any two CLK_ outputs Rise Time tR1 20% VDD to 80% VDD 1.8 2.5 ns Fall Time tF1 80% VDD to 20% VDD 1.8 2.5 ns 60 % -50 Duty Cycle 40 Output Period Jitter JP RMS 53 ps Power-Up Time tPO VDD > 2.8V to PLL lock 2 ms PLL dividing ratio set to PLL lock 20 µs PLL Lockup Time Margin Accuracy tLock Select ±5% or ±10% margin -1 +1 % _______________________________________________________________________________________ 3 MAX9489 DC ELECTRICAL CHARACTERISTICS (continued) MAX9489 Multiple-Output Network Clock Generator SERIAL INTERFACE TIMING (VDD = AVDD = +3.3V, TA = -40°C to +85°C.) (Note 1, Figure 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz Serial Clock fSCL Bus Free Time Between STOP and START Conditions tBUF 1.3 µs Hold Time, Repeated START Condition tHD,STA 0.6 µs Repeated START Condition Setup Time tSU,STA 0.6 µs STOP Condition Setup Time tSU,STO Data Hold Time Master tHD,DAT (Note 4) 0.6 15 900 µs ns Data Hold Time Slave tHD,DAT (Note 4) 15 900 ns Data Setup Time tSU,DAT 100 ns SCL Clock Low Period tLOW 1.3 µs SCL Clock High Period µs tHIGH 0.7 Rise Time of SDA and SCL, Receiving tR (Notes 2, 5) 20 + 0.1Cb 300 ns Fall Time of SDA and SCL, Receiving tF (Notes 2, 5) 20 + 0.1Cb 300 ns tF,TX (Notes 2, 5) 20 + 0.1Cb 250 ns Pulse Width of Spike Suppressed tSP (Notes 2, 6) 0 50 ns Capacitive Load for Each Bus Line Cb (Note 2) 400 pF Fall Time of SDA, Transmitting Note 1: All DC parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design. Note 3: No high output level is specified but only the output resistance to the bus. For I2C, the high-level voltage is provided by pullup resistors on the bus. Note 4: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL’s falling edge. Note 5: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3(VDD) and 0.7(VDD). Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. 4 _______________________________________________________________________________________ Multiple-Output Network Clock Generator RISE AND FALL TIMES vs. TEMPERATURE 130 120 110 2.1 tFALL 1.9 tRISE 1.7 1.4 1.2 -40 -15 10 35 60 40 30 25MHz 20 0 -40 85 50 10 1.0 100 133MHz 60 RMS PERIOD JITTER (ps) TRANSITION TIME (ns) 2.3 140 -15 10 35 85 60 -40 -15 TEMPERATURE (°C) TEMPERATURE (°C) 35 60 85 TYPICAL CLOCK WAVEFORMS MAX9489 toc05 MAX9489 toc04 60 10 TEMPERATURE (°C) JITTER vs. FREQUENCY 75 RMS PERIOD JITTER (ps) SUPPLY CURRENT (mA) 150 JITTER vs. TEMPERATURE 70 MAX9489 toc03 MAX9489 toc01 160 MAX9489 toc02 SUPPLY CURRENT vs. TEMPERATURE A 45 30 B 15 0 25 43 61 79 97 FREQUENCY (MHz) 115 133 10ns/div A: 100MHz, 100mV/div B: 25MHz, 100mV/div _______________________________________________________________________________________ 5 MAX9489 Typical Operating Characteristics (VDD = 3.3V, TA = +25°C, unless otherwise noted.) Multiple-Output Network Clock Generator MAX9489 Pin Description PIN NAME 1, 29 GND Digital Ground 2 SCL Serial Clock Input. Serial interface clock. 3 SDA Serial Data I/O. Data I/O of serial interface. 4 SEL Frequency Select for CLK1. Selects the frequency for CLK1 at power-up. SEL is a tri-level input. Force SEL high for CLK1 = 100MHz. Leave SEL open for CLK1 = 125MHz. Force SEL low for CLK1 = 133MHz. 5 AVDD 6 X1 7 X2 8 AGND Analog GND 9 CLK1 Clock 1 Output 10 CLK2 Clock 2 Output 11 CLK3 Clock 3 Output 12, 16, 20, 24, 28, 32 VDD 13 CLK4 Clock 4 Output 14 CLK5 Clock 5 Output 15 CLK6 Clock 6 Output 17 CLK7 Clock 7 Output 18 CLK8 Clock 8 Output 19 CLK9 Clock 9 Output 21 CLK10 Clock 10 Output 22 CLK11 Clock 11 Output 23 CLK12 Clock 12 Output 25 CLK13 Clock 13 Output 26 CLK14 Clock 14 Output 27 CLK15 Clock 15 Output 30 SA0 31 SA1 EP — 6 FUNCTION Power-Supply Input for Analog Circuits Crystal Connection or Clock Input. If using a 25MHz crystal, connect it to X1 and X2. If using a reference clock, connect the clock signal to X1, and leave X2 floating. See the Typical Operating Circuit. Power-Supply Input for Digital Circuits Address-Select Inputs for Serial Interface. SA0 and SA1 select the serial interface address, as shown in Table 1. SA0 and SA1 are tri-level inputs, making nine possible address combinations. Exposed pad. Connect to GND. _______________________________________________________________________________________ Multiple-Output Network Clock Generator The MAX9489 clock generator produces 15 clock signals, CLK1 through CLK15. Each output is programmable through control registers to any of 10 individual frequencies: 133MHz, 125MHz, 100MHz, 83MHz, 80MHz, 66MHz, 62.5MHz, 50MHz, 33MHz, or 25MHz. Additionally, the frequency of all outputs can be changed ±5% or ±10% through the frequency-margin control register. At power-up, the frequency of CLK1 is pin programmable to 100MHz, 125MHz, or 133MHz, and all other CLK outputs are logic low. The required 25MHz input reference frequency can be either a crystal or an external clock signal. Figure 1 shows the MAX9489 functional block diagram. The MAX9489 is programmed through its I 2C serial interface. The I2C address is selected with two, tri-level inputs, allowing up to nine MAX9489 devices to share the same I2C bus. Power-supply and logic interface signals are +3.0V to +3.6V. The operating state of the MAX9489 is set by writing to the control registers, and read by reading the control registers. Reference Frequency Input A reference frequency is required for the MAX9489. The reference can be a 25MHz crystal or an external clock signal. If using a 25MHz crystal, connect it across X1 and X2, and connect 10pF capacitors from X1 and X2 to GND (see the Typical Operating Circuit). If using an external clock, connect the signal to X1 and leave X2 floating. Serial Interface The MAX9489 is programmed through its I 2C serial interface. This interface has a clock, SCL, and a bidirectional data line, SDA. In an I2C system, a master, typically a microcontroller, initiates all data transfers to and from slave devices, and generates the clock to synchronize the data transfers. The MAX9489 operates as a slave device. The timing of the SDA and SCL signals is detailed in Figure 2, the Serial Interface Timing diagram. SDA operates as both an input and an open-drain output. A pullup resistor, typically 4.7kΩ, is required on SDA. SCL operates only as an input. A pullup resistor, typically 4.7kΩ, is required on SCL if there are multiple masters on the 2wire bus, or if the master in a single-master system has an open-drain SCL output. Bit Transfer One data bit is transferred during each SCL clock cycle. SDA must remain stable during the high period of SCL, because changes in SDA while SCL is high are START and STOP control signals. Both SDA and SCL idle high. START and STOP Conditions AVDD VDD SEL SCL SDA MUX I2C SA0 SA1 CLK1 Acknowledge Bits MUX X1 400MHz PLL1 DIVIDE BY 3, 4, 5, 6, 12 400MHz PLL2 DIVIDE BY 2, 3, 4, 5, 10 CLK2 25MHz OSC X2 A master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high (Figure 2). When communication is complete, a master issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. Device Address MAX9489 AGND After each 8 bits transferred, the receiving device generates an acknowledge signal by pulling SDA low for the entire duration of the 9th clock pulse. If the receiving device does not pull SDA low, a not-acknowledge is indicated (Figure 3). MUX CLK14 MUX CLK15 The MAX9489 has a 7-bit device address, pin configured by the two tri-level address inputs SA1 and SA0. To select the device address, connect SA1 and SA0 to VDD, GND, or leave open, as indicated in Table 1. The MAX9489 has nine possible addresses, allowing up to nine MAX9489 devices to share the same interface bus. GND Figure 1. MAX9489 Functional Diagram _______________________________________________________________________________________ 7 MAX9489 Detailed Description MAX9489 Multiple-Output Network Clock Generator SDA tBUF tSU, STA tSU, DAT tHD, STA tLOW tSU, STO tHD, DAT SCL tHIGH tHD, STA tR tF REPEATED START CONDITION START CONDITION STOP CONDITION START CONDITION Figure 2. Serial Interface Timing Table 1. Device I2C Address Selection PIN SA0 DEVICE ADDRESS Open VDD 110 0010 Open GND 110 0100 Open Open 110 1000 GND VDD 111 0000 GND GND 110 1001 GND Open 110 1100 VDD VDD 111 0100 VDD GND 111 0010 VDD Open 111 0001 SA1 Writing to the MAX9489 Writing to the MAX9489 begins with a START condition (Figures 3 and 4). Following the START condition, each pulse on SCL transfers 1 bit of data. The first 7 bits comprise the device address (see the Device Address section). The 8th bit is low to indicate a write operation. An acknowledge bit is then generated by the MAX9489, signaling that it recognizes its address. The next 8 bits form the register address byte (Table 2) and determine which control register will receive the following data byte. The MAX9489 then generates another acknowledge bit. The data byte is then written into the addressed register of the MAX9489. An acknowledge bit by the MAX9489 followed by a required STOP condition by the master complete the communication. To write to the device again, repeat the entire write procedure; I 2C burst write mode is not supported by the MAX9489. 8 Reading the MAX9489 Setup Reading from the MAX9489 registers begins with a START condition and a device address with the write bit set low, then the register address that is to be read, followed by a repeated START condition and a device address with the write bit set high, and finally the data are shifted out (Figure 4). Following a START condition, the first 7 bits comprise the device address. The 8th bit is low to indicate a write operation (to write in the following register address). An acknowledge bit is then generated by the MAX9489, signaling that it recognizes its address. The next 8 bits form the register address, indicating the location of the data to be read, followed by another acknowledge, again generated by the MAX9489. The master then produces a repeated START condition and readdresses the device, this time with the R/W bit high to indicate a read operation (Figure 4). The MAX9489 generates an acknowledge bit, signaling that it recognizes its address. The data byte is then clocked out of the MAX9489. A final notacknowledge bit, generated by the master (not required), and a STOP condition, also generated by the master, complete the communication. To read from the device again, the entire read procedure is repeated; I2C burst read mode is not supported by the MAX9489. Device Control Registers The MAX9489 has 17 control registers. The register addresses and functions are shown in Table 2. The first 16 registers are used to set the 15 outputs, with register 0x00 controlling all outputs simultaneously and the rest mapped to individual outputs. Register 0x10 accesses the frequency-margin control. All other addresses are reserved and are not to be used. _______________________________________________________________________________________ Multiple-Output Network Clock Generator MAX9489 NOT ACKNOWLEDGE 1 SDA 1 A4 A3 A2 A1 A0 ACKNOWLEDGE LSB MSB ACK R/W SCL START Figure 3. I2C Address and Acknowledge MASTER-WRITE DATA STRUCTURE START S DEVICE ADDRESS 1 1 A4 A3 A2 A1 R/W REGISTER ADDRESS 0 ACK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK DATA IN D7 D6 D5 D4 D6 D5 D4 D3 D3 STOP D2 D1 D0 D0 ACK ACK P MASTER-READ DATA STRUCTURE START S DEVICE ADDRESS 1 1 A4 A3 A2 A1 R/W REGISTER ADDRESS 0 ACK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK DEVICE ADDRESS RS S = START CONDITION A_ = DEVICE ADDRESS ACK = ACKNOWLEDGE ACK = NOT ACKNOWLEDGE 1 RA_ = REGISTER ADDRESS D_ = DATA P = STOP CONDITION RS = REPEATED START 1 A4 A3 A2 A1 R/W A0 1 DATA OUT ACK D7 D2 D1 STOP P DATA DIRECTION = MASTER TO SLAVE = SLAVE TO MASTER Figure 4. I2C Interface Data Structure Setting the Clock Frequencies Each CLK_ output has an associated control register. The contents of the registers determine the frequency of their associated outputs. Table 3 provides the frequency mapping for the registers. Example: To program CLK3 to 80MHz, first address the device with R/W low, then send register address byte 0x03 followed by data byte 0x05 (Figure 5). Frequency Margin Control Frequency margin is controlled through control register 0x10. Table 4 provides the mapping for the available margins. A selected margin applies to all outputs. Example: To increase all clock outputs by 5%, address the device, then send register address byte 0x10 followed by data byte 0x01. Bypass each VDD at the device with a 0.1µF capacitor. Also bypass AVDD at the device with a 0.1µF capacitor. Additionally, use a bulk bypass capacitor of 10µF where power enters the circuit board. Board Layout Considerations As with all high-frequency devices, board layout is critical to proper operation. Place the crystal as close as possible to X1 and X2, and minimize parasitic capacitance around the crystal leads. Ensure that the exposed pad makes good contact with GND. Chip Information TRANSISTOR COUNT: 15,219 PROCESS: CMOS Power Supply The MAX9489 uses a 3.0V to 3.6V power supply connected to VDD, and 3.0V to 3.6V connected to AVDD. _______________________________________________________________________________________ 9 MAX9489 Multiple-Output Network Clock Generator Table 2. Register Address Mapping Table 3. Output Frequency Control REGISTER ADDRESS BYTE REGISTER FUNCTION 0x00 Broadcast to all CLK registers CLK_ REGISTER DATA BYTE OUTPUT FREQUENCY (MHz) 0x01 CLK1 0x00 Logic low* 0x02 CLK2 0x01 133.3 0x03 CLK3 0x02 125 0x04 CLK4 0x03 100 0x05 CLK5 0x04 83.3 0x06 CLK6 0x05 80 0x07 CLK7 0x06 66.6 0x08 CLK8 0x07 62.5 0x09 CLK9 0x08 50 0x0A CLK10 0x09 33 0x0A 25 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x10 Frequency margin control 0x11 – 0xFF Reserved, do not use START S DEVICE ADDRESS 1 1 A4 S = START CONDITION A_ = DEVICE ADDRESS A3 A2 A1 R/W 0 *Power-up default for CLK2 through CLK15. Table 4. Output Frequency Margin Control MARGIN REGISTER DATA BYTE OUTPUT FREQUENCY (MHz) 0x00 0% 0x01 5% 0x02 10% 0x07 -5% 0x06 -10% REGISTER ADDRESS ACK ACK = ACKNOWLEDGE P = STOP CONDITION 0 0 0 0 0 0 DATA IN 1 1 ACK 0 0 0 0 0 STOP 1 DATA DIRECTION = MASTER TO SLAVE = SLAVE TO MASTER Figure 5. Example—Setting CLK3 to 80MHz 10 ______________________________________________________________________________________ 0 1 ACK P Multiple-Output Network Clock Generator b C L 0.10 M C A B D2/2 D/2 k 0.15 C B MARKING QFN THIN.EPS D2 0.15 C A D XXXXX E/2 E2/2 C L (NE-1) X e E E2 k L DETAIL A PIN # 1 I.D. e PIN # 1 I.D. 0.35x45∞ (ND-1) X e DETAIL B e L1 L C L C L L L e e 0.10 C A C 0.08 C A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm 21-0140 -DRAWING NOT TO SCALE- COMMON DIMENSIONS A1 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 A3 b D E L1 0 0.20 REF. 0.02 0.05 0 0.20 REF. 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. e k L 0.02 0.05 0 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.25 - 0.25 - 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 - - - - - N ND NE 16 4 4 20 5 5 JEDEC WHHB WHHC - - 1 2 EXPOSED PAD VARIATIONS PKG. 32L 5x5 16L 5x5 20L 5x5 28L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A F - - - 28 7 7 WHHD-1 - - 32 8 8 WHHD-2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. D2 L E2 PKG. CODES MIN. NOM. MAX. MIN. NOM. MAX. ±0.15 T1655-1 T1655-2 T1655N-1 3.00 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.10 3.20 3.10 3.20 T2055-2 T2055-3 T2055-4 3.00 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.10 3.10 3.20 3.20 3.20 ** ** ** ** T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 ** ** 0.40 DOWN BONDS ALLOWED NO YES NO NO YES NO Y ** NO NO YES YES NO ** ** 0.40 ** ** ** ** ** NO YES Y N NO YES NO NO ** ** ** ** ** SEE COMMON DIMENSIONS TABLE 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm 21-0140 -DRAWING NOT TO SCALE- F 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9489 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)