AD AD73422BB-40 Dual low power cmos analog front end with dsp microcomputer Datasheet

a
Dual Low Power CMOS
Analog Front End with DSP Microcomputer
AD73422
FEATURES
AFE PERFORMANCE
Two 16-Bit A/D Converters
Two 16-Bit D/A Converters
Programmable Input/Output Sample Rates
78 dB ADC SNR
77 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25 ␮s Typ per ADC Channel,
50 ␮s Typ per DAC Channel)
Programmable Input/Output Gain
On-Chip Reference
DSP PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
GENERAL DESCRIPTION
The AD73422 is a single device incorporating a dual analog
front end and a microcomputer optimized for digital signal
processing (DSP) and other high speed numeric processing
applications.
The AD73422’s analog front end (AFE) section features a dual
front-end converter for general purpose applications including
speech and telephony. The AFE section features two 16-bit A/D
conversion channels and two 16-bit D/A conversion channels.
Each channel provides 77 dB signal-to-noise ratio over a
voiceband signal bandwidth. It also features an input-to-output
gain network in both the analog and digital domains. This is
featured on both codecs and can be used for impedance matching or scaling when interfacing to Subscriber Line Interface
Circuits (SLICs).
The AD73422 is particularly suitable for a variety of applications in the speech and telephony area including low bit rate,
high quality compression, speech enhancement, recognition
and synthesis. The low group delay characteristic of the AFE
makes it suitable for single or multichannel active control
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
DATA
ADDRESS
GENERATORS
PROGRAM
SEQUENCER
DAG 1 DAG 2
MEMORY
16K PM
16K DM
(OPTIONAL (OPTIONAL
8K)
8K)
FULL MEMORY
MODE
PROGRAMMABLE
I/O
AND
FLAGS
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
PROGRAM MEMORY DATA
OR
DATA MEMORY DATA
ARITHMETIC UNITS
ALU
MAC
SHIFTER
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
ADSP-2100 BASE
ARCHITECTURE
INTERNAL
DMA
PORT
HOST MODE
REF
ADC1
SERIAL PORT
SPORT 2
DAC1
ADC2
DAC2
ANALOG FRONT END
SECTION
applications. The A/D and D/A conversion channels feature
programmable input/output gains with ranges 38 dB and 21 dB
respectively. An on-chip reference voltage is included to allow
single supply operation.
The sampling rate of the AFE is programmable with four separate settings offering 64, 32, 16 and 8 kHz sampling rates (from
a master clock of 16.384 MHz), while the serial port (SPORT2)
allows easy expansion of the number of I/O channels by cascading extra AFEs external to the AD73422.
The AD73422’s DSP engine combines the ADSP-2100 family
base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities and on-chip program
and data memory.
The AD73422-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM, and 16K
words (16-bit) of data RAM. The AD73422-40 integrates 40K
bytes of on-chip memory configured as 8K words (24-bit) of
program RAM, and 8K words (16-bit) of data RAM. Powerdown circuitry is also provided to meet the low power needs of
battery operated portable equipment. The AD73422 is available
in a 119-ball PBGA package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
(AVDD = DVDD = VDD = +3 V to 3.6 V; DGND = AGND = 0 V, fDMCLK = 16.384 MHz,
SAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted.)
AD73422–SPECIFICATIONS f
Parameter
Min
AFE SECTION
REFERENCE
REFCAP
Absolute Voltage, VREFCAP
REFCAP TC
REFOUT
Typical Output Impedance
Absolute Voltage, VREFOUT
Minimum Load Resistance
Maximum Load Capacitance
Typ
1.125 1.25
50
1.08
1
130
1.2
Max
Units
1.375
V
ppm/°C
1.32
100
INPUT AMPLIFIER
Offset
Maximum Output Swing
Ω
V
kΩ
pF
Test Conditions
0.1 µF Capacitor Required from
REFCAP to AGND2
Unloaded
± 1.0
1.578
mV
V
Feedback Resistance
Feedback Capacitance
50
100
kΩ
pF
ANALOG GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Gain Accuracy
Settling Time
Delay
+1
–1
5
± 1.0
1.0
0.5
Bits
%
ms
ms
Gain Step Size = 0.0625
Output Unloaded
Tap Gain Change of –FS to +FS
1.578
–2.85
1.0954
–6.02
V p-p
dBm
V p-p
dBm
Measured Differentially.
Max Input = (1.578/1.25) × VREFCAP
Measured Differentially
dB
dB
dB
1.0 kHz, 0 dBm0
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to –50 dBm0
dB
dB
dB
dB
300 Hz to 3400 Hz; fSAMP = 64 kHz
300 Hz to 3400 Hz; fSAMP = 8 kHz
0 Hz to fSAMP/2; fSAMP = 64 kHz
300 Hz to 3400 Hz; fSAMP = 64 kHz
dB
dB
dB
dBm0
dB
300 Hz to 3400 Hz; fSAMP = 64 kHz
300 Hz to 3400 Hz; fSAMP = 64 kHz
PGA = 0 dB
PGA = 0 dB
ADC Input Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
ADC1 Input Level: 1.0 kHz, 0 dBm0
ADC2 Input at Idle. Input Amps Bypassed
Input Amplifiers Included in Input
Channel
PGA = 0 dB
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
ADC SPECIFICATIONS
Maximum Input Range at VIN2, 3
Nominal Reference Level at VIN
(0 dBm0)
Absolute Gain
PGA = 0 dB
PGA = 38 dB
Gain Tracking Error
Signal to (Noise + Distortion)
PGA = 0 dB
–0.5
0.4
–0.7
± 0.1
72
78
78
57
56
55
PGA = 38 dB
Total Harmonic Distortion
PGA = 0 dB
PGA = 38 dB
Intermodulation Distortion
Idle Channel Noise
Crosstalk, ADC-to-DAC
–84
–70
–65
–71
–100
ADC-to-ADC
DC Offset
Power Supply Rejection
Group Delay4, 5
Input Resistance at PGA2, 4, 6
DIGITAL GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Delay
Settling Time
–30
+1.2
–73
–100
dB
–70
dB
+10
–65
+45
mV
dB
25
20
µs
kΩ
+1
–1
16
25
100
Bits
ms
ms
–2–
Max Output Swing = (1.578/1.25) ×
VREFCAP
fC = 32 kHz
DMCLK = 16.384 MHz; Input
Amplifiers Bypassed and AGT Off
Tested to 5 MSBs of Settings
Includes DAC Delay
Tap Gain Change from –FS to +FS;
Includes DAC Settling Time
REV. 0
AD73422
Parameter
Min
DAC SPECIFICATIONS
Maximum Voltage Output Swing2
Single-Ended
Differential
Output Bias Voltage
Absolute Gain
Gain Tracking Error
Signal to (Noise + Distortion) at 0 dBm0
PGA = 6 dB
Total Harmonic Distortion at 0 dBm0
PGA = 6 dB
Intermodulation Distortion
Idle Channel Noise
Crosstalk, DAC-to-ADC
Max
1.578
–2.85
3.156
3.17
Differential
Nominal Voltage Output Swing (0 dBm0)
Single-Ended
Typ
1.0954
–6.02
2.1909
0
1.2
–0.85 +0.4
± 0.1
62.5
+0.85
77
–80
–85
–85
–90
–62.5
Units
Test Conditions
V p-p
dBm
V p-p
dBm
PGA = 6 dB
Max Output = (1.578/1.25) × VREFCAP
PGA = 6 dB
Max Output = 2 × ((1.578/1.25) × VREFCAP)
V p-p
dBm
V p-p
dBm
V
dB
dB
PGA = 6 dB
dB
300 Hz to 3400 Hz; fSAMP = 64 kHz
dB
dB
dBm0
dB
300 Hz to 3400 Hz; fSAMP = 64 kHz
PGA = 0 dB
PGA = 0 dB
ADC Input Level: AGND;
DAC Output Level: 1.0 kHz, 0 dBm0;
Input Amplifiers Bypassed
Input Amplifiers Included in Input Channel
DAC1 Output Level: AGND;
DAC2 Output Level: 1.0 kHz, 0 dBm0
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Interpolator Bypassed
DAC-to-DAC
–77
–100
dB
dB
Power Supply Rejection
–65
dB
Group Delay4, 5
25
50
+20
µs
µs
mV
Output DC Offset2, 7
Minimum Load Resistance, RL2, 8
Single-Ended4
Differential
Maximum Load Capacitance, CL2, 8
Single-Ended4
Differential
–20
+60
REFOUT Unloaded
1.0 kHz, 0 dBm0; Unloaded
1.0 kHz, +3 dBm0 to –50 dBm0
Ω
Ω
600
600
500
100
pF
pF
V
V
µA
pF
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IIH, Input Current
CIN, Input Capacitance4
DVDD – 0.8
0
–10
12
DVDD
0.8
+10
24
LOGIC OUTPUT
VOH, Output High Voltage
VOL, Output Low Voltage
Three-State Leakage Current
DVDD – 0.4
0
–10
DVDD V
0.4
V
+10
µA
3.0
3.0
3.6
3.6
POWER SUPPLIES
AVDD
DVDD
IDD10
PGA = 6 dB
|IOUT| ≤ 100 µA
|IOUT| ≤ 100 µA
V
V
See Table I
NOTES
1
Operating temperature range is as follows: –20°C to +85°C; therefore, T MIN = –20°C and TMAX = +85°C.
2
Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).
3
At input to sigma-delta modulator of ADC.
4
Guaranteed by design.
5
Overall group delay will be affected by the sample rate and the external digital filtering.
6
The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3 × 1011)/DMCLK.
7
Between VOUTP1 and VOUTN1 or between VOUTP2 and VOUTN2.
8
At VOUT output.
9
Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier bypassed and input gain of 0 dB.
10
Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
REV. 0
–3–
(AVDD = DVDD = VDD = +3 V to 3.6 V; DGND = AGND = 0 V, fDMCLK = 16.384 MHz,
SAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted.)
AD73422–SPECIFICATIONS f
Parameter
DSP SECTION
VIH
VIH
VIL
VOH
Hi-Level Input Voltage1, 2
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage1, 4, 5
VOL
Lo-Level Output Voltage1, 4, 5
IIH
Hi-Level Input Current3
IIL
Lo-Level Input Current3
IOZH
Three-State Leakage Current7
IOZL
Three-State Leakage Current7
IDD
Supply Current (Idle)9
IDD
Supply Current (Dynamic)11
CI
Input Pin Capacitance3, 6, 12
CO
Output Pin Capacitance6, 7, 12, 13
Test Conditions
Min
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min
IOH = –0.5 mA
@ VDD = min
IOH = –100 µA6
@ VDD = min
IOL = 2 mA
@ VDD = max
VIN = VDD max
@ VDD = max
VIN = 0 V
@ VDD = max
VIN = VDD max8
@ VDD = max
VIN = 0 V8
@ VDD = 3.6
tCK = 19 ns10
tCK = 25 ns10
tCK = 30 ns10
@ VDD = 3.6
TAMB = +25°C
tCK = 19 ns10
tCK = 25 ns10
tCK = 30 ns10
@ VIN = 2.5 V
fIN = 1.0 MHz
TAMB = +25°C
@ VIN = 2.5 V
fIN = 1.0 MHz
TAMB = +25°C
2.0
2.2
Typ
Max
Units
0.8
V
V
V
2.4
V
VDD – 0.3
V
0.4
V
10
µA
10
µA
10
µA
10
µA
12
10
9
mA
mA
mA
54
43
37
mA
mA
mA
8
12
pF
10
20
pF
NOTES
1
Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2
Input only pins: RESET, BR, DR0, DR1, PWD.
3
Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.
5
Although specified for TTL outputs, all AD73422 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.
8
0 V on BR.
9
Idle refers to AD73422 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.
10
VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
11
IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.
12
Applies to PBGA package type.
13
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
–4–
REV. 0
AD73422
POWER CONSUMPTION
Conditions
AFE SECTION
ADCs Only On
DACs Only On
ADCs and DACs On
ADCs and DACs
and Input Amps On
ADCs and DACs
and AGT On
All Sections On
REFCAP Only On
REFCAP and
REFOUT Only On
All AFE Sections Off
All AFE Sections Off
Typ
Max
SE
AMCLK On
Test Conditions
11.5
20
24.5
12
22
27
1
1
1
YES
YES
YES
REFOUT Disabled
REFOUT Disabled
REFOUT Disabled
30
34
1
YES
REFOUT Disabled
29
37
0.8
32.5
43.5
1.25
1
1
0
YES
YES
NO
REFOUT Disabled
3.5
1.5
10 µA
4.75
3.0
40 µA
0
0
0
NO
YES
NO
REFOUT Disabled
AMCLK Active Levels Equal to 0 V and DVDD
Digital Inputs Static and Equal to 0 V or DVDD
NOTES
The above values are in mA and are typical values unless otherwise noted.
Specifications subject to change without notice.
TIMING CHARACTERISTICS–AFE SECTION1
Parameter
Clock Signals
t1
t2
t3
Serial Port
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Limit
Units
61
24.4
24.4
ns min
ns min
ns min
t1
0.4 × t1
0.4 × t1
20
0
10
10
10
10
30
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
Description
See Figure 1
16.384 MHz AMCLK Period
AMCLK Width High
AMCLK Width Low
See Figures 3 and 4
SCLK Period (SCLK = AMCLK)
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from AMCLK
NOTES
1
For details of the DSP section timing, please refer to the ADSP-2185L data sheet and the ADSP-2100 Family User’s Manual, Third Edition.
Specifications subject to change without notice.
REV. 0
–5–
AD73422
ABSOLUTE MAXIMUM RATINGS*
Reflow Soldering
Maximum Temperature . . . . . . . . . . . . . . . . . . . . . . +225°C
Time at Maximum Temperature . . . . . . . . . . . . . . . . . 15 sec
Maximum Temperature Ramp Rate . . . . . . . . . . . . 1.3°C/sec
(TA = +25°C unless otherwise noted)
AVDD, DVDD to GND . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –20°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –40°C to +125°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +150°C
PBGA, θJA Thermal Impedance . . . . . . . . . . . . . . . . . 25°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD73422 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
AD73422BB-80
AD73422BB-40
EVAL-AD73422EB
Temperature
Range
Package
Description
Package
Option
–20°C to +85°C
–20°C to +85°C
119-Ball Plastic Ball Grid Array
119-Ball Plastic Ball Grid Array
Evaluation Board
B-119
B-119
PBGA BALL CONFIGURATION
1
2
3
4
5
6
7
A
IRQE/PF4
DMS
VDD (INT)
CLKIN
A11/IAD10
A7/IAD6
A4/IAD3
B
IRQL0/PF5
PMS
WR
XTAL
A12/IAD11
A8/IAD7
A5/IAD4
C
IRQL1/PF6
IOMS
RD
VDD (EXT)
A13/IAD12
A9/IAD8
GND
D
IRQ2/PF7
CMS
BMS
CLKOUT
GND
A10/IAD9
A6/IAD5
A1/IAD0
A0
E
DT0
TFS0
RFS0
A3/IAD2
A2/IAD1
F
DR0
SCLK0
DT1/F0
PWDACK
BGH
G
TFS1/IRQ1
RFS1/IRQ0
DR1/FI
GND
PWD
VDD (EXT)
H
SCLK1
ERESET
RESET
PF3
FL0
FL1
FL2
EE
ECLK
D23
D22
D21
D20
MODE A /PF0 MODE B/PF1
MODE C /PF2
J
EMS
K
ELOUT
ELIN
EINT
D19
D18
D17
D16
L
BG
D3/IACK
D5/IAL
D8
D9
D12
D15
M
EBG
D2/IAD15
D4/IS
D7/IWR
VDD (EXT)
D11
D14
N
BR
D1/IAD14
VDD (INT)
D6/IRD
GND
D10
D13
DVDD
DGND
ARESET
SCLK2
AMCLK
P
EBR
D0/IAD13
R
SDO
SDOFS
SDIFS
SDI
SE
REFCAP
REFOUT
T
VFBP1
VINP1
VFBN1
VINN1
VFBN2
VINN2
VFBP2
U
AGND
AVDD
VOUTP2
VOUTN2
VOUTP1
VOUTN1
VINP2
TOP VIEW
NOTES:
VDD (INT) – DSP CORE SUPPLY
VDD (EXT) – DSP I/O DRIVER SUPPLY
BOTH VDD (INT) AND VDD (EXT) SHOULD BE POWERED FROM THE SAME SUPPLY.
–6–
REV. 0
AD73422
PBGA BALL CONFIGURATION DESCRIPTIONS
Mnemonic
BGA
Location
VINP1
VFBP1
T2
T1
VINN1
VFBN1
T4
T3
REFOUT
R7
REFCAP
R6
DGND
DVDD
ARESET
P4
P3
P5
SCLK2
P6
AMCLK
P7
SDO
R1
SDOFS
R2
SDIFS
R3
SDI
R4
SE
R5
AGND
AVDD
VOUTP2
VOUTN2
VOUTP1
VOUTN1
VINP2
VFBP2
U1
U2
U3
U4
U5
U6
U7
T7
VINN2
VFBN2
T6
T5
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2/
PF7
IRQL1/
PF6
H3
N1
L1
F5
A2
B2
C2
D3
D2
C3
B3
REV. 0
D1
C1
Function
Analog Input to the inverting terminal of the inverting input amplifier on Channel 1’s Positive Input.
Feedback connection from the output of the inverting amplifier on Channel 1’s positive input. When the input
amplifiers are bypassed, this pin allows direct access to the positive input of Channel 1’s sigma-delta modulator.
Analog Input to the inverting terminal of the inverting input amplifier on Channel 1’s Negative Input.
Feedback connection from the output of the inverting amplifier on Channel 1’s positive input. When the input
amplifiers are bypassed, this pin allows direct access to the negative input of Channel 1’s sigma-delta modulator.
Buffered Reference Output, which has a nominal value of 1.2 V. As the reference is common to the two
codec units, the reference value is set by the wired OR of the CRC:7 bits in each codec’s status register.
A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should be
fixed to this pin.
AFE Digital Ground/Substrate Connection.
AFE Digital Power Supply Connection.
Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the
digital circuitry.
Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock data
or control information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the master clock (AMCLK) divided by an integer number—this integer number being the product of the external master clock rate divider and the serial clock rate divider.
AFE Master Clock Input. AMCLK is driven from an external clock signal. If it is required to run the DSP
and AFE sections from a common clock crystal, AMCLK should be connected to the XTAL pin of the
DSP section.
Serial Data Output of the Codec. Both data and control information may be output on this pin and is clocked on
the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low.
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK
period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK.
SDOFS is in three-state when SE is low.
Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is
ignored when SE is low.
Serial Data Input of the Codec. Both data and control information may be input on this pin and are clocked
on the negative edge of SCLK. SDI is ignored when SE is low.
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in
order to decrease power dissipation. When SE is brought high, the control and data registers of the SPORT
are at their original values (before SE was brought low), however the timing counters and other internal
registers are at their reset values.
AFE Analog Ground/Substrate Connection.
AFE Analog Power Supply Connection.
Analog Output from the Positive Terminal of Output Channel 2.
Analog Output from the Negative Terminal of Output Channel 2.
Analog Output from the Positive Terminal of Output Channel 1.
Analog Output from the Negative Terminal of Output Channel 1.
Analog Input to the inverting terminal of the inverting input amplifier on Channel 2’s Positive Input.
Feedback connection from the output of the inverting amplifier on Channel 2’s positive input. When the input
amplifiers are bypassed, this pin allows direct access to the positive input of Channel 2’s sigma-delta modulator.
Analog Input to the inverting terminal of the inverting input amplifier on Channel 2’s Negative Input.
Feedback connection from the output of the inverting amplifier on Channel 2’s Negative Input. When the input
amplifiers are bypassed, this pin allows direct access to the negative input of Channel 2’s sigma-delta modulator.
(Input) Processor Reset Input.
(Input) Bus Request Input.
(Output) Bus Grant Output.
(Output) Bus Grant Hung Output.
(Output) Data Memory Select Output.
(Output) Program Memory Select Output.
(Output) Memory Select Output.
(Output) Byte Memory Select Output.
(Output) Combined Memory Select Output.
(Output) Memory Read Enable Output.
(Output) Memory Write Enable Output.
(Input) Edge- or Level-Sensitive Interrupt Request 1.
(Input/Output) Programmable I/O Pin.
(Input) Level-Sensitive Interrupt Requests 1.
(Input/Output) Programmable I/O Pin.
–7–
AD73422
PBGA BALL CONFIGURATION DESCRIPTIONS (Continued)
Mnemonic
IRQL0/
PF5
IRQE/
PF4
PF3
Mode C/
PF2
Mode B/
PF1
Mode A/
PF0
CLKIN
XTAL
CLKOUT
SPORT0
TFS0
RFS0
DT0
DR0
SCLK0
SPORT1
TFS1/
IRQ1
RFS1
IRQ0
DT1/
FO
DR1/
FI
SCLK1
FL0
FL1
FL2
VDD(INT)
VDD(EXT)
GND
EZ-ICE Port
ERESET
EMS
EE
ECLK
ELOUT
ELIN
EINT
EBR
EBG
Address Bus
Data Bus
BGA
Location
Function
F6
A4
B4
D4
(Input) Level-Sensitive Interrupt Requests 1.
(Input/Output) Programmable I/O Pin.
(Input) Edge-Sensitive Interrupt Requests 1.
(Input/Output) Programmable I/O Pin.
(Input/Output) Programmable I/O Pin During Normal Operation.
(Input) Mode Select Input—Checked Only During RESET.
(Input/Output) Programmable I/O Pin During Normal Operation.
(Input) Mode Select Input—Checked Only During RESET.
(Input/Output) Programmable I/O Pin During Normal Operation.
(Input) Mode Select Input—Checked Only During RESET.
(Input/Output) Programmable I/O Pin During Normal Operation.
(Inputs) Clock or Quartz Crystal Input. The CLKIN input cannot be halted or changed during operation
nor operated below 10 MHz during normal operation.
(Output) Processor Clock Output.
E2
E3
E1
F1
F2
(Input/Output) SPORT0 Transmit Frame Sync.
(Input/Output) SPORT0 Receive Frame Sync.
(Output) SPORT0 Transmit Data.
(Input) SPORT0 Receive Data.
(Input/Output) SPORT0 Serial Clock.
B1
A1
H4
G7
F7
G1
G2
F3
G3
H1
H5
H6
H7
A3
N3
C4
G6
M5
C7
D5
G4
N5
(Input/Output) SPORT1 Transmit Frame Sync.
(Input) Edge or Level Sensitive Interrupt.
(Input/Output) SPORT1 Receive Frame Sync.
(Input) Edge or Level Sensitive Interrupt.
(Output) SPORT1 Transmit Data.
(Output) Flag Out 2.
(Input) SPORT1 Receive Data.
(Input) Flag In2.
(Input/Output) SPORT1 Serial Clock.
(Output) Flag 0.
(Output) Flag 1.
(Output) Flag 2.
(Input) DSP Core Supply.
(Input) DSP I/O Interface Supply.
DSP Ground.
H2
J1
J2
J3
K1
K2
K3
P1
M1
A0–E7; A1/IAD0–E6; A2/IAD1–E5; A3/IAD2–E4; A4/IAD3–A7; A5/IAD4–B7; A6/IAD5–D7; A7/IAD6–A6;
A8/IAD7–B6; A9/IAD8–C6; A10/IAD9–D6; A11/IAD10–A5; A12/IAD11–B5; A13/IAD12–C5
D0/IAD13–P2; D1/IAD14–N2; D2/IAD15–M2; D3/IACK–L2; D4/IS–M3; D5/IAL–L3; D6/IRD–N4; D7/IWR–
M4; D8–L4; D9–L5; D10–N6; D11–M6; D12–L6; D13–N7; D14–M7; D15–L7; D16–K7; D17–K6; D18–K5;
D19–K4; D20–J7; D21–J6; D22–J5; D23–J4
NOTES
1
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt
vector address when the pin is asserted, either by external devices, or set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Software configurable.
–8–
REV. 0
AD73422
ARCHITECTURE OVERVIEW
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
The AD73422 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single processor cycle. The AD73422 assembly language uses an algebraic
syntax for ease of coding and readability. A comprehensive set
of development tools supports program development.
POWER-DOWN
CONTROL
DATA
ADDRESS
GENERATORS
PROGRAM
SEQUENCER
DAG 1 DAG 2
MEMORY
16K PM
16K DM
(OPTIONAL (OPTIONAL
8K)
8K)
The AD73422 can respond to eleven interrupts. There can be
up to six external interrupts (one edge-sensitive, two levelsensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and
a wide variety of framed or frameless data transmit and receive
modes of operation.
FULL MEMORY
MODE
PROGRAMMABLE
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
PROGRAM MEMORY DATA
OR
DATA MEMORY DATA
ARITHMETIC UNITS
ALU
MAC
SHIFTER
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
EXTERNAL
DATA
BUS
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
ADSP-2100 BASE
ARCHITECTURE
Each port can generate an internal programmable serial clock or
accept an external serial clock.
INTERNAL
DMA
PORT
The AD73422 provides up to 13 general-purpose flag pins. The
data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs and three flags are
always outputs.
HOST MODE
REF
ADC1
SERIAL PORT
SPORT 2
DAC1
ADC2
DAC2
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n processor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
ANALOG FRONT END
SECTION
Figure 1. Functional Block Diagram
Figure 1 is an overall block diagram of the AD73422. The processor section contains three independent computational units:
the ALU, the multiplier/accumulator (MAC) and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs singlecycle multiply, multiply/add and multiply/subtract operations
with 40 bits of accumulation. The shifter performs logical and
arithmetic shifts, normalization, denormalization and derive
exponent operations.
Analog Front End
The AFE section is configured as a separate block that is normally connected to either SPORT0 or SPORT1 of the DSP
section. As it is not hardwired to either SPORT, the user has
total flexibility in how they wish to allocate system resources to
support the AFE. It is also possible to further expand the number of analog I/O channels connected to the SPORT by cascading other single or dual channel AFEs (AD73311 or AD73322)
external to the AD73422.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
The AFE is configured as a cascade of two I/O channels (similar
to that of the discrete AD73322—refer to the AD73322 data sheet
for more details), with each channel having a separate 16-bit
sigma-delta based ADC and DAC. Both channels share a common reference whose nominal value is 1.2 V. Figure 2 shows a
block diagram of the AFE section of the AD73422. It shows two
channels of ADC and DAC conversion, along with a common
reference. Communication to both channels is handled by the
SPORT2 block which interfaces to either SPORT0 or SPORT1 of
the DSP section.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the AD73422 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
Figure 3 shows the analog connectivity available on each channel of the AFE (Channel 1 is detailed here). Both channels
feature fully differential inputs and outputs. The input section
allows direct connection to the internal Programmable Gain
Amplifier at the input of the sigma-delta ADC section, or optional inverting amplifiers may be configured to provide some
fixed external gain or to interface to a transducer with relatively
high source impedance. The input section also features programmable differential channel inversion and configuration of
the differential input as two separate single-ended inputs. The
ADC features a second order sigma-delta modulator which
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
REV. 0
–9–
AD73422
VFBN1
VINN1
INVERT
SINGLE-ENDED
ENABLE
ANALOG
LOOPBACK
VREF
0/38dB
PGA
ANALOG
SIGMA-DELTA
MODULATOR
DECIMATOR
SDI
VINP1
VFBP1
SDIFS
GAIN
1
VOUTP1
CONTINUOUS
TIME
LOW-PASS
FILTER
+6/–15dB
PGA
VOUTN1
GAIN
1
SWITCHED
CAPACITOR
LOW-PASS
FILTER
1-BIT
DAC
DIGITAL
SIGMADELTA
MODULATOR
SCLK2
INTERPOLATOR
SERIAL
I/O
PORT
REFERENCE
REFCAP
AD73422
AFE SECTION
REFOUT
ARESET
AMCLK
VFBN2
SE
VINN2
INVERT
SINGLE-ENDED
ENABLE
ANALOG
LOOPBACK
VREF
0/38dB
PGA
ANALOG
SIGMA-DELTA
MODULATOR
DECIMATOR
VINP2
VFBP2
GAIN
1
VOUTP2
VOUTN2
+6/–15dB
PGA
GAIN
1
CONTINUOUS
TIME
LOW-PASS
FILTER
SWITCHED
CAPACITOR
LOW-PASS
FILTER
1-BIT
DAC
DIGITAL
SIGMADELTA
MODULATOR
SDO
SDOFS
INTERPOLATOR
Figure 2. Functional Block Diagram of Analog Front End Section
samples at DMCLK/8. Its bitstream output is filtered and decimated by a Sinc-cubed decimator to provide a sample rate selectable from 64 kHz, 32 kHz, 16 kHz or 8 kHz (based on an
AMCLK of 16.384 MHz).
INVERTING
OP AMPS
ANALOG
LOOP-BACK
SELECT
INVERT
Each channel also features two programmable gain elements,
Analog Gain Tap (AGT) and Digital Gain Tap (DGT), which,
when enabled, add a signed and scaled amount of the input
signal to the DAC’s output signal. This is of particular use in
line impedance balancing when interfacing the AFE to Subscriber Line Interface Circuits (SLICs).
SINGLE-ENDED
ENABLE
FUNCTIONAL DESCRIPTION - AFE
Encoder Channels
VFBN1
VINN1
Both encoder channels consist of a pair of inverting op amps
with feedback connections that can be bypassed if required, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part
of the sigma-delta ADC, also performs critical system-level
filtering. Due to the high level of oversampling, the input antialias requirements are reduced such that a simple single-pole
RC stage is sufficient to give adequate attenuation in the band
of interest.
VREF
0/38dB
PGA
VINP1
VFBP1
GAIN
1
VREF
ANALOG
GAIN TAP
VOUTP1
+6/–15dB
PGA
VOUTN1
REFOUT
REFCAP
REFERENCE
CONTINUOUS
TIME
LOW-PASS
FILTER
Programmable Gain Amplifier
AD73422
AFE SECTION
Figure 3. Analog Front End Configuration
The DAC channel features a Sinc-cubed interpolator which
increases the sample rate from the selected rate to the digital
sigma-delta modulator rate of DMCLK/8. The digital sigmadelta modulator’s output bitstream is fed to a single-bit DAC
whose output is reconstructed/filtered by two stages of low-pass
filtering (switched capacitor and continuous time) before being
applied to the differential output driver.
Each encoder section’s analog front end comprises a switched
capacitor PGA which also forms part of the sigma-delta modulator. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table I, may be
used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in control register D.
–10–
REV. 0
AD73422
of these techniques, followed by the application of a digital
filter, sufficiently reduces the noise in band to ensure good
dynamic performance from the part (Figure 4c).
Table I. PGA Settings for the Encoder Channel
IGS2
IGS1
IGS0
Gain (dB)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
6
12
18
20
26
32
38
ADC
Both ADCs consist of an analog sigma-delta modulator and a
digital antialiasing decimation filter. The sigma-delta modulator noise-shapes the signal and produces 1-bit samples at a
DMCLK/8 rate. This bitstream, representing the analog input
signal, is input to the antialiasing decimation filter. The decimation filter reduces the sample rate and increases the resolution.
Analog Sigma-Delta Modulator
The AD73422’s input channels employ a sigma-delta conversion technique, which provides a high resolution 16-bit output
with system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as oversampling where the sampling rate is many times the highest
frequency of interest. In the case of the AD73422, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to FS/2 = DMCLK/16
(Figure 4a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 4b). The combination
Figure 5 shows the various stages of filtering that are employed
in a typical AD73422 application. In Figure 5a we see the transfer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes
care of any signals that could be aliased by the sampling frequency. This also shows the major difference between the initial
oversampling rate and the bandwidth of interest. In Figure 5b,
the signal and noise-shaping responses of the sigma-delta modulator are shown. The signal response provides further rejection
of any high frequency signals, while the noise-shaping will push
the inherent quantization noise to an out-of-band position. The
detail of Figure 5c shows the response of the digital decimation filter (Sinc-cubed response) with nulls every multiple of
DMCLK/256, which corresponds to the decimation filter update rate for a 64 kHz sampling. The nulls of the Sinc3 response
correspond with multiples of the chosen sampling frequency.
The final detail in Figure 5d shows the application of a final
antialias filter in the DSP engine. This has the advantage of
being implemented according to the user’s requirements and
available MIPS. The filtering in Figures 5a through 5c is implemented in the AD73422.
FSINIT = DMCLK/8
FB = 4kHz
a. Analog Antialias Filter Transfer Function
SIGNAL TRANSFER FUNCTION
NOISE TRANSFER FUNCTION
BAND
OF
INTEREST
FS /2
DMCLK/16
FSINIT = DMCLK/8
FB = 4kHz
a.
b. Analog Sigma-Delta Modulator Transfer Function
NOISE-SHAPING
BAND
OF
INTEREST
FS /2
DMCLK/16
FB = 4kHz
b.
FSINTER = DMCLK/256
c. Digital Decimator Transfer Function
DIGITAL FILTER
BAND
OF
INTEREST
c.
FS /2
DMCLK/16
FB = 4kHz FSFINAL = 8kHz
Figure 4. Sigma-Delta Noise Reduction
REV. 0
FSINTER = DMCLK/256
d. Final Filter LPF (HPF) Transfer Function
Figure 5. ADC Frequency Responses
–11–
AD73422
Decimation Filter
The digital filter used in the AD73422’s AFE section carries out
two important functions. Firstly, it removes the out-of-band
quantization noise, which is shaped by the analog modulator,
and secondly, it decimates the high frequency bitstream to a
lower rate 16-bit word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/
256, and increases the resolution from a single bit to 15 bits or
greater (depending on chosen sampling rate). Its Z transform is
given as: [(1–Z–N)/(1–Z–1)]3 where N is set by the sampling rate
(N = 32 @ 64 kHz sampling . . . N = 256 @ 8 kHz sampling)
Thus when the sampling rate is 64 kHz a minimal group delay
of 25 µs can be achieved.
The ADC coding scheme is in twos complement format (see
Figure 6). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a word length of up to 18 bits
(depending on decimation rate chosen), which is the final output of the ADC block. In Data Mode this value is truncated to
16 bits for output on the Serial Data Output (SDO) pin. For
input values equal to or greater than positive full scale, however,
ANALOG
INPUT
VREF
VREF – (VREF ⴛ 0.32875)
10...00
VFBN
00...00
01...11
ADC CODE DIFFERENTIAL
The decoder channels consist of digital interpolators, digital
sigma-delta modulators, single bit digital-to-analog converters
(DAC), analog smoothing filters and programmable gain amplifiers with differential outputs.
The DAC coding scheme is in twos complement format with
0x7FFF being full-scale positive and 0x8000 being full-scale
negative.
ADC Coding
VFBP
Decoder Channel
DAC Coding
Word growth in the decimator is determined by the sampling
rate. At 64 kHz sampling, where the oversampling ratio between
sigma-delta modulator and decimator output equals 32, we get
five bits per stage of the three stage Sinc3 filter. Due to symmetry within the sigma-delta modulator, the LSB will always be a
zero, therefore the 16-bit ADC output word will have 2 LSBs
equal to zero, one due to the sigma-delta symmetry and the
other being a padding zero to make up the 16-bit word. At
lower sampling rates, decimator word growth will be greater
than the 16-bit sample word, therefore truncation occurs in
transferring the decimator output as the ADC word. For example
at 8 kHz sampling, word growth reaches 24 bits due to the OSR
of 256 between sigma-delta modulator and decimator output.
This yields eight bits per stage of the 3-stage Sinc3 filter.
VREF + (VREF ⴛ 0.32875)
the output word is set at 0x7FFF, which has the LSB set to 1.
In mixed Control/Data Mode, the resolution is fixed at 15 bits,
with the MSB of the 16-bit transfer being used as a flag bit to
indicate either control or data in the frame.
Interpolation Filter
The anti-imaging interpolation filter is a sinc-cubed digital filter
that up-samples the 16-bit input words from the input sample
rate to a rate of DMCLK/8, while filtering to attenuate images
produced by the interpolation process. Its’ Z transform is given
as: [(1–Z–N)/(1–Z–1)]3 where N is determined by the sampling
rate (N = 32 @ 64 kHz . . . N = 256 @ 8 kHz). The DAC receives 16-bit samples from the host DSP processor at the programmed sample rate of DMCLK/N. If the host processor fails
to write a new value to the serial port, the existing (previous)
data is read again. The data stream is filtered by the anti-imaging
interpolation filter, but there is an option to bypass the interpolator for the minimum group delay configuration by setting the
IBYP bit (CRE:5) of Control Register E. The interpolation filter
has the same characteristics as the ADC’s antialiasing decimation filter.
The output of the interpolation filter is fed to the DAC’s digital
sigma-delta modulator, which converts the 16-bit data to 1-bit
samples at a rate of DMCLK/8. The modulator noise-shapes
the signal so that errors inherent to the process are minimized in
the passband of the converter. The bitstream output of the
sigma-delta modulator is fed to the single bit DAC where it is
converted to an analog voltage.
Analog Smoothing Filter and PGA
The output of the single-bit DAC is sampled at DMCLK/8,
therefore it is necessary to filter the output to reconstruct the
low frequency signal. The decoder’s analog smoothing filter
consists of a continuous-time filter preceded by a third-order
switched-capacitor filter. The continuous-time filter forms part
of the output programmable gain amplifier (PGA). The PGA
can be used to adjust the output signal level from –15 dB to
+6 dB in 3 dB steps, as shown in Table II. The PGA gain is
set by bits OGS0, OGS1 and OGS2 (CRD:4-6) in Control
Register D.
Table II. PGA Settings for the Decoder Channel
VREF + (VREF ⴛ 0.6575)
VFBP
ANALOG
INPUT
VREF
VREF – (VREF ⴛ 0.6575)
VFBN
10...00
00...00
01...11
ADC CODE SINGLE-ENDED
Figure 6. ADC Transfer Function
OGS2
OGS1
OGS0
Gain (dB)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+6
+3
0
–3
–6
–9
–12
–15
–12–
REV. 0
AD73422
Differential Output Amplifiers
Table III. Analog Gain Tap Settings*
The decoder has a differential analog output pair (VOUTP and
VOUTN). The output channel can be muted by setting the
MUTE bit (CRD:7) in Control Register D. The output signal is
dc-biased to the codec’s on-chip voltage reference.
Voltage Reference
The AD73422 reference, REFCAP, is a bandgap reference that
provides a low noise, temperature-compensated reference to the
DAC and ADC. A buffered version of the reference is also made
available on the REFOUT pin and can be used to bias other
external analog circuitry. The reference has a nominal value of
1.2 V.
The reference output (REFOUT) can be enabled for biasing
external circuitry by setting the RU bit (CRC:6) of CRC.
INVERTING
OP AMPS
ANALOG
LOOP-BACK
SELECT
AGTC3
AGTC2
AGTC1 AGTC0
Gain
0
0
0
0
0
—
0
1
—
1
1
1
0
0
0
0
0
—
1
0
—
1
1
1
0
0
0
0
1
—
1
0
—
1
1
1
0
0
1
1
0
—
1
0
—
0
1
1
+1.00
+0.9375
+0.875
+0.8125
+0.075
—
+0.0625
–0.0625
—
–0.875
–0.9375
–1.00
VFBN1
Digital Gain Tap
The digital gain tap features a programmable gain block whose
input is taken from the bitstream from the ADC’s sigma-delta
modulator. This single bit input (1 or 0) is used to add or subtract a programmable value, which is the digital gain tap setting,
to the output of the DAC section’s interpolator. The programmable setting has 16-bit resolution and is programmed using the
settings in Control Registers G and H.
VINN1
VREF
0/38dB
PGA
VINP1
VFBP1
GAIN
1
VREF
ANALOG
GAIN TAP
VOUTP1
+6/–15dB
PGA
VOUTN1
REFERENCE
REFOUT
Table IV. Digital Gain Tap Settings*
CONTINUOUS
TIME
LOW-PASS
FILTER
AD73422
AFE SECTION
REFCAP
Figure 7. Analog Input/Output Section
Analog and Digital Gain Taps
The AD73422 features analog and digital feedback paths between input and output. The amount of feedback is determined
by the gain setting that is programmed in the control registers.
This feature can typically be used for balancing the effective
impedance between input and output when used in Subscriber
Line Interface Circuit (SLIC) interfacing.
DGT15-0 (Hex)
Gain
0x8000
0x9000
0xA000
0xC000
0xE000
0x0000
0x2000
0x4000
0x6000
0x7FFF
–1.00
–0.875
–0.75
–0.5
–0.25
–0.00
+0.25
+0.5
+0.75
+0.99999
*AGE and DGT weights are given for the case of VFBNx (connected to the
sigma-delta modulator’s positive input) being at a higher potential than VFBPx
(connected to the sigma-delta modulator’s negative input).
Analog Gain Tap
The analog gain tap is configured as a programmable differential
amplifier whose input is taken from the ADC’s input signal
path. The output of the analog gain tap is summed with the
output of the DAC. The gain is programmable using Control
Register F (CRF:0-4) to achieve a gain of –1 to +1 in 32 steps,
with muting being achieved through a separate control setting
(Control Register F Bit _). The gain increment per step is 0.0625.
The AGT is enabled by powering up the AGT control bit in the
power control register (CRC:1). When this bit is set (=1) CRF
becomes an AGT control register with CRF:0-4 holding the
AGT coefficient, CRF:5 becomes an AGT enable and CRF:7
becomes an AGT mute control bit. Control bit CRF:5 connects/
disconnects the AGT output to the summer block at the output
of the DAC section while control bit CRF:7 overrides the gain
tap setting with a mute, or zero gain, setting (which is omitted
from the gain settings). Table III shows the gain versus digital
setting for the AGT.
REV. 0
0
1
0
1
0
—
1
0
—
1
0
1
*AGE and DGT weights are given for the case of VFBNx (connected to the
sigma-delta modulator’s positive input) being at a higher potential than VFBPx
(connected to the sigma-delta modulator’s negative input).
SINGLE-ENDED
ENABLE
INVERT
AGTC4
AFE Serial Port (SPORT2)
The AFE section communicates with the DSP section via its
bidirectional synchronous serial port (SPORT2), which interfaces
to either SPORT0 or SPORT1 of the DSP section. SPORT2 is
used to transmit and receive digital data and control information. The dual AFE is implemented using two separate AFE
blocks that are internally cascaded with serial port access to the
input of AFE Channel 1 and the output of AFE Channel 2.
This allows other single or dual codec devices to be cascaded
together (up to a limit of eight codec units).
In both transmit and receive modes, data is transferred at the
serial clock (SCLK2) rate with the MSB being transferred first.
Communications between the AFE section and the DSP section
must always be initiated by the AFE section (AFE is in master
mode—DSP SPORT is in slave mode). This ensures that there
is no collision between input data and output samples.
–13–
AD73422
AMCLK
(EXTERNAL)
AMCLK
(EXTERNAL)
DMCLK
AMCLK (INTERNAL)
DIVIDER
DMCLK
AMCLK (INTERNAL)
DIVIDER
3
SE
RESET
SDIFS
SDI
SCLK
SCLK
DIVIDER
SERIAL PORT 1
(SPORT 1)
RESET
(SDIFS2)
(SDOFS1)
(SDO1)
SERIAL REGISTER 1
3
SE
SCLK
DIVIDER
SERIAL PORT 2
(SPORT 2)
(SDI2)
SDOFS
8
CONTROL
REGISTER
1A
8
CONTROL
REGISTER
1B
8
CONTROL
REGISTER
1C
16
CONTROL
REGISTER
1G
2
8
8
8
CONTROL
REGISTER
1D
SDO
SERIAL REGISTER
2
CONTROL
REGISTER
1E
CONTROL
REGISTER
2A
8
CONTROL
REGISTER
2B
8
8
CONTROL
REGISTER
2C
16
CONTROL
REGISTER
1F
CONTROL
REGISTER
2G
CONTROL
REGISTER
1H
8
8
CONTROL
REGISTER
2D
CONTROL
REGISTER
2E
8
CONTROL
REGISTER
2F
CONTROL
REGISTER
2H
Figure 8. SPORT2 Block Diagram
SPORT2 Overview
SPORT2 is a flexible, full-duplex, synchronous serial port
whose protocol has been designed to allow extra AFE devices
(AD733xx series), up to a maximum of eight I/O channels, to be
connected in cascade to a DSP SPORT (0 or 1). It has a very
flexible architecture that can be configured by programming two
of the internal control registers in each AFE block. SPORT2 has
three distinct modes of operation: Control Mode, Data Mode
and Mixed Control/Data Mode.
NOTE: As each AFE has its own control section, the register
settings in each must be programmed. The registers that control
serial transfer and sample rate operation (CRA and CRB) must
be programmed with the same values, otherwise incorrect operation may occur.
In Control Mode (CRA:0 = 0), the device’s internal configuration can be programmed by writing to the eight internal control
registers. In this mode, control information can be written to or
read from the codec. In Data Mode (CRA:0 = 1), information
that is sent to the device is used to update the decoder section
(DAC), while the encoder section (ADC) data is read from the
device. In this mode, only DAC and ADC data is written to or
read from the device. Mixed mode (CRA:0 = 1 and CRA:1 = 1)
allows the user to choose whether the information being sent to
the device contains either control information or DAC data.
This is achieved by using the MSB of the 16-bit frame as a flag
bit. Mixed mode reduces the resolution to 15 bits with the MSB
being used to indicate whether the information in the 16-bit
frame is control information or DAC/ADC data.
SPORT2 features a single 16-bit serial register that is used for
both input and output data transfers. As the input and output
data must share the same register, some precautions must be
observed. The primary precaution is that no information must
be written to SPORT2 without reference to an output sample
event, which is when the serial register will be overwritten with
the latest ADC sample word. Once SPORT2 starts to output
the latest ADC word, it is safe for the DSP to write new control
or data words to the codec. In certain configurations, data can
be written to the device to coincide with the output sample
being shifted out of the serial register—see section on AFE
interfacing. The serial clock rate (CRB:2–3) defines how many
16-bit words can be written to a device before the next output
sample event will happen.
The SPORT2 block diagram, shown in Figure 8, details the
blocks associated with codecs 1 and 2, including the eight control registers (A–H), external AMCLK to internal DMCLK
divider and serial clock divider. The divider rates are controlled
by the setting of Control Register B. The AD73422 features a
master clock divider that allows users the flexibility of dividing
externally available high frequency DSP or CPU clocks to generate a lower frequency master clock internally in the codec
which may be more suitable for either serial transfer or sampling
rate requirements. The master clock divider has five divider
options (÷ 1 default condition, ÷ 2, ÷ 3, ÷ 4, ÷ 5) that are set by
loading the master clock divider field in Register B with the appropriate code. Once the internal device master clock (DMCLK) has
been set using the master clock divider, the sample rate and
serial clock settings are derived from DMCLK.
The SPORT can work at four different serial clock (SCLK)
rates: chosen from DMCLK, DMCLK/2, DMCLK/4 or
DMCLK/8, where DMCLK is the internal or device master
clock resulting from the external or pin master clock being divided by the master clock divider. When working at the lower
SCLK rate of DMCLK/8, which is intended for interfacing with
slower DSPs, the SPORT will support a maximum of two codecs
in cascade (a single AD73422 or two AD73311s) with the sample
rate of DMCLK/256.
SPORT2 Register Maps
There are two register banks for each AFE channel in the
AD73422: the control register bank and the data register bank.
The control register bank consists of eight read/write registers,
each eight bits wide. Table IX shows the control register map
for the AD73422. The first two control registers, CRA and
CRB, are reserved for controlling serial activity. They hold
settings for parameters such as serial clock rate, internal master
clock rate, sample rate and device count. As both codecs are
internally cascaded, registers CRA and CRB on each codec
must be programmed with the same setting to ensure correct
operation (this is shown in the programming examples). The
–14–
REV. 0
AD73422
other five registers; CRC through CRH are used to hold control
settings for the ADC, DAC, Reference, Power Control and
Gain Tap sections of the device. It is not necessary that the
contents of CRC through CRH on each codec are similar. Control registers are written to on the negative edge of SCLK. The
data register bank consists of two 16-bit registers that are the
DAC and ADC registers.
Sample Rate Divider
Master Clock Divider
The AD73422’s AFE features a programmable master clock
divider that allows the user to reduce an externally available
master clock, at pin AMCLK, by one of the ratios 1, 2, 3, 4 or
5, to produce an internal master clock signal (DMCLK) that is
used to calculate the sampling and serial clock rates. The master
clock divider is programmable by setting CRB:4-6. Table V
shows the division ratio corresponding to the various bit settings. The default divider ratio is divide-by-one.
The AD73422 features a programmable sample rate divider that
allows users flexibility in matching the codec’s ADC and DAC
sample rates (decimation/interpolation rates) to the needs of the
DSP software. The maximum sample rate available is DMCLK/
256, which offers the lowest conversion group delay, while the
other available rates are: DMCLK/512, DMCLK/1024 and
DMCLK/2048. The slowest rate (DMCLK/2048) is the default
sample rate. The sample rate divider is programmable by setting
bits CRB:0-1. Table VII shows the sample rate corresponding to
the various bit settings.
Table VII. Sample Rate Divider Settings
Table V. DMCLK (Internal) Rate Divider Settings
MCD2
MCD1
MCD0
DMCLK Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AMCLK
AMCLK/2
AMCLK/3
AMCLK/4
AMCLK/5
AMCLK
AMCLK
AMCLK
0
0
1
1
0
1
0
1
DMCLK/8
DMCLK/4
DMCLK/2
DMCLK
0
0
1
1
0
1
0
1
DMCLK/2048
DMCLK/1024
DMCLK/512
DMCLK/256
NOTE: The DAC advance register should not be changed while
the DAC section is powered up.
Table VIII. DAC Timing Control
Table VI. SCLK Rate Divider Settings
SCLK Rate
SCLK Rate
The loading of the DAC is internally synchronized with the
unloading of the ADC data in each sampling interval. The default DAC load event happens one SCLK cycle before the
SDOFS flag is raised by the ADC data being ready. However,
this DAC load position can be advanced before this time by
modifying the contents of the DAC Advance field in Control
Register E (CRE:0–4). The field is five bits wide, allowing 31
increments of weight 1/(FS × 32); see Table VIII. The sample
rate FS is dependent on the setting of both the AMCLK divider
and the Sample Rate divider; see Tables VII and IX. In certain
circumstances this DAC update adjustment can reduce the
group delay when the ADC and DAC are used to process data
in series. See AD73322 data sheet (Appendix C) for details of
how the DAC advance feature can be used.
The AD73422’s AFE features a programmable serial clock
divider that allows users to match the serial clock (SCLK) rate
of the data to that of the DSP engine or host processor. The
maximum SCLK rate available is DMCLK, and the other available rates are: DMCLK/2, DMCLK/4 and DMCLK/8. The
slowest rate (DMCLK/8) is the default SCLK rate. The serial
clock divider is programmable by setting bits CRB:2–3. Table
VI shows the serial clock rate corresponding to the various bit
settings.
SCD0
DIR0
DAC Advance Register
Serial Clock Rate Divider
SCD1
DIR1
DA4
DA3
DA2
DA1
DA0
Time Advance
0
0
0
—
1
1
0
0
0
—
1
1
0
0
0
—
1
1
0
0
1
—
1
1
0
1
0
—
0
1
0s
1/(FS × 32) s
2/(FS × 32) s
—
30/(FS × 32) s
31/(FS × 32) s
Table IX. Control Register Map
REV. 0
Address (Binary)
Name
Description
Type
Width
Reset Setting (Hex)
000
001
010
011
100
100
100
100
CRA
CRB
CRC
CRD
CRE
CRF
CRG
CRH
Control Register A
Control Register B
Control Register C
Control Register D
Control Register E
Control Register F
Control Register G
Control Register H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
–15–
AD73422
Table X. Control Word Description
15
14
C/D
R/W
13
12
11
DEVICE ADDRESS
Control
Frame
Bit 15
Control/Data
10
9
8
7
6
5
REGISTER ADDRESS
4
3
2
1
0
REGISTER DATA
Description
When set high, it signifies a control word in Program or Mixed Program/Data Modes. When set low, it
signifies a data word in Mixed Program/Data Mode or an invalid control word in Program Mode.
Bit 14
Read/Write
When set low, it tells the device that the data field is to be written to the register selected by the register field setting provided the address field is zero. When set high, it tells the device that the selected
register is to be written to the data field in the input serial register and that the new control word is to
be output from the device via the serial output.
Bits 13–11 Device Address This 3-bit field holds the address information. Only when this field is zero is a device selected. If the
address is not zero, it is decremented and the control word is passed out of the device via the serial
output.
Bits 10–8 Register Address This 3-bit field is used to select one of the five control registers on the AFE section of the AD73422.
Bits 7–0
Register Data
This 8-bit field holds the data that is to be written to or read from the selected register provided the
address field is zero.
Table XI. Control Register A Description
CONTROL REGISTER A
7
6
RESET
DC2
5
DC1
4
DC0
3
SLB
2
DLB
1
MM
Bit
Name
Description
0
1
2
3
4
5
6
7
DATA/PGM
MM
DLB
SLB
DC0
DC1
DC2
RESET
Operating Mode (0 = Program; 1 = Data Mode)
Mixed Mode (0 = Off; 1 = Enabled)
Digital Loop-Back Mode (0 = Off; 1 = Enabled)
SPORT Loop-Back Mode (0 = Off; 1 = Enabled)
Device Count (Bit 0)
Device Count (Bit 1)
Device Count (Bit 2)
Software Reset (0 = Off; 1 = Initiates Reset)
0
DATA/
PGM
Table XII. Control Register B Description
CONTROL REGISTER B
7
6
5
4
3
2
1
0
CEE
MCD2
MCD1
MCD0
SCD1
SCD0
DIR1
DIR0
Bit
Name
Description
0
1
2
3
4
5
6
7
DIR0
DIR1
SCD0
SCD1
MCD0
MCD1
MCD2
CEE
Decimation/Interpolation Rate (Bit 0)
Decimation/Interpolation Rate (Bit 1)
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
Control Echo Enable (0 = Off; 1 = Enabled)
–16–
REV. 0
AD73422
Table XIII. Control Register C Description
CONTROL REGISTER C
7
6
5VEN
RU
5
4
3
PUREF PUDAC PUADC
2
1
0
PUIA
PUAGT
PU
Bit
Name
Description
0
1
2
3
4
5
6
7
PU
PUAGT
PUIA
PUADC
PUDAC
PUREF
RU
—
Power-Up Device (0 = Power-Down; 1 = Power-On)
Analog Gain Tap Power (0 = Power-Down; 1 = Power-On)
Input Amplifier Power (0 = Power-Down; 1 = Power-On)
ADC Power (0 = Power-Down; 1 = Power-On)
DAC Power (0 = Power-Down; 1 = Power-On)
REF Power (0 = Power-Down; 1 = Power On)
REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)
Reserved (Must be Programmed to 0)
Table XIV. Control Register D Description
CONTROL REGISTER D
7
6
5
4
3
2
1
0
MUTE
OGS2
OGS1
OGS0
RMOD
IGS2
IGS1
IGS0
Bit
Name
Description
0
1
2
3
4
5
6
7
IGS0
IGS1
IGS2
RMOD
OGS0
OGS1
OGS2
MUTE
Input Gain Select (Bit 0)
Input Gain Select (Bit 1)
Input Gain Select (Bit 2)
Reset ADC Modulator (0 = Off; 1 = Reset Enabled)
Output Gain Select (Bit 0)
Output Gain Select (Bit 1)
Output Gain Select (Bit 2)
Output Mute (0 = Mute Off; 1 = Mute Enabled)
Table XV. Control Register E Description
CONTROL REGISTER E
REV. 0
7
6
5
4
3
2
1
0
TME
DGTE
IBYP
DA4
DA3
DA2
DA1
DA0
Bit
Name
Description
0
1
2
3
4
5
DA0
DA1
DA2
DA3
DA4
IBYP
6
7
DGTE
TME
DAC Advance Setting (Bit 0)
DAC Advance Setting (Bit 1)
DAC Advance Setting (Bit 2)
DAC Advance Setting (Bit 3)
DAC Advance Setting (Bit 4)
Interpolator Bypass (0 = Bypass Disabled;
1 = Bypass Enabled)
Digital Gain Tap Enable (0 = Disabled; 1 = Enabled)
Test Mode Enable (0 = Disabled; 1 = Enabled)
–17–
AD73422
Table XVI. Control Register F Description
CONTROL REGISTER F
7
ALB/
AGTM
6
5
INV
SEEN/
AGTE
4
3
2
1
0
AGTC4 AGTC3 AGTC2 AGTC1 AGTC0
Bit
Name
Description
0
1
2
3
4
5
AGTC0
AGTC1
AGTC2
AGTC3
AGTC4
SEEN/
AGTE
INV
ALB/
AGTM
Analog Gain Tap Coefficient (Bit 0)
Analog Gain Tap Coefficient (Bit 1)
Analog Gain Tap Coefficient (Bit 2)
Analog Gain Tap Coefficient (Bit 3)
Analog Gain Tap Coefficient (Bit 4)
Single-Ended Enable (0 = Disabled; 1 = Enabled)
Analog Gain Tap Enable (0 = Disabled; 1 = Enabled)
Input Invert (0 = Disabled; 1 = Enabled)
Analog Loop-Back of Output to Input (0 = Disabled; 1 = Enabled)
Analog Gain Tap Mute (0 = Off; 1 = Muted)
6
7
Table XVII. Control Register G Description
CONTROL REGISTER G
7
6
5
4
3
2
1
0
DGTC7 DGTC6 DGTC5 DGTC4 DGTC3 DGTC2 DGTC1 DGTC0
Bit
Name
Description
0
1
2
3
4
5
6
7
DGTC0
DGTC1
DGTC2
DGTC3
DGTC4
DGTC5
DGTC6
DGTC7
Digital Gain Tap Coefficient (Bit 0)
Digital Gain Tap Coefficient (Bit 1)
Digital Gain Tap Coefficient (Bit 2)
Digital Gain Tap Coefficient (Bit 3)
Digital Gain Tap Coefficient (Bit 4)
Digital Gain Tap Coefficient (Bit 5)
Digital Gain Tap Coefficient (Bit 6)
Digital Gain Tap Coefficient (Bit 7)
Table XVIII. Control Register H Description
CONTROL REGISTER H
7
6
5
4
3
2
1
DGTC15 DGTC14 DGTC13 DGTC12 DGTC11 DGTC10 DGTC9
Bit
Name
Description
0
1
2
3
4
5
6
7
DGTC8
DGTC9
DGTC10
DGTC11
DGTC12
DGTC13
DGTC14
DGTC15
Digital Gain Tap Coefficient (Bit 8)
Digital Gain Tap Coefficient (Bit 9)
Digital Gain Tap Coefficient (Bit 10)
Digital Gain Tap Coefficient (Bit 11)
Digital Gain Tap Coefficient (Bit 12)
Digital Gain Tap Coefficient (Bit 13)
Digital Gain Tap Coefficient (Bit 14)
Digital Gain Tap Coefficient (Bit 15)
–18–
0
DGTC8
REV. 0
AD73422
OPERATION
Resetting the AD73422’s AFE
The pin ARESET resets all the control registers. All registers are
reset to zero indicating that the default SCLK rate (DMCLK/8)
and sample rate (DMCLK/2048) are at a minimum to ensure
that slow speed DSP engines can communicate effectively. As
well as resetting the control registers using the ARESET pin, the
device can be reset using the RESET bit (CRA:7) in Control
Register A. Both hardware and software resets require four
DMCLK cycles. On reset, DATA/PGM (CRA:0) is set to 0
(default condition) thus enabling Program Mode. The reset
conditions ensure that the device must be programmed to the
correct settings after power-up or reset. Following a reset, the
SDOFS will be asserted 2048 DMCLK cycles after ARESET
going high. The data that is output following reset and during
Program Mode is random and contains no valid information
until either data or mixed mode is set.
Power Management
The individual functional blocks of the AD73422 can be enabled separately by programming the power control register
CRC. It allows certain sections to be powered down if not required, which adds to the device’s flexibility in that the user
need not incur the penalty of having to provide power for a
certain section if it is not necessary to their design. The power
control registers provides individual control settings for the
major functional blocks on each codec unit and also a global
override that allows all sections to be powered up by setting the
bit. Using this method the user could, for example, individually
enable a certain section, such as the reference (CRC:5), and
disable all others. The global power-up (CRC:0) can be used to
enable all sections but if power-down is required using the global control, the reference will still be enabled, in this case, because its individual bit is set. Refer to Table XIII for details of
the settings of CRC.
Following reset, when the SE pin is enabled, the codec responds
by raising the SDOFS pin to indicate that an output sample
event has occurred. Control words can be written to the device
to coincide with the data being sent out of the SPORT or they
can lag the output words by a time interval that should not
exceed the sample interval. After reset, output frame sync pulses
will occur at a slower default sample rate, which is DMCLK/
2048, until Control Register B is programmed after which the
SDOFS pulses will revert to the DMCLK/256 rate. During
Program Mode, the data output by the ADCs is random and
should not be interpreted as valid data.
Data Mode
NOTE: As both codec units share a common reference, the
reference control bits (CRC:5–7) in each SPORT are wire ORed
to allow either device to control the reference. Hence the reference is only in a reset state when the relevant control bit of both
codec units is set to 0.
AFE Operating Modes
There are three main modes of operation available on the
AD73422; Program, Data and Mixed Program/Data modes.
There are also two other operating modes which are typically
reserved as diagnostic modes: Digital and SPORT Loopback.
The device configuration—register settings—can be changed
only in Program and Mixed Program/Data Modes. In all modes,
transfers of information to or from the device occur in 16-bit
packets, therefore the DSP engine’s SPORT will be programmed
for 16-bit transfers.
Program (Control) Mode
In Program Mode, CRA:0 = 0, the user writes to the control
registers to set up the device for desired operation—SPORT
operation, cascade length, power management, input/output
gain, etc. In this mode, the 16-bit information packet sent to the
device by the DSP engine is interpreted as a control word whose
format is shown in Table X. In this mode, the user must address
the device to be programmed using the address field of the control word. This field is read by the device and if it is zero (000 bin)
then the device recognizes the word as being addressed to it. If the
address field is not zero, it is then decremented and the control
REV. 0
word is passed out of the device—either to the next device in a
cascade or back to the DSP engine. This 3-bit address format
allows the user to uniquely address any one of up to eight devices in a cascade; please note that this addressing scheme is
valid only in sending control information to the device—a different format is used to send DAC data to the device(s). As the
AD73422 features a dual AFE, these two channels have separate device addresses for programming purposes—the two device addresses correspond to 0 and 1.
Once the device has been configured by programming the correct settings to the various control registers, the device may exit
Program Mode and enter Data Mode. This is done by programming the DATA/PGM (CRA:0) bit to a 1 and MM (CRA:1) to
0. Once the device is in Data Mode, the 16-bit input data frame
is now interpreted as DAC data rather than a control frame.
This data is therefore loaded directly to the DAC register. In
Data Mode, as the entire input data frame contains DAC data,
the device relies on counting the number of input frame syncs
received at the SDIFS pin. When that number equals the device
count stored in the device count field of CRA, the device knows
that the present data frame being received is its own DAC update data. When the device is in normal Data Mode (i.e., mixed
mode disabled), it must receive a hardware reset to reprogram
any of the control register settings. In a single AD73422 configuration, each 16-bit data frame sent from the DSP to the
device is interpreted as DAC data but it is necessary to send two
DAC words per sample period in order to ensure DAC update.
Also as the device count setting defaults to 1, it must be set
to 2 (001b) to ensure correct update of both DACs on the
AD73422.
Mixed Program/Data Mode
This mode allows the user to send control words to the device
along with the DAC data. This permits adaptive control of the
device whereby control of the input/output gains can be effected
by interleaving control words along with the normal flow of
DAC data. The standard data frame remains 16 bits, but now
the MSB is used as a flag bit to indicate whether the remaining
15 bits of the frame represent DAC data or control information.
In the case of DAC data, the 15 bits are loaded with MSB
justification and LSB set to 0 to the DAC register. Mixed mode
is enabled by setting the MM bit (CRA:1) to 1 and the DATA/
PGM bit (CRA:0) to 1. In the case where control setting changes
will be required during normal operation, this mode allows the
ability to load both control and data information with the slight
inconvenience of formatting the data. Note that the output
samples from the ADC will also have the MSB set to zero to
indicate it is a data word.
–19–
AD73422
A description of a single device operating in mixed mode is
detailed in Appendix B, while Appendix D details the initialization and operation of a dual codec cascade operating in mixed
mode. Note that it is not essential to load the control registers in
Program Mode before setting mixed mode active. It is also
possible to initiate mixed mode by programming CRA with the
first control word and then interleaving control words with
DAC data.
Digital Loop-Back
This mode can be used for diagnostic purposes and allows the
user to feed the ADC samples from the ADC register directly to
the DAC register. This forms a loop-back of the analog input to
the analog output by reconstructing the encoded signal using
the decoder channel. The serial interface will continue to work,
which allows the user to control gain settings, etc. Only when
DLB is enabled with mixed mode operation can the user disable
the DLB, otherwise the device must be reset.
SPORT Loop-Back
This mode allows the user to verify the DSP interfacing and
connection by writing words to the SPORT of the devices and
have them returned back unchanged after a delay of 16 SCLK
cycles. The frame sync and data words that are sent to the device are returned via the output port. Again, SLB mode can only
be disabled when used in conjunction with mixed mode, otherwise the device must be reset.
Analog Loop-Back
In Analog Loop-Back mode, the differential DAC output is
connected, via a loop-back switch, to the ADC input. This
mode allows the ADC channel to check functionality of the
DAC channel as the reconstructed output signal can be monitored using the ADC as a sampler. Analog Loop-Back is enabled by setting the ALB bit (CRF:7)
NOTE: Analog Loop-Back can only be enabled if the Analog
Gain Tap is powered down (CRC:1 = 0).
INVERTING
OP AMPS
ANALOG
LOOP-BACK
SELECT
which is active high one clock cycle before the start of the 16-bit
word or during the last bit of the previous word if transmission
is continuous. The serial clock (SCLK) is an output from the
codec and is used to define the serial transfer rate to the DSP’s
Tx and Rx ports. Two primary configurations can be used: the
first is shown in Figure 10 where the DSP’s Tx data, Tx frame
sync, Rx data and Rx frame sync are connected to the codec’s
SDI, SDIFS, SDO and SDOFS respectively. This configuration, referred to as indirectly coupled or nonframe sync loopback, has the effect of decoupling the transmission of input data
from the receipt of output data. The delay between receipt of
codec output data and transmission of input data for the codec
is determined by the DSP’s software latency. When programming the DSP serial port for this configuration, it is necessary to
set the Rx FS as an input and the Tx FS as an output generated
by the DSP. This configuration is most useful when operating in
mixed mode, as the DSP has the ability to decide how many
words (either DAC or control) can be sent to the codecs. This
means that full control can be implemented over the device
configuration as well as updating the DAC in a given sample
interval. The second configuration (shown in Figure 11) has the
DSP’s Tx data and Rx data connected to the codec’s SDI and
SDO, respectively while the DSP’s Tx and Rx frame syncs are
connected to the codec’s SDIFS and SDOFS. In this configuration, referred to as directly coupled or frame sync loop-back, the
frame sync signals are connected together and the input data to
the codec is forced to be synchronous with the output data from
the codec. The DSP must be programmed so that both the Tx
FS and Rx FS are inputs as the codec SDOFS will be input to
both. This configuration guarantees that input and output
events occur simultaneously and is the simplest configuration
for operation in normal Data Mode. Note that when programming the DSP in this configuration it is advisable to preload the
Tx register with the first control word to be sent before the
codec is taken out of reset. This ensures that this word will be
transmitted to coincide with the first output word from the
device(s).
SINGLE-ENDED
ENABLE
INVERT
TFS (0/1)
VFBN1
VINN1
DSP
SECTION
VREF
SCLK (0/1)
DR (0/1)
0/38dB
PGA
VINP1
SDIFS
SDI
DT (0/1)
CHANNEL 1
AFE
SECTION
SCLK2
SDO
RFS (0/1)
SDOFS
CHANNEL 2
VFBP1
GAIN
1
AD73422
VREF
ANALOG GAIN TAP
POWERED DOWN
VOUTP1
+6/–15dB
PGA
VOUTN1
REFOUT
REFERENCE
Figure 10. Indirectly Coupled or Nonframe Sync LoopBack Configuration
CONTINUOUS
TIME
LOW-PASS
FILTER
Cascade Operation
AD73422
AFE SECTION
REFCAP
Figure 9. Analog Loop-Back Connectivity
AFE Interfacing
The AFE section SPORT (SPORT2) can be interfaced to either
SPORT0 or SPORT1 of the DSP section. Both serial input and
output data use an accompanying frame synchronization signal
The AD73422 has been designed to support cascading of extra
external AFEs from either SPORT0 or SPORT1. Cascaded
operation can support mixes of dual or single channel devices with
maximum number of codec units being eight (the AD73422 has
two codec units configured on the device). The SPORT2 interface protocol has been designed so that device addressing is
built into the packet of information sent to the device. This
allows the cascade to be formed with no extra hardware overhead for control signals or addressing. A cascade can be formed
in either of the two modes previously discussed.
–20–
REV. 0
AD73422
There may be some restrictions in cascade operation due to the
number of devices configured in the cascade and the sampling
rate and serial clock rate chosen. The following relationship
details the restrictions in configuring a codec cascade.
FUNCTIONAL DESCRIPTION—DSP
The AD73422 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single processor cycle. The AD73422 assembly language uses an algebraic
syntax for ease of coding and readability. A comprehensive set
of development tools supports program development.
Number of Codecs × Word Size (16) × Sampling Rate ≤ Serial
Clock Rate
SDI
DT (0/1)
DSP
SECTION
POWER-DOWN
CONTROL
SDIFS
TFS (0/1)
SCLK (0/1)
CHANNEL 1
AFE
SECTION
SCLK2
DR (0/1)
DATA
ADDRESS
GENERATORS
PROGRAM
SEQUENCER
DAG 1 DAG 2
MEMORY
16K PM
16K DM
(OPTIONAL (OPTIONAL
8K)
8K)
FULL MEMORY
MODE
PROGRAMMABLE
I/O
AND
FLAGS
EXTERNAL
DATA
BUS
SDO
PROGRAM MEMORY ADDRESS
RFS (0/1)
SDOFS
CHANNEL 2
DATA MEMORY ADDRESS
AD73422
OR
DATA MEMORY DATA
When using the indirectly coupled frame sync configuration in
cascaded operation, it is necessary to be aware of the restrictions
in sending data to all devices in the cascade. Effectively the time
allowed is given by the sampling interval (M/DMCLK, where M
can be one of 256, 512, 1024 or 2048) which is 125 µs for a
sample rate of 8 kHz. In this interval, the DSP must transfer
N × 16 bits of information, where N is the number of devices in
the cascade. Each bit will take 1/SCLK and, allowing for any
latency between the receipt of the Rx interrupt and the transmission of the Tx data, the relationship for successful operation
is given by:
M/DMCLK > ((N × 16/SCLK) + TINTERRUPT LATENCY)
The interrupt latency will include the time between the ADC
sampling event and the RX interrupt being generated in the
DSP—this should be 16 SCLK cycles.
As the AD73422 is configured in Cascade Mode, each device
must know the number of devices in the cascade because the
Data and Mixed modes use a method of counting input frame
sync pulses to decide when they should update the DAC
register from the serial input register. Control Register A contains a 3-bit field (DC0–2) that is programmed by the DSP
during the programming phase. The default condition is that the
field contains 000b, which is equivalent to a single device in
cascade (see Table XIX). However, for cascade operation this
field must contain a binary value that is one less than the number
of devices in the cascade, which is 001b for a single AD73422
device configuration.
Table XIX. Device Count Settings
DC2
DC1
DC0
Cascade Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
REV. 0
BYTE DMA
CONTROLLER
PROGRAM MEMORY DATA
Figure 11. Directly Coupled or Frame Sync LoopBack Configuration
ARITHMETIC UNITS
ALU
MAC
SHIFTER
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
ADSP-2100 BASE
ARCHITECTURE
INTERNAL
DMA
PORT
HOST MODE
REF
ADC1
SERIAL PORT
SPORT 2
DAC1
ADC2
DAC2
ANALOG FRONT END
SECTION
Figure 12. Functional Block Diagram
Figure 12 is an overall block diagram of the AD73422. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations.
The shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the AD73422 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
–21–
AD73422
Serial Ports
Efficient data transfer is achieved with the use of five internal
buses:
•
•
•
•
•
The AD73422 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
Here is a brief list of the capabilities of the AD73422 SPORTs.
For additional information on Serial Ports, refer to the ADSP2100 Family User’s Manual, Third Edition.
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permitting
the AD73422 to fetch two operands in a single cycle, one from
program memory and one from data memory. The AD73422
can fetch an operand from program memory and the next instruction in the same cycle.
In lieu of the address and data bus for external memory connection, the AD73422 may be configured for 16-bit Internal DMA
port (IDMA port) connection to external systems. The IDMA
port is made up of 16 data/address pins and five control pins.
The IDMA port provides transparent, direct access to the DSPs
on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain
control of external buses with bus request/grant signals (BR,
BGH, and BG). One execution mode (Go Mode) allows the
AD73422 to continue running from on-chip memory. Normal
execution mode requires the processor to halt while buses are
granted.
• SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
DSP SECTION PIN DESCRIPTIONS
The AD73422 can respond to eleven interrupts. There can be
up to six external interrupts (one edge-sensitive, two levelsensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and
a wide variety of framed or frameless data transmit and receive
modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The AD73422 provides up to 13 general-purpose flag pins. The
data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, there
are eight flags that are programmable as inputs or outputs and
three flags that are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n processor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
The AD73422 will be available in a 119-ball PBGA package. In
order to maintain maximum functionality and reduce package
size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality.
The external bus pins are configured during RESET only, while
serial port pins are software configurable during program
execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is
reconfigurable, the default state is shown in plain text; alternate
functionality is shown in italics. See Pin Descriptions section.
Memory Interface Pins
The AD73422 processor can be used in one of two modes, Full
Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which
allows IDMA operation with limited external addressing capabilities. The operating mode is determined by the state of the
Mode C pin during RESET and cannot be changed while the
processor is running. See Full Memory Mode Pins and Host
Mode Pins tables for descriptions.
–22–
REV. 0
AD73422
Full Memory Mode Pins (Mode C = 0)
Pin
Name(s)
# of
Pins
Input/
Output Function
A13:0
14
O
D23:0
24
I/O
Pin Terminations (Continued)
Address Output Pins for Program,
Data, Byte and I/O Spaces
Data I/O Pins for Program, Data,
Byte and I/O Spaces (8 MSBs are
also used as Byte Memory
addresses)
Pin
Name
I/O
3-State
(Z)
Reset
State
CMS
RD
WR
BR
BG
BGH
IRQ2/PF7
O (Z)
O (Z)
O (Z)
I
O (Z)
O
I/O (Z)
O
O
O
I
O
O
I
Host Mode Pins (Mode C = 1)
Pin
Name(s)
# of
Pins
Input/
Output Function
IRQL1/PF6 I/O (Z)
I
IAD15:0
A0
16
1
I/O
O
IRQL0/PF5 I/O (Z)
I
D23:8
16
I/O
IRQE/PF4
I/O (Z)
I
IWR
IRD
IAL
IS
IACK
1
1
1
1
1
I
I
I
I
O
SCLK0
I/O
I
RFS0
DR0
TFS0
DT0
SCLK1
I/O
I
I/O
O
I/O
I
I
O
O
I
RFS1/IRQ0
DR1/FI
TFS1/IRQ1
DT1/FO
EE
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
I/O
I
I/O
O
I
I
O
I
O
I
I
I
O
I
I
O
O
I
I
O
I
O
I
I
I
O
IDMA Port Address/Data Bus
Address Pin for External I/O,
Program, Data or Byte Access
Data I/O Pins for Program, Data
Byte and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge Configurable in Mode D; Open Source
NOTE
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS and IOMS signals.
Terminating Unused Pin
The following table shows the recommendations for terminating
unused pins.
Pin Terminations
Pin
Name
XTAL
CLKOUT
A13:1 or
IAD12:0
A0
D23:8
D7 or
IWR
D6 or
IRD
D5 or
IAL
D4 or
IS
D3 or
IACK
D2:0 or
IAD15:13
PMS
DMS
BMS
IOMS
REV. 0
I/O
3-State
(Z)
Reset
State
I
O
O (Z)
I/O (Z)
O (Z)
I/O (Z)
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z
I/O (Z)
I/O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
Hi-Z
Hi-Z
O
O
O
O
Hi-Z*
Caused
By
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
Unused
Configuration
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
Float
High (Inactive)
Float
Low (Inactive)
Float
High (Inactive)
Float
Float
Float
Float
Float
Float
Float
Float
Hi-Z*
Caused
By
BR, EBR
BR, EBR
BR, EBR
EE
Unused
Configuration
Float
Float
Float
High (Inactive)
Float
Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
NOTES
*Hi-Z = High Impedance.
1. If the CLKOUT pin is not used, turn it OFF.
2. If the Interrupt/Programmable Flag pins are not used, there are two options:
Option 1: When these pins are configured as INPUTS at reset and function
as interrupts and input flag pins, pull the pins High (inactive).
Option 2: Program the unused pins as OUTPUTS, set them to 1, and let
them float.
3. All bidirectional pins have three-stated outputs. When the pins is configured
as an output, the output is Hi-Z (high impedance) when inactive.
4. CLKIN, RESET, and PF3:0 are not included in the table because these pins
must be used.
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and RESET with minimum overhead.
The AD73422 provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,
SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN
and FLAG_OUT, for a total of six external interrupts. The
AD73422 also supports internal interrupts from the timer, the
byte DMA port, the two serial ports, software and the powerdown control circuit. The interrupt levels are internally prioritized and individually maskable (except power-down and reset).
–23–
AD73422
The IRQ2, IRQ0 and IRQ1 input pins can be programmed to
be either level- or edge-sensitive. IRQL0 and IRQL1 are levelsensitive and IRQE is edge-sensitive. The priorities and vector
addresses of all interrupts are shown in Table XX.
Power-Down
The AD73422 processor has a low power feature that lets the
processor enter a very low power dormant state through hardware or software control. Here is a brief list of power-down
features. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, “System Interface” chapter, for detailed information
about the power-down feature.
Table XX. Interrupt Priority and Interrupt Vector Addresses
Source of Interrupt
Interrupt Vector
Address (Hex)
RESET (or Power-Up with PUCR = 1)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
0000 (Highest Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATION
The AD73422 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Power-Down
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and
letting the oscillator run to allow 400 CLKIN cycle start up.
• Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit. Interrupt support
allows an unlimited number of instructions to be executed
before optionally powering down. The power-down interrupt
also can be used as a nonmaskable, edge-sensitive interrupt.
• The RESET pin also can be used to terminate power-down.
• Power-down acknowledge pin indicates when the processor
has entered power-down.
Idle
The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
ENA INTS;
DIS INTS;
• Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during
power-down without affecting the 400 CLKIN cycle recovery.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
The AD73422 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are twelve levels deep to allow interrupt, loop and subroutine
nesting. The following instructions allow global enable or disable servicing of the interrupts (including power-down), regardless of the state of IMASK. Disabling the interrupts does not
affect serial port autobuffering or DMA.
• Quick recovery from power-down. The processor begins
executing instructions in as few as 400 CLKIN cycles.
When the AD73422 is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
In Idle Mode IDMA, BDMA and autobuffer cycle steals still
occur.
Slow Idle
The IDLE instruction on the AD73422 slows the processor’s
internal clock signal, further reducing power consumption. The
reduced clock frequency, a programmable fraction of the normal
clock rate, is specified by a selectable divisor given in the IDLE
instruction. The format of the instruction is
IDLE (n);
where n = 16, 32, 64 or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows
down the processor’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, the AD73422 will remain in the
idle state for up to a maximum of n processor cycles (n = 16, 32,
64 or 128) before resuming normal operation.
–24–
REV. 0
AD73422
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
FULL MEMORY MODE
AD73422
1/2x CLOCK
OR
CRYSTAL
CLKIN
XTAL
24
A0-A21
BYTE
MEMORY
D15-8
DATA
DATA23-0
BMS
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
Figure 13 shows a typical basic system configuration with the
AD73422, two serial devices, a byte-wide EPROM, and
optional external program and data overlay memories (mode
selectable). Programmable wait state generation allows the
processor to connect easily to slow peripheral devices. The
AD73422 also provides four external interrupts and two serial
ports or six external interrupts and one serial port. Host Memory
Mode allows access to the full external data bus, but limits
addressing to a single address bit (A0). Additional system peripherals can be added in this mode through the use of external
hardware to generate and latch address signals.
A13-0
D23-16
FL0-2
PF3
SYSTEM INTERFACE
14
ADDR13-0
CS
A10-0
ADDR
WR
RD
MODE C/PF2
MODE B/PF1
MODE A/PF0
AFE*
SECTION
OR
SERIAL
DEVICE
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
AFE*
SECTION
OR
SERIAL
DEVICE
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
D23-8
IOMS
A13-0
D23-0
PMS
DMS
CMS
I/O SPACE
(PERIPHERALS)
DATA
2048
LOCATIONS
CS
ADDR OVERLAY
MEMORY
DATA
TWO 8K
PM SEGMENTS
TWO 8K
DM SEGMENTS
BR
BG
BGH
PWD
PWDACK
HOST MEMORY MODE
Clock Signals
AD73422
The AD73422 can be clocked by either a crystal or a TTLcompatible clock signal.
1/2x CLOCK
OR
CRYSTAL
CLKIN
A0
16
XTAL
The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal operation. The only exception is while the processor is in the powerdown state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed
information on this power-down feature.
DATA23-8
FL0-2
PF3
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
BMS
MODE C/PF2
MODE B/PF1
MODE A/PF0
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is connected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.
The AD73422 uses an input clock with a frequency equal to
half the instruction rate; a 26.00 MHz input clock yields a 19 ns
processor cycle (which is equivalent to 52 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Because the AD73422 includes an on-chip oscillator circuit, an
external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 14. Capacitor values are dependent
on crystal type and should be specified by the crystal manufacturer.
A parallel-resonant, fundamental frequency, microprocessorgrade crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLK0DIS bit in the SPORT0 Autobuffer Control Register.
1
WR
RD
SPORT1
IOMS
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1 PMS
DT1 OR FO
DMS
DR1 OR FI
CMS
AFE*
SECTION
OR
SERIAL
DEVICE
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
AFE*
SECTION
OR
SERIAL
DEVICE
SYSTEM
INTERFACE
OR
␮CONTROLLER
16
BR
BG
BGH
PWD
PWDACK
IDMA PORT
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
*AFE SECTION CAN BE
CONNECTED TO EITHER
SPORT0 OR SPORT1
IAD15-0
Figure 13. Basic System Configuration
CLKIN
XTAL
CLKOUT
DSP
Figure 14. External Crystal Connections
REV. 0
–25–
AD73422
Reset
The RESET signal initiates a master reset of the AD73422. The
RESET signal must be asserted during the power-up sequence
to assure proper initialization. RESET during initial power-up
must be held long enough to allow the internal clock to stabilize.
If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this powerup sequence the RESET signal should be held low. On any
subsequent resets, the RESET signal must meet the minimum
pulsewidth specification, tRSP.
The RESET input contains some hysteresis; however, if an
RC circuit is used to generate the RESET signal, an external
Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from onchip program memory location 0x0000 once boot loading completes.
MODES OF OPERATION
Setting Memory Mode
Memory Mode selection for the AD73422 is made during chip
reset through the use of the Mode C pin. This pin is multiplexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
Passive configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 kΩ, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as
a programmable flag output without undue strain on the
processor’s output driver. For minimum power consumption
during power-down, reconfigure PF2 to be an input, as the pullup or pull-down will hold the pin in a known state and will not
switch.
Active configuration involves the use of a three-statable external driver connected to the Mode C pin. A driver’s output enable should be connected to the DSP’s RESET signal such that
it only drives the PF2 pin when RESET is active (low). When
RESET is deasserted, the driver should three-state, thus allowing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a threestated buffer. This ensures that the pin will be held at a constant
level and not oscillate should the three-state driver’s level hover
around the logic switching point.
Table XXI summarizes the AD73422 memory modes.
Table XXI. Modes of Operations1
MODE C2
MODE B3
MODE A4
Booting Method
0
0
0
0
1
0
1
0
0
1
0
1
BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is configured
in Full Memory Mode.5
No Automatic boot operations occur. Program execution starts at external memory location
0. Chip is configured in Full Memory Mode. BDMA can still be used, but the processor does
not automatically use or wait for these operations.
BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode. (REQUIRES ADDITIONAL HARDWARE.)
IDMA feature is used to load any internal memory as desired. Program execution is held off
until internal program memory location 0 is written to. Chip is configured in Host Mode.5
NOTES
1
All mode pins are recognized while RESET is active (low).
2
When Mode C = 0, Full Memory enabled. When Mode C = 1, Host Memory Mode enabled.
3
When Mode B = 0, Auto Booting enabled. When Mode B = 1, no Auto Booting.
4
When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.
5
Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
–26–
REV. 0
AD73422
MEMORY ARCHITECTURE
DATA MEMORY
The AD73422 provides a variety of memory and peripheral
interface options. The key functional groups are Program
Memory, Data Memory, Byte Memory and I/O. Refer to the
following figures and tables for PM and DM memory allocations in the AD73422.
Data Memory (Full Memory Mode) is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The AD73422-80 has 16K words on Data
Memory RAM on chip (the AD73422-40 has 8K words on Data
Memory RAM on chip), consisting of 16,352 user-accessible
locations in the case of the AD73422-80 (8,160 user-accessible
locations in the case of the AD73422-40) and 32 memorymapped registers. Support also exists for up to two 8K external
memory overlay spaces through the external data bus. All internal accesses complete in one cycle. Accesses to external memory
are timed using the wait states specified by the DWAIT register.
PROGRAM MEMORY
Program Memory (Full Memory Mode) is a 24-bit-wide
space for storing both instruction op codes and data. The
AD73422-80 has 16K words of Program Memory RAM on chip
(the AD73422-40 has 8K words of Program Memory RAM on
chip), and the capability of accessing up to two 8K external
memory overlay spaces using the external data bus.
DATA MEMORY
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is 16 bits wide only.
INTERNAL
MEMORY
ACCESSIBLE WHEN
DMOVLAY = 0
EXTERNAL
MEMORY
Memory
A13
A12:0
0
1
Internal
External
Overlay 1
Not Applicable Not Applicable
0
13 LSBs of Address
Between 0x2000
and 0x3FFF
1
13 LSBs of Address
Between 0x2000
and 0x3FFF
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF
ACCESSIBLE WHEN
PMOVLAY = 0
RESERVED
INTERNAL
MEMORY
0x2000–
0x3FFF
0x2000–
0x3FFF2
ACCESSIBLE WHEN
PMOVLAY = 1
EXTERNAL
MEMORY
0x2000–
0x3FFF2
ACCESSIBLE WHEN
PMOVLAY = 2
0x2000–
0x3FFF
ACCESSIBLE WHEN
PMOVLAY = 0
0x3FFF
0x3FE0
0x3FDF
0x2000
0x1FFF
8K INTERNAL
DMOVLAY = 0
OR
EXTERNAL 8K
DMOVLAY = 1, 2
0x0000
ACCESSIBLE WHEN
DMOVLAY = 2
Figure 16. Data Memory Map
Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address
line (A0). The DMOVLAY bits are defined in Table XXIII.
Table XXIII. DMOVLAY Bits
DMOVLAY
Memory
0
1
Internal
Not Applicable Not Applicable
External 0
13 LSBs of Address
Overlay 1
Between 0x2000
and 0x3FFF
External 1
13 LSBs of Address
Overlay 2
Between 0x2000
and 0x3FFF
0x0000–
0x1FFF2
ACCESSIBLE WHEN
PMOVLAY = 0
EXTERNAL
MEMORY
2
A13
A12:0
RESERVED
1WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0
2SEE TABLE III FOR PMOVLAY BITS
PROGRAM MEMORY
MODE B = 0
ADDRESS
PROGRAM MEMORY
MODE B = 1
ADDRESS
0x3FFF
0x3FFF
8K INTERNAL
PMOVLAY = 0
OR
8K EXTERNAL
PMOVLAY = 1 OR 2
8K INTERNAL
PMOVLAY = 0
0x2000
0x1FFF
0x2000
0x1FFF
8K EXTERNAL
8K INTERNAL
0x0000
Figure 15. Program Memory Map
REV. 0
0x0000–
0x1FFF
ADDRESS
PM (MODE B = 1)1
PM (MODE B = 0)
INTERNAL
MEMORY
INTERNAL
8160
WORDS
0x0000–
0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 1
PMOVLAY
External
Overlay 2
32 MEMORY
MAPPED
REGISTERS
0x0000–
0x1FFF
Table XXII. PMOVLAY Bits
2
DATA MEMORY
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
0x0000
I/O Space (Full Memory Mode)
The AD73422 supports an additional external memory space
called I/O space. This space is designed to support simple connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space
supports 2048 locations of 16-bit wide data. The lower eleven
bits of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated 3-bit wait state
registers, IOWAIT0-3, that specify up to seven wait states to be
automatically generated for each of four regions. The wait states
act on address ranges as shown in Table XXIV.
–27–
AD73422
Table XXIV. Wait States
Byte Memory DMA (BDMA, Full Memory Mode)
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally, and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
Address Range Wait State Register
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
IOWAIT0
IOWAIT1
IOWAIT2
IOWAIT3
15 14 13 12 11 10
0
Composite Memory Select (CMS)
0
The AD73422 has a programmable memory select signal that is
useful for generating memory select signals for memories mapped
to more than one space. The CMS signal is generated to have
the same timing as each of the individual memory select signals
(PMS, DMS, BMS, IOMS) but can combine their functionality.
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip select
of the memory; use either DMS or PMS as the additional
address bit.
The AD73422 also lets you boot the processor from one external memory space while using a different external memory space
for BDMA transfers during normal operation. You can use the
CMS to select the first external memory space for BDMA transfers and BMS to select the second external memory space for
booting. The BMS signal can be disabled by setting Bit 3 of the
System Control Register to 1. The System Control Register is
illustrated in Figure 17.
2
1
0
1
1
1 DM (0ⴛ3FFF)
0
0
0
SPORT0 ENABLE
1 = ENABLED
0 = DISABLED
SPORT1 ENABLE
1 = ENABLED
0 = DISABLED
SPORT1 CONFIGURE
1 = SERIAL PORT
0 = FI, FO, IRQ0,
IRQ1, SCLK
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
3
2
1
0
0
1
0
0
0
DM (0ⴛ3FE3)
BTYPE
BMPAGE
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table XXV shows the data formats supported by the BDMA circuit.
Boot Memory Select (BMS) Disable
0
0
Figure 18. BDMA Control Register
The CMS pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at
reset, except the BMS bit.
SYSTEM CONTROL REGISTER
15 14 13 12 11 10 9 8 7 6 5 4 3
0
BDMA CONTROL
9 8 7 6 5
PWAIT
PROGRAM MEMORY
WAIT STATES
Table XXV. Data Formats
BTYPE
Internal
Memory Space
Word Size
Alignment
00
01
10
11
Program Memory
Data Memory
Data Memory
Data Memory
24
16
8
8
Full Word
Full Word
MSBs
LSBs
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external
byte memory space. The 8-bit BMPAGE register specifies the
starting page for the external byte memory space. The BDIR
register field selects the direction of the transfer. Finally the
14-bit BWCOUNT register specifies the number of DSP words
to transfer and initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
BMS ENABLE
0 = ENABLED
1 = DISABLED
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
Figure 17. System Control Register
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Register is shown in Figure 18. The byte memory space consists of
256 pages, each of which is 16K × 8.
The byte memory space on the AD73422 supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses.
–28–
REV. 0
AD73422
Once an access has occurred, the latched address is automatically incremented and another access can occur.
The BDMA Context Reset bit (BCR) controls whether or not
the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue
operations. Setting the BCR bit to 1 causes the processor to
stop execution while the BDMA accesses are occurring, to clear
the context of the processor and start execution at address 0
when the BDMA accesses have completed.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) directs the AD73422 to write the address onto the IAD0–14 bus
into the IDMA Control Register. If IAD[15] is set to 0, IDMA
latches the address. If IAD[15] is set to 1, IDMA latches OVLAY
memory. The IDMA OVLAY and address are stored in separate
memory-mapped registers. The IDMAA register, shown below,
is memory mapped at address DM (0x3FE0). Note that the
latched address (IDMAA) cannot be read back by the host. The
IDMA OVLAY register is memory mapped at address DM
(0x3FE7). See Figure 19 for more information on IDMA and
DMA memory maps.
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient means of communication
between a host system and the AD73422. The port is used to
access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot be used, however, to write to the DSP’s memorymapped control registers. A typical IDMA transfer process is
described as follows:
IDMA CONTROL (U = UNDEFINED AT RESET)
15 14 13 12 11 10 9 8 7 6 5 4 3 2
U
1. Host starts IDMA transfer.
2. Host checks IACK control line to see if the DSP is busy.
3. Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP’s IDMA control registers.
If IAD[15] = 1, the value of IAD[7:0] represents the IDMA
overlay: IAD[14:8] must be set to 0.
If IAD[15] = 0, the value of IAD[13:0] represents the starting address of internal memory to be accessed and IAD[14]
reflects PM or DM for access.
4. Host uses IS and IRD (or IWR) to read (or write) DSP internal memory (PM or DM).
5. Host checks IACK line to see if the DSP has completed the
previous IDMA operation.
6. Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to while the
AD73422 is operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can, therefore, access a block of sequentially addressed memory
by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for
each memory access.
U
U
U
U
U
U
U
U
U
U
U
U
1
0
U
U DM(0ⴛ3FE0)
IDMAA ADDRESS
IDMAD
DESTINATION MEMORY TYPE:
0 = PM
1 = DM
Figure 19. IDMA Control/OVLAY Registers
Bootstrap Loading (Booting)
The AD73422 has two mechanisms to allow automatic loading
of the internal program memory after reset. The method for
booting after reset is controlled by the Mode A, B and C configuration bits.
When the mode pins specify BDMA booting, the AD73422
initiates a BDMA boot sequence when reset is released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of onchip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
The ADSP-2100 Family Development Software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a
14-bit address and 1-bit destination type can be driven onto the
bus by an external device. The address specifies an on-chip
memory location; the destination type specifies whether it is a
DM or PM access. The falling edge of the address latch signal
latches this value into the IDMAA register.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the addresses to boot memory must be constructed externally to the
AD73422. The only memory address bit provided by the processor is A0.
Once the address is stored, data can either be read from or
written to the AD73422’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the AD73422 that a particular transaction is required. In either case, there is a one-processor-cycle
delay for synchronization. The memory access consumes one
additional processor cycle.
The AD73422 can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0 and Mode A = 1, the
AD73422 boots from the IDMA port. IDMA feature can load
as much on-chip memory as desired. Program execution is held
off until on-chip program memory location 0 is written to.
REV. 0
IDMA Port Booting
–29–
AD73422
Bus Request and Bus Grant (Full Memory Mode)
The AD73422 can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
AD73422 is not performing an external memory access, it responds to the active BR input in the following processor cycle
by:
• three-stating the data and address buses and the PMS, DMS,
BMS, CMS, IOMS, RD, WR output drivers,
• asserting the bus grant (BG) signal and
• halting program execution.
If Go Mode is enabled, the AD73422 will not halt program
execution until it encounters an instruction that requires an
external memory access.
• Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
• The syntax is a superset ADSP-2100 Family assembly language
and is completely source and object code compatible with other
family members. Programs may need to be relocated to utilize
on-chip memory and conform to the AD73422’s interrupt
vector and reset vector map.
• Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
• Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
If the AD73422 is performing an external memory access when
the external device asserts the BR signal, it will not three-state
the memory interfaces or assert the BG signal until the processor cycle after the access completes. The instruction does not
need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be
granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The BGH pin is asserted when the AD73422 is ready to execute
an instruction, but is stopped because the external bus is already
granted to another device. The other device can release the bus
by deasserting bus request. Once the bus is released, the
AD73422 deasserts BG and BGH and executes the external
memory access.
Flag I/O Pins
The AD73422 has eight general-purpose programmable input/
output flag pins. They are controlled by two memory mapped
registers. The PFTYPE register determines the direction, 1 =
output and 0 = input. The PFDATA register is used to read and
write the values on the pins. Data being read from a pin configured as an input is synchronized to the AD73422’s clock. Bits
that are programmed as outputs will read the value being output. The PF pins default to input during reset.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The AD73422 has on-chip emulation support and an ICE-Port,
a special set of pins that interface to the EZ-ICE. These features
allow in-circuit emulation without replacing the target system
processor by using only a 14-pin connection from the target
system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
See the ADSP-2100 Family EZ-Tools data sheet for complete
information on ICE products.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
prior to issuing a chip reset command from the emulator user
interface. If you are using a passive method of maintaining
mode information (as discussed in Setting Memory Modes), it
does not matter that the mode information is latched by an
emulator reset. However, if you are using the RESET pin as a
method of setting the value of the mode pins, you have to take
the effects of an emulator reset into consideration.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 20. This circuit forces the value located on the Mode
A pin to logic high; regardless if it latched via the RESET or
ERESET pin.
ERESET
RESET
In addition to the programmable flags, the AD73422 has
five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1
and FL2. FL0–FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.
Note: Pins PF0, PF1, PF2 and PF3 are also used for device
configuration during reset.
INSTRUCTION SET DESCRIPTION
The AD73422 assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:
• The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic
add instruction, such as AR = AX0 + AY0, resembles a
simple equation.
AD73422
1k⍀
MODE A/PFO
PROGRAMMABLE
I/O
Figure 20. Mode A Pin/EZ-ICE Circuit
The ICE-Port interface consists of the following AD73422 pins:
EBR
EMS
ELIN
EBG
EINT
ELOUT
ERESET
ECLK
EE
These AD73422 pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pulldown resistors. The traces for these signals between the AD73422
and the connector must be kept as short as possible, no longer
than three inches.
–30–
REV. 0
AD73422
The following pins are also used by the EZ-ICE:
BR
RESET
Note: If your target does not meet the worst case chip specification for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing requirements within published limits.
BG
GND
The EZ-ICE uses the EE (emulator enable) signal to take control of the AD73422 in the target system. This causes the processor to use its ERESET, EBR and EBG pins instead of the
RESET, BR and BG pins. The BG output is three-stated. These
signals do not need to be jumper-isolated in your system.
Restriction: All memory strobe signals on the AD73422 (RD,
WR, PMS, DMS, BMS, CMS and IOMS) used in your target
system must have 10 kΩ pull-up resistors connected when the
EZ-ICE is being used. The pull-up resistors are necessary because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is 10 inches in length
with one end fixed to the EZ-ICE. The female plug is plugged
onto the 14-pin connector (a pin strip header) on the target
board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 21. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
EBG
BR
EINT
EBR
KEY (NO PIN)
ⴛ
ELIN
ECLK
ELOUT
EE
RESET
BG
EMS
ERESET
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals changes. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:
• EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the RESET
signal.
• EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the BR signal.
• EZ-ICE emulation ignores RESET and BR when singlestepping.
• EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted).
• EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE board’s DSP.
TOP VIEW
ANALOG FRONT END (AFE) INTERFACING
Figure 21. Target Board Connector for EZ-ICE
The AFE section of the AD73422 features two voiceband input/
output channels, each with 16-bit linear resolution. Connectivity to the AFE section from the DSP is uncommitted, thus
allowing the user the flexibility of connecting in the mode or
configuration of their choice. This section will detail several
configurations—with no extra AFE channels configured and
with two extra AFE channels configured (using an external
AD73322 dual AFE).
The 14-pin, 2-row pin strip header is keyed at the Pin 7 location—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie and Samtec.
DSP SPORT to AFE Interfacing
Target Memory Interface
For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed
below.
PM, DM, BM, IOM and CM
Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM) and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as specified in the DSP’s data sheet. The performance of the EZ-ICE
may approach published worst case specification for some memory
access timing requirements and switching characteristics.
REV. 0
The SCLK, SDO, SDOFS, SDI and SDIFS pins of SPORT2
must be connected to the Serial Clock, Receive Data, Receive
Data Frame Sync, Transmit Data and Transmit Data Frame
Sync pins respectively of either SPORT0 or SPORT1. The SE
pin may be controlled from a parallel output pin or flag pin such
as FL0-2 or, where SPORT2 power-down is not required, it can
be permanently strapped high using a suitable pull-up resistor.
The ARESET pin may be connected to the system hardware
reset structure or it may also be controlled using a dedicated
control line. In the event of tying it to the global system reset, it
is advisable to operate the device in mixed mode, which allows a
software reset, otherwise there is no convenient way of resetting
the AFE section.
–31–
AD73422
SCLK
SDO
AD73422
DR
RFS
SDOFS
AFE
SECTION
RFS
FL0
ARESET
FL1
SE
FL0
SCLK
SDOFS
SDIFS
SCLK
Cascade Operation
AMCLK
ADDITIONAL
AD73322
CODEC
D
Q
1/2
74HC74
SE SIGNAL
SYNCHRONIZED
TO AMCLK
CLK
D
Q
1/2
74HC74
ARESET SIGNAL
SYNCHRONIZED
TO AMCLK
CLK
Figure 23. SE and ARESET Sync Circuit for Cascaded
Operation
Connection of a cascade of devices to a DSP, as shown in Figure 24, is no more complicated than connecting a single device.
Instead of connecting the SDO and SDOFS to the DSP’s Rx
port, these are now daisy-chained to the SDI and SDIFS of the
next device in the cascade. The SDO and SDOFS of the final
device in the cascade are connected to the DSP section’s Rx
port to complete the cascade. SE and ARESET on all devices
are fed from the signals that were synchronized with the AMCLK
using the circuit as described above. The SCLK from only one
device need be connected to the DSP section’s SCLK input(s)
as all devices will be running at the same SCLK frequency and
phase.
SDOFS
D1
D2
AMCLK
SE
ARESET
SDO
Where it is required to configure extra analog I/O channels to
the existing two channels on the AD73422, it is possible to
cascade up to six more channels (using single channel AD73311
or dual channel AD73322 AFEs) by using the scheme described
in Figure 24. It is necessary, however, to ensure that the timing
of the SE and ARESET signals is synchronized at each device in
the cascade. A simple D-type flip-flop is sufficient to sync each
signal to the master clock AMCLK, as in Figure 23.
DSP
CONTROL
TO ARESET
ARESET
DEVICE 1
FL1
Figure 22. AD73422 AFE to DSP Connection
AMCLK
SE
AFE
SECTION
SDO
SDI
DSP
CONTROL
TO SE
AMCLK
SDI
SCLK
DSP
SECTION
SCLK
DR
SDIFS
DT
SDI
DT
DSP
SECTION
TFS
SDIFS
TFS
DEVICE 2
Q1
74HC74
Q2
Figure 24. Connection of an AD73322 Cascaded to
AD73422
Interfacing to the AFE’s Analog Inputs and Outputs
The AFE section of the AD73422 offers a flexible interface for
microphone pickups, line level signals or PSTN line interfaces.
This section will detail some of the configurations that can be
used with the input and output sections.
The AD73422 features both differential inputs and outputs on
each channel to provide optimal performance and avoid commonmode noise. It is also possible to interface either inputs or outputs in single-ended mode. This section details the choice of
input and output configurations and also gives some tips toward
successful configuration of the analog interface sections.
ANTIALIAS
FILTER
100⍀
VFBN1
VINN1
0.047␮F
VREF
VINP1
0.047␮F
100⍀
0/38dB
PGA
VFBP1
VREF
GAIN
1
VOUTP1
+6/–15dB
PGA
VOUTN1
REFOUT
AD73422
CONTINUOUS
TIME
LOW-PASS
FILTER
REFERENCE
REFCAP
0.1␮F
Figure 25. Analog Input (DC-Coupled)
–32–
REV. 0
AD73422
Analog Inputs
There are several different ways in which the analog input (encoder) section of the AD73422 can be interfaced to external
circuitry. It provides optional input amplifiers which allows
sources with high source impedance to drive the ADC section
correctly. When the input amplifiers are enabled, the input
channel is configured as a differential pair of inverting amplifiers
referenced to the internal reference (REFCAP) level. The inverting terminals of the input amplifier pair are designated as
pins VINP1 and VINN1 for Channel 1 (VINP2 and VINN2 for
Channel 2) and the amplifier feedback connections are available
on pins VFBP1 and VFBN1 for Channel 1 (VFBP2 and VFBN2
for Channel 2).
ANTIALIAS
FILTER
100⍀
VINN1
VREF
0.047␮F
VINP1
0/38dB
PGA
VFBP1
100⍀
VREF
GAIN
1
For applications where external signal buffering is required, the
input amplifiers can be bypassed and the ADC driven directly.
When the input amplifiers are disabled, the sigma-delta modulator’s input section (SC PGA) is accessed directly through the
VFBP1 and VFBN1 pins for Channel 1 (VFBP2 and VFBN2
for Channel 2).
VOUTP1
+6/–15dB
PGA
VOUTN1
OPTIONAL
BUFFER
It is also possible to drive the ADCs in either differential or
single-ended modes. If the single-ended mode is chosen it is
possible using software control to multiplex between two singleended inputs connected to the positive and negative input pins.
The primary concerns in interfacing to the ADC are firstly to
provide adequate antialias filtering and to ensure that the signal
source will correctly drive the switched-capacitor input of the
ADC. The sigma-delta design of the ADC and its oversampling
characteristics simplify the antialias requirements, but it must be
remembered that the single-pole RC filter is primarily intended
to eliminate aliasing of frequencies above the Nyquist frequency of the sigma-delta modulator’s sampling rate (typically 2.048 MHz). It may still require a more specific digital
filter implementation in the DSP to provide the final signal
frequency response characteristics. It is recommended that for
optimum performance the capacitors used for the antialiasing
filter be of high quality dielectric (NPO). The second issue
mentioned above is interfacing the signal source to the ADC’s
switched capacitor input load. The SC input presents a complex
dynamic load to a signal source, so it is important to understand
that the slew rate characteristic is an important consideration
when choosing external buffers for use with the AD73422. The
internal inverting op amps on the AD73422’s AFE are specifically designed to interface to the ADC’s SC input stage.
VFBN1
0.047␮F
REFOUT
AD73422
CONTINUOUS
TIME
LOW-PASS
FILTER
REFERENCE
REFCAP
0.1␮F
Figure 26. Analog Input (DC-Coupled) Using External
Amplifiers
The AD73422’s ADC inputs are biased about the internal reference level (REFCAP level), therefore it may be necessary to
either bias external signals to this level using the buffered
REFOUT level as the reference. This is applicable in either dcor ac-coupled configurations. In the case of dc-coupling, the
signal (biased to REFOUT) may be applied directly to the inputs (using amplifier bypass), as shown in Figure 25, or it may
be conditioned in an external op amp where it can also be biased to the reference level using the buffered REFOUT signal as
shown in Figure 26. It is also possible to connect inputs directly
to the AD73422’s input op amps as shown in Figure 27.
The AD73422’s on-chip 38 dB preamplifier can be enabled
when there is not enough gain in the input circuit; the preamplifier is configured by bits IGS0–2 of CRD. The total gain must
be configured to ensure that a full-scale input signal produces a
signal level at the input to the sigma-delta modulator of the
ADC that does not exceed the maximum input range.
The dc biasing of the analog input signal is accomplished with
an on-chip voltage reference. If the input signal is not biased at
the internal reference level (via REFOUT), it must be ac-coupled
with external coupling capacitors. CIN should be 0.1 µF or
larger. The dc biasing of the input can then be accomplished
using resistors to REFOUT as in Figures 28 and 29.
100pF
50k⍀
VFBN1
50k⍀
VINN1
50k⍀
VINP1
VREF
50k⍀
0/38dB
PGA
VFBP1
100pF
VREF
GAIN
1
VOUTP1
+6/–15dB
PGA
VOUTN1
REFOUT
AD73422
CONTINUOUS
TIME
LOW-PASS
FILTER
REFERENCE
REFCAP
0.1␮F
Figure 27. Analog Input (DC-Coupled) Using Internal
Amplifiers
REV. 0
–33–
AD73422
In the case of ac-coupling, a capacitor is used to couple the
signal to the input of the ADC. The ADC input must be biased
to the internal reference (REFCAP) level, which is done by
connecting the input to the REFOUT pin through a 10 kΩ
resistor as shown in Figure 28.
If best performance is required from a single-ended source, it is
possible to configure the AD73422’s input amplifiers as a
single-ended-to-differential converter as shown in Figure 30.
100pF
50k⍀
0.1␮F
100⍀
VFBN1
0.047␮F
VINN1
VINN1
50k⍀
VINP1
0.1␮F
10k⍀
100⍀
VREF
50k⍀
VREF
10k⍀
VFBN1
0/38dB
PGA
VFBP1
VINP1
50k⍀
0/38dB
PGA
VFBP1
100pF
0.047␮F
VREF
VREF
GAIN
1
GAIN
1
AD73422
AD73422
VOUTP1
VOUTP1
+6/–15dB
PGA
VOUTN1
VOUTN1
REFOUT
REFOUT
CONTINUOUS
TIME
LOW-PASS
FILTER
+6/–15dB
PGA
CONTINUOUS
TIME
LOW-PASS
FILTER
REFERENCE
REFERENCE
REFCAP
REFCAP
0.1␮F
0.1␮F
Figure 30. Single-Ended-to-Differential Conversion On
Analog Input
Figure 28. Analog Input (AC-Coupled) Differential
If the ADC is being connected in single-ended mode, the
AD73422 should be programmed for single-ended mode using
the SEEN and INV bits of CRF and the inputs connected as
shown in Figure 29. When operated in single-ended input
mode, the AD73422 can multiplex one of the two inputs to the
ADC input.
0.1␮F
100⍀
VFBN1
0.047␮F
VINN1
Interfacing to an Electret Microphone
Figure 31 details an interface for an electret microphone which
may be used in some voice applications. Electret microphones
typically feature a FET amplifier whose output is accessed on
the same lead that supplies power to the microphone, therefore
this output signal must be capacitively coupled to remove the
power supply (dc) component. In this circuit the AD73422
+5V
RA
VREF
10k⍀
10␮F
C1
VINP1
0/38dB
PGA
VFBP1
R2
RB
VREF
GAIN
1
VOUTP1
+6/–15dB
PGA
VOUTN1
REFOUT
C2
R1
VFBN1
VINN1
ELECTRET
PROBE
AD73422
VREF
VINP1
0/38dB
PGA
VFBP1
CONTINUOUS
TIME
LOW-PASS
FILTER
VREF
GAIN
1
AD73422
REFERENCE
VOUTP1
REFCAP
+6/–15dB
PGA
0.1␮F
VOUTN1
Figure 29. Analog Input (AC-Coupled) Single-Ended
REFOUT
CONTINUOUS
TIME
LOW-PASS
FILTER
REFERENCE
REFCAP
CREFCAP
Figure 31. Electret Microphone Interface Circuit
–34–
REV. 0
AD73422
Figure 33 shows an example circuit for providing a single-ended
output with ac coupling. The capacitor of this circuit (COUT) is
not optional if dc current drain is to be avoided.
input channel is being used in single-ended mode where the
internal inverting amplifier provides suitable gain to scale the
input signal relative to the ADC’s full-scale input range. The
buffered internal reference level at REFOUT is used via an
external buffer to provide power to the electret microphone.
This provides a quiet, stable supply for the microphone. If this
is not a concern, then the microphone can be powered from the
system power supply.
VFBN1
VINN1
VREF
Analog Output
VINP1
The AD73422’s differential analog output (VOUT) is produced
by an on-chip differential amplifier. The differential output can
be ac-coupled or dc-coupled directly to a load that can be a
headset or the input of an external amplifier (the specified
minimum resistive load on the output section is 150 Ω.) It is
possible to connect the outputs in either a differential or a
single-ended configuration, but please note that the effective
maximum output voltage swing (peak-to-peak) is halved in the
case of single-ended connection. Figure 32 shows a simple circuit providing a differential output with ac coupling. The capacitors in this circuit (COUT) are optional; if used, their value
can be chosen as follows:
COUT =
VFBP1
GAIN
1
COUT
AD73422
VOUTP1
CONTINUOUS
TIME
LOW-PASS
FILTER
+6/–15dB
PGA
RLOAD
VOUTN1
REFOUT
REFERENCE
REFCAP
0.1␮F
1
2π fC RLOAD
Figure 33. Example Circuit for Single-Ended Output
where fC = desired cutoff frequency.
Differential-to-Single-Ended Output
In some applications it may be desirable to convert the full
differential output of the decoder channel to a single-ended
signal. The circuit of Figure 34 shows a scheme for doing this.
VFBN1
VINN1
VREF
VFBN1
VINP1
0/38dB
PGA
VFBP1
VINN1
VREF
VINP1
VREF
GAIN
1
COUT
0/38dB
PGA
VFBP1
AD73422
VOUTP1
RLOAD
VOUTN1
+6/–15dB
PGA
VREF
CONTINUOUS
TIME
LOW-PASS
FILTER
GAIN
1
AD73422
VOUTP1
COUT
REFOUT
RI
REFERENCE
RF
REFCAP
VOUTN1
+6/–15dB
PGA
CONTINUOUS
TIME
LOW-PASS
FILTER
RI
CREFCAP
RLOAD
Figure 32. Example Circuit for Differential Output
RF
REFOUT
REFERENCE
REFCAP
0.1␮F
Figure 34. Example Circuit for Differential-to-SingleEnded Output Conversion
REV. 0
–35–
AD73422
Grounding and Layout
As the analog inputs to the AD73422’s AFE section are differential, most of the voltages in the analog modulator are commonmode voltages. The excellent common-mode rejection of the
part will remove common-mode noise on these inputs. The
analog and digital supplies of the AD73422 are independent and
separately pinned out to minimize coupling between analog and
digital sections of the device. The digital filters on the encoder
section will provide rejection of broadband noise on the power
supplies, except at integer multiples of the modulator sampling
frequency. The digital filters also remove noise from the analog
inputs provided the noise source does not saturate the analog
modulator. However, because the resolution of the AD73422’s
ADC is high, and the noise levels from the AD73422 are so low,
care must be taken with regard to grounding and layout.
AFE DIGITAL
AFE ANALOG
DSP
C3505–8–6/99
7
6
5
4
3
2
1
A B C D E F G H J K L M N P R T U
DIGITAL
GROUND PLANE
The printed circuit board that houses the AD73422 should be
designed so the analog and digital sections are separated and
confined to certain sections of the board. The AD73422 ballout configuration offers a major advantage in that its analog
interfaces are confined to the last three rows of the package.
This facilitates the use of ground planes that can be easily separated, as shown in Figure 35. A minimum etch technique is
generally best for ground planes as it gives the best shielding.
Digital and analog ground planes should be joined in only one
place. If this connection is close to the device, it is recommended
to use a ferrite bead inductor.
ANALOG
GROUND PLANE
Figure 35. Ground Plane Layout
the analog inputs. Traces on opposite sides of the board should
run at right angles to each other. This will reduce the effects of
feedthrough through the board. A microstrip technique is by far
the best but is not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes while signals are placed on the other side.
Good decoupling is important when using high speed devices.
On the AD73422 both the reference (REFCAP) and supplies
need to be decoupled. It is recommended that the decoupling
capacitors used on both REFCAP and the supplies, be placed as
close as possible to their respective ball connections to ensure
high performance from the device. All analog and digital supplies should be decoupled to AGND and DGND respectively,
with 0.1 µF ceramic capacitors in parallel with 10 µF tantalum
capacitors. The AFE’s digital section supply (DVDD) should be
connected to the digital supply that feeds the DSP’s VDD(Ext)
connections while the AFE’s digital ground DGND should be
returned to the digital ground plane.
Avoid running digital lines under the AFE section of the device
for they will couple noise onto the die. The analog ground plane
should be allowed to run under the AD73422’s AFE section to
avoid noise coupling (see Figure 35). The power supply lines to
the AD73422 should use as large a trace as possible to provide
low impedance paths and reduce the effects of glitches on the
power supply lines. Fast switching signals such as clocks should
be shielded with digital ground to avoid radiating noise to other
sections of the board, and clock signals should never be run near
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
119-Ball Plastic Ball Grid Array (PBGA)
B-119
0.300 (7.62) BSC
BOTTOM
VIEW
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
A1
TOP VIEW
0.050
(1.27)
BSC
0.874 (22.20)
0.858 (21.80)
0.033
(0.84)
REF
0.126 (3.19)
REF
DETAIL A
0.089 (2.27)
0.073 (1.85)
0.028 (0.70)
0.020 (0.50)
SEATING
PLANE
–36–
PRINTED IN U.S.A.
0.559 (14.20)
0.543 (13.80)
0.800
(20.32)
BSC
0.050 (1.27)
BSC
DETAIL A
0.035 (0.90)
0.024 (0.60)
BALL DIAMETER
0.037 (0.95)
0.033 (0.85)
0.022 (0.56)
REF
REV. 0