DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 DS92LX2121/DS92LX2122 10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer Check for Samples: DS92LX2121, DS92LX2122 FEATURES APPLICATIONS • • • 1 2 • General – Up to 1050 Mbits/sec Data Throughput – 10 MHz to 50 MHz Input Clock Support – Supports 18-bit Color Depth (RGB666 + HS, VS, DE) – Embedded Clock with DC Balanced Coding to Support AC-Coupled Interconnects – Capable to Drive up to 10 Meters Shielded Twisted-Pair – Bi-Directional Control Interface Channel with I2C Support – I2C Interface for Device Configuration. Single-Pin ID Addressing – Up to 4 GPI on DES and GPO on SER – AT-SPEED BIST Diagnosis Feature to Validate Link Integrity – Individual Power-Down Controls for both SER and DES – User-Selectable Clock Edge for Parallel Data on both SER and DES – Integrated Termination Resistors – 1.8V- or 3.3V-Compatible Parallel Bus Interface – Single Power Supply at 1.8V – IEC 61000–4–2 ESD Compliant – Temperature Range −40°C to +85°C DESERIALIZER — DS92LX2122 – No Reference Clock Required on Deserializer – Programmable Receive Equalization – LOCK Output Reporting Pin to Ensure – EMI/EMC Mitigation – Programmable Spread Spectrum (SSCG) Outputs – Receiver Output Drive Strength Control (RDS) – Receiver Staggered Outputs Industrial Displays, Touch Screens Medical Imaging DESCRIPTION The DS92LX2121/DS92LX2122 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex control channel for data transmission over a single differential pair. The DS92LX2121/DS92LX2122 incorporates differential signaling on both the high-speed and bi-directional back channel control data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with a bidirectional back channel control bus. The primary transport converts 21 bit data over a single highspeed serial stream, along with a separate low latency bi-directional back channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional back channel control information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce cable width, connector size and pins. In addition, the Deserializer provides input equalization to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. A sleep function provides a power-savings mode when the high speed forward channel and embedded bi-directional control channel are not needed. The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2014, Texas Instruments Incorporated DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com Typical Application Diagram Channel Link III Parallel Data In 18+3 Graphics Controller, Camera Parallel Data Out 18+3 4 Display Module, Frame Grabber 4 DS92LX2121 DS92LX2122 GPO GPI Back Channel 2 Serial Control Bus 2 Serializer Deserializer Serial Control Bus DOUT+ DOUT- RIN+ RT RT Output Latch RT Decoder Serializer 4 RT Deserializer GPO[3:0] Encoder Data [17:0], 21 Control [2:0] Input Latch Block Diagrams 21 Data [17:0], Control [2:0] 4 GPI[3:0] RINPCLK PDB BISTEN M/S LOCK PASS I2C Controller Encoder FIFO Encoder Decoder Timing and Control Decoder CAD I2C Controller SCL Clock Gen CDR Timing and Control PDB M/S SDA Clock Gen PLL FIFO PCLK SDA SCL CAD DS92LX2122 - DESERIALIZER DS92LX2121 - SERIALIZER Figure 1. Block Diagram DS92LX2121 Serializer Graphics Controller --Video Processor -Camera Channel Link III R[5:0] G[5:0] B[5:0] VS HS DE PCLK PDB M/S DS92LX2122 Deserializer R[5:0] G[5:0] B[5:0] VS HS DE PCLK PLL Config. Config. PDB M/S BISTEN GPI[3:0] Timing Controller -Display -Frame Grabber GPO[3:0] PC SDA SCL 2 I C 2 I C SDA SCL PC Figure 2. Application Block Diagram 2 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 DS92LX2121 Pin Diagram DIN[7] DIN[6] DIN[5] DIN[4] DIN[3] DIN[2] DIN[1] DIN[0] GPO[3] GPO[2] 30 29 28 27 26 25 24 23 22 21 Top View 20 GPO[1] 19 GPO[0] 33 18 VDDCML VDDD 34 17 DOUT+ DIN[10] 35 16 DOUT- DIN[11] 36 15 VDDT DIN[12] 37 14 VDDPLL DIN[13] 38 13 PDB DIN[14] 39 12 M/S DIN[15] 40 11 RES 3 4 5 6 7 8 9 10 DIN[19] DIN[20] PCLK SCL SDA CAD RES DS92LX2121 (Top View) DIN[18] DIN[9] DAP = GND 2 32 DIN[17] DIN[8] 1 31 DIN[16] VDDIO Figure 3. Serializer - DS92LX2121 40-Pin WQFN (RTA Package) DS92LX2121 Serializer PIN DESCRIPTIONS Pin Name Pin No. I/O, Type Description LVCMOS PARALLEL INTERFACE DIN[20:0] PCLK 5, 4, 3, 2, 1, 40, 39, 38, 37, 36, 35, 33, 32, 30, 29, 28, 27, 26, 25, 24, 23 Inputs, LVCMOS w/ pull down Parallel data inputs. 6 Input, LVCMOS w/ pull down Pixel Clock Input Pin. Strobe edge set by TRFB configuration. GENERAL PURPOSE OUTPUT (GPO) GPO[3:0] 22, 21, 20, 19 Output, LVCMOS General-purpose pins individually configured as outputs; which are used to control and respond to various commands. SERIAL CONTROL BUS - I2C COMPATIBLE SCL 7 Input/Output, Open Drain Clock line for the serial control bus communication SCL requires an external pull-up resistor to VDDIO. SDA 8 Input/Output, Open Drain Data line for the serial control bus communication SDA requires an external pull-up resistor to VDDIO. Input, LVCMOS w/ pull down I2C Mode Select M/S = L, Master mode (default); device generates and drives the SCL clock line. Device is connected to a slave peripheral on the bus. (Serializer initially starts up in Standby mode and is enabled through remote wakeup by the Deserializer) M/S = H, Slave; device accepts SCL clock input M/S CAD 12 9 Input, analog Continuous Address Decoder Input pin to select the Slave Device Address. Input is connect to external resistor divider to programmable Device ID address (see Serial Control Bus Connection). Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 3 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com DS92LX2121 Serializer PIN DESCRIPTIONS (continued) Pin Name Pin No. I/O, Type Description CONTROL AND CONFIGURATION PDB 13 Input, LVCMOS w/ pull down Power down Mode Input Pin. PDB = H, Transmitter is enabled and is ON. PDB = L, Transmitter is in Sleep (Power Down). When the transmitter is in the SLEEP state, the PLL is shutdown, and IDD is minimized. RES 10, 11 Input, LVCMOS w/ pull down Reserved. This pin MUST be tied LOW. Channel Link III INTERFACE DOUT+ 17 Input/Output, CML Non-inverting differential output, back-channel input. DOUT- 16 Input/Output, CML Inverting differential output, back-channel input. VDDPLL 14 Power, Analog PLL Power, 1.8V ±5% VDDT 15 Power, Analog Tx Analog Power, 1.8V ±5% VDDCML 18 Power, Analog LVDS & BC Dr Power, 1.8V ±5% VDDD 34 Power, Digital Digital Power, 1.8V ±5% VDDIO 31 Power, Digital Power for input stage, The single-ended inputs are powered from VDDIO. DAP Ground, DAP DAP must be grounded. Connect to the ground plane (GND) with at least 16 vias. Power and Ground VSS DS92LX2122 Pin Diagram ROUT[0] ROUT[1] ROUT[2] ROUT[3] 27 26 25 GPI[2] 31 28 GPI[1] 32 GPI[3] GPI[0] 33 VDDOR1 LOCK 34 29 PDB 35 30 VDDR 36 Top View 24 ROUT[4] 23 ROUT[5] PASS 37 RES 38 RES 39 22 ROUT[6] VDDCML 40 21 ROUT[7] RIN+ 41 20 VDDOR2 19 ROUT[8] 18 ROUT[9] DAP = GND RIN- 42 RES 43 BISTEN 44 17 VDDD VDDPLL 45 16 ROUT[10] RES 46 15 ROUT[11] M/S 47 14 ROUT[12] CAD 48 13 ROUT[13] 9 10 11 12 ROUT[16] ROUT[15] ROUT[14] 8 ROUT[17] 7 6 ROUT[19] VDDOR3 5 ROUT[18] 4 PCLK 3 ROUT[20] 2 SCL VDDSSCG SDA 1 DS92LX2122 (Top View) Figure 4. Deserializer - DS92LX2122 48-Pin WQFN (RHS Package) 4 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 DS92LX2122 Deserializer PIN DESCRIPTIONS Pin Name Pin No. I/O, Type Description LVCMOS PARALLEL INTERFACE ROUT[20:0] PCLK 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 21, 22, 23, 24, 25, 26, 27, 28 Outputs, LVCMOS Parallel data outputs. 4 Output, LVCMOS Pixel Clock Output Pin. Strobe edge set by RFB configuration. In SLEEP, outputs are controlled by the OSS_SEL. General Purpose Input (GPI) GPI[3:0] 30, 31, 32, 33 Input, Digital General-purpose pins individually configured as inputs; which are used to control and respond to various commands. SERIAL CONTROL BUS - I2C COMPATIBLE SCL 2 Input/Output, Open Drain Clock line for the serial control bus communication SCL requires an external pull-up resistor to VDDIO. SDA 1 Input/Output, Open Drain Data line for serial control bus communication SDA requires an external pull-up resistor to VDDIO. I2C Mode Select M/S 47 Input, LVCMOS w/ pull up M/S = L, Master; device generates and drives the SCL clock line. Device is connected to slave peripheral on teh bus. M/S = H, Slave (default); device accepts SCL clock input and is attached to an I2C controller master on the bus. Slave mode does not generate the SCL clock, but uses the clock generated by teh Master for teh data transfer. Continuous Address Decoder CAD 48 Input, analog Input pin to select the Slave Device Address. Input is connect to external resistor divider to programmable Device ID address (see Serial Control Bus Connection) CONTROL AND CONFIGURATION Power down Mode Input Pin. PDB 35 Input, LVCMOS w/ pull down PDB = H, Receiver is enabled and is ON. PDB = L, Receiver is in Sleep (Power down mode). When the Receiver is in the SLEEP state, the LVCMOS Outputs are in TRI-STATE, the PLL is shutdown and IDD is minimized. LOCK Status Output Pin. LOCK 34 Output, LVCMOS LOCK = H, PLL is Locked, outputs are active LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by OSS_SEL. May be used as Link Status. Reserved. RES 38, 39, 43, 46 - Pin 43: Leave pin open. Pin 46: This pin MUST be tied LOW. Pins 38, 39: Route to test point as differential pair or leave open if unused. BIST MODE BIST Enable Pin. BISTEN 44 Input, LVCMOS w/ pull down BISTEN = H, BIST Mode is enabled. BISTEN = L, BIST Mode is disabled. PASS Output Pin for BIST mode. PASS 37 Output, LVCMOS PASS = H, ERROR FREE Transmission PASS = L, one or more errors were detected in the received payload. Leave Open if unused. Route to test point (pad) recommended. Channel Link III INTERFACE RIN+ 41 Input/Output, CML Non-inverting differential input, back channel output. The interconnect must be AC coupled with a 0.1μF capacitor. RIN- 42 Input/Output, CML Inverting differential input, back channel output. The interconnect must be AC coupled with a 0.1 μF capacitor. Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 5 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com DS92LX2122 Deserializer PIN DESCRIPTIONS (continued) Pin Name Pin No. I/O, Type Description POWER AND GROUND 3 Digital Power SSCG Power, 1.8V ±5% Power supply must be connect regardless if SSCG function is in operation 29, 20, 7 Digital Power TTL Output Buffer Power, The single-ended outputs and control input are powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10% VDDSSCG VDDOR1/2/3 VDDD 17 Digital Power Digital Core Power, 1.8V ±5% VDDR 36 Analog Power Rx Analog Power, 1.8V ±5% VDDCML 40 Analog Power Bi-directional Channel Driver Power, 1.8V ±5% VDDPLL 45 Analog Power PLL Power, 1.8V ±5% DAP Ground, DAP DAP must be grounded. Connect to the ground plane (GND) with at least 16 vias. VSS These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage ( VDD1V8) −0.3V to +2.5V Supply Voltage (VDD3V3) −0.3V to +4.0V LVCMOS Input Voltage (VDD1V8) −0.3V to +(VDD1V8 + 0.3V) LVCMOS Input Voltage (VDD3V3) −0.3V to +(VDD3V3 + 0.3V) −0.3V to +(VDD + 0.3V) LVCMOS Output Voltage (VDD) CML Receiver Input Voltage (VDD1V8) −0.3V to (VDD1V8 + 0.3V) CML Driver Output Voltage (VDD1V8) −0.3V to (VDD1V8 + 0.3V) Junction Temperature +150°C Storage Temperature −65°C to +150°C Maximum Package Power Dissipation Capacity 1/θJA °C/W above +25° Package Derating: DS92LX2121 40L WQFN θJA(based on 16 thermal vias) 30.7 °C/W θJC(based on 16 thermal vias) 6.8 °C/W DS92LX2122 48L WQFN θJA(based on 16 thermal vias) 26.9 °C/W θJC(based on 16 thermal vias) 4.4 °C/W ESD Rating (IEC61000–4–2) RD = 330Ω, CS = 150 pF Air Discharge (DOUT+, DOUT-, RIN+, RIN-) ≥±25 kV Contact Discharge (DOUT+, DOUT-, RIN+, RIN-) ≥±10 kV ≥±8 kV ESD Rating (HBM) For soldering specifications, see the Absolute Maximum Ratings for Soldering Application Report (literature number SNOA549). (1) (2) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Recommended Operating Conditions Min Nom Max Units VDD (1.8V) 1.71 1.8 1.89 V VDDIO (1.8V Mode) 1.71 1.8 1.89 V VDDIO (3.3V Mode) 3 3.3 3.6 V 6 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 Recommended Operating Conditions (continued) Min Nom Max Units VDDn (1.8 V) 25 mVP-P VDDIO (1.8 V) 25 mVP-P 50 mVP-P Supply Noise (1) VDDIO (3.3 V) Operating Free Air Temperature (TA) -40 Input Clock Rate (1) 25 10 85 °C 50 MHz Supply noise testing was done with minimum capacitors (as shown on Figures 35, 36) on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on the other hand shows no error when the noise frequency is less than 750 kHz. Serializer Electrical Characteristics (1) (2) (3) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units LVCMOS DC SPECIFICATIONS 3.3V I/O (TX INPUTS, RX OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS) VIH High Level Input Voltage VIN = 3.0V to 3.6V 2.0 VIN V VIL Low Level Input Voltage VIN = 3.0V to 3.6V GND 0.8 V IIN Input Current VIN = 0V or 3.6V VIN = 3.0V to 3.6V -20 +20 µA VOH High Level Output Voltage VDDIO = 3.0V to 3.6V 2.4 VDDIO VOL Low Level Output Voltage VDDIO = 3.0V to 3.6V IOH = +4mA GND 0.4 IOS IOZ Output Short Circuit Current VOUT = 0V RPWDNB = 0V, VOUT = 0V or VDD TRI-STATE Output Current ±1 V V Serializer GPO Outputs -24 Deserializer LVCMOS Outputs -39 mA Register Address (OSS_SEL = 0) -20 ±1 +20 µA LVCMOS DC SPECIFICATIONS 1.8V I/O (TX INPUTS, RX OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS) VIH High Level Input Voltage VIN = 1.71V to 1.89V 0.65 VIN VIN + 0.3 VIL Low Level Input Voltage VIN = 1.71V to 1.89V GND 0.35 VIN IIN Input Current VIN = 0V or 1.89V VIN = 1.71V to 1.89V -20 VOH High Level Output Voltage VDDIO = 1.71V to 1.89V IOH = −4mA VOL Low Level Output Voltage VDDIO = 1.71V to 1.89V IOL = +4 mA (1) (2) (3) V ±1 +20 µA VDDIO - 0.45 VDDIO V GND 0.45 V The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 7 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com Serializer Electrical Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol IOS Parameter Conditions Output Short Circuit Current IOZ VOUT = 0V (4) RPWDNB = 0V, VOUT = 0V or VDD TRI-STATE Output Current Min Typ Serializer GPO Outputs -11 Deserializer LVCMOS Outputs -20 Max Units mA Register Address (OSS_SEL = 0) -20 ±1 +20 µA 268 340 412 mV 1 50 mV VDD (MIN) - VOD VDD - VOD VDD (MAX) VOD (MIN) V 1 50 mV CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-) RT = 100Ω (SeeFigure 9) |VOD| Output Differential Voltage ΔVOD Output Differential Voltage Unbalance RL = 100Ω RL = 100Ω (See Figure 9) VOS Output Differential Offset Voltage ΔVOS Offset Voltage Unbalance RL = 100Ω IOS Output Short Circuit Current DOUT+/- = 0V, PDB = L or H (4) RT Differential Internal Termination Resistance Differential across DOUT+ and DOUT- (MAX) -27 80 100 mA 120 Ω CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-) VTH Differential Threshold High Voltage VTL Differential Threshold Low Voltage +90 VIN Differential Input Voltage Range RIN+ - RIN- 180 IIN Input Current VIN = VDD or 0 V, VDD = 1.89 V -20 ±1 +20 µA RT Differential Internal Termination Resistance Differential across RIN+ and RIN- 80 100 120 Ω 62 90 VCM = 1.2V -90 mV mV SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDDS Serializer (Tx) Total Supply Current Mode (includes load current) IDDT IDDIOT RT = 100Ω WORST CASE pattern (See Figure 6) RT = 100Ω RANDOM pattern RT = 100Ω Serializer (Tx) WORST CASE VDDIO Supply Current (includes load pattern (See current) Figure 6) IDDTZ IDDIOTZ (4) 8 Serializer (Tx) Supply Current Power-down PDB = 0V; All other LVCMOS Inputs = 0V VDDn = 1.89 V f = 50 MHz Default Registers mA 55 VDDIO = 1.89 V PCLK = 50 MHz Default Registers 2 VDDIO = 3.6 V PCLK = 50 MHz Default Registers 7 15 VDD = 1.89 V 370 775 VDDIO = 1.89 V 55 125 VDDIO = 3.6 V 65 135 5 mA µA Specification is ensured by characterization and is not tested in production. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 Serializer Electrical Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Deserializer (Rx) VDDn Supply Current (includes load current) IDDR IDDIOR IDDRZ Typ Max 96 VDDn = 1.89V CL = 8pF WORST CASE Pattern (See Figure 6) PCLK = 50 MHz SSCG[3:0] = ON Default Registers 60 VDDn = 1.89V CL = 8pF RANDOM Pattern PCLK = 50 MHz Default Registers 53 VDDIO = 1.89 V CL = 8pF WORST CASE Pattern (See Figure 6) PCLK = 50 MHz Default Registers Deserializer (Rx) VDDIO Supply Current (includes load VDDIO = 3.6 V current) CL = 8pF WORST CASE Pattern (See Figure 6) PDB = 0V; All other LVCMOS Inputs = 0V Deserializer (Rx) Supply Current Power-down Min IDDIORZ Units mA 21 32 mA PCLK = 50 MHz Default Registers 49 83 VDDn = 1.89 V 42 400 VDDIO = 1.89 V 8 40 VDDIO = 3.6 V 350 800 µA Serializer Electrical Characteristics Recommended Serializer Timing for PCLK (1) (2) (3) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter tTCP Transmit Clock Period tTCIH Transmit Clock Input High Time Conditions 10 MHz – 50 MHz Transmit Clock Input Low Time tCLKT PCLK Input Transition Time tOSC Internal oscillator clock source (2) (3) (4) Typ Max Units 20 T 100 ns 0.4T 0.5T 0.6T ns 0.4T 0.5T 0.6T ns 3 ns (4) tTCIL (1) Min 0.5 25 MHz The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Specification is ensured by characterization and is not tested in production. Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 9 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com Serializer Electrical Characteristics Serializer Switching Characteristics (1) (2) (3) Symbol Typ Max Units tLHT CML Low-to-High Transition Time RL = 100Ω (Figure 7) 150 330 ps tHLT CML High-to-Low Transition Time RL = 100Ω (Figure 7) 150 330 ps tDIS Data Input Setup to PCLK tDIH Data Input Hold from PCLK tPLD Serializer PLL Lock Time RL = 100Ω tSD Serializer Delay RT = 100Ω f = 10-50 MHz Reg Address 0x03h b[0] (TRFB = 1) (Figure 15) tJIND Serializer Output Deterministic Jitter Serializer output intrinsic deterministic jitter . Measured (cycle-cycle) with PRBS-7 test pattern PCLK = 50 MHz 0.13 UI tJINR Serializer Output Random Jitter Serializer output intrinsic random jitter (cycle-cycle). Alternating-1,0 pattern. PCLK = 50 MHz 0.04 UI tJINT Peak-to-peak Serializer Output Jitter Serializer output peak-to-peak jitter includes deterministic jitter, random jitter, and jitter transfer from serializer input. Measured (cycle-cycle) with PRBS-7 test pattern. PCLK = 50MHz 0.396 UI λSTXBW Serializer Jitter Transfer Function -3 dB Bandwidth PCLK = 50 MHz Default Registers 1.90 MHz δSTX Serializer Jitter Transfer Function (Peaking PCLK = 50 MHz Default Registers 0.944 dB δSTXf Serializer Jitter Transfer Function (Peaking Frequency) PCLK = 50 MHz Default Registers 500 kHz (1) (2) (3) Parameter Conditions Min Serializer Data Inputs (Figure 13) 2.0 ns 2.0 ns 6.386T + 5 1 2 ms 6.386T + 12 6.386T + 19.7 ns The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Serializer Electrical Characteristics Deserializer Switching Characteristics (1) (2) (3) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter tRCP Receiver Output Clock Period tPDC PCLK Duty Cycle tCLH LVCMOS Low-to-High Transition Time tCHL (1) (2) (3) (4) 10 LVCMOS High-to-Low Transition Time Conditions tRCP = tTCP VDDIO: 1.71 V to 1.89 V or 3.0 V to 3.6 V, CL = 8pF (lumped load) Default Registers (Figure 16 ) (4) Min Typ Max Units PCLK Pin/Freq. 20 T 100 ns PCLK 45 50 55 % 1.3 2.0 2.8 1.3 2.0 2.8 Deserializer PCLK Output ns The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Specification is ensured by design and is not tested in production. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 Serializer Electrical Characteristics Deserializer Switching Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter LVCMOS Low-to-High Transition Time tCLH tCHL LVCMOS High-to-Low Transition Time tROS ROUT Setup Data to PCLK tROH ROUT Hold Data to PCLK tDD Deserializer Delay tDDLT Deserializer Data Lock Time tRJIT Receiver Input Jitter Tolerance tDCJ Deserializer Clock Jitter tDPJ Deserializer Period Jitter tDCCJ Deserializer Cycle-to-Cycle Clock Jitter fDEV Spread Spectrum Clocking Deviation Frequency fMOD Spread Spectrum Clocking Modulation Frequency (5) (6) (7) (8) (9) (10) (11) Conditions Pin/Freq. VDDIO: 1.71 V to 1.89 V or 3.0 V to 3.6 V, CL = 8pF (lumped load) Default Registers (Figure 17) (4) Deserializer Data Outputs VDDIO: 1.71 V to 1.89 V or 3.0 V to 3.6 V, CL = 8pF (lumped load) Default Registers Deserializer Data Outputs Default Registers Register 0x03h b[0] (RRFB = 1) Figure 18 10 MHz - 50 MHz (5) Min Typ Max 1.6 2.4 3.3 1.6 2.4 3.3 0.38 0.5 0.38T 0.5T 4.571T + 8 4.571T + 12 Units ns 10 MHz - 50 MHz T 4.571T + 16 ns 10 ms (6) (7) 0.53 PCLK SSCG[3:0] = OFF 10 MHz 300 550 50 MHz 120 250 PCLK SSCG[3:0] = OFF 10 MHz 425 600 (10) (9) 50 MHz 320 480 PCLK SSCG[3:0] = OFF 10 MHz 320 500 (11) (9) 50 MHz 300 500 LVCMOS Output Bus SSC[3:0] = ON Figure 20 20 MHz - 50 MHz ±0.5% to ±2.0% % 20 MHz - 50 MHz 9 kHz to 66 kHz kHz 50 MHz (8) (9) UI ps ps ps tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK. UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency. tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI. tDCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE). Specification is ensured by characterization and is not tested in production. tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples. tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples. Bi-Directional Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant (Figure 5) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units 100 kHz RECOMMENDED INPUT TIMING REQUIREMENTS (1) fSCL SCL Clock Frequency fLOW SCL Low Period 4.7 µs fHIGH SCL High Period 4.0 µs tHD:STA Hold time for a start or a repeated start condition 4.0 µs tSU:STA Set Up time for a start or a repeated start condition 4.7 µs tHD:DAT Data Hold Time tSU:DAT Data Set Up Time 250 ns tSU:STO Set Up Time for STOP Condition, 4.0 µs tr SCL & SDA Rise Time 1000 tf SCL & SDA Fall Time 300 ns Cb Capacitive load for bus 400 pF (1) fSCL = 100 kHz >0 0 3.45 µs ns Recommended Input Timing Requirements are input specifications and not tested in production. Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 11 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com Bi-Directional Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant (Figure 5) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units SWITCHING CHARACTERISTICS () fSCL SCL Clock Frequency tLOW Serializer MODE = 0 – R/W Register 0x05 = 0x40'h 100 Deserializer MODE = 0 – READ Register 0x06 b[6:4] = 0x00'h 100 kHz Serializer MODE = 0 – R/W Register 0x05 = 0x40'h SCL Low Period Deserializer MODE = 0 – READ Register 0x06 b[6:4] = 0x00'h Serializer MODE = 0 – R/W Register 0x05 = 0x40'h 4.7 μs 4.0 μs tHIGH SCL High Period tHD:STA Hold time for a start or a repeated start condition Serializer MODE = 0 Register 0x05 = 0x40'h 4.0 μs tSU:STA Set Up time for a start or a repeated start condition Serializer MODE = 0 Register 0x05 = 0x40'h 4.7 μs tHD:DAT Data Hold Time tSU:DAT Data Set Up Time tSU:STO Set Up Time for STOP Condition tf SCL & SDA Fall Time tBUF Bus free time between a stop and start condition tTIMEOUT NACK Time out Deserializer MODE = 0 – READ Register 0x06 b[6:4] = 0x00'h 0 3.45 Serializer M/S = 0 μs 4.0 300 Serializer M/S = 0 μs μs 250 4.7 μs µs Serializer 1 Deserializer 25 ms SDA tLOW tf tHD;STA tr tf tBUF tr tSP SCL tSU;STA tHD;STA tHIGH tSU;STO tSU;DAT tHD;DAT START STOP REPEATED START START Figure 5. Serial Control Bus Timing Bi-Directional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant Symbol Parameter Conditions Min Typ Max Units VDDIO V 0.3 x VDDIO V VIH Input High Level SDA and SCL 0.7 x VDDIO VIL Input Low Level Voltage SDA and SCL GND VHY Input Hysteresis IOZ TRI-STATE Output Current PDB = 0V VOUT = 0V or VDD -20 ±1 +20 µA IIN Input Current SDA or SCL, Vin = VDDIO or GND -20 ±1 +20 µA CIN Input Pin Capacitance 12 Submit Documentation Feedback >50 <5 mV pF Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 Bi-Directional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant (continued) Symbol VOL Parameter Conditions Low Level Output Voltage Max Units SCL and SDA VDDIO = 3.0V IOL = 1.5 mA Min Typ 0.36 V SCL and SDA VDDIO = 1.71V IOL = 1 mA 0.36 V AC Timing Diagrams and Test Circuits Device Pin Name Signal Pattern T PCLK ODD DIN/ROUT EVEN DIN/ROUT Figure 6. “Worst Case” Test Pattern 80% Vdiff 80% 20% Vdiff = 0V 20% tLHT tHLT Vdiff = (DOUT+) - (DOUT-) Figure 7. Serializer CML Output Load and Transition Times DOUT+ 100 nF 50: ZDiff = 100: SCOPE BW 8 4.0 GHz 100: 50: DOUT- 100 nF 16 DIN/HS/VS PARALLEL-TO-SERIAL Figure 8. Serializer CML Output Load and Transition Times DOUT+ RL DOUT- PCLK Figure 9. Serializer VOD DC Diagram Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 13 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com DOUT- Single Ended V V OD V OD+ ODV DOUT+ | OS 0V Differential V OD+ 0V (DOUT+)-(DOUT-) V OD- Figure 10. Serializer VOD DC Diagram RIN+ VCM = 1.2V RIN+ VT H VID VTL VIN VID VIN RIN- RIN- GND Figure 11. Low-Voltage Differential VTH/VTL Definition Diagram 80% VDD 80% PCLK 20% 20% 0V tCLKT tCLKT Figure 12. Serializer Input Clock Transition Times tTCP PCLK VDDIO/2 tDIS VDDIO/2 VDDIO/2 tDIH VDDIO DIN/HS/VS VDDIO/2 Setup Hold VDDIO/2 0V Figure 13. Serializer Setup/Hold Times 14 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 PDB (3.3V I/O) 2.0V PCLK tPLD TRI-STATE DOUT± TRI-STATE Output Active DIN/HS/VS SYMBOL N SYMBOL N+1 SYMBOL N+2 | | Figure 14. Serializer Data Lock Time SYMBOL N+3 tSD SYMBOL N | | SYMBOL N-1 | | DOUT+- SYMBOL N-2 | | SYMBOL N-3 | | SYMBOL N-4 | | | PCLK Figure 15. Serializer Delay 2.0V PDB (3.3V I/O) | | t DDLT RIN ± LOCK | TRI - STATE Figure 16. Deserializer Data Lock Time 80% 80% Deserializer 8 pF lumped 20% 20% tCLH tCHL Figure 17. Deserializer LVCMOS Output Load and Transition Times SYMBOL N+4 | | | | SYMBOL N+3 | | RIN± SYMBOL N+2 | | SYMBOL N+1 | | SYMBOL N t DD SYMBOL N | | SYMBOL N - 1 | || SYMBOL N- 2 | | SYMBOL N - 3 | | ROUT/ VS/HS | | PCLK SYMBOL N+1 Figure 18. Deserializer Delay Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 15 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com tROS VDDIO VDDIO/2 ROUT/HS/VS VDDIO/2 0V tROH VDDIO PCLK VDDIO/2 0V Figure 19. Deserializer Output Setup/Hold Times Frequency FPCLK+ fdev fdev (max) FPCLK FPCLK- fdev (min) Time 1 / fmod Figure 20. Spread Spectrum Clock Output Profile 2 JITTER TRANSFER (dB) 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 1.0E+04 1.0E+05 1.0E+06 1.0E+07 MODULATION FREQUENCY (Hz) Figure 21. Typical Serializer Jitter Transfer Function Curve at 43 MHz 0.62 JITTER AMPLITUDE (UI) 0.61 0.60 0.59 0.58 0.57 0.56 0.55 0.54 0.53 0.52 1.0E+04 1.0E+05 1.0E+06 1.0E+07 JITTER FREQUENCY (Hz) Figure 22. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz 16 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 Table 1. DS92LX2121 Control Registers Addr (Hex) 0 Name Bits Field R/W Default 7:1 DEVICE ID RW 0x58 SER ID RW 0 0: Device ID is from CAD 1: Register I2C Device ID overrides CAD 0 Reserved. Standby mode control. Retains control register data. Supported only when M/S = 0 0: Enabled. Low-current Standby mode with wake-up capability. Suspends all clocks and functions. 1: Disabled. Standby and wake-up disabled I2C Device ID 0 7:3 1 7-bit address of Serializer; 0x58h (1011_000X) default 2 STANDBY RW 0 1 DIGITAL RESET0 RW 0 self clear 1: Digital Reset, retained register value 0 DIGITAL RESET1 RW 0 self clear 1: Digital Reset, retains all register values Reset 2 3 RESERVED Description Reserved 7:0 RESERVED 0x20'h Reserved. Reserved 7:6 RESERVED 11'b Reserved. VDDIO Control 5 VDDIO CONTOL RW 1 Auto VDDIO detect Allows manual setting of VDDIO by register. 0: Disable 1: Enable (auto detect mode) VDDIO Mode 4 VDDIO MODE RW 1 VDDIO voltage set Only used when VDDIOCONTROL = 0 0: 1.8V 1: 3.3V I2C Pass-Through 3 I2C PASSTHROUGH RW 1 I2C Pass-Through Mode 0: Disabled 1: Enabled Reserved 2 RESERVED 0 Reserved. PCLK_AUTO 1 PCLK_AUTO 1 Switch over to internal 25 MHz oscillator clock in the absence of PCLK 0: disable 1: enable 1 Pixel Clock Edge Select: 0: Parallel Interface Data is strobed on the Falling Clock Edge. 1: Parallel Interface Data is strobed on the Rising Clock Edge. 4 TRFB 0 Reserved 7:0 2 5 I C Bus Rate 6 DES ID TRFB RW RW RESERVED 0x80'h Reserved. 7:0 I C BUS RATE RW 0x40'h I2C SCL frequency is determined by the following: fSCL = 6.25 MHz / Register value (in decimal) 0x40'h = ~100 kHz SCL (default) Note: Register values <0x32'h are NOT supported. 7:1 DES DEV ID RW 0x60'h Deserializer Device ID = 0x60 (1100_000X) default 0 RESERVED 0 Slave Device ID. Sets remote slave I2C address. 0 Reserved. Reserved 7:0 RESERVED 0 Reserved. 8 RW Reserved. RESERVED Slave ID SLAVE DEV ID 0 0 7 7:1 2 9 Reserved 7:0 RESERVED 0x01'h Reserved. A Reserved 7:0 RESERVED 0 Reserved. B Reserved 7:0 RESERVED 0 Reserved. Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 17 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com Table 1. DS92LX2121 Control Registers (continued) Addr (Hex) C Name Bits Field R/W Reserved 7:3 RESERVED PCLK Detect 2 PCLK DETECT R Default Description 0 Reserved. 0 1: Valid PCLK detected 0: Valid PCLK not detected Reserved 1 RESERVED Cable Link Detect Status 0 LINK DETECT D Reserved 7:0 RESERVED 0x11'h Reserved. E Reserved 7:0 RESERVED 0x01'h Reserved. F Reserved 7:0 RESERVED 0x03'h Reserved. 10 Reserved 7:0 RESERVED 0x03'h Reserved. 11 Reserved 7:0 RESERVED 0x03'h Reserved. 12 Reserved 7:0 RESERVED 0x03'h Reserved. 7:0 GPCR[7] GPCR[6] GPCR[5] GPCR[4] GPCR[3] GPCR[2] GPCR[1] GPCR[0] 13 General Purpose Control Reg Reserved. R RW 0 0 0: Cable link not detected 1: Cable link detected 0: LOW 1: HIGH Table 2. DS92LX2122 Control Registers Addr (Hex) Name Bits 7:1 0 7:3 18 R/W Default DEVICE ID RW 0x60h DES ID RW 0 I2C Device ID 0 1 Field RESERVED 0x00'h Description 7-bit address of Deserializer; 0x60h (1100_000X) default 0: Device ID is from CAD 1: Register I2C Device ID overrides CAD Reserved 2 REM_WAKEUP RW 0 Remote Wake-up Select 1: Enable. Generate remote wakeup signal automatically wake-up the Serializer in Standby mode 0: Disable. Puts the Serializer in Standby mode 1 DIGITALRESET0 RW 0 self clear 1: Resets the device to default register values. Does not affect device I2C Bus or Device ID 0 DIGITALRESET1 RW 0 self clear 1: Digital Reset, retained register value Reset Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 Table 2. DS92LX2122 Control Registers (continued) Addr (Hex) Name Bits Field Reserved 7:6 RESERVED Auto Clock 5 AUTO_CLOCK OSS Select 4 OSS_SEL R/W Default 0 Reserved. RW 0 1: Output PCLK or internal 25 MHz Oscillator clock 0: Only PCLK when valid PCLK present RW 0 Output Sleep State Select 0: Outputs = TRI-STATE , when LOCK = L 1: Outputs = LOW, when LOCK = L 0 SSCG Select 0000: Normal Operation, SSCG OFF 0001: fmod (KHz) PCLK/2168, fdev ±0.50% 0010: fmod (KHz) PCLK/2168, fdev ±1.00% 0011: fmod (KHz) PCLK/2168, fdev ±1.50% 0100: fmod (KHz) PCLK/2168, fdev ±2.00% 0101: fmod (KHz) PCLK/1300, fdev ±0.50% 0110: fmod (KHz) PCLK/1300, fdev ±1.00% 0111: fmod (KHz) PCLK/1300, fdev ±1.50% 1000: fmod (KHz) PCLK/1300, fdev ±2.00% 1001: fmod (KHz) PCLK/868, fdev ±0.50% 1010: fmod (KHz) PCLK/868, fdev ±1.00% 1011: fmod (KHz) PCLK/868, fdev ±1.50% 1100: fmod (KHz) PCLK/868, fdev ±2.00% 1101: fmod (KHz) PCLK/650, fdev ±0.50% 1110: fmod (KHz) PCLK/650, fdev ±1.00% 1111: fmod (KHz) PCLK/650, fdev +/-1.50% 2 3 Description SSCG 3:0 SSCG Reserved 7:6 RESERVED VDDIO Control 5 VDDIO CONTROL RW 1 Auto voltage control 0: Disable 1: Enable (auto detect mode) VDDIO Mode 4 VDDIO MODE RW 0 VDDIO voltage set Only used when VDDIOCONTROL = 0 0: 1.8V 1: 3.3V I2C Pass-Through 3 I2C PASSTHROUGH RW 1 I2C Pass-Through Mode 0: Pass-Through Enabled 1: Pass-Through Disabled Auto ACK 2 AUTO ACK RW 0 0: Disable 1: Enable Reserved 1 RESERVED 0 Reserved. 1 Pixel Clock Edge Select 0: Parallel Interface Data is strobed on the Falling Clock Edge 1: Parallel Interface Data is strobed on the Rising Clock Edge. 0 EQ Gain 00'h = ~0.0 dB 01'h = ~4.5 dB 03'h = ~6.5 dB 07'h = ~7.5 dB 0F'h = ~8.0 dB 1F'h = ~11.0 dB 3F'h = ~12.5 dB FF'h = ~14.0 dB 0 Reserved. RRFB 0 RRFB 11'b RW 4 EQ Control 7:0 EQ RW 5 Reserved 7:0 RESERVED Reserved. Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 19 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com Table 2. DS92LX2122 Control Registers (continued) Addr (Hex) Name Bits Reserved 7 SCL Prescale 6 Remote NACK Remote NACK 7 8 ID[0] Index 9 ID[1] Index A ID[2] Index B ID[3] Index C ID[4] Index D ID[5] Index E ID[6] Index F ID[7] Index 10 20 SER ID ID[0] Match 11 ID[1] Match 12 ID[2] Match 13 ID[3] Match 14 ID[4] Match Field R/W Default Description RESERVED Reserved. 6:4 SCL_PRESCALE 0 Prescales the SCL clock line when reading data byte from a slave device (MODE = 0) 000 : ~100 kHz SCL (default) 001 : ~125 kHz SCL 101 : ~11 kHz SCL 110 : ~33 kHz SCL 111 : ~50 kHz SCL Other values are NOT supported. 3 REM_NACK_TIM ER 1 Remote NACK Timer Enable In slave mode (MODE = 1) if bit is set the I2C core will automatically timeout when no acknowledge condition was detected. 1: Enable 0: Disable RW RW 2:0 REM_NACK_TIME R RW 111'b Remote NACK Timeout 000: 2.0 ms 001: 5.2 ms 010: 8.6 ms 011: 11.8 ms 100: 14.4 ms 101: 18.4 ms 110: 21.6 ms 111: 25.0 ms 7:1 SER DEV ID RW 0x58h Serializer Device ID = 0x58 (1011_000X) default 0 RESERVED 7:1 ID[0] INDEX 0 RESERVED 7:1 ID[1] INDEX 0 RESERVED 7:1 ID[2] INDEX 0 RESERVED 7:1 ID[3] INDEX 0 RESERVED 7:1 ID[4] INDEX 0 RESERVED 7:1 ID[5] INDEX 0 RESERVED 7:1 ID[6] INDEX 0 RESERVED 7:1 ID[7] INDEX 0 RESERVED 7:1 ID[0] MATCH 0 RESERVED 7:1 ID[1] MATCH 0 RESERVED 7:1 ID[2] MATCH 0 RESERVED 7:1 ID[3] MATCH 0 RESERVED 7:1 ID[4] MATCH 0 RESERVED Submit Documentation Feedback RW RW RW RW RW RW RW RW RW RW RW RW RW 0 Reserved 0 Target slave Device ID slv_id1 [7:1] 0 Reserved. 0 Target slave Device ID slv_id1 [7:1] 0 Reserved. 0 Target slave Device ID slv_id2 [7:1] 0 Reserved. 0 Target slave Device ID slv_id3 [7:1] 0 Reserved. 0 Target slave Device ID slv_id4 [7:1] 0 Reserved. 0 Target slave Device ID slv_id5 [7:1] 0 Reserved. 0 Target slave Device ID slv_id6 [7:1] 0 Reserved. 0 Target slave Device ID slv_id7 [7:1] 0 Reserved. 0 Alias to match Device ID slv_id0 [7:1] 0 Reserved. 0 Alias to match Device ID slv_id1 [7:1] 0 Reserved. 0 Alias to match Device ID slv_id2 [7:1] 0 Reserved. 0 Alias to match Device ID slv_id3 [7:1] 0 Reserved. 0 Alias to match Device ID slv_id4 [7:1] 0 Reserved. Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 Table 2. DS92LX2122 Control Registers (continued) Addr (Hex) Name 15 ID[5] Match 16 ID[6] Match Bits Field 7:1 ID[5] MATCH 0 RESERVED 7:1 ID[6] MATCH 0 RESERVED 7:1 ID[7] MATCH 0 RESERVED R/W Default RW 0 Alias to match Device ID slv_id5 [7:1] 0 Reserved 0 Alias to match Device ID slv_id6 [7:1] 0 Reserved. 0 Alias to match Device ID slv_id [7:1] 0 Reserved. RW RW Description 17 ID[7] Match 18 Reserved 7:0 RESERVED 0 Reserved. 19 Reserved 7:0 RESERVED 0x01'h Reserved. 1A Reserved 7:0 RESERVED 0 Reserved. 1B Reserved 7:0 RESERVED 0 Reserved. Reserved 7:2 RESERVED 0 1C Signal Detect Status 1 R 0 0: Active signal not detected 1: Active signal detected LOCK Pin Status 0 R 0 0: CDR/PLL Unlocked 1: CDR/PLL Locked 1D Reserved 7:0 RESERVED 0x17'h Reserved. 1E Reserved 7:0 RESERVED 0x07'h Reserved. 1F Reserved 7:0 RESERVED 0x01'h Reserved. 20 Reserved 7:0 RESERVED 0x01'h Reserved. 21 Reserved 7:0 RESERVED 0x01'h Reserved. 22 Reserved 7:0 RESERVED 0x01'h Reserved. General Purpose Control Reg 7:0 GPCR[7] GPCR[6] GPCR[5] GPCR[4] GPCR[3] GPCR[2] GPCR[1] GPCR[0] Reserved 7:1 RESERVED BIST 0 25 BIST_ERR 7:0 BIST_ERR 26 Remote Wake Enable 7:6 23 24 27 BCC 0 0: LOW 1: HIGH 0 Reserved. RW 0 BIST Enable 0: Normal operation 1: Bist Enable R 0 Bist Error Counter REM_WAKEUP_E N RW 0 11: Enable remote wake up mode 00: Normal operation mode Other values are NOT supported. 5:0 RESERVED RW 0 Reserved 7:0 BCC RW 0 0xE0: Normal operation mode. Users MUST program this value. BIST_EN RW Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 21 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com FUNCTIONAL DESCRIPTION The DS92LX2121 / DS92LX2122 Channel Link III chipset is intended for camera applications. The Serializer/ Deserializer chipset operates from a 10 MHz to 50 MHz pixel clock frequency. The DS92LX2121 transforms a 21-bit wide parallel LVCMOS data bus along with a bi-directional back channel control bus into a single highspeed differential pair. The high speed serial bit stream contains an embedded clock and DC-balance information which enhances signal quality to support AC coupling. The DS92LX2122 receives the single serial data stream and converts it back into a 21-bit wide parallel data bus together with the back channel data bus. The control channel function of the DS92LX2121 / DS92LX2122 provides bi-directional communication between the image sensor and Electronic Control Unit (ECU). The integrated back channel transfers data bi-directionally over the same differential pair used for video data interface. This interface offers advantages over other chipsets by eliminating the need for additional wires for programming and control. The back channel bus is controlled via an I2C port. The bi-directional back channel offers asymmetrical communication and is not dependent on video blanking intervals. DISPLAY APPLICATION The DS92LX2121 / DS92LX2122 chipset is intended for interface between a host (graphics processor, FPGA, etc.) and a Display. It supports a 21 bit parallel video bus for 18-bit color depth (RGB666) display format. In a RGB666 configuration, 18 color bits (R [5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported across the serial link. The DS92LX2121 Serializer accepts a 21-bit parallel data bus along with a bi-directional control bus. The parallel data and bi-directional control channel information is converted into a single differential link. The integrated bi-directional control channel bus supports I2C compatible operation for controlling auxiliary data transport to and from host processor and display module. The DS92LX2122 Deserializer extracts the clock/control information from the incoming data stream and reconstructs the 21-bit data with control channel data. SERIAL FRAME FORMAT The DS92LX2121 / DS92LX2122 chipset will transmit and receive a pixel of data in the following format: I2C CLK0 CLK1 Bit 0 to Bit 20 Figure 23. Serial Bitstream for 28-bit Symbol The High Speed Forward Channel is a 28-bit symbol composed of 21 bits of data containing video data & control information transmitted from Serializer to Deserializer. CLK1 and CLK0 represent the embedded clock in the serial stream. CLK1 is always HIGH and CLK0 is always LOW. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized, balanced and scrambled. The bi-directional control channel data is transferred along with the high-speed forward data over the same serial link. This architecture provides a full duplex low speed forward channel across the serial link together with a high speed forward channel without the dependence of the video blanking phase. DESCRIPTION OF BI-DIRECTIONAL CONTROL BUS AND I2C MODES The I2C compatible interface allows programming of the DS92LX2121, DS92LX2122, or an external remote device (such as a display) through the bi-directional control channel. Register programming transactions to/from the DS92LX2121 / DS92LX2122 chipset are employed through the clock (SCL) and data (SDA) lines. These two signals have open drain I/Os and both lines must be pulled-up to VDDIO by external resistor. Figure 5 shows the timing relationships of the clock (SCL) and data (SDA) signals. Pull-up resistors or current sources are required on the SCL and SDA busses to pull them high when they are not being driven low. A logic zero is transmitted by driving the output low. A logic high is transmitted by releasing the output and allowing it to be pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus capacitance and operating speed. The DS92LX2121 / DS92LX2122 I2C bus data rate supports up to 100 kbps according to I2C specification. 22 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 Bus Activity: Master SDA Line Register Address Slave Address 7-bit Address S Stop Start To start any data transfer, the DS92LX2121 / DS92LX2122 must be configured in the proper I2C mode. Each device can function as an I2C slave proxy or master proxy depending on the mode determined by M/S pin. The Ser/Des interface acts as a virtual bridge between the host device and the remote device. When the M/S pin is set to HIGH, the device is treated as a slave proxy; and acts as a slave on behalf of the remote slave. When addressing a remote peripheral or Serializer/ Deserializer (not wired directly to the host device), the slave proxy will forward any byte transactions sent by the host controller to the target device. When M/S pin is set to LOW, the device will function as a master proxy device, and acts as a master on behalf of the I2C master controller. Note that the devices must have complementary settings for the M/S configuration. For example, if the Serializer M/S pin is set to HIGH then the Deserializer M/S pin must be set to LOW and vice-versa. Data P 0 A C K A C K A C K Bus Activity: Slave S Register Address Slave Address 7-bit Address S 0 A C K Bus Activity: Slave N A C K Slave Address 7-bit Address A C K Stop SDA Line Start Bus Activity: Master Start Figure 24. Write Byte P 1 A C K Data Figure 25. Read Byte SDA 1 2 6 MSB R/W Direction Bit Acknowledge from the Device 7-bit Slave Address SCL ACK LSB MSB 7 8 9 LSB N/ACK Data Byte *Acknowledge or Not-ACK 1 8 2 Repeated for the Lower Data Byte and Additional Data Transfers START 9 STOP Figure 26. Basic Operation SDA SCL S START condition, or START repeat condition P STOP condition Figure 27. START and STOP Conditions Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 23 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com 1.8V 10k VDDIO CAD 4.7k 4.7k RCAD HOST SCL SCL SDA SDA SER or DES To other Devices Figure 28. Serial Control Bus Connection SLAVE CLOCK STRETCHING In order to communicate and synchronize with remote devices on the I2C bus through the bi-directional control channel, slave clock stretching must be supported by the I2C master controller/host device. The chipset utilizes bus clock stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line low on the 9th clock of every I2C data transfer (before the ACK signal). The slave device will not control the clock and only stretches it until the remote peripheral has responded; which is typically in the order of 12 μs (typical). CAD PIN ADDRESS DECODER The CAD pin is used to decode and set the physical slave address of the Serializer/Deserializer (I2C only) to allow up to six devices on the bus using only a single pin. The pin sets one of six possible addresses for each Serializer/Deserializer device. The pin must be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor and a pull down resistor (RID) of the recommended value to set the physical device address. The recommended maximum resistor tolerance is 0.1% worst case (0.2% total tolerance). Table 3. DS92LX2121 RID Resistor Values CAD Values - DS92LX2121 Ser Resistor RID kΩ Address 7'b Address 8'b 0 appended (WRITE) 0 GND 7b' 101 1000 (h'58) 8b' 1011 0000 (h'B0) 2.0k 7b' 101 1001 (h'59) 8b' 1011 0010 (h'B2) 4.7k 7b' 101 1010 (h'5A) 8b' 1011 0100 (h'B4) 8.2k 7b' 101 1011 (h'5B) 8b' 1011 0110 (h'B6) 12.1k 7b' 101 1100 (h'5C) 8b' 1011 1000 (h'B8) 39.0k 7b' 101 1110 (h'5E) 8b' 1011 1100 (h'BC) Table 4. DS92LX2122 RID Resistor Values CAD Values - DS92LX2122 Des 24 Resistor RID kΩ Address 7'b Address 8'b 0 appended (WRITE) 0 GND 7b' 110 0000 (h'60) 8b' 1100 0000 (h'C0) 2.0k 7b' 110 0001 (h'61) 8b' 1100 0010 (h'C2) 4.7k 7b' 110 0010 (h'62) 8b' 1100 0100 (h'C4) 8b' 1101 0110 (h'C6) 8.2k 7b' 110 0011 (h'63) 12.1k 7b' 110 0100 (h'64) 8b' 1101 1000 (h'C8) 39.0k 7b' 110 0110 (h'66) 8b' 1100 1100 (h'CC) Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 CAMERA MODE OPERATION In Camera mode, I2C transactions originate from the Deserializer from the host controller. The I2C slave core in the Deserializer will detect if a transaction is intended for the Serializer or a slave at the Serializer. Commands are sent over the bi-directional control channel to initiate the transactions. The Serializer will receive the command and generate an I2C transaction on its local I2C bus. At the same time, the Serializer will capture the response on the I2C bus and return the response as a command on the forward channel link. The Deserializer parses the response and passes the appropriate response to the Deserializer I2C bus. To configure the devices for camera mode operation, set the Serializer M/S pin to LOW and the Deserializer M/S pin to HIGH. Before initiating any I2C commands, the Deserializer needs to be programmed with the target slave device addresses and Serializer device address. SER_DEV_ID Register 0x07h sets the Serializer device address and SLAVE_x_MATCH/SLAVE_x_INDEX registers 0x08h~0x17h set the remote target slave addresses. The slave address match registers must also be set. In slave mode the address register is compared with the address byte sent by the I2C master. If the addresses are equal to any of registers values, the I2C slave will acknowledge the transaction to the I2C master allowing reads or writes to target device. DISPLAY MODE OPERATION In Display mode, I2C transactions originate from the controller attached to the Serializer. The I2C slave core in the Serializer will detect if a transaction targets (local) registers within the Serializer or the (remote) registers within the Deserializer or a remote slave connected to the I2C master interface of the Deserializer. Commands are sent over the forward channel link to initiate the transactions. The Deserializer will receive the command and generate an I2C transaction on its local I2C bus. At the same time, the Deserializer will capture the response on the I2C bus and return the response as a command on the bi-directional control channel. The Serializer parses the response and passes the appropriate response to the Serializer I2C bus. The physical device ID of the I2C slave in the Serializer is determined by the analog voltage on the CAD pin input. It can be reprogrammed by using the SER_DEV_ID register and setting the bit . The device ID of the logical I2C slave in the Deserializer is determined by programming the DES ID in the Serializer. The state of the CAD pin input on the Deserializer is used to set the device ID. The I2C transactions between Ser/ Des will be bridged between the host to the remote slave. To configure the devices for display mode operation, set the Serializer M/S pin to HIGH and the Deserializer M/S pin to LOW. Before initiating any I2C commands, the Serializer needs to be programmed with the target slave device address and Serializer device address. DES_DEV_ID Register 0x06h sets the Deserializer device address and SLAVE_DEV_ID register 0x7h sets the remote target slave address. If the I2C slave address matches any of registers values, the I2C slave will acknowledge the transaction allowing read or write to target device. Note: In Display mode operation, registers 0x08h~0x17h on Deserializer must be reset to 0x00. PROGRAMMABLE CONTROLLER An integrated I2C slave controller is embedded in each of the DS92LX2121 Serializer and DS92LX2122 Deserializer. It must be used to access and program the extra features embedded within the configuration registers. Refer to Table 1 and Table 2 for details of control registers. I2C PASS THROUGH I2C pass-through provides an alternative means to independently address slave devices. The mode enables or disables I2C bidirectional control channel communication to the remote I2C bus. This option is used to determine whether or not an I2C instruction is to be transferred over to the remote I2C device. When enabled, the I2C bus traffic will continue to pass through and will be received by I2C devices downstream. If disabled, I2C commands will be excluded to the remote I2C device. The pass through function also provides access and communication to only specific devices on the remote bus. The feature is effective for both Camera mode and Display mode. Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 25 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com SYNCHRONIZING MULTIPLE LINKS For applications requiring synchronization across multiple links, it is recommended to utilize the General Purpose Input/ Output (GPI/GPO) pins to transmit control signals to synchronize slave peripherals together. To synchronize the peripherals properly, the system controller needs to provide a sync signal output. Note this form of synchronization timing relationship has a non-deterministic latency. After the control data is reconstructed from the bi-directional control channel, there will be a time variation of the GPI/GPO signals arriving at the different target devices (between the parallel links). The maximum latency delta (t1) of the GPI/GPO data transmitted across multiple links is 25 μs. Note: The user must verify that the timing variations between the different links are within their system and timing specifications. The maximum time (t1) between the rising edge of GPI/GPO (i.e. sync signal) arriving at Camera A and Camera B is 25 μs. DES A GPIO[n] Input SER B GPIO[n] Output | SER A GPIO[n] Output | DES B GPIO[n] Input t1 Figure 29. GPIO Delta Latency GENERAL PURPOSE I/O (GPIO) The DS92LX2121 / DS92LX2122 has up to 4 GPO and 4 GPI on the Serializer and Deserializer respectively. The GPI/GPO maximum switching rate is up to 66 kHz for communication between Deserializer GPI to Serializer GPO. AT-SPEED BIST (BISTEN, PASS) An optional AT SPEED Built in Self Test (BIST) feature supports at speed testing of the high-speed serial and the back-channel link. Control pins allow the system to initiate the test and set the duration. A HIGH on PASS pin indicates that all payloads received during the test were error free during the BIST duration test. A LOW on this pin at the conclusion of this test indicates that one or more payloads were detected with errors. The BIST duration is defined by the width of BISTEN. BIST starts when BISTEN goes HIGH. BIST ends when BISTEN goes LOW. PASS flag will go HIGH when no errors detected after BIST Duration completes. Any errors detected after the BIST Duration are not included in PASS logic. The following diagram shows how to perform system AT SPEED BIST: 26 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 Serializer MODE = 0 and Deserializer MODE = 1 Apply power for Serializer and Deserializer Normal Step 1: Enable AT SPEED BIST by placing the Deserializer in BIST by mode setting BISTEN = H BIST Wait Step 4: Place System in Normal Operating Mode BISTEN = L Step 2: Deserializer will setup Serializer and enable BIST mode through Bidirectional control channel communication and then reacquire forward channel clock BIST Start Step 3: Stop AT SPEED BIST by turning off BIST mode with BISTEN = L at the Deserializer. BIST Stop Figure 30. AT-SPEED BIST System Flow Diagram Step 1: Place the Deserializer in BIST Mode. Serializer and Deserializer power supply must be supplied. Set the Serializer M/S pin to LOW and the Deserializer M/S pin to HIGH. Enable the AT SPEED BIST mode on the Deserializer by setting the BISTEN pin High. The DS92LX2122 GPIO[1:0] pins are used to select the PCLK frequency of the on-chip oscillator for the BIST test on high speed data path. Table 5. Oscillator Frequency Select Freq Control Oscillator Range min (MHz) typ (MHz) 00 External PCLK 10 01 Internal 10 Internal 25 11 Internal 12.5 max (MHz) 50 50 The Deserializer GPIO[1:0] set to 00 will bypass the on-chip oscillator and an external oscillator to Serializer PCLK input is required. This allows the user to operate BIST under different frequencies other than the predefined ranges. Step 2: Enable AT SPEED BIST by placing the Serializer into BIST mode. Deserializer will communicate through the back-channel to configure Serializer into BIST mode. Once the BIST mode is set, the Serializer will initiate BIST transmission to the Deserializer. Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 27 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com Wait 10 ms for Deserializer to acquire lock and then monitor the LOCK pin transition from LOW to HIGH. At this point, AT SPEED BIST is operational and the BIST process has begun. The Serializer will start transfer of an internally generated PRBS data pattern through the high speed serial link. This pattern traverses across the interconnecting link to the Deserializer. Check the status of the PASS pin; a HIGH indicates a pass, a LOW indicates a fail. A fail will stay LOW for ½ a clock cycle. If two or more bits fail in a row the PASS pin will toggle ½ clock cycle HIGH and ½ clock cycle low. The user can use the PASS pin to count the number of fails on the high speed link. In addition, there is a defined SER and DES register that will keep track of the accumulated error count. The Serializer DS92LX2121 GPIO[0] pin will be assigned as a PASS flag error indicator for the backchannel link. Recovered Pixel Clock Case 1: No bit errors Start Pixel BISTEN Recovered Pixel Data PASS Previous ³&5&´6WDWH ³&5&´6WDWH Case 2: Bit error(s) Recovered Pixel Data PASS B B B B Previous ³&5&´6WDWH ³&5&´6WDWH E E E E Case 3: Bit error(s) AFTER BIST Duration Recovered Pixel Data PASS B Previous ³&5&´6WDWH B = Bad Pixel PE = Payload Error ³&5&´6WDWH BIST Duration (when BISTEN=H) CRC Status (when BISTEN=L) Figure 31. BIST Timing Diagram Step 3: Stop at SPEED BIST by turning off BIST mode in the Deserializer to determine Pass/Fail. To end BIST, the system must pull BISTEN pin of the Deserializer LOW. The BIST duration is fully defined by the BISTEN width and thus the Bit Error Rate is determined by how long the system holds BISTEN HIGH. fpixel (MHz) BIST Duration (s) x Total Pixels Transmitted = Total Bits Transmitted = BIST Duration (s) x Pixel 1 Pixel period (ns) x Total Bits Bit (Pixel) Error Rate -1 = [Total Bits Transmitted] (for passing BIST) = [Total Bits Transmitted x Bits/Pixel] -1 Figure 32. BIST BER Calculation For instance, if BISTEN is held HIGH for 1 second and the PCLK is running at 43 MHz with 16 bpp, then the Bit Error Rate is no better than 1.46E-9. Step 4: Place system in Normal Operating Mode by disabling BIST at the Serializer. Once Step 3 is complete, AT SPEED BIST is over and the Deserializer is out of BIST mode. To fully return to Normal mode, apply Normal input data into the Serializer. 28 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 Any PASS result will remain unless it is changed by a new BIST session or cleared by asserting and releasing PDB. The default state of PASS after a PDB toggle is HIGH. It is important to note that AT SPEED BIST will only determine if there is an issue on the link that is not related to the clock and data recovery of the link (whose status is flagged with LOCK pin). LVCMOS VDDIO OPTION 1.8V or 3.3V SER Inputs and DES Outputs are user configurable to provide compatibility with 1.8V and 3.3V system interfaces. REMOTE WAKE UP (Camera Mode) After initial power up, the SER is in a low-power Standby mode. The DES (controlled by the host ) 'Remote Wakeup' register allows the DES side to generate a signal across the link to remotely wakeup the SER. Once the SER detects the wakeup signal, the SER switches from Standby mode to active mode. In active mode, the SER locks onto PCLK input (if present), otherwise the on-chip oscillator is used as the input clock source. Note the host controller should monitor the DES LOCK pin and confirm LOCK = H before performing any I2C communication across the link. For Remote Wakeup to function properly: • The chipset needs to be configured in Camera mode: Serializer M/S = 0 and Deserializer M/S = 1 • The SER expects remote wake up by default at power on. • Configure the control channel driver of the DES to be in remote wake up mode by setting DES register 0x26 to 0xC0. • Perform remote wake up on SER by setting DES register 0x01 b[2] to 1. • Return the control channel driver of the DES to the normal operation mode by setting DES register 0x26 to 0. The SER can also be put into standby mode by programming the DES remote wake up control register 0x01 b[2] REM_WAKEUP to 0. POWERDOWN The SER has a PDB input pin to ENABLE or Powerdown the device. The modes can be controlled by the host and is used to disable the Link to save power when the remote device is not operational. An auto mode is also available. In this mode, the PDB pin is tied High and the SER switches over to an internal oscillator when the PCLK stops or not present. When a PCLK starts again, the SER will then lock to the valid input PCLK and transmits the data to the DES. In powerdown mode, the high-speed driver outputs are static (HIGH). The DES has a PDB input pin to ENABLE or Powerdown the device. This pin can be controlled by the system and is used to disable the DES to save power. An auto mode is also available. In this mode, the PDB pin is tied High and the DES will enter powerdown when the serial stream stops. When the serial stream starts up again, the DES will lock to the input stream and assert the LOCK pin and output valid data. In powerdown mode, the Data and PCLK outputs are set by the OSS_SEL control register. POWER UP REQUIREMENTS AND PDB PIN The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO, it is recommended to use a 10 kΩ pull-up and a 22 uF cap to GND to delay the PDB input signal. SIGNAL QUALITY ENHANCERS Des - Receiver Input Equalization (EQ) The receiver inputs provided input equalization filter in order to compensate for loss from the media. The level of equalization is controlled via register setting. Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 29 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com EMI REDUCTION Des - Receiver Staggered Output The Receiver staggered outputs allows for outputs to switch in a random distribution of transitions within a defined window. Outputs transitions are distributed randomly. This minimizes the number of outputs switching simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall EMI. Des Spread Spectrum Clocking Compatibilty The DS92LX2122 parallel data and clock outputs have programmable SSCG ranges from 70 kHz and +-2% (4% total) from 20 MHz to 50 MHz. The modulation rate and modulation frequency variation of output spread is controlled through the SSC control registers. PIXEL CLOCK EDGE SELECT (TRFB/RRFB) The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0, data is strobed on the Falling edge of the PCLK. PCLK DIN/ ROUT TRFB/RRFB: 0 TRFB/RRFB: 1 Figure 33. Programmable PCLK Strobe Select Applications Information AC COUPLING The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme. External AC coupling capacitors must be placed in series in the Channel Link III signal path as illustrated in Figure 34. DOUT+ RIN+ DOUT- RIN- D R Figure 34. AC-Coupled Application For high-speed Channel Link III transmissions, the smallest available package should be used for the AC coupling capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 0.1 μF AC coupling capacitors to the line. 30 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 TYPICAL APPLICATION CONNECTION Figure 35 shows a typical connection of the DS92LX2121 Serializer. DS92LX2121 (SER) VDDIO VDDIO C12 FB1 C8 1.8V VDDT C4 FB2 C10 C5 FB3 C11 C6 FB4 C7 FB5 C3 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 DIN10 DIN11 DIN12 DIN13 LVCMOS Parallel Bus DIN14 DIN15 DIN16 DIN17 DIN18 DIN19 DIN20 MODE PDB GPO Control Interface GPO[0] GPO[1] GPO[2] GPO[3] VDDCML VDDD C1 I2C Bus Interface C2 1.8V 10 k: ID[X] RID NOTE: C1 - C2 = 0.1 PF (50 WV) C3 - C9 = 0.1 PF C10 - C13 = 4.7 PF C14 - C15 = >100 pF RPU = 1 k: to 4.7 k: RID (see ID[x] Resistor Value Table) FB1 - FB7: Impedance = 1 k: (@ 100 MHz) low DC resistance (<1:) RPU SCL FB6 SDA FB7 C14 Serial Channel Link III Interface DOUT+ DOUT- VDDIO RPU C13 VDDPLL PCLK LVCMOS Control Interface C9 RES DAP (GND) C15 Optional The "Optional" components shown are provisions to provide higher system noise immunity and will therefore result in higher performance. Optional Figure 35. DS92LX2121 Typical Connection Diagram Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 31 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com Figure 36 shows a typical connection of the DS92LX2122 Deserializer. DS92LX2122 (DES) 1.8V VDDD C13 C11 FB1 C3 FB2 C4 FB3 C5 FB5 C16 C7 VDDCML C1 Serial Channel Link III Interface RIN+ RINC2 TP_A RES_PIN38 RES_PIN39 TP_B LVCMOS Control Interface MODE PDB VDDIO RPU I2C Bus Interface C12 C14 VDDIO2 VDDIO3 C10 VDDPLL C6 FB6 C9 VDDSSCG C15 VDDIO1 C8 VDDR FB4 VDDIO ROUT0 ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 ROUT6 ROUT7 ROUT8 ROUT9 ROUT10 ROUT11 ROUT12 ROUT13 LVCMOS Parallel Bus ROUT14 ROUT15 ROUT16 ROUT17 ROUT18 ROUT19 ROUT20 PCLK GPI[0] GPI[1] GPI[2] GPI[3] RPU GPI Control Interface SCL FB7 SDA FB8 C17 LOCK PASS 1.8V C18 Optional Optional NOTE: C1 - C2 = 0.1 PF (50 WV) C3 - C12 = 0.1 PF C13 - C16 = 4.7 PF C17 - C18 = >100 pF RPU = 1 k: to 4.7 k: RID (see ID[x] Resistor Value Table) FB1 - FB8: Impedance = 1 k: (@ 100 MHz) low DC resistance (<1:) 10 k: ID[X] RES_PIN46 DAP (GND) RID The "Optional" components shown are provisions to provide higher system noise immunity and will therefore result in higher performance. Figure 36. DS92LX2122 Typical Connection Diagram 32 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 TRANSMISSION MEDIA The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment. The interconnect for Channel Link III interface should present a differential impedance of 100 Ohms. Use of cables and connectors that have matched differential impedance will minimize impedance discontinuities. Shielded or un-shielded cables may be used depending upon the noise environment and application requirements. The chipset's optimum cable drive performance is achieved at 43 MHz at 10 meters length. The maximum signaling rate increases as the cable length decreases. Therefore, the chipset supports 50 MHz at shorter distances. Other cable parameters that may limit the cable's performance boundaries are: cable attenuation, near-end crosstalk and pair-to-pair skew. For obtaining optimal performance the system should use: • Shielded Twisted Pair (STP) cable • 100Ω ± 10% differential impedance and 24 AWG (or lower AWG) cable • Low intra-pair skew (less than 0.1UI), impedance matched • Terminate unused conductors • Optimum settings for deserializer Register 0x27 (See Table 2) PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used. Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor will increase the inductance of the path. A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential lines of 100 Ohms are typically recommended for differential interconnect. The closely coupled lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less. Information on the LLP style package is provided in the AN-1187 Leadless Leadframe Package (LLP) Application Report (literature number SNOA401). Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 33 DS92LX2121, DS92LX2122 SNLS330J – MAY 2010 – REVISED JANUARY 2014 www.ti.com INTERCONNECT GUIDELINES For full details, see the Channel-Link PCB and Interconnect Design-In Guidelines (literature number SNLA008) and the Transmission Line RAPIDESIGNER Operation and Applications Guide (literature number SNLA035). • Use 100Ω coupled differential pairs • Use the S/2S/3S rule in spacings – S = space between the pair – 2S = space between pairs – 3S = space to LVCMOS signal • Minimize the number of Vias • Use differential connectors when operating above 500Mbps line speed • Maintain balance of the traces • Minimize skew within the pair Additional general guidance can be found in the LVDS Owner’s Manual (literature number SNLA187), which is available in PDF format from the TI LVDS & CML Solutions web site. 34 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 REVISION HISTORY Changes from Revision I (April 2013) to Revision J Page • Changed "tri-state" and "low" OSS values to reflect correct bit definition .......................................................................... 19 • Added user-recommended value for deserializer echo cancellation in general-purpose cables ....................................... 21 • Added tolerance for transmission cable impedance ........................................................................................................... 33 • Added tolerance range for transmission cable skew .......................................................................................................... 33 • Added reference to optimum settings information in deserialzier Reg 0x27 ...................................................................... 33 Changes from Revision H (April 2013) to Revision I • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 34 Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX2121 DS92LX2122 Submit Documentation Feedback 35 PACKAGE OPTION ADDENDUM www.ti.com 22-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DS92LX2121SQ/NOPB ACTIVE WQFN RTA 40 1000 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR -40 to 85 LX2121 DS92LX2121SQE/NOPB ACTIVE WQFN RTA 40 250 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR -40 to 85 LX2121 DS92LX2121SQX/NOPB ACTIVE WQFN RTA 40 2500 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR -40 to 85 LX2121 DS92LX2122SQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LX2122 DS92LX2122SQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LX2122 DS92LX2122SQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LX2122 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 22-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS92LX2121SQ/NOPB WQFN RTA 40 DS92LX2121SQE/NOPB WQFN RTA DS92LX2121SQX/NOPB WQFN RTA DS92LX2122SQ/NOPB WQFN DS92LX2122SQE/NOPB DS92LX2122SQX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 40 250 178.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LX2121SQ/NOPB WQFN RTA 40 1000 367.0 367.0 38.0 DS92LX2121SQE/NOPB WQFN RTA 40 250 213.0 191.0 55.0 DS92LX2121SQX/NOPB WQFN RTA 40 2500 367.0 367.0 38.0 DS92LX2122SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS92LX2122SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS92LX2122SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA RTA0040A SQA40A (Rev B) www.ti.com MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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