ISSI IS93C66A-2ZLI 2k-bit/4k-bit serial electrically erasable prom Datasheet

IS93C56A
ISSI
IS93C66A
2K-BIT/4K-BIT SERIAL ELECTRICALLY
ERASABLE PROM
®
MAY 2006
FEATURES
DESCRIPTION
• Industry-standard Microwire Interface
— Non-volatile data storage
— Wide voltage operation:
Vcc = 1.8V to 5.5V
— Auto increment for efficient data dump
• User Configured Memory Organization
— By 16-bit or by 8-bit
• Hardware and software write protection
— Defaults to write-disabled state at power-up
— Software instructions for write-enable/disable
• Enhanced low voltage CMOS E2PROM
technology
• Versatile, easy-to-use Interface
— Self-timed programming cycle
— Automatic erase-before-write
— Programming status indicator
— Word and chip erasable
— Chip select enables power savings
• Durable and reliable
— 40-year data retention after 1M write cycles
— 1 million write cycles
— Unlimited read cycles
— Schmitt-trigger inputs
• Industrial and Automotive Temperature Grade
• Lead-free available
The IS93C56A/66A are 2kb/4kb non-volatile,
ISSI ® serial EEPROMs. They are fabricated using
an enhanced CMOS design and process. The
IS93C56A/66A contain power-efficient read/write
memory, and organization of either 256/512 bytes
of 8 bits or 128/256 words of 16 bits. When the
ORG pin is connected to Vcc or left unconnected,
x16 is selected; when it is connected to ground,
x8 is selected. The IS93C56A/66A are fully
backward compatible with IS93C56/66.
An instruction set defines the operation of the
devices, including read, write, and mode-enable
functions. To protect against inadvertent data
modification, all erase and write instructions are
accepted only while the devices are write-enabled.
A selected x8 byte or x16 word can be modified
with a single WRITE or ERASE instruction.
Additionally, the two instructions WRITE ALL or
ERASE ALL can program an entire array. Once a
device begins its self-timed program procedure,
the data out pin (Dout) can indicate the READY/
BUSY status by raising chip select (CS). The selftimed write cycle includes an automatic erasebefore-write capability. The devices can output
any number of consecutive bytes/words using a
single READ instruction.
FUNCTIONAL BLOCK DIAGRAM
DATA
REGISTER
INSTRUCTION
REGISTER
DIN
CS
SK
DUMMY
BIT
DOUT
R/W
AMPS
INSTRUCTION
DECODE,
CONTROL,
AND
CLOCK
GENERATION
ADDRESS
REGISTER
ADDRESS
DECODER
EEPROM
ARRAY
256/512x8
128/256x16
WRITE
ENABLE
HIGH VOLTAGE
GENERATOR
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/02/06
1
IS93C56A
ISSI
IS93C66A
®
PIN CONFIGURATIONS
8-Pin JEDEC SOIC “GR”
8-Pin DIP, 8-Pin TSSOP
CS
1
8
VCC
CS
1
8
VCC
SK
2
7
NC
SK
2
7
NC
DIN
3
6
ORG
DIN
3
6
ORG
DOUT
4
5
GND
DOUT
4
5
GND
PIN DESCRIPTIONS
CS
Chip Select
SK
Serial Data Clock
DIN
Serial Data Input
DOUT
Serial Data Output
ORG
Organization Select
NC
Not Connected
Vcc
Power
GND
Ground
instruction begins with a start bit of the logical “1” or
HIGH. Following this are the opcode (2 bits),
address field (8 or 9 bits), and data, if appropriate. The
clock signal may be held stable at any moment to
suspend the device at its last state, allowing clockspeed flexibility. Upon completion of bus
communication, CS would be pulled LOW. The device
then would enter Standby mode if no internal
programming is underway.
Read (READ)
Applications
The IS93C56A/66A are very popular in many
applications which require low-power, low-density
storage. Applications using these devices include
industrial controls, networking, and numerous other
consumer electronics.
Endurance and Data Retention
The IS93C56A/66A are designed for applications requiring
up to 1M programming cycles (WRITE, WRALL, ERASE
and ERAL). They provide 40 years of secure data retention
without power after the execution of 1M programming cycles.
Device Operations
The IS93C56A/66A are controlled by a set of
instructions which are clocked-in serially on the Din pin.
Before each low-to-high transition of the clock (SK), the
CS pin must have already been raised to HIGH, and the
Din value must be stable at either LOW or HIGH. Each
2
The READ instruction is the only instruction that outputs
serial data on the DOUT pin. After the read instruction and
address have been decoded, data is transferred from the
selected memory register into a serial shift register. (Please
note that one logical “0” bit precedes the actual 8 or 16-bit
output data string.) The output on DOUT changes during the
low-to-high transitions of SK (see Figure 3).
Low Voltage Read
The IS93C56A/66A are designed to ensure that data read
operations are reliable in low voltage environments. They
provide accurate operation with Vcc as low as 1.8V.
Auto Increment Read Operations
In the interest of memory transfer operation applications,
the IS93C56A/66A are designed to output a continuous
stream of memory content in response to a single read
operation instruction. To utilize this function, the system
asserts a read instruction specifying a start location address. Once the 8 or 16 bits of the addressed register have
been clocked out, the data in consecutively higher address
locations is output. The address will wrap around continuously with CS HIGH until the chip select (CS) control pin is
brought LOW. This allows for single instruction data dumps
to be executed with a minimum of firmware overhead.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/02/06
IS93C56A
ISSI
IS93C66A
®
Write Enable (WEN)
Write All (WRALL)
The write enable (WEN) instruction must be executed
before any device programming (WRITE, WRALL,
ERASE, and ERAL) can be done. When Vcc is applied,
this device powers up in the write disabled state. The
device then remains in a write disabled state until a WEN
instruction is executed. Thereafter, the device remains
enabled until a WDS instruction is executed or until Vcc
is removed. (See Figure 4.) (Note: Chip select must
remain LOW until Vcc reaches its operational value.)
The write all (WRALL) instruction programs all registers
with the data pattern specified in the instruction. As with the
WRITE instruction, the falling edge of CS must occur to
initiate the self-timed programming cycle. If CS is then
brought HIGH after a minimum wait of 200 ns (tCS), the DOUT
pin indicates the READY/BUSY status of the chip (see
Figure 6). Vcc is required to be above 4.5V for WRALL to
function properly.
Write (WRITE)
The WRITE instruction includes 8 or 16 bits of data to be
written into the specified register. After the last data bit
has been applied to DIN, and before the next rising edge
of SK, CS must be brought LOW. If the device is writeenabled, then the falling edge of CS initiates the selftimed programming cycle (see WEN).
If CS is brought HIGH, after a minimum wait of 200 ns (5V
operation) after the falling edge of CS (tCS) DOUT will
indicate the READY/BUSY status of the chip. Logical “0”
means programming is still in progress; logical “1” means
the selected register has been written, and the part is
ready for another instruction (see Figure 5). The READY/
BUSY status will not be available if: a) The CS input goes
HIGH after the end of the self-timed programming cycle,
tWP; or b) Simultaneously CS is HIGH, Din is HIGH, and
SK goes HIGH, which clears the status flag.
Write Disable (WDS)
The write disable (WDS) instruction disables all programming
capabilities. This protects the entire device against accidental modification of data until a WEN instruction is
executed. (When Vcc is applied, this part powers up in the
write disabled state.) To protect data, a WDS instruction
should be executed upon completion of each programming
operation.
Erase Register (ERASE)
After the erase instruction is entered, CS must be brought
LOW. The falling edge of CS initiates the self-timed internal
programming cycle. Bringing CS HIGH after a minimum of
tCS, will cause DOUT to indicate the READ/BUSY status of the
chip: a logical “0” indicates programming is still in progress;
a logical “1” indicates the erase cycle is complete and the
part is ready for another instruction (see Figure 8).
Erase All (ERAL)
Full chip erase is provided for ease of programming. Erasing
the entire chip involves setting all bits in the entire memory
array to a logical “1” (see Figure 9). Vcc is required to be
above 4.5V for ERALL to function properly.
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Rev. A
05/02/06
3
IS93C56A
ISSI
IS93C66A
®
INSTRUCTION SET - IS93C56A (2kb)
Instruction (2)
8-bit Organization
(ORG = GND)
Address (1) Input Data
Start Bit OP Code
16-bit Organization
(ORG = Vcc)
Address (1)
Input Data
READ
1
10
x(A7-A0)
—
x(A6-A0)
—
WEN (Write Enable)
1
00
11xxxxxxx
—
11xxxxxx
—
WRITE
1
01
x(A7-A0)
(D7-D0)
x(A6-A0)
(D15-D0)
WRALL (Write All Registers)
1
00
01xxxxxxx
(D7-D0)
01xxxxxx
(D15-D0)
WDS (Write Disable)
1
00
00xxxxxxx
—
00xxxxxx
—
ERASE
1
11
x(A7-A0)
—
x(A6-A0)
—
ERAL (Erase All Registers)
1
00
10xxxxxxx
—
10xxxxxx
—
Notes:
1. x = Don't care bit.
2. If the number of bits clocked-in does not match the number corresponding to a selected command, all extra trailing bits are ignored,
and WRITE, WRALL, ERASE, and ERAL are also ignored, but READ, WEN, WDS are accepted.
INSTRUCTION SET - IS93C66A (4kb)
Instruction (2)
Start Bit OP Code
8-bit Organization
(ORG = GND)
Address (1) Input Data
16-bit Organization
(ORG = Vcc)
Address (1)
Input Data
READ
1
10
(A8-A0)
—
(A7-A0)
—
WEN (Write Enable)
1
00
11xxxxxxx
—
11xxxxxx
—
WRITE
1
01
(A8-A0)
(D7-D0)
(A7-A0)
(D15-D0)
WRALL (Write All Registers)
1
00
01xxxxxxx
(D7-D0)
01xxxxxx
(D15-D0)
WDS (Write Disable)
1
00
00xxxxxxx
—
00xxxxxx
—
ERASE
1
11
(A8-A0)
—
(A7-A0)
—
ERAL (Erase All Registers)
1
00
10xxxxxxx
—
10xxxxxx
—
Notes:
1. x = Don't care bit.
2. If the number of bits clocked-in does not match the number corresponding to a selected command, all extra trailing bits are ignored,
and WRITE, WRALL, ERASE, and ERAL are also ignored, but READ, WEN, WDS are accepted.
4
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Rev. A
05/02/06
IS93C56A
ISSI
IS93C66A
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VS
VP
TBIAS
TSTG
IOUT
Parameter
Supply Voltage
Voltage on Any Pin
Temperature Under Bias
Storage Temperature
Output Current
Value
–0.5 to +6.5
–0.5 to Vcc + 0.5
–55 to +125
–65 to +150
5
Unit
V
V
°C
°C
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OPERATING RANGE
(IS93C56A-2, IS93C66A-2)
Range
Industrial
Ambient Temperature
–40°C to +85°C
VCC
1.8V to 5.5V
Note: ISSI offers Industrial grade for Commercial applications (0oC to +70oC)
OPERATING RANGE
(IS93C56A-3, IS93C66A-3)
Range
Automotive
Ambient Temperature
–40°C to +125°C
VCC
2.5V to 5.5V
CAPACITANCE
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
5
pF
VOUT = 0V
5
pF
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Rev. A
05/02/06
5
IS93C56A
ISSI
IS93C66A
®
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C for Industrial and –40°C to +125°C for Automotive.
Symbol
Parameter
Test Conditions
VOL2
Output LOW Voltage
IOL = 100 µA
VOL1
Output LOW Voltage
VOH2
Vcc
Min.
Max.
Unit
1.8V to 2.7V
—
0.2
V
IOL = 2.1mA
2.7V to 5.5V
—
0.4
V
Output HIGH Voltage
IOH = –100 µA
1.8V to 2.7V
VCC – 0.2
—
V
VOH1
Output HIGH Voltage
IOH = –400 µA
2.7V to 5.5V
2.4
—
V
VIH
Input HIGH Voltage
1.8V to 5.5V
0.7XVCC
VCC+1
V
VIL
Input LOW Voltage
1.8V to 5.5V
–0.3
0.2XVCC
V
ILI
Input Leakage
VIN = 0V to VCC (CS, SK,DIN,ORG)
0
2.5
µA
ILO
Output Leakage
VOUT = 0V to VCC, CS = 0V
0
2.5
µA
Notes:
Automotive grade devices in this table are tested with Vcc = 2.5V to 5.5V. An operation with Vcc <2.5V is not specified.
POWER SUPPLY CHARACTERISTICS
TA = –40°C to +85°C for Industrial, –40°C to +125°C for Automotive.
Symbol Parameter
6
Test Conditions
Vcc
Min.
Typ. Max. Unit
ICC1
Vcc Read Supply Current
CS = VIH, SK = 1 MHz, CMOS input levels
CS = VIH, SK = 2 MHz, CMOS input levels
CS = VIH, SK = 2 MHz, CMOS input levels
1.8V
2.5V
5.0V
—
—
—
0.1
0.2
0.5
1
1
2
mA
mA
mA
ICC2
Vcc Write Supply Current
CS = VIH, SK = 1 MHz, CMOS input levels
CS = VIH, SK = 2 MHz, CMOS input levels
CS = VIH, SK = 2 MHz, CMOS input levels
1.8V
2.5V
5.0V
—
—
—
0.5
1
2
1
2
3
mA
mA
mA
ISB1
Standby Current
CS = GND, SK = GND,
ORG = VCC or Floating (x16)
1.8V
2.5V
5.0V
—
—
—
0.1
0.1
0.2
1
2
4
µA
µA
µA
ISB2
Standby Current
CS = GND, SK = GND,
ORG = GND (x8)
1.8V
2.5V
5.0V
—
—
—
6
6
10
10
10
15
µA
µA
µA
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Rev. A
05/02/06
IS93C56A
ISSI
IS93C66A
®
AC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C for Industrial
Symbol Parameter
Test Conditions
Min.
Max.
Unit
fSK
SK Clock Frequency
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
0
0
0
1
2
3
Mhz
Mhz
Mhz
tSKH
SK HIGH Time
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
250
200
200
—
—
—
ns
ns
ns
tSKL
SK LOW Time
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
250
200
100
—
—
—
ns
ns
ns
tCS
Minimum CS LOW Time
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
250
200
200
—
—
—
ns
ns
ns
tCSS
CS Setup Time
Relative to SK
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
200
100
50
—
—
—
ns
ns
ns
tDIS
Din Setup Time
Relative to SK
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
100
50
50
—
—
—
ns
ns
ns
tCSH
CS Hold Time
Relative to SK
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
0
0
0
—
—
—
ns
ns
ns
tDIH
Din Hold Time
Relative to SK
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
50
50
50
—
—
—
ns
ns
ns
tPD1
Output Delay to “1”
AC Test
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
—
—
—
400
200
100
ns
ns
ns
tPD0
Output Delay to “0”
AC Test
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
—
—
—
400
200
100
ns
ns
ns
tSV
CS to Status Valid
AC Test
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
—
—
—
400
200
200
ns
ns
ns
tDF
CS to Dout in 3-state
AC Test, CS=VIL
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
—
—
—
100
100
100
ns
ns
ns
tWP
Write Cycle Time
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
—
—
—
10
5
5
ms
ms
ms
Notes:
1. C L = 100pF
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Rev. A
05/02/06
7
IS93C56A
ISSI
IS93C66A
®
AC ELECTRICAL CHARACTERISTICS
TA = –40°C to +125°C for Automotive
Symbol Parameter
fSK
tSKH
tSKL
tCS
tCSS
tDIS
tCSH
tDIH
tPD1
tPD0
tSV
tDF
tWP
Test Conditions
SK Clock Frequency
SK HIGH Time
SK LOW Time
Minimum CS LOW Time
CS Setup Time
Din Setup Time
CS Hold Time
Din Hold Time
Output Delay to “1”
Output Delay to “0”
CS to Status Valid
CS to Dout in 3-state
Write Cycle Time
Relative to SK
Relative to SK
Relative to SK
Relative to SK
AC Test
AC Test
AC Test
AC Test, CS=VIL
Min.
Max.
Unit
2.5V ≤ Vcc < 4.5V
0
2
Mhz
4.5V ≤ Vcc ≤ 5.5V
0
3
Mhz
2.5V ≤ Vcc < 4.5V
200
—
ns
4.5V ≤ Vcc ≤ 5.5V
200
—
ns
2.5V ≤ Vcc < 4.5V
200
—
ns
4.5V ≤ Vcc ≤ 5.5V
100
—
ns
2.5V ≤ Vcc < 4.5V
200
—
ns
4.5V ≤ Vcc ≤ 5.5V
200
—
ns
2.5V ≤ Vcc < 4.5V
100
—
ns
4.5V ≤ Vcc ≤ 5.5V
50
—
ns
2.5V ≤ Vcc < 4.5V
50
—
ns
4.5V ≤ Vcc ≤ 5.5V
50
—
ns
2.5V ≤ Vcc < 4.5V
0
—
ns
4.5V ≤ Vcc ≤ 5.5V
0
—
ns
2.5V ≤ Vcc < 4.5V
50
—
ns
4.5V ≤ Vcc ≤ 5.5V
50
—
ns
2.5V ≤ Vcc < 4.5V
—
200
ns
4.5V ≤ Vcc ≤ 5.5V
—
100
ns
2.5V ≤ Vcc < 4.5V
—
200
ns
4.5V ≤ Vcc ≤ 5.5V
—
100
ns
2.5V ≤ Vcc < 4.5V
—
200
ns
4.5V ≤ Vcc ≤ 5.5V
—
200
ns
2.5V ≤ Vcc < 4.5V
—
100
ns
4.5V ≤ Vcc ≤ 5.5V
—
100
ns
2.5V ≤ Vcc < 4.5V
—
5
ms
4.5V ≤ Vcc ≤ 5.5V
—
5
ms
Notes:
1. C L = 100pF
8
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Rev. A
05/02/06
IS93C56A
ISSI
IS93C66A
®
AC WAVEFORMS
FIGURE 2. SYNCHRONOUS DATA TIMING
CS
T
tCSS
tSKH
tSKL
tCSH
SK
tDIS
tDIH
DIN
tPD0
tPD1
tDF
DOUT
(READ)
tSV
tDF
DOUT
(WRITE)
(WRALL)
(ERASE)
(ERAL)
STATUS VALID
FIGURE 3. READ CYCLE TIMING
tCS
CS
DIN
DOUT
1
1
0
An
A0
0
Dm
D0
*
*Address Pointer Cycles to the Next Register
Notes:
To determine address bits An-A0 and data bits Dm-Do, see Instruction Set for the specific device.
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Rev. A
05/02/06
9
IS93C56A
ISSI
IS93C66A
®
AC WAVEFORMS
FIGURE 4.
WRITE ENABLE (WEN) CYCLE TIMING
tCS
CS
DIN
1
0
0
1
1
DOUT = 3-state
FIGURE 5.
WRITE (WRITE) CYCLE TIMING
tCS
CS
DIN
1
0
1
An
A0
Dm
D0
tSV
DOUT
BUSY
tDF
READY
tWP
Notes:
1. After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status
(DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction.
2. To determine address bits An-A0 and data bits Dm-D0, see Instruction Set for the specific device.
10
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Rev. A
05/02/06
IS93C56A
ISSI
IS93C66A
®
AC WAVEFORMS
FIGURE 6.
WRITE ALL (WRALL) CYCLE TIMING
tCS
CS
1
DIN
0
0
0
1
Dm
D0
tSV
BUSY
DOUT
READY
tWP
Notes:
1. After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status
(DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction.
2. To determine data bits Dm-D0, see Instruction Set for the appropriate device.
FIGURE 7. WRITE DISABLE (WDS) CYCLE TIMING
tCS
CS
DIN
1
0
0
0
0
DOUT = 3-STATE
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Rev. A
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11
IS93C56A
ISSI
IS93C66A
®
AC WAVEFORMS
FIGURE 8. ERASE (REGISTER ERASE) CYCLE TIMING
tCS
CS
DIN
1
1
1
An
An-1
A0
tSV
DOUT
tDF
BUSY
READY
tWP
Notes:
To determine data bits An - A0, see Instruction Set for the appropriate device.
FIGURE 9. ERASE ALL (ERAL) CYCLE TIMING
tCS
CS
DIN
1
0
0
1
0
tSV
DOUT
BUSY
tDF
READY
tWP
Note for Figures 8 and 9:
After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status
(DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction.
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/02/06
IS93C56A
ISSI
IS93C66A
®
ORDERING INFORMATION
Industrial Range: -40ºC to +85ºC
Voltage Range
1.8V to 5.5V
1.8V to 5.5V
2.5V to 5.5V
2.5V to 5.5V
Order Part No.
IS93C56A-2PI
IS93C56A-2GRI
IS93C56A-2ZI
IS93C66A-2PI
IS93C66A-2GRI
IS93C66A-2ZI
IS93C56A-3PI
IS93C56A-3GRI
IS93C66A-3PI
IS93C66A-3GRI
Package
300-mil Plastic DIP
SOIC JEDEC
169-mil TSSOP
300-mil Plastic DIP
SOIC JEDEC
169-mil TSSOP
300-mil Plastic DIP
SOIC JEDEC
300-mil Plastic DIP
SOIC JEDEC
Automotive Range: -40ºC to +125ºC, Lead-free
Voltage Range
2.5V to 5.5V
2.5V to 5.5V
Order Part No.
IS93C56A-3PLA3
IS93C56A-3GRLA3
IS93C56A-3ZLA3
IS93C66A-3PLA3
IS93C66A-3GRLA3
IS93C66A-3ZLA3
Package
300-mil Plastic DIP
SOIC JEDEC
169-mil TSSOP
300-mil Plastic DIP
SOIC JEDEC
169-mil TSSOP
Industrial Range: -40ºC to +85ºC, Lead-free
Voltage Range
1.8V to 5.5V
1.8V to 5.5V
Order Part No.
IS93C56A-2PLI
IS93C56A-2GRLI
IS93C56A-2ZLI
IS93C66A-2PLI
IS93C66A-2GRLI
IS93C66A-2ZLI
Package
300-mil Plastic DIP
SOIC JEDEC
169-mil TSSOP
300-mil Plastic DIP
SOIC JEDEC
169-mil TSSOP
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/02/06
13
ISSI
PACKAGING INFORMATION
®
300-mil Plastic DIP
Package Code: N,P
N
E1
1
D
S
S
SEATING PLANE
B1
E
A
L
C
A1
FOR
32-PIN ONLY
e
MILLIMETERS
Sym.
Min.
INCHES
Max.
Min.
Max.
4.57
9.53
8.26
0.145
0.015
0.014
0.045
0.032
0.008
0.359
0.300
0.180
E
3.68
0.38
0.36
1.14
0.81
0.20
9.12
7.62
E1
6.20
6.60
0.244
0.260
eA
e
8.13
9.65
0.320
0.380
L
3.18
—
0.125
—
S
0.64
0.762
0.025
0.030
N0.
Leads
A
A1
B
B1
B2
C
D
B2
B
eA
Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should
be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within 0.004
inches at the seating plane.
8
—
0.56
1.52
1.17
0.33
2.54 BSC
—
0.022
0.060
0.046
0.013
0.375
0.325
0.100 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/14/03
ISSI
PACKAGING INFORMATION
150-mil Plastic SOP
Package Code: G, GR
®
N
E
H
1
D
SEATING PLANE
A
A1
e
L
α
C
B
Symbol
Ref. Std.
No. Leads
A
A1
B
C
D
E
H
e
L
150-mil Plastic SOP (G, GR)
Min
Max
Min
Max
Inches
mm
8
8
—
0.068
—
1.73
0.004
0.009
0.1
0.23
0.013
0.020
0.33
0.51
0.007
0.010
0.18
0.25
0.189
0.197
4.8
5
0.150
0.157
3.81
3.99
0.228
0.245
5.79
6.22
0.050 BSC
1.27 BSC
0.020
0.035
0.51
0.89
Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should be
measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within 0.004 inches at the
seating plane.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
10/03/01
2
ISSI
PACKAGING INFORMATION
Thin Shrink Small Outline TSSOP
Package Code: Z (8 pin, 14 pin)
N
E1
1
E
α
N/2
A1
D
A2
A
L
C
e
B
TSSOP (Z)
Ref. Std.
JEDEC MO-153
No. Leads
8
Millimeters
Inches
Symbol Min Max
Min Max
A
—
1.20
— 0.047
A1
0.05 0.15
0.002 0.006
A2
0.80 1.05
0.032 0.041
B
0.19 0.30
0.007 0.012
C
0.09 0.20
0.004 0.008
D
2.90 3.10
0.114 0.122
E1
4.30 4.50
0.169 0.177
E
6.40 BSC
0.252 BSC
e
0.65 BSC
0.026 BSC
L
0.45 0.75
0.018 0.030
α
—
8°
—
8°
TSSOP (Z)
Ref. Std.
JEDEC MO-153
No. Leads
14
Millimeters
Inches
Symbol Min Max
Min
Max
A
—
1.20
—
0.047
A1
0.05 0.15
0.002 0.006
A2
0.80 1.05
0.031 0.041
B
0.19 0.30
0.007 0.012
C
0.09 0.20
0.0035 0.008
D
4.90 5.10
0.193 0.201
E1
4.30 4.50
0.170 0.177
E
6.40 BSC
0.252 BSC
e
0.65 BSC
0.026 BSC
L
0.45 0.75
0.0177 0.0295
α
—
8°
—
8°
SSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may
appear in this publication. © Copyright 2002, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
Rev B 02/01/02
®