Siemens FEB4065 High voltage subscriber line ic hv-slic Datasheet

ICs for Communications
High Voltage Subscriber Line IC
HV-SLIC
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Data Sheet 03.98
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PEB/F 4065 Version 3.0
PEB/F 4065
Revision History:
Current Version: 03.98
Previous Version:
01.96
Page
(in previous
Version)
Page
(in current
Version)
Subjects (major changes since last revision)
SLICOFI® is a registered trademark of SIEMENS AG.
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in Germany or the Siemens Companies and Representatives worldwide: see our webpage at http:/
/www.siemens.de/Semiconductor/address/address.htm.
Edition 03.98
Published by Siemens AG,
HL SP,
Balanstraße 73,
81541 München
© Siemens AG 1998.
All Rights Reserved.
Attention please!
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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or
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1 A critical component is a component used in a life-support device or system whose failure can reasonably be
expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
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2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or
maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
PEB/F 4065
Table of Contents
Page
1
1.1
1.2
1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2
2.1
2.2
2.3
2.4
2.5
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
AC-Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Semiconductor Group
3
1998-03-01
High Voltage Subscriber Line IC
HV-SLIC
PEB/F 4065
Version 1.1
1
SPT
Overview
The High Voltage Subscriber Line IC PEB 4065 is a
rugged and reliable interface between the telephone
line and the SLICOFI, a low voltage Subscriber Line
Interface and Codec Filter IC. It is fabricated in a Smart
Power Technology offering a breakthrough voltage of
at least 170 V.
P-DSO-20-5
The PEB 4065 provides battery feeding between
– 24 V and – 80 V and internal ringing injection with a
differential ring voltage up to 85 Vrms. In order to
achieve these high amplitudes an auxiliary positive battery voltage is used during
ringing. This voltage can also be applied in order to drive very long telephone lines.
The SLIC is designed for a voltage feeding – current sensing line interface concept and
provides sensing of transversal and longitudinal current on both wires.
A power-down mode offers reduced power consumption at full functionality; in the power
denial mode the device is switched off turning the line outputs to a high impedance state.
1.1
Features
•
•
•
•
•
•
High voltage line feeding
Internal ring and metering signal injection
Sensing of transversal and longitudinal line current
Reliable 170 V Smart Power Technology
Battery voltage – 24 V … – 80 V
Boosted battery mode for long telephone lines
and up to 85 Vrms balanced ringing
• Polarity reversal
• Small P-DSO-20-5 power package
Type
Ordering Code
Package
PEB/F 4065
on request
P-DSO-20-5
Semiconductor Group
4
1998-03-01
PEB/F 4065
Overview
1.2
Functional Description
VH
BGND
Supply
Switch
RING
VHINT
Ιa
Differential
I/V-Converter
Ιb
V/I Converter
V2W
Reference
PDN
Buffer
Current sensor
ΙT
Figure 1
C1
C2
Buffer
Vab
TIP
Control
ΙL
VBAT
Supply
VBAT
VBIM
AGND VSS VDD
ITB10371
Block Diagram
The PEB 4065 supports AC and DC control loops based on feeding a voltage Vab to the
line and sensing the transversal line current Iab (Figure 2).
It converts a unipolar input voltage V2W into a differential output voltage Vab with an AC
receiving gain of
Gr = VabAC/V2WAC = 40.
This is accomplished by converting the input voltage to a current which is used to
transpose the low voltage signals of the interface to the high voltage line feeding section.
This current is reconverted to two voltages of opposite phase which are referenced to
the positive and negative supply voltage, respectively. Thus the differential DC
line-voltage in all normal polarity modes except ringing is related to the input voltage by
VabDC = VBAT – VHINT + Vfix – 40 × V2WDC
VBAT negative battery voltage
VHINT internal positive supply voltage
Vfix
internal voltage drop of supply filter (appr. 2 V).
Depending on the operation mode, VHINT is switched either to VH (VHINT = VH – 1 V) or to
BGND (VHINT = – 0.5 V) via the supply switch.
Semiconductor Group
5
1998-03-01
PEB/F 4065
Overview
Controlled by C2, the polarity of Vab can be reversed and the DC-line-voltage then is
VabDC = – (VBAT – VHINT + Vfix – 40 × V2WDC).
The transversal and longitudinal currents are measured in the buffers and scaled images
are provided at the IT and IL pin, respectively:
IT = (Ia + Ib)/100 = Iab/50
IL = – (Ia – Ib)/100 = – ILong/50.
The PEB 4065 operates in four modes controlled by ternary logic signals at the C1 and
C2 input. Additionally, in the active modes a polarity reversal of the output voltage can
be programmed (see Table 1).
Power down (PD): Power consumption is reduced by decreasing bias current levels. All
functions operate at some small performance reductions. In this mode each of the line
outputs can be programmed to show high impedance. HI b switches off the TIP buffer,
while the current through the RING output still can be measured by IT or IL. Programming
HI a reverses the polarity and switches off the RING buffer.
Conversation (CONV): This is the regular transmit and receive mode for voiceband and
teletax. The line driving section is operated between VBAT and BGND.
Boosted battery (BB): In order to drive longer telephone lines an auxiliary positive battery
voltage VH is used, enabling a higher DC-voltage across the line.
Ringing (RING): This mode also uses the auxiliary voltage VH in order to provide a
balanced ring signal of up to 85 Vrms. The ring tone without any DC-component has to
be switched to the V2W input. Internally a DC-voltage is superimposed. This voltage is
proportional to the total supply voltage VH – VBAT and amounts to typically 23 V at
VH – VBAT = 120 V. The current sensing functions are available for ring trip detection.
The Power Denial (PDN) state is intended to reduce power consumption of the linecard
to a minimum: the PEB 4065 is switched off completely by connecting the PDN pin to
VDD, no operation is available.
With respect to the output impedance of TIP and RING two PDN-modes have to be
distinguished. A resistive one (PDNR) provides a connection of 15 kΩ each from TIP to
BGND and RING to VBAT, respectively, while the outputs of the buffers show high
impedance (Figure 3).
The other mode (PDNH) offers high impedance at TIP and RING. It is entered when, in
addition to connecting PDN to VDD, the programming inputs C1, C2 are tied to VIL.
All other combinations of C1, C2 yield the resistive power denial state PDNR.
Semiconductor Group
6
1998-03-01
PEB/F 4065
Overview
Table 1
Programming of Operation Modes
C2 (Pin 13)
C1 (Pin 12)
VIL
VIZ
VIH
VIL
VIZ
VIH
RING RP
RING NP
HI a RP
BB RP
BB NP
HI b NP
CONV RP
CONV NP
PD NP
NP
Normal Polarity
RP...Reverse Polarity
HI a RP
Ring wire set to high impedance
HI b NP
Tip wire set to high impedance
Ι Long
Buffer
Ιa
RING
ZL
2
Vab
ZL
2
Ι ab
~
~
Buffer
Ιb
TIP
Ι Long
Ι ab = ( Ι a + Ι b ) /2
Ι Long = ( Ι a - Ι b ) /2
Figure 2
ITS10372
Definition of Output Current Directions
Semiconductor Group
7
1998-03-01
PEB/F 4065
Overview
BGND
PDNH
HIZ
PDNR
R TG
15 k Ω
TIP
HIZ
RING
R RB
15 k Ω
PDNH
PDNR
VBAT
Figure 3
ITS10373
TIP and RING Impedance in Power Denial
Semiconductor Group
8
1998-03-01
PEB/F 4065
Overview
1.3
Pin Description
P-DSO-20-5 (11 mm)
V BAT
V SS
ΙL
ΙT
AGND
C2
C1
AGND
PDN
V BAT
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
V BAT
RING
TIP
N.C.
VH
BGND
V DD
V 2W
V BIM
V BAT
ITP10374
Due to reverse bending of the leads,
the numbering of the pins is also reversed.
Figure 4
Pin Configuration (top view)
Table 2
Pin Definition and Functions
Pin No.
Symbol
Type
Function
Input (I)
Output (O)
1, 10, 11, VBAT
20
Supply
Negative battery supply voltage (– 24 … – 80 V),
referred to BGND
2
RING
O
Subscriber loop connection, negative wire in
normal polarity; direction of positive Ia current out of
this pin
3
TIP
O
Subscriber loop connection, more positive wire in
normal polarity; direction of positive Ib current into
this pin
4
–
N.C.
Not connected
5
VH
Supply
Auxiliary positive battery supply voltage
(0 … + 90 V) used in ringing and boosted battery
mode
6
BGND
Supply
Battery ground: TIP, RING, VBAT and VH refer to this
pin
7
VDD
Supply
Positive supply voltage (+ 5 V), referred to AGND
Semiconductor Group
9
1998-03-01
PEB/F 4065
Overview
Table 2
Pin Definition and Functions (cont’d)
Pin No.
Symbol
Type
Function
Input (I)
Output (O)
8
V2W
I
Two wire input voltage; multiplied by + 20 and – 20,
respectively, it appears at the TIP and RING
outputs
9
VBIM
O
Down scaled image of the total supply voltage
(VHINT – VBAT); scaling factor 40
12
PDN
I/O
Power denial, reference output when connected to
ground via a resistor, switches the device off when
connected to VDD
13, 16
AGND
Supply
Analog ground: VDD, VSS and all signal and control
pins with exception of TIP and RING refer to AGND
14
C1
I/O
Ternary logic input, controlling the operation mode;
in case of thermal overload this pin sinks a current
of typ. 550 µA
15
C2
I
Ternary logic input, controlling the operation mode
17
IT
O
Current output representing the transversal current
scaled down by 50; In normal polarity this pin sinks
the IT current.
18
IL
O
Current output representing the longitudinal current
scaled down by 50;
For Ilong flowing out of TIP and RING this pin sinks
the IL current.
19
VSS
Supply
Negative supply voltage (– 5 V), referred to AGND
Semiconductor Group
10
1998-03-01
PEB/F 4065
Electrical Characteristics
2
Electrical Characteristics
2.1
Absolute Maximum Ratings
Table 3
Parameter
Symbol
Limit Values
Unit Condition
min.
max.
– 90
0.5
V
referred to BGND
– 0.5
90
V
referred to BGND
Total battery supply VH – VBAT
voltage, continuously
–
160
V
–
VH – VBAT
Total battery supply
voltage, pulse < 1 ms
–
170
V
–
5.5
V
referred to AGND
0.4
V
referred to AGND
0.5
V
–
–
150
°C
–
V2W, VC1, VC2
VIT, VIL
VSS – 0.3
VDD + 0.3 V
VDD + 0.3 V
–
VPDN
Va, Vb
– 0.3
VDD + 0.3 V
VBAT – 0.3 VH + 0.3 V
–
RING, TIP voltages,
pulse < 1 ms1)
Va, Vb
VBAT – 10 VH + 10
V
–
RING, TIP voltages,
1)
pulse < 1 µs
Va, Vb
VBAT – 30 VH + 30
V
–
–
kV
Human body
model
Battery voltage
Auxiliary supply
voltage
VDD supply voltage
VSS supply voltage
Ground voltage
difference
VBAT
VH
VDD
– 0.4
VSS
– 5.5
VBGND – VAGND – 0.5
Junction temperature Tj
Input voltages
Voltages on current
outputs
Voltages on PDN
RING, TIP voltages,
continuously
ESD-voltage, all pins –
1)
– 3.5
1
–
–
See Test Figure 10.
Note: Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
Semiconductor Group
11
1998-03-01
PEB/F 4065
Electrical Characteristics
2.2
Operating Range
Table 4
Parameter
Symbol
Limit Values
Unit
Condition
min.
max.
– 80
– 24
V
referred to BGND
5
85
V
referred to BGND
–
150
V
–
VDD supply voltage
VSS supply voltage
VBAT
VH
VH – VBAT
VDD
VSS
4.75
5.25
V
referred to AGND
– 5.25
– 4.75
V
referred to AGND
Ground voltage difference
–
– 0.3
0.3
V
–
Ambient temperature
Tamb
0
– 40
70
85
°C
°C
PEB 4065
PEF 4065
Voltage compliance IT, IL
VIT, VIL
V2W
–3
3
V
–
– 3.2
+ 3.2
V
RING
– 3.2
0
V
CONV, PD, BB
Battery voltage
Auxiliary supply voltage
Total battery supply voltage
Input range V2W
Note: In the operating range the functions given in the circuit description are fulfilled.
2.3
Thermal Resistances
Table 5
Parameter
Symbol
Limit
Values
Unit
Condition
Junction to case
Rth, jC
Rth, jA
5
K/W
–
20
K/W
with heatsink, typ.
Junction to ambient
Semiconductor Group
12
1998-03-01
PEB/F 4065
Electrical Characteristics
2.4
Electrical Parameters
Min/max values are valid within the full operating range. If PEB- and PEF-specifications
are different, both values can be found in the respective column.
Testing is performed according to the test figures with external circuitry as depicted in
Figure 4. Unless otherwise stated, load impedance RL = 600 Ω. Test temperatures are
25 and 70 °C for PEB, – 40, 25 and 85 °C for PEF-type (without heatsink). DC line
voltages refer to VBAT = – 70 V and VH = + 60 V.
Table 6
No.
Supply Currents and Power Dissipation
Parameter
Symbol
Mode
Limit Values
min. typ.
max.
PEB/PEF
Unit Test
Fig.
Power Denial
1.
VDD current
IDD
PDNH,
PDNR
–
50
120/150
µA
1
2.
VSS current
ISS
PDNH
PDNR
–
50
150
120/150
250/300
µA
1
3.
VBAT current
IBAT
PDNH
PDNR
–
10
50
30
120
µA
1
4.
VH current
IH
PDNH,
PDNR
–
1
10
µA
1
V2W = – 0.5 V1)
Power Down
5.
6.
7.
8.
9.
VDD current
VSS current
VBAT current
VH current
Quiescent power
dissipation
IDD
ISS
IBAT
IH
PQ
PD
–
0.5
1.0
mA
1
PD
–
0.3
0.4
mA
1
PD
–
3.3
4.3/4.4
mA
1
PD
–
1
10
µA
1
PD
–
–
315
mW 1
V2W = – 0.5 V1)
Conversation, Normal and Reverse Polarity
10.
11.
12.
13.
14.
VDD current
VSS current
VBAT current
VH current
Quiescent power
dissipation
Semiconductor Group
IDD
ISS
IBAT
IH
PQ
CONV
–
0.8
1.0/1.1
mA
1
CONV
–
0.4
0.5/0.6
mA
1
CONV
–
4.0
5.8/5.9
mA
1
CONV
–
1
10
µA
1
CONV
–
–
420
mW 1
13
1998-03-01
PEB/F 4065
Electrical Characteristics
Table 6
No.
Supply Currents and Power Dissipation (cont’d)
Parameter
Symbol
Mode
Limit Values
min. typ.
max.
PEB/PEF
V2W = – 0.5 V1)
Boosted Battery Mode Normal and Reverse Polarity
15.
16.
17.
18.
19.
VDD current
VSS current
VBAT current
VH current
Quiescent power
dissipation
IDD
ISS
IBAT
IH
PQ
BB
–
0.8
1.0
mA
1
BB
–
1.7
2.0
mA
1
BB
–
4.0
6.1/6.2
mA
1
BB
–
3.0
4.8
mA
1
BB
–
–
740
mW 1
V2W = 0 V
Ringing Mode Normal and Reverse Polarity
20.
21.
22.
23.
24.
1)
VDD current
VSS current
VBAT current
VH current
Quiescent power
dissipation
IDD
ISS
IBAT
IH
PQ
Unit Test
Fig.
RING
–
2.3
2.6
mA
1
RING
–
2.8
3.2
mA
1
RING
–
8.8
12/12.5
mA
1
RING
–
7.1
10
mA
1
RING
–
1300 1500
mW 1
IBAT and IH depend on the value of V2W:
IBAT (V2W) = IBAT(0) + |V2W|/440 Ω
typ. (PD, CONV, BB)
IH (V2W) = IH(0) + |V2W|/440 Ω
typ. (BB)
Semiconductor Group
14
1998-03-01
PEB/F 4065
Electrical Characteristics
Table 7
DC-Characteristics
No. Parameter
Symbol
Mode
Limit Values
Unit Test Test Condition
Fig.
min.
PEB/
PEF
typ.
max.
PEB/
PEF
PD
46
49
52
V
26.
PD
– 14
– 11
–8
V
27. Conversation |Vab,DC|
DC line
voltage
CONV 65
66.5
68.5
V
28.
CONV 46.6
47.8
48.8
V
29.
CONV – 14
– 12.2 – 10.4 V
25
27.7
V
2
V2W = 0 V
–
–
130
130/
135
mA
mA
3
V2W = – 0.5 V
Va, Vb acc. to
Line Termination TIP, RING
25. Power down
DC line
voltage
|Vab,DC|
30. Ringing DC
line voltage
|Vab,DC|
RING
31. Output
current limit
|Ia,max|,
|Ib,max|
PD
85/80
others 90/85
22.1
PDNR 12/11
15
18/19 kΩ
RRB
33. Loop open
resistance
RING to VBAT
PDNR 12/11
15
18/19 kΩ
34. Power denial ILeak,a
output
leakage
current
PDNH – 30
–
30
µA
35.
ILeak,b
– 30
–
30
µA
36. High
impedance
output
leakage
current
ILeak,a
HI a
– 30
–
30
µA
37.
Ileak,b
HI b
– 30
–
30
µA
15
V2W = – 0.5 V
V2W = – 2 V
2
V2W = 0 V
V2W = – 0.5 V
V2W = – 2 V
Test Figure 3
RTG
32. Loop open
resistance
TIP to BGND
Semiconductor Group
2
9
Ib = 2 mA
Ia = 2 mA
–
VBAT < Va < VH
VBAT < Va < VH
–
VBAT < Va < VH-3
VBAT < Vb < VH-3
1998-03-01
PEB/F 4065
Electrical Characteristics
Table 7
DC-Characteristics (cont’d)
No. Parameter
Symbol
Mode
Limit Values
min.
PEB/
PEF
typ.
max.
PEB/
PEF
1.25
1.35
Unit Test Test Condition
Fig.
Reference Voltage Outputs PDN, VBIM
38. Output
voltage on
PDN
Vref
all
1.15
V
1
–
– 1.65 V
1
–
39. Battery image VBIM
voltage
CONV, – 1.75 – 1.7
PD
40.
BB,
RING
– 3.25 – 3.18 – 3.1
V
Two-wire Input V2W
41. Input current
I2W
all
– 30
–
30
µA
–
– 3.2 V < V2W < 3.2 V
42. Input
capacitance
–
–
–
–
20
pF
–
–
Current Outputs IT, IL
43. IT output
current
| IT |
V2W = – 0.5 V
PD,
–
CONV
–
15
µA
2
Ia = Ib = 0
44.
PD,
380
CONV
420
µA
Ia = Ib = 20 mA1)
45.
CONV 0.95
1.05
mA
Ia = Ib = 50mA1)
46.
RING
20
µA
Ia = Ib = 0
30
µA
47. IL output
current
|IL|
PD,
–
CONV
–
2
Ia = Ib = 0
48.
PD,
CONV
30
µA
Ia = Ib = 20 mA1)
49.
PD,
65
CONV
135
µA
Ia = 15 mA,
Ib = 25 mA
50.
CONV 180
320
µA
Ia = 37.5 mA,
Ib = 62.5 mA
Semiconductor Group
16
1998-03-01
PEB/F 4065
Electrical Characteristics
Table 7
DC-Characteristics (cont’d)
No. Parameter
Symbol
Mode
Limit Values
min.
PEB/
PEF
typ.
max.
PEB/
PEF
Unit Test Test Condition
Fig.
Control Inputs C1, C2
51. H-input
voltage
VIH
all
2
–
–
V
–
–
52. Z-input
voltage
VIZ
all
– 0.8
–
0.8
V
–
–
53. L-input
voltage
VIL
all
–
–
–2
V
–
–
54. Input
leakage
current
ILeak
all
–5
–
5
µA
–
– 5 V < VC1(2) < + 5 V
55. Thermal
overload
current C1
Itherm
all
500
550
–
µA
–
VC1 = – 3.2 V
all
all
–
–
165
145
–
–
°C
°C
–
–
–
–
Tjoff
56. Switching
Temperature Tjon
(guaranteed
by design)
1)
Polarity of Ia and Ib is reversed for measurement in reverse polarity mode
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and
the given supply voltage.
Semiconductor Group
17
1998-03-01
PEB/F 4065
Electrical Characteristics
2.5
AC-Characteristics
(Normal and reverse polarity unless otherwise stated)
Table 8
No. Parameter
Symbol Mode
Limit Values
min.
typ.
Unit
max.
PEB/
PEF
Test Test Condition
Fig.
Line Termination TIP, RING
57.
CONV, 31.92 32.04
BB
32.16
dB
V2W,AC = 50 mVrms
f = 1015 Hz
Iab = 20 mA
58.
CONV 31.88 32.04
32.2
dB
Iab = 50 mA
59. Gain flatness dGr
(guaranteed
by design)
CONV, – 0.05 –
BB
0.05
dB
–
300 Hz < f < 3400 Hz
V2W,AC = 50 mVrms
60. Gain tracking dGr
(guaranteed
by design)
CONV – 0.2
–
0.2
dB
–
3 dBm0 > Vab >
– 20 dBm0
f = 1015 Hz
CONV –
–
0.3
%
4
V2W,AC = 50 mVrms
f = 1015 Hz
Iab = 20 mA
5
f = 16 kHz
RL = 200 Ω
Iab = 50 mA
Vab,AC = 2 Vrms
Receive gain
61. Total
harmonic
distortion Vab
Teletax
distortion
Gr
THD
4
THDTTX CONV
62.
–
–
3
%
63.
–
–
3
%
Vab,AC = 5 Vrms
Iab = 0 mA,
Vab = 55 V
64.
–
–
5
%
Vab,AC = 2 Vrms
65. Psophometric NP, Vab
noise
CONV –
–
– 75
dBmp 4
Iab = 30 mA
66. Longitudinal LTRR
to transversal
rejection ratio
Vlong/Vab
CONV 61/58 –
–
dB
6
Vlong = 3 Vrms
300 Hz < f < 3.4 kHz
Iab = 30 mA
TLRR
67. Transversal
to
longitudinal
rejection ratio
Vab/Vlong
CONV 50
–
dB
7
V2W,AC = 150 mVrms
300 Hz < f < 3.4 kHz
Iab = 30 mA
Semiconductor Group
–
18
1998-03-01
PEB/F 4065
Electrical Characteristics
Table 8
(cont’d)
No. Parameter
Symbol Mode
Limit Values
min.
typ.
Unit
max.
PEB/
PEF
Power supply PSRR
rejection ratio
68. VBAT/Vab
Test Test Condition
Fig.
4
300 Hz < f < 3.4 kHz
VSupply,AC = 100 mVp
Iab = 30 mA
CONV, 33
40
BB
PD
30/28 –
–
dB
–
dB
69. VH/Vab
BB
–
dB
70. VDD/Vab
CONV, 33
BB
50
–
dB
71. VSS/Vab
CONV, 33
BB
50
25
–
dB
dB
RING
67
–
–
Vrms, 8
diff
RL = 1 kΩ
CL = 1 µF
f = 66 Hz
V2W = 1.7 Vrms
84
–
–
Vrms, 8
diff
VH = 80 V
f = 20 Hz
V2W = 2.2 Vrms
–
–
4
%
8
f = 66 Hz
V2W = 1.7 Vrms
4
72. Ringing
voltage
VRING
73. Ringing
voltage with
extended VH
74. Ringing
distortion
THD
RING
33/30 40
Transversal Current Output IT
75.
CONV, 33.89 33.98
BB
34.07
dB
V2W = 50 mVrms
f = 1015 Hz
Iab = 20 mA
76.
CONV 33.89 33.98
34.07
dB
Iab = 50 mA
77. Gain flatness dGit
(guaranteed
by design)
CONV, – 0.05 –
BB
0.05
dB
–
300 Hz < f < 3400 Hz
V2W,AC = 50 mVrms
Iab = 20 mA
78. Gain tracking dGit
(guaranteed
by design)
CONV – 0.2
–
0.2
dB
–
3 dBm0 > Vab >
– 20 dBm0
f = 1015 Hz
CONV –
0.01
0.3
%
4
V2W,AC = 50 mVrms
f = 1015 Hz
Iab = 15 mA
Transversal
current ratio
79. Total
harmonic
distortion VIT
Git
THD, IT
Semiconductor Group
19
1998-03-01
PEB/F 4065
Electrical Characteristics
Table 8
(cont’d)
No. Parameter
Symbol Mode
Limit Values
min.
80. Psophometric NP, VIT
noise
CONV –
Frequency
response
VIT/V2W
(guaranteed
by design)
81. Amplitude
CONV
–
82. Phase
Longitudinal LITRR
to transversal
current
output
rejection ratio
Vlong/VIT
typ.
max.
PEB/
PEF
–
– 100
-97
Unit
Test Test Condition
Fig.
dBmp 4
Iab = 30 mA, T>00C
-400C<T<00C
– 0.5
1.7
1.95
dB
100
–
–
deg
CONV
4
f = 200 kHz
V2W,AC = 50 mVrms
ILine = 20 mA
Cs = 0.2 nF
6
Vlong = 3 Vrms
Iab = 30 mA
83.
75
–
–
dB
300 Hz < f < 3.4 kHz
84.
81
–
–
dB
f = 1015 Hz
Power supply PSRR
rejection ratio
85. VBAT/VIT
4
CONV, 50
PD
60
–
dB
86. VH/VIT
BB
50
60
–
dB
87. VDD/VIT
CONV 50
60
–
dB
88. VSS/VIT
CONV 50
60
–
dB
Semiconductor Group
20
300 Hz < f < 3.4 kHz
Vsupply,AC = 100 mVp
Iab = 30 mA
1998-03-01
PEB/F 4065
Electrical Characteristics
Table 9
External Elements in the Application Circuit (Figure 5)
Typical values are used in the test circuits, unless otherwise specified.
Ext. Part Function
Typ. Value Tolerance
Limit Values
Comment
min.
max.
–
50 kΩ
power
dissipation
increases with
smaller R1
R1
Biasing,
current
reference
25 kΩ
–
R2 , R3
IT, IL gain
1 kΩ
0.1% (rel.) –
–
clipping for
IT × R 2 > 3 V
or IL × R3 > 3 V
adjustment
RS
Protection,
isolation of
capacitive
load
50 Ω
0.1% (rel.) 30 Ω
–
–
R5 , R6
C1
Protection
50 Ω
0.1% (rel.) –
–
–
C for the
internal
supply
voltage filter
20%
22 µF
(f3dB ≈ 3 Hz)
–
f3dB increases
with smaller C1,
CS
Suppression 15 nF
of voltage
spikes,
frequency
compensation
C2, C3
VDD, VSS
10 nF
causing worse
low frequency
PSRR from VBAT
5% (rel.)
200 pF 20 nF
–
1 µF
20%
10 nF
–
100 nF
–
–
–
C2, C3 > 1 µF
and C4 ≈ C5
allows arbitrary
switching
sequence of all
supply voltages
incl.
20%
100 nF –
supply
voltage
blocking
C4
VH blocking
C5
VBAT blocking 100 nF
ground
Note: Exceeding the min./max. limits can cause stability problems!
Semiconductor Group
21
1998-03-01
PEB/F 4065
Electrical Characteristics
5 V -5 V
PEB 3065
SLICOFI
14 C1
15 C2
5V
R1
24.9 k Ω
7 19
VDD VSS
8 V
2W
12 PDN
ΙT
ΙT
17
18
R IT
1 kΩ
1)
2)
60 V -70 V
5
VH
C2
1 µF
C3
1 µF
C4
100 nF
C5
100 nF
1, 10, 11, 20
VBAT
TIP
1)
RS
1)
R5
30 Ω
CS
15 nF
51 Ω
RS
CS
15 nF
R6
PEB 4065
RING 2
30 Ω
BGND AGND VBIM
6
13 16 9
2)
C1
+ 22 µ F/10 V
51 Ω
b
a
R IL
1 kΩ
Careful symmetrical board layout with respect to a and b
Connect close to pin 16
Figure 5
3
Subscriber
Line
ITS10506
Application Circuit
Semiconductor Group
22
1998-03-01
PEB/F 4065
Electrical Characteristics
V DD
VBIM
VSS
PDN
C BIM
R PDN
VREF
Ι SS
VBIM
VSS
V DD
V BAT
Ι DD
V DD
VH
Ι BAT
V BAT
ΙH
VH
TIP
PDN
RING
PEB 4065
BGND
V2W
C1
C2
ΙL
ΙT
R IL
AGND
R IT
See Testcond.
Test Figure 1
ITS10507
DC Characteristics and Power Dissipation
Semiconductor Group
23
1998-03-01
PEB/F 4065
Electrical Characteristics
VSS
V DD
V BAT
VH
VSS
V DD
V BAT
VH
RING
C BIM
VBIM
25 k Ω
Ιa
Vab
PDN
TIP
Ιb
PEB 4065
BGND
V2W
C1
C2
AGND
ΙT
ΙL
ΙL
ΙT
See Testcond.
Test Figure 2
ITS10508
DC Line Voltage and Currents
Semiconductor Group
24
1998-03-01
PEB/F 4065
Electrical Characteristics
VSS
V DD
V BAT
VH
VSS
V DD
V BAT
VH
RING
C BIM
VBIM
25 k Ω
PDN
Ι a, max
Va
Ι b, max
Vb
TIP
PEB 4065
BGND
V2W
C2
C1
AGND
ΙT
ΙL
R IL
R IT
Va , Vb : BGND / VBAT in PDN, CONV
BGND in BB, RING
See Testcond.
ITS10509
Test Figure 3
Output Current Limit
DC and AC
VSS
V DD
V BAT
VH
VSS
V DD
V BAT
VH
C BIM
VBIM
RS
TIP
25 k Ω
PDN
RS
RL
Vab, AC
RING
PEB 4065
V2W, AC
V2W, DC
BGND
V2W
C1
C2
ΙL
ΙT
R IL
R IT
See Testcond.
Test Figure 4
AGND
VIT, AC
ITS10510
Gr =
Vab, AC
V2W, AC
G IT =
Vab, AC 1000
VIT, AC 660
Receive Gain, Transversal Current Ratio, THD, Noise and Power
Supply Rejection
Semiconductor Group
25
1998-03-01
PEB/F 4065
Electrical Characteristics
VSS
V DD
V BAT
VH
VSS
V DD
V BAT
VH
C BIM
VBIM
RS
TIP
25 k Ω
2 µF
PDN
RS
RL
Vab, AC
RING
PEB 4065
V2W, AC
V2W, DC
BGND
V2W
AGND
ΙT
ΙL
C2
C1
R IL
R IT
See Testcond.
Test Figure 5
ITS10511
Teletax Distortion
VSS
V DD
V BAT
VH
VSS
V DD
V BAT
VH
C BIM
VBIM
RS
R L/2
VLong
TIP
25 k Ω
PDN
RS
R L/2
~
~
Vab, AC
RING
PEB 4065
V2W, DC
BGND
V2W
C1
C2
AGND
ΙT
ΙL
R IL
R IT
See Testcond.
Test Figure 6
V IT
ITS10512
Longitudinal to Transversal Rejection Ratio
Semiconductor Group
26
1998-03-01
PEB/F 4065
Electrical Characteristics
VSS
V DD
V BAT
VH
VSS
V DD
V BAT
VH
C BIM
VBIM
RS
R L/2
RS
R L/2
TIP
25 k Ω
PDN
VLong, AC
Vab, AC
RING
PEB 4065
V2W, AC
V2W, DC
BGND
V2W
C1
AGND
ΙT
ΙL
C2
R IL
R IT
See Testcond.
Test Figure 7
ITS10513
Transversal to Longitudinal Rejection Ratio
VSS
V DD
V BAT
VH
VSS
V DD
V BAT
VH
C BIM
VBIM
25 k Ω
RS
TIP
PDN
CL
RL
RS
VRING
RING
PEB 4065
V2W
BGND
V2W
C1
C2
AGND
ΙT
ΙL
R IL
R IT
See Testcond.
Test Figure 8
ITS10514
Ringing
Semiconductor Group
27
1998-03-01
PEB/F 4065
Electrical Characteristics
V DD
VSS
PDN
Ι SS
C BIM
VBIM
R PDN
V DD
VSS
V BAT
Ι DD
V DD
VH
Ι BAT
V BAT
ΙH
V TIP
Ιb
VH
TIP
PDN
V BAT
Ιa
RING
PEB 4065
VRING
BGND
V2W
VBAT
AGND
ΙT
ΙL
C2
C1
R IL
R IT
See Testcond.
Test Figure 9
ITS10515
Output Resistance in PDNR Mode
V DD
VBIM
VSS
PDN
C BIM
R PDN
Ι SS
VBIM
VREF
VSS
V DD
V BAT
Ι DD
V DD
Ι BAT
V BAT
VH
ΙH
30 Ω
VH
TIP
PDN
30 Ω
RING
VH +10 V / 1 ms
VH +20 V / 1 µ s
VBAT -10 V / 1 ms
VBAT -20 V / 1 µs
PEB 4065
BGND
V2W
C1
C2
AGND
ΙT
ΙL
R IL
R IT
ITS10516
Test Figure 10
TIP, RING Overvoltage Pulses
Semiconductor Group
28
1998-03-01
PEB/F 4065
Package Outlines
3
Package Outlines
GPS05755
P-DSO-20-5
(Plastic Dual Small Outline Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
29
Dimensions in mm
1998-03-01