MC10ELT22, MC100ELT22 5VDual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. • • • • • • • • • • • http://onsemi.com MARKING DIAGRAMS* 1.2 ns Typical Propagation Delay <300 ps Typical Output to Output Skew 8 8 PNP TTL Inputs for Minimal Loading Flow Through Pinouts ESD Protection: >2 KV HBM, >200 V MM Operating Range: VCC= 4.75 V to 5.25 V with GND= 0 V SO–8 D SUFFIX CASE 751 8 HLT22 ALYW 1 1 KLT22 ALYW 1 No Internal Input Pulldown Resistors Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34 Transistor Count = 51 devices LOGIC DIAGRAM AND PINOUT ASSIGNMENT Q0 1 8 VCC Q0 7 D0 2 PECL Q1 1 TSSOP–8 DT SUFFIX CASE 948R 1 KT22 ALYW 1 L = Wafer Lot Y = Year W = Work Week ORDERING INFORMATION 6 4 HT22 ALYW H = MC10 K = MC100 A = Assembly Location Device D1 Package Shipping SO–8 98 Units/Rail MC10ELT22DR2 SO–8 2500 Tape & Reel MC100ELT22D SO–8 98 Units/Rail MC100ELT22DR2 SO–8 2500 Tape & Reel TSSOP–8 98 Units/Rail MC10ELT22DTR2 TSSOP–8 2500 Tape & Reel MC100ELT22DT TSSOP–8 98 Units/Rail MC10ELT22D Q1 8 *For additional information, see Application Note AND8002/D TTL 3 8 8 5 GND MC10ELT22DT PIN DESCRIPTION PIN FUNCTION Qn, Qn Dn VCC GND PECL Differential Outputs* TTL Inputs Positive Supply Ground MC100ELT22DTR2 TSSOP–8 2500 Tape & Reel * Output state undetermined when inputs are open. Semiconductor Components Industries, LLC, 2000 October, 2000 – Rev. 4 1 Publication Order Number: MC10ELT22/D MC10ELT22, MC100ELT22 MAXIMUM RATINGS (Note 1.) Symbol Parameter Condition 1 Rating Units 7 V 7 V 50 100 mA mA Operating Temperature Range –40 to +85 °C Storage Temperature Range –65 to +150 °C 8 SOIC 8 SOIC 190 130 °C/W °C/W std bd 8 SOIC 41 to 44 °C/W Thermal Resistance (Junction to Ambient) 0 LFPM 500 LFPM 8 TSSOP 8 TSSOP 185 140 °C/W °C/W θJC Thermal Resistance (Junction to Case) std bd 8 TSSOP 41 to 44 ± 5% °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C VCC Positive Power Supply GND = 0 V VIN Input Voltage GND = 0 V Iout Output Current Continuous Surge TA Tstg θJA Thermal Resistance (Junction to Ambient) 0 LFPM 500 LFPM θJC Thermal Resistance (Junction to Case) θJA Condition 2 VI VCC 1. Maximum Ratings are those values beyond which device damage may occur. 10ELT SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; GND = 0.0 V (Note 1.) –40°C Symbol Characteristic Min Typ 25°C Max Min Typ 22 85°C Max Min ICC Power Supply Current VOH Output HIGH Voltage (Note 2.) 3920 4010 4110 4020 4105 4190 4090 VOL Output LOW Voltage (Note 2.) 3050 3200 3350 3050 3210 3370 3050 Typ Max Unit 22 mA 4185 4280 mV 3227 3405 mV 22 NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Output parameters vary 1:1 with VCC. VCC can vary ± 0.25 V. 2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts. 100ELT SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; GND = 0.0 V (Note 1.) –40°C Symbol Characteristic Min Typ 25°C Max Min Typ 22 85°C Max Min ICC Power Supply Current VOH Output HIGH Voltage (Note 2.) 3915 3995 4120 3975 4045 4120 3975 VOL Output LOW Voltage (Note 2.) 3170 3305 3445 3190 3295 3380 3190 Typ Max Unit 22 mA 4050 4120 mV 3295 3380 mV 22 NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Output parameters vary 1:1 with VCC. VCC can vary ± 0.25 V. 2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts. http://onsemi.com 2 MC10ELT22, MC100ELT22 TTL INPUT DC CHARACTERISTICS VCC = 4.75 V to 5.25 V; TA = –40°C to 85°C Symbol Max Unit IIH Input HIGH Current Characteristic VIN = 2.7 V Condition Min Typ 20 µA IIHH Input HIGH Current VIN = 7.0 V 100 µA IIL Input LOW Current VIN = 0.5 V –0.6 mA VIK Input Clamp Diode Voltage IIN = –18 mA –1.2 V VIH Input HIGH Voltage VIL Input LOW Voltage 2.0 V 0.8 V AC CHARACTERISTICS VCC= 4.75 V to 5.25 V; GND= 0.0 V –40°C Symbol Typ 25°C Max Min Typ 85°C Characteristic Min Max fMAX Maximum Input Frequency 100 tPLH Propagation Delay (Note 1.) 1.5 V to 50% 0.6 1.2 0.9 1.2 1.5 0.6 1.35 ns tPHL Propagation Delay (Note 1.) 1.5 V to 50% 0.4 1.0 0.5 0.8 1.1 0.7 1.30 ns tJITTER Cycle–to–Cycle Jitter TBD TBD tr/tf Output Rise/Fall Time (20–80%) 1.6 0.4 100 0.4 Min 0.4 Receiver Device Qb Db 50 50 V TT V TT = V CC – 2.0 V Figure 1. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 – Termination of ECL Logic Devices.) http://onsemi.com 3 Unit MHz TBD 1.6 D Driver Device Max 100 1. Specifications for standard TTL input signal. Q Typ ps 1.6 ns MC10ELT22, MC100ELT22 Resource Reference of Application Notes AN1400 – MC10/100H640 Clock Driver Family I/O SPICE Modeling Kit AN1404 – ECLinPS Circuit Performance at Non–Standard VIH Levels AN1405 – ECL Clock Distribution Techniques AN1406 – Designing with PECL (ECL at +5.0 V) AN1503 – ECLinPS I/O SPICE Modeling Kit AN1504 – Metastability and the ECLinPS Family AN1560 – Low Voltage ECLinPS SPICE Modeling Kit AN1568 – Interfacing Between LVDS and ECL AN1596 – ECLinPS Lite Translator ELT Family SPICE I/O Model Kit AN1650 – Using Wire–OR Ties in ECLinPS Designs AN1672 – The ECL Translator Guide AND8001 – Odd Number Counters Design AND8002 – Marking and Date Codes AND8020 – Termination of ECL Logic Devices http://onsemi.com 4 MC10ELT22, MC100ELT22 PACKAGE DIMENSIONS SO–8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751–07 ISSUE V –X– NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. A 8 5 0.25 (0.010) S B 1 M Y M 4 K –Y– G C N X 45 SEATING PLANE –Z– 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M S http://onsemi.com 5 J DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 MC10ELT22, MC100ELT22 PACKAGE DIMENSIONS TSSOP–8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R–02 ISSUE A 8x 0.15 (0.006) T U K REF 0.10 (0.004) S 2X L/2 8 1 PIN 1 IDENT S T U S V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S 5 0.25 (0.010) B –U– L 0.15 (0.006) T U M M 4 A –V– F DETAIL E C 0.10 (0.004) –T– SEATING PLANE D –W– G DETAIL E http://onsemi.com 6 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0 6 INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0 6 MC10ELT22, MC100ELT22 Notes http://onsemi.com 7 MC10ELT22, MC100ELT22 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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