Freescale MC68HC08AS20CFN M68hc08 microcontroller Datasheet

MC68HC08AS20
Data Sheet
M68HC08
Microcontrollers
Rev. 4.1
MC68HC08AS20/D
July 13, 2005
freescale.com
List of Sections
Section 1. General Description. . . . . . . . . . . . . . . . . . . . . . . . . . 27
R E Q U I R E D
Advance Information — MC68HC08AS20
Section 4. Read-Only Memory (ROM) . . . . . . . . . . . . . . . . . . . . 53
Section 5. Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Section 6. Electrically Erasable
Programmable ROM (EEPROM) . . . . . . . . . . . . 59
Section 7. Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . 71
Section 8. Clock Generator Module (CGM) . . . . . . . . . . . . . . . 89
Section 9. System Integration Module (SIM) . . . . . . . . . . . . . . 117
Section 10. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . 141
Section 11. Break Module (Break) . . . . . . . . . . . . . . . . . . . . . . 147
Section 12. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . 153
Section 13. Computer Operating Properly (COP). . . . . . . . . . 163
Section 14. External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . 169
Section 15. Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . 177
Section 16. Timer Interface (TIM) . . . . . . . . . . . . . . . . . . . . . . . 199
Section 17. Serial Communications Interface (SCI) . . . . . . . . 231
Section 18. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . 271
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N O N - D I S C L O S U R E
Section 3. Random-Access Memory (RAM) . . . . . . . . . . . . . . . 51
A G R E E M E N T
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
R E Q U I R E D
Section 19. Analog-to-Digital Converter (ADC) . . . . . . . . . . . 305
Section 20. Byte Data Link Controller–Digital (BDLC–D) . . . . . 317
Section 21. Electrical Specifications . . . . . . . . . . . . . . . . . . . . 365
Section 22. Mechanical Specifications . . . . . . . . . . . . . . . . . . 379
N O N - D I S C L O S U R E
A G R E E M E N T
Section 23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 381
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MC68HC08AS20 —Rev. 4.1
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1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.1
Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . 32
1.5.2
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . 33
1.5.3
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.5.4
External Interrupt Pin (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . 33
1.5.5
Analog Power Supply Pin (VDDA/VDDAREF). . . . . . . . . . . . . 33
1.5.6
Analog Ground Pin (VSSA/VREFL) . . . . . . . . . . . . . . . . . . . . 33
1.5.7
External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . . 34
1.5.8
Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . . . 34
1.5.9
Port B I/O Pins (PTB7/ATD7–PTB0/ATD0). . . . . . . . . . . . . 34
1.5.10
Port C I/O Pins (PTC4–PTC0). . . . . . . . . . . . . . . . . . . . . . . 34
1.5.11
Port D I/O Pins (PTD6/ATD14/TCLKA–PTD0/ATD8) . . . . . 34
1.5.12
Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . . 35
1.5.13
Port F I/O Pins (PTF3/TCH5–PTF0/TCH2) . . . . . . . . . . . . . 35
1.5.14
J1850 Transmit Pin Digital (BDTxD) . . . . . . . . . . . . . . . . . . 35
1.5.15
J1850 Receive Pin Digital (BDRxD) . . . . . . . . . . . . . . . . . . 35
Section 2. Memory Map
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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R E Q U I R E D
Section 1. General Description
A G R E E M E N T
Table of Contents
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
R E Q U I R E D
Section 3. Random-Access Memory (RAM)
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
A G R E E M E N T
Section 4. Read-Only Memory (ROM)
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Section 5. Mask Options
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.4
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
N O N - D I S C L O S U R E
Section 6. Electrically Erasable
Programmable ROM (EEPROM)
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.4.1
EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.4.2
EEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.4.3
EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.4
EEPROM Redundant Mode . . . . . . . . . . . . . . . . . . . . . . . .65
6.4.5
EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.4.6
EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.4.7
EEPROM Nonvolatile Register
and EEPROM Array Configuration Register . . . . . . . . . 68
6.4.8
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.4.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.4.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.4.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.4.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.4.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.4.4
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.4.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.6
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.7
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.8
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Section 8. Clock Generator Module (CGM)
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
8.4.1
Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.4.2
Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . . 93
8.4.2.1
Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.4.2.2
Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . 95
8.4.2.3
Manual and Automatic PLL Bandwidth Modes . . . . . . . . 95
8.4.2.4
Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.4.2.5
Special Programming Exceptions . . . . . . . . . . . . . . . . . . 99
8.4.3
Base Clock Selector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . 99
8.4.4
CGM External Connections. . . . . . . . . . . . . . . . . . . . . . . . 100
8.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8.5.1
Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . 101
8.5.2
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . 101
8.5.3
External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . 101
8.5.4
Analog Power Pin (VDDA/VDDAREF). . . . . . . . . . . . . . . . . . 102
8.5.5
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . 102
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R E Q U I R E D
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
A G R E E M E N T
7.1
N O N - D I S C L O S U R E
Section 7. Central Processor Unit (CPU)
R E Q U I R E D
8.5.6
8.5.7
8.5.8
Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . 102
CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . 102
CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . 102
8.6
CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8.6.1
PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
8.6.2
PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .106
8.6.3
PLL Programming Register . . . . . . . . . . . . . . . . . . . . . . . . 108
8.7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
A G R E E M E N T
8.8
Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.9
CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 111
8.10.1
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . 111
8.10.2
Parametric Influences on Reaction Time . . . . . . . . . . . . . 113
8.10.3
Choosing a Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . . 114
8.10.4
Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . 115
N O N - D I S C L O S U R E
Section 9. System Integration Module (SIM)
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 121
9.3.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.3.2
Clock Startup from POR or LVI Reset. . . . . . . . . . . . . . . . 121
9.3.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . 122
9.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 122
9.4.1
External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.4.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . 124
9.4.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
9.4.2.2
Computer Operating Properly (COP) Reset. . . . . . . . . . 126
9.4.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.4.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .126
9.4.2.5
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . 126
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9.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
9.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
9.8.1
SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . 136
9.8.2
SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . 138
9.8.3
SIM Break Flag Control Register. . . . . . . . . . . . . . . . . . . .139
Section 10. Low-Voltage Inhibit (LVI)
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
10.4.1
Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
10.4.2
Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 143
10.5
LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
10.6
LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
10.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
10.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
10.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
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R E Q U I R E D
A G R E E M E N T
9.6
Program Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . .128
9.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.6.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.6.1.2
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.6.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
9.6.3
Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9.6.4
Status Flag Protection in Break Mode. . . . . . . . . . . . . . . . 132
N O N - D I S C L O S U R E
9.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.5.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 127
9.5.2
SIM Counter During Stop Mode Recovery . . . . . . . . . . . . 127
9.5.3
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . 127
R E Q U I R E D
Section 11. Break Module (Break)
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
A G R E E M E N T
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.4.1
Flag Protection During Break Interrupts . . . . . . . . . . . . . . 150
11.4.2
CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . 150
11.4.3
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .150
11.4.4
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . 150
11.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.5.1
Break Status and Control Register . . . . . . . . . . . . . . . . . . 151
11.5.2
Break Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.6.1
Wait or Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
N O N - D I S C L O S U R E
Section 12. Monitor ROM (MON)
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
12.4.1
Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.4.2
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.4.3
Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.4.4
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.4.5
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.4.6
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Section 13. Computer Operating Properly (COP)
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
13.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
13.4.1
CGMXCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
13.4.2
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Advance Information
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COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
13.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
13.7
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
13.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
13.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
13.9
COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 168
Section 14. External Interrupt (IRQ)
14.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
14.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
14.5
IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
14.6
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 174
14.7
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 174
Section 15. Input/Output (I/O) Ports
15.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
15.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15.3.2
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . 181
15.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
15.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
15.4.2
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . 184
15.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
15.5.1
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
15.5.2
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . 187
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Freescale Semiconductor
Advance Information
11
R E Q U I R E D
13.5
A G R E E M E N T
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Internal Reset Resources . . . . . . . . . . . . . . . . . . . . . . . . . 166
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
COPL (COP Long Timeout) . . . . . . . . . . . . . . . . . . . . . . .167
N O N - D I S C L O S U R E
13.4.3
13.4.4
13.4.5
13.4.6
13.4.7
R E Q U I R E D
15.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.6.1
Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.6.2
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . 190
15.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
15.7.1
Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
15.7.2
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . 194
A G R E E M E N T
15.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
15.8.1
Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
15.8.2
Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . . 197
Section 16. Timer Interface (TIM)
16.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
16.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
N O N - D I S C L O S U R E
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
16.4.1
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
16.4.2
Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
16.4.3
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
16.4.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 206
16.4.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .207
16.4.4
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . 208
16.4.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 209
16.4.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 210
16.4.4.3
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
16.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
16.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
16.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
16.7
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 214
16.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
16.8.1
TIM Clock Pin (PTD6/ATD14/TCLK) . . . . . . . . . . . . . . . . . 215
16.8.2
TIM Channel I/O Pins (PTF3/TCH5–PTF0/TCH2
and PTE3/TCH1–PTE2/TCH0) . . . . . . . . . . . . . . . . . . 215
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17.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
17.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
17.4.1
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
17.4.2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
17.4.3
Character Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
17.4.4
Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . 238
17.4.5
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
17.4.6
Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
17.4.7
Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . 242
17.4.8
Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
17.4.9
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
17.4.10 Character Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
17.4.11 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
17.4.12 Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
17.4.13 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
17.4.14 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
17.5 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
17.5.1
Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
17.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
17.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
17.7
SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .252
17.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
17.8.1
PTE0/TxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . . 253
17.8.2
PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . 253
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A G R E E M E N T
Section 17. Serial Communications Interface (SCI)
N O N - D I S C L O S U R E
16.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
16.9.1
TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .216
16.9.2
TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
16.9.3
TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 220
16.9.4
TIM Channel Status and Control Registers. . . . . . . . . . . . 221
16.9.5
TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
R E Q U I R E D
17.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
17.9.1
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
17.9.2
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
17.9.3
SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
17.9.4
SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
17.9.5
SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
17.9.6
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
17.9.7
SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . 268
A G R E E M E N T
Section 18. Serial Peripheral Interface (SPI)
18.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
18.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
18.4
Pin Name and Register Name Conventions . . . . . . . . . . . . . . 273
18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
18.5.1
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
18.5.2
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
N O N - D I S C L O S U R E
18.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
18.6.1
Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . 278
18.6.2
Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . 279
18.6.3
Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . 280
18.6.4
Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . 282
18.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
18.7.1
Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
18.7.2
Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
18.8
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
18.9
Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 289
18.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
18.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
18.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
18.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
18.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 293
18.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
18.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . .294
18.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . .295
Advance Information
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Freescale Semiconductor
SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
VSS (Clock Ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
18.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
18.14.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
18.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .300
18.14.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
R E Q U I R E D
18.13.3
18.13.4
18.13.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
19.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
19.4.1
ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
19.4.2
Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
19.4.3
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
19.4.4
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .309
19.4.5
Accuracy and Precision. . . . . . . . . . . . . . . . . . . . . . . . . . .309
19.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
19.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
19.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
19.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
19.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
19.7.1
ADC Analog Power Pin (VDDA/VDDAREF)/ADC
Voltage Reference Pin (VREFH) . . . . . . . . . . . . . . . . . . 310
19.7.2
ADC Analog Ground Pin (VSSA)/ADC
Voltage Reference Low Pin (VREFL). . . . . . . . . . . . . . . 310
19.7.3
ADC Voltage In (ADCVIN). . . . . . . . . . . . . . . . . . . . . . . . . 311
19.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
19.8.1
ADC Status and Control Register . . . . . . . . . . . . . . . . . . . 311
19.8.2
ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
19.8.3
ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 314
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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N O N - D I S C L O S U R E
19.1
A G R E E M E N T
Section 19. Analog-to-Digital Converter (ADC)
R E Q U I R E D
Section 20. Byte Data Link Controller–Digital (BDLC–D)
20.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
20.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
20.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
A G R E E M E N T
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
20.4.1
BDLC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 322
20.4.1.1
Power Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
20.4.1.2
Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
20.4.1.3
Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
20.4.1.4
BDLC Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
20.4.1.5
BDLC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
20.4.1.6
Digital Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . 324
20.4.1.7
Analog Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . 324
N O N - D I S C L O S U R E
20.5 BDLC MUX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
20.5.1
Rx Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
20.5.1.1
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
20.5.1.2
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
20.5.2
J1850 Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
20.5.3
J1850 VPW Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
20.5.4
J1850 VPW Valid/Invalid Bits and Symbols . . . . . . . . . . . 334
20.5.5
Message Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
20.6 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
20.6.1
Protocol Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
20.6.2
Rx and Tx Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . 341
20.6.3
Rx and Tx Shadow Registers . . . . . . . . . . . . . . . . . . . . . . 342
20.6.4
Digital Loopback Multiplexer . . . . . . . . . . . . . . . . . . . . . . . 342
20.6.5
State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
20.6.5.1
4X Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
20.6.5.2
Receiving a Message in Block Mode . . . . . . . . . . . . . . . 343
20.6.5.3
Transmitting a Message in Block Mode . . . . . . . . . . . . . 343
20.6.5.4
J1850 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
20.6.5.5
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
20.7 BDLC CPU Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
20.7.1
BDLC Analog and Roundtrip Delay. . . . . . . . . . . . . . . . . . 346
20.7.2
BDLC Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . 348
20.7.3
BDLC Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . 351
Advance Information
16
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Section 21. Electrical Specifications
21.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
21.2
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
21.3
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 367
21.4
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
21.5
5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 368
21.6
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
21.7
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
21.8
5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing . . . . . 371
21.9
CGM Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .374
21.10 CGM Component Information. . . . . . . . . . . . . . . . . . . . . . . . . 374
21.11 CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . . 375
21.12 Timer Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 376
21.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
21.14 BDLC Transmitter VPW Symbol Timings . . . . . . . . . . . . . . . . 376
21.15 BDLC Receiver VPW Symbol Timings . . . . . . . . . . . . . . . . . . 377
21.16 BDLC Transmitter DC Electrical Characteristics . . . . . . . . . . 378
21.17 BDLC Receiver DC Electrical Characteristics . . . . . . . . . . . . 378
Section 22. Mechanical Specifications
22.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
22.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
22.3
52-Pin Plastic Leaded Chip Carrier Package (Case 778). . . . 380
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
17
R E Q U I R E D
20.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
20.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
20.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
A G R E E M E N T
BDLC State Vector Register . . . . . . . . . . . . . . . . . . . . . . .358
BDLC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
N O N - D I S C L O S U R E
20.7.4
20.7.5
R E Q U I R E D
23.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
23.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
23.3
MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
23.4
Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .382
23.5
ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
23.6
ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . . 384
23.7
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
N O N - D I S C L O S U R E
A G R E E M E N T
Section 23. Ordering Information
Advance Information
18
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Page
1-1
1-2
1-3
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
52-Pin PLCC Assignments (Top View) . . . . . . . . . . . . . . . . 31
Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2-1
2-2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Control, Status, and Data Registers. . . . . . . . . . . . . . . . . . . 43
5-1
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . 56
6-1
6-2
6-3
EEPROM Control Register (EECR) . . . . . . . . . . . . . . . . . . . 66
EEPROM Array Control Register (EEACR) . . . . . . . . . . . . . 68
EEPROM Nonvolatile Register (EENVR). . . . . . . . . . . . . . . 68
7-1
7-2
7-3
7-4
7-5
7-6
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . 77
8-1
8-2
8-3
8-4
8-5
CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . 101
PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . 104
PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . 106
PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . 108
9-1
9-2
9-3
9-4
9-5
9-6
9-7
SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
CGM Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . 124
POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Hardware Interrupt Entry Timing . . . . . . . . . . . . . . . . . . . . 128
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Title
Advance Information
19
R E Q U I R E D
Figure
A G R E E M E N T
List of Figures
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
R E Q U I R E D
N O N - D I S C L O S U R E
A G R E E M E N T
Figure
Advance Information
20
Title
Page
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Hardware Interrupt Recovery Timing . . . . . . . . . . . . . . . . . 130
Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . 131
Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Wait Recovery from Interrupt or Break. . . . . . . . . . . . . . . . 134
Wait Recovery from Internal Reset . . . . . . . . . . . . . . . . . . 134
Stop Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .135
Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . 135
SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . 136
SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . 138
SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . 139
10-1
10-2
LVI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 142
LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . 143
11-1
11-2
11-3
11-4
Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 149
Break Status and Control Register (BRKSCR) . . . . . . . . . 151
Break Address Register (BRKH) . . . . . . . . . . . . . . . . . . . . 152
Break Address Register (BRKL). . . . . . . . . . . . . . . . . . . . . 152
12-1
12-2
12-3
12-4
12-5
Monitor Mode Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Monitor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 157
Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Break Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
13-1
13-2
COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . .167
14-1
14-2
14-3
IRQ Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
IRQ Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . 175
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . 180
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . 181
Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . 183
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . 184
Port B I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . 186
Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . . 187
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . 208
TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . 217
TIM Counter Registers (TCNTH and TCNTL) . . . . . . . . . . 219
TIM Counter Modulo Registers (TMODH and TMODL) . . . 220
TIM Channel Status and Control Registers (TSC0–TSC5) 221
CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
TIM Channel Registers (TCH0H/L–TCH3H/L) . . . . . . . . . . 227
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
17-12
17-13
SCI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 235
SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .244
Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . .247
SCI Control Register 1 (SCC1) . . . . . . . . . . . . . . . . . . . . . 255
SCI Control Register 2 (SCC2) . . . . . . . . . . . . . . . . . . . . . 258
SCI Control Register 3 (SCC3) . . . . . . . . . . . . . . . . . . . . . 261
SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . 262
Flag Clearing Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . .265
SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . 266
SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . 267
SCI BAUD Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . 268
18-1
18-2
18-3
18-4
18-5
18-6
18-7
SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 275
Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . 276
Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . 279
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . 281
Transmission Start Delay (Master). . . . . . . . . . . . . . . . . . . 283
Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . 285
Advance Information
21
R E Q U I R E D
Port C I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . 189
Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . 190
Port D I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . 192
Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . 194
Port E I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . 196
Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . 197
Port F I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
A G R E E M E N T
Page
15-9
15-10
15-11
15-12
15-13
15-14
15-15
15-16
15-17
15-18
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Title
N O N - D I S C L O S U R E
Figure
R E Q U I R E D
A G R E E M E N T
Figure
Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . 286
SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . 289
SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . . 290
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . 298
SPI Status and Control Register (SPSCR). . . . . . . . . . . . . 301
SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . 304
19-1
19-2
19-3
19-4
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
ADC Status and Control Register (ADSCR). . . . . . . . . . . . 311
ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . 314
ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . 314
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
BDLC Operating Modes State Diagram . . . . . . . . . . . . . . . 322
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
BDLC Rx Digital Filter Block Diagram . . . . . . . . . . . . . . . . 326
J1850 Bus Message Format (VPW). . . . . . . . . . . . . . . . . . 328
J1850 VPW Symbols with Nominal Symbol Times . . . . . . 332
J1850 VPW Received Passive Symbol Times . . . . . . . . . . 335
J1850 VPW Received Passive EOF
and IFS Symbol Times . . . . . . . . . . . . . . . . . . . . . . . . . 336
J1850 VPW Received Active Symbol Times . . . . . . . . . . . 337
J1850 VPW Received BREAK Symbol Times . . . . . . . . . . 338
J1850 VPW Bitwise Arbitrations. . . . . . . . . . . . . . . . . . . . . 339
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
BDLC Protocol Handler Outline . . . . . . . . . . . . . . . . . . . . . 341
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
BDLC Analog and Roundtrip Delay Register (BARD) . . . . 346
BDLC Control Register 1 (BCR1). . . . . . . . . . . . . . . . . . . .348
BDLC Control Register 2 (BCR2). . . . . . . . . . . . . . . . . . . .351
Types of In-Frame Response (IFR) . . . . . . . . . . . . . . . . . . 355
BDLC State Vector Register (BSVR) . . . . . . . . . . . . . . . . . 359
BDLC Data Register (BDR) . . . . . . . . . . . . . . . . . . . . . . . . 361
N O N - D I S C L O S U R E
21-1
21-2
21-3
22
Page
18-8
18-9
18-10
18-11
18-12
18-13
18-14
20-9
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
20-20
Advance Information
Title
SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
BDLC Variable Pulse Width Modulation (VPW)
Symbol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Page
1-1
1-2
External Pins Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Clock Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2-1
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6-1
6-2
6-3
EEPROM Program/Erase Cycling Reduction. . . . . . . . . . . . . 63
EEPROM Array Address Blocks. . . . . . . . . . . . . . . . . . . . . . . 64
EEPROM Program/Erase Mode Select . . . . . . . . . . . . . . . . . 67
7-1
7-2
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8-1
8-2
8-3
CGM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 93
CGM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . 103
VCO Frequency Multiplier (N) Selection. . . . . . . . . . . . . . . . 108
9-1
9-2
9-3
SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 120
Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10-1
10-2
LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 142
LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11-1
Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 149
12-1
12-2
12-3
12-4
12-5
Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . 159
WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . .160
IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . .160
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Title
Advance Information
23
R E Q U I R E D
Table
A G R E E M E N T
List of Tables
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
R E Q U I R E D
N O N - D I S C L O S U R E
A G R E E M E N T
Table
Advance Information
24
Title
Page
12-6
12-7
12-8
12-9
IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . 161
READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . 161
RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . 162
Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . 162
13-1
COP I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 164
14-1
IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 171
15-1
15-2
15-3
15-4
15-5
15-6
15-7
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Port F Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
16-1
16-2
16-3
TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 202
Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . 225
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 236
SCI Transmitter I/O Register Summary . . . . . . . . . . . . . . . . 240
SCI Receiver I/O Register Summary . . . . . . . . . . . . . . . . . . 245
Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . 257
SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . 268
SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . 270
18-1
18-2
18-3
18-4
18-5
Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
I/O Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 274
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Page
SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . 303
19-1
19-2
Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
20-1
20-2
20-3
20-4
20-5
20-6
BDLC Input/Output (I/O) Register Summary . . . . . . . . . . . . 321
BDLC J1850 Bus Error Summary. . . . . . . . . . . . . . . . . . . . . 345
BDLC Transceiver Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
BDLC Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350
BDLC Transmit In-Frame Response
Control Bit Priority Encoding . . . . . . . . . . . . . . . . . . . . . . 354
BDLC Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
23-1
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
N O N - D I S C L O S U R E
18-6
R E Q U I R E D
Title
A G R E E M E N T
Table
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
25
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Advance Information
26
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.1
Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . 32
1.5.2
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . 33
1.5.3
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.5.4
External Interrupt Pin (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . 33
1.5.5
Analog Power Supply Pin (VDDA/VDDAREF). . . . . . . . . . . . . 33
1.5.6
Analog Ground Pin (VSSA/VREFL) . . . . . . . . . . . . . . . . . . . . 33
1.5.7
External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . . 34
1.5.8
Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . . . 34
1.5.9
Port B I/O Pins (PTB7/ATD7–PTB0/ATD0). . . . . . . . . . . . . 34
1.5.10
Port C I/O Pins (PTC4–PTC0). . . . . . . . . . . . . . . . . . . . . . . 34
1.5.11
Port D I/O Pins (PTD6/ATD14/TCLKA–PTD0/ATD8) . . . . . 34
1.5.12
Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . . 35
1.5.13
Port F I/O Pins (PTF3/TCH5–PTF0/TCH2) . . . . . . . . . . . . . 35
1.5.14
J1850 Transmit Pin Digital (BDTxD) . . . . . . . . . . . . . . . . . . 35
1.5.15
J1850 Receive Pin Digital (BDRxD) . . . . . . . . . . . . . . . . . . 35
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
27
R E Q U I R E D
1.1 Contents
A G R E E M E N T
Section 1. General Description
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
R E Q U I R E D
The MC68HC08AS20 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
1.3 Features
Features of the MC68HC08AS20 include:
N O N - D I S C L O S U R E
A G R E E M E N T
1.2 Introduction
Advance Information
28
•
High-Performance M68HC08 Architecture
•
Fully Upward-Compatible Object Code with M6805, M146805,
and M68HC05 Families
•
8.4-MHz Internal Bus Frequency
•
20,480 Bytes of Read-Only Memory (ROM)
•
ROM Data Security
•
512 Bytes of On-Chip Electrically Erasable Programmable
Read-Only Memory (EEPROM)
•
640 Bytes of On-Chip RAM
•
Serial Peripheral Interface Module (SPI)
•
Serial Communications Interface Module (SCI)
•
16-Bit, 6-Channel Timer Interface Module (TIM)
•
Clock Generator Module (CGM)
•
8-Bit, 15-Channel Analog-to-Digital Converter Module (ADC)
•
SAE J1850 Byte Data Link Controller Digital Module (BDLC–D)
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
•
System Protection Features
– Computer Operating Properly (COP) with Optional Reset
– Low-Voltage Detection with Optional Reset
– Illegal Opcode Detection with Optional Reset
– Illegal Address Detection with Optional Reset
•
Low-Power Design (Fully Static with Stop and Wait Modes)
•
Master Reset Pin and Power-On Reset
Enhanced HC05 Programming Model
•
Extensive Loop Control Functions
•
16 Addressing Modes (Eight More Than the HC05)
•
16-Bit Index Register and Stack Pointer
•
Memory-to-Memory Data Transfers
•
Fast 8 × 8 Multiply Instruction
•
Fast 16/8 Divide Instruction
•
Binary-Coded Decimal (BCD) Instructions
•
Optimization for Controller Applications
•
C Language Support
N O N - D I S C L O S U R E
•
A G R E E M E N T
Features of the CPU08 include:
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC08AS20.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
29
CONTROL AND STATUS REGISTERS — 69 BYTES
BREAK
MODULE
PTA
ANALOG-TO-DIGITAL CONVERTER
MODULE
DDRA
ARITHMETIC/LOGIC
UNIT
PTA7–PTA0
PTB
CPU
REGISTERS
VREFH
PTB7/ATD7–PTB0/ATD0
PTC4–PTC3
PTC2/MCLK
PTC1–PTC0
DDRC
Advance Information
30
INTERNAL BUS
M68HC08 CPU
R E Q U I R E D
DDRB
A G R E E M E N T
PTC
N O N - D I S C L O S U R E
USER ROM — 20,480 BYTES
LOW-VOLTAGE INHIBIT
MODULE
PTD
PTD5/ATD13–PTD0/ATD8
PTE7/SPSCK
PTE6/MOSI
PTE5/MISO
PTE4/SS
PTE3/TCH1
PTE2/TCH0
PTE1/RxD
PTE0/TxD
PTF
MONITOR ROM — 224 BYTES
PTD6/ATD14/TCLK
PTE
USER RAM — 640 BYTES
COMPUTER OPERATING PROPERLY
MODULE
DDRD
USER EEPROM — 512 BYTES
PTF3/TCH5
PTF2/TCH4
PTF1/TCH3
PTF0/TCH2
TIMER INTERFACE
MODULE
RST
IRQ
CLOCK GENERATOR
MODULE
SERIAL PERIPHERAL INTERFACE
MODULE
SYSTEM INTEGRATION
MODULE
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
VDDA/VDDAREF
VSSA/VREFL
BYTE DATA LINK CONTROLLER
DIGITAL MODULE
IRQ
MODULE
POWER-ON RESET
MODULE
VSS
VDD
SERIAL COMMUNICATIONS INTERFACE
MODULE
BDRxD
BDTxD
POWER
Figure 1-1. MCU Block Diagram
DDRF
OSC1
OSC2
CGMXFC
DDRE
USER ROM VECTOR SPACE — 36 BYTES
R E Q U I R E D
1.5 Pin Assignments
VREFH
PTD6/ATD14/TCLK
PTD5/ATD13
50
49
48
47
46
PTD3/ATD11
IRQ
9
45
PTD2/ATD10
RST
10
44
PTD1/ATD9
PTF0/TCH2
11
43
PTD0/ATD8
PTF1/TCH3
12
42
PTB7/ATD7
PTF2/TCH4
13
41
PTB6/ATD6
PTF3/TCH5
14
40
PTB5/ATD5
BDRxD
15
39
PTB4/ATD4
BDTxD
16
38
PTB3/ATD3
PTE0/TxD
17
37
PTB2/ATD2
PTE1/RxD
18
36
PTB1/ATD1
PTE2/TCH0
19
35
PTB0/ATD0
34
21
22
23
24
25
26
27
28
29
30
31
32
33
PTE5/MISO
PTE6/MOSI
PTE7/SPSCK
VSS
VDD
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
20
PTE4/SS
PTE3/TCH1
A G R E E M E N T
8
N O N - D I S C L O S U R E
PTC4
PTD4/ATD12
VDDA/VDDAREF
OSC2
2
51
OSC1
3
VSSA/VREFL
PTC0
4
52
PTC1
5
CGMXFC
PTC2/MCLK
6
1
PTC3
7
Figure 1-2 shows the 52-pin PLCC assignments.
PTA7
Figure 1-2. 52-Pin PLCC Assignments (Top View)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
31
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-3
shows. Place the C1 bypass capacitor as close to the MCU as possible.
Use a high-frequency-response ceramic capacitor for C1. C2 is an
optional bulk current bypass capacitor for use in applications that require
the port pins to source high current levels.
A G R E E M E N T
R E Q U I R E D
1.5.1 Power Supply Pins (VDD and VSS)
MCU
VSS
VDD
C1
0.1 µF
N O N - D I S C L O S U R E
+
C2
VDD
NOTE: Component values shown represent typical applications.
Figure 1-3. Power Supply Bypassing
VSS is also the ground for the port output buffers and the ground return
for the serial clock in the serial peripheral interface module (SPI). (See
Section 18. Serial Peripheral Interface (SPI).)
NOTE:
Advance Information
32
VSS must be grounded for proper MCU operation.
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
A logic 0 on the RST pin forces the MCU to a known startup state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. (See Section 9. System
Integration Module (SIM) for more information.)
1.5.4 External Interrupt Pin (IRQ)
IRQ is an asynchronous external interrupt pin. (See Section 14.
External Interrupt (IRQ).)
1.5.5 Analog Power Supply Pin (VDDA/VDDAREF)
VDDA/VDDAREF is the power supply pin for the analog portion of the chip.
These modules are the analog-to-digital converter (ADC) and the clock
generator module (CGM). (See Section 8. Clock Generator Module
(CGM) and Section 19. Analog-to-Digital Converter (ADC).)
1.5.6 Analog Ground Pin (VSSA/VREFL)
The VSSA/VREFL analog ground pin is used only for the ground
connections for the analog sections of the circuit and should be
decoupled as per the VSS digital ground pin. The analog sections consist
of a clock generator module (CGM) and an analog-to-digital converter
(ADC). VSSA/VREFL is also the lower reference supply for the ADC. (See
Section 8. Clock Generator Module (CGM) and Section 19.
Analog-to-Digital Converter (ADC).)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
33
R E Q U I R E D
1.5.3 External Reset Pin (RST)
A G R E E M E N T
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. (See Section 8. Clock Generator Module (CGM).)
N O N - D I S C L O S U R E
1.5.2 Oscillator Pins (OSC1 and OSC2)
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
1.5.7 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. (See
Section 8. Clock Generator Module (CGM).)
1.5.8 Port A Input/Output (I/O) Pins (PTA7–PTA0)
PTA7–PTA0 are general-purpose bidirectional I/O port pins. (See
Section 15. Input/Output (I/O) Ports.)
1.5.9 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0)
Port B is an 8-bit special function port that shares all eight pins with the
analog-to-digital converter (ADC). (See Section 19. Analog-to-Digital
Converter (ADC) and Section 15. Input/Output (I/O) Ports.)
1.5.10 Port C I/O Pins (PTC4–PTC0)
PTC4–PTC3 and PTC1–PTC0 are general-purpose bidirectional I/O
port pins. PTC2/MCLK is a special function port that shares its pin with
the system clock. (See Section 15. Input/Output (I/O) Ports.)
1.5.11 Port D I/O Pins (PTD6/ATD14/TCLKA–PTD0/ATD8)
Port D is a 7-bit special function port that shares all of its pins with the
analog-to-digital converter module (ADC) and one of its pins with the
timer interface module (TIM). (See Section 16. Timer Interface (TIM),
Section 19. Analog-to-Digital Converter (ADC), and
Section 15. Input/Output (I/O) Ports.)
Advance Information
34
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
1.5.13 Port F I/O Pins (PTF3/TCH5–PTF0/TCH2)
Port F is a 4-bit special function port that shares all of its pins with the
timer interface module (TIM). (See Section 16. Timer Interface (TIM)
and Section 15. Input/Output (I/O) Ports.)
1.5.14 J1850 Transmit Pin Digital (BDTxD)
BDTxD is a serial digital output data physical interface to the J1850. (See
Section 20. Byte Data Link Controller–Digital (BDLC–D).)
R E Q U I R E D
Port E is an 8-bit special function port that shares two of its pins with the
timer interface module (TIM), four of its pins with the serial peripheral
interface module (SPI), and two of its pins with the serial communication
interface module (SCI). (See Section 17. Serial Communications
Interface (SCI), Section 18. Serial Peripheral Interface (SPI), Section
16. Timer Interface (TIM), and Section 15. Input/Output (I/O) Ports.)
A G R E E M E N T
1.5.12 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD)
BDRxD is a serial digital input data physical interface from the J1850.
(See Section 20. Byte Data Link Controller–Digital (BDLC–D).)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
35
N O N - D I S C L O S U R E
1.5.15 J1850 Receive Pin Digital (BDRxD)
R E Q U I R E D
Pin Name
Function
Driver Type
Hysteresis
Reset State
PTA7–PTA0
General-Purpose I/O
Dual State
No
Input, Hi-Z
PTB7/ATD7–
PTB0/ATD0
General-Purpose I/O
ADC Channel
Dual State
No
Input, Hi-Z
PTC4–PTC3
General-Purpose I/O
Dual State
No
Input, Hi-Z
PTC2/MCLK
General-Purpose I/O,
Bus Clock Output
Dual State
No
Input, Hi-Z
PTC1–PTC0
General-Purpose I/O
Dual State
No
Input, Hi-Z
PTD6/ATD14/TCLK
General-Purpose I/O
ADC Channel/Timer External
Input Clock
Dual State
No
Input, Hi-Z
PTD5/ATD13–
PTD0/ATD8
General-Purpose/O
ADC Channel
Dual State
No
Input, Hi-Z
PTE7/SPSCK
General-Purpose I/O
SPI Clock
Dual State
Open Drain
Yes
Input, Hi-Z
PTE6/MOSI
General-Purpose I/O
SPI Data Path
Dual State
Open Drain
Yes
Input, Hi-Z
PTE5/MISO
General-Purpose I/O
SPI Data Path
Dual State
Open Drain
Yes
Input, Hi-Z
PTE4/SS
General-Purpose I/O
SPI Slave Select
Dual State
Yes
Input, Hi-Z
PTE3/TCH1
General-Purpose I/O
Timer Channel 1
Dual State
Yes
Input, Hi-Z
PTE2/TCH0
General-Purpose I/O
Timer Channel 0
Dual State
Yes
Input, Hi-Z
PTE1/RxD
General-Purpose I/O
SCI Receive Data
Dual State
Yes
Input, Hi-Z
PTE0/TxD
General-Purpose I/O
SCI Transmit Data
Dual State
Yes
Input, Hi-Z
PTF3/TCH5
General-Purpose I/O
Timer Channel 5
Dual State
Yes
Input, Hi-Z
PTF2/TCH4
General-Purpose I/O
Timer Channel 4
Dual State
Yes
Input, Hi-Z
PTF1/TCH3
General-Purpose I/O
Timer Channel 3
Dual State
Yes
Input, Hi-Z
N O N - D I S C L O S U R E
A G R E E M E N T
Table 1-1. External Pins Summary
Advance Information
36
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Function
Driver Type
Hysteresis
Reset State
PTF0/TCH2
General-Purpose I/O
Timer Channel 2
Dual State
Yes
Input, Hi-Z
VDD
Chip Power Supply
N/A
N/A
N/A
VSS
Chip Ground
N/A
N/A
N/A
VDDA/VDDAREF
Analog Power Supply
(CGM and ADC)
N/A
N/A
N/A
VSSA/VREFL
Analog Ground
A/D Reference Voltage
N/A
N/A
N/A
VREFH
A/D Reference Voltage
N/A
N/A
N/A
OSC1
External Clock In
N/A
N/A
Input, Hi-Z
OSC2
External Clock Out
N/A
N/A
Output
CGMXFC
PLL Loop Filter Cap
N/A
N/A
N/A
IRQ
External Interrupt Request
N/A
N/A
Input, Hi-Z
RST
Reset
N/A
N/A
Output Low
BDRxD
BDLC-D Serial Input
N/A
No
Input, Hi-Z
BDTxD
BDLC-D Serial Output
Output
No
Output Low
N O N - D I S C L O S U R E
A G R E E M E N T
Pin Name
R E Q U I R E D
Table 1-1. External Pins Summary (Continued)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
37
R E Q U I R E D
Module
Clock Source
ADC
CGMXCLK or Bus Clock
BDLC
CGMXCLK
COP
CGMXCLK
CPU
Bus Clock
EEPROM
Internal RC Oscillator or Bus Clock
SPI
Bus Clock/SPSCK
SCI
CGMXCLK
TIM
Bus Clock or PTD6/ATD14/TCLK
SIM
CGMOUT and CGMXCLK
IRQ
Bus Clock
BRK
Bus Clock
LVI
Bus Clock
CGM
OSC1 and OSC2
N O N - D I S C L O S U R E
A G R E E M E N T
Table 1-2. Clock Source Summary
Advance Information
38
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.2 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory
map, shown in Figure 2-1, includes:
•
20,480 bytes of user ROM
•
640 bytes of RAM
•
512 bytes of EEPROM
•
36 bytes of user-defined vectors
•
224 bytes of monitor ROM
These definitions apply to the memory map representation of reserved
and unimplemented locations.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
•
Reserved — Accessing a reserved location can have
unpredictable effects on MCU operation.
•
Unimplemented — Accessing an unimplemented location
causes an illegal address reset if illegal address resets are
enabled.
Advance Information
39
R E Q U I R E D
2.1 Contents
A G R E E M E N T
Section 2. Memory Map
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
R E Q U I R E D
$0000
↓
$003F
I/O REGISTERS — 58 BYTES
($000A, $000B, $000E, $000F, $001B, AND $0021
ARE UNIMPLEMENTED)
$0040
↓
UNIMPLEMENTED — 16 BYTES
$004F
$0050
A G R E E M E N T
↓
RAM — 640 BYTES
$02CF
$02D0
↓
$07FF
RESERVED — 2 BYTES
UNIMPLEMENTED — 1326 BYTES
$0800
↓
EEPROM — 512 BYTES
$09FF
$0A00
↓
N O N - D I S C L O S U R E
$ADFF
RESERVED — 2 BYTES
UNIMPLEMENTED — 41,982 BYTES
$AE00
↓
ROM — 20,480 BYTES
$FDFF
$FE00
SIM BREAK STATUS REGISTER (SBSR)
$FE01
SIM RESET STATUS REGISTER (SRSR)
$FE02
RESERVED
$FE03
SIM BREAK FLAG CONTROL REGISTER (SBFCR)
$FE04
RESERVED
$FE05
RESERVED
$FE06
RESERVED
$FE07
RESERVED
Figure 2-1. Memory Map
Advance Information
40
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
$FE09
RESERVED
$FE0A
RESERVED
$FE0B
RESERVED
$FE0C
BREAK ADDRESS REGISTER HIGH (BRKH)
$FE0D
BREAK ADDRESS REGISTER LOW (BRKL)
$FE0E
BREAK STATUS AND CONTROL REGISTER (BRKSCR)
$FE0F
LVI STATUS REGISTER (LVISR)
R E Q U I R E D
RESERVED
A G R E E M E N T
$FE08
$FE10
↓
RESERVED — 12 BYTES
$FE1B
$FE1C
EEPROM NONVOLATILE REGISTER (EENVR)
$FE1D
EEPROM CONTROL REGISTER (EECR)
$FE1E
RESERVED
$FE1F
EEPROM ARRAY CONFIGURATION REGISTER (EEACR)
$FE20
↓
MONITOR ROM — 224 BYTES
N O N - D I S C L O S U R E
$FEFF
$FF00
↓
UNIMPLEMENTED — 220 BYTES
$FFDB
$FFDC
↓
INTERRUPT AND RESET VECTORS — 36 BYTES
$FFFF
Figure 2-1. Memory Map (Continued)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
41
Addresses $0000–$003F, shown in Figure 2-2, contain most of the
control, status, and data registers. Additional I/O registers have these
addresses:
A G R E E M E N T
R E Q U I R E D
2.3 Input/Output (I/O) Section
•
$FE00, SIM break status register, SBSR
•
$FE01, SIM reset status register, SRSR
•
$FE03, SIM break flag control register, SBFCR
•
$FE0C and $FE0D, break address registers, BRKH and BRKL
•
$FE0E, break status and control register, BRKSCR
•
$FE0F, LVI status register, LVISR
•
$FE1C, EEPROM nonvolatile register, EENVR
•
$FE1D, EEPROM control register, EECR
•
$FE1F, EEPROM array configuration register, EEACR
•
$FFFF, COP control register, COPCTL
N O N - D I S C L O S U R E
Table 2-1 is a list of vector locations.
Advance Information
42
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
Read:
Port B Data Register
Write:
(PTB)
Reset:
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC2
PTC1
PTC0
PTD2
PTD1
PTD0
DDRA2
DDRA1
DDRA0
Unaffected by Reset
PTB7
0
Read:
Port D Data Register
Write:
(PTD)
Reset:
0
R
PTB3
0
0
PTC4
PTC3
PTD6
PTD5
PTD4
PTD3
Unaffected by Reset
Read:
DDRB7
Data Direction Register B
Write:
(DDRB)
Reset:
0
DDRA6
DDRA5
DDRA4
DDRA3
Unaffected by Reset
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
0
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDR2
DDRD1
DDRD0
0
0
0
0
0
0
0
0
PTE7
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
PTF2
PTF1
PTF0
Read:
MCLKEN
Data Direction Register C
Write:
(DDRC)
Reset:
0
Read:
Port F Data Register
Write:
(PTF)
Reset:
PTB4
Unaffected by Reset
Read:
DDRA7
Data Direction Register A
Write:
(DDRA)
Reset:
Read:
Port E Data Register
Write:
(PTE)
Reset:
PTB5
Unaffected by Reset
Read:
Port C Data Register
Write:
(PTC)
Reset:
Read:
Data Direction Register D
Write:
(DDRD)
Reset:
PTB6
0
0
Unaffected by Reset
0
0
0
0
PTF3
Unaffected by Reset
$000A
= Unimplemented
R
= Reserved
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 7)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
43
R E Q U I R E D
$0001
Read:
Port A Data Register
Write:
(PTA)
Reset:
Bit 7
A G R E E M E N T
$0000
Register Name
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
A G R E E M E N T
Addr.
Bit 7
6
5
4
3
2
1
Bit 0
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
0
0
0
0
0
0
DDRF3
DDRF2
DDRF1
DDRF0
0
0
0
0
0
0
0
0
SPRIE
R
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
0
0
1
0
1
0
0
0
OVRF
MODF
SPTE
MODFEN
SPR1
SPR0
$000B
$000C
$000D
Read:
DDRE7
Data Direction Register E
Write:
(DDRE)
Reset:
0
Read:
Data Direction Register F
Write:
(DDRF)
Reset:
$000E
$000F
$0010
$0011
$0012
N O N - D I S C L O S U R E
Register Name
$0013
$0014
$0015
$0016
Read:
SPI Control Register
Write:
(SPCR)
Reset:
Read:
SPI Status and Control
Write:
Register (SPSCR)
Reset:
Read:
SPI Data Register
Write:
(SPDR)
Reset:
SPRF
0
0
0
0
1
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Indeterminate after Reset
Read:
LOOPS
SCI Control Register 1
Write:
(SCC1)
Reset:
0
Read:
SCI Control Register 2
Write:
(SCC2)
Reset:
ERRIE
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
T8
R
R
ORIE
NEIE
FEIE
PEIE
Read:
SCI Control Register 3
Write:
(SCC3)
Reset:
R8
U
U
0
0
0
0
0
0
Read:
SCI Status Register 1
Write:
(SCS1)
Reset:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
R
R
R
R
R
R
R
R
1
1
0
0
0
0
0
0
R
= Reserved
= Unimplemented
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 7)
Advance Information
44
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
$0019
$001A
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
BKF
RPF
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
SCI Data Register
Write:
(SCDR)
Reset:
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Read:
SCI Baud Rate Register
Write:
(SCBR)
Reset:
0
0
SCR2
SCR1
SCR0
0
0
0
0
IMASK
MODE
Read:
SCI Status Register 2
Write:
(SCS2)
Reset:
Read:
IRQ Status and Control
Write:
Register (ISCR)
Reset:
Unaffected by Reset
SCP1
SCP0
0
0
0
0
0
0
0
0
IRQF
0
ACK
0
0
0
0
$001B
$001C
$001D
$001E
$001F
$0020
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
Reserved
Read:
PLL Control Register
Write:
(PCTL)
Reset:
Read:
PLL Bandwidth Control
Write:
Register (PBWC)
Reset:
Read:
PLL Programming Register
Write:
(PPG)
Reset:
Read:
Mask Option Register
Write:
(MOR)
Reset:
Read:
TIM Status and Control
Write:
Register (TSC)
Reset:
PLLIE
0
AUTO
PLLF
0
LOCK
PLLON
BCS
1
0
ACQ
XLD
0
0
0
0
0
0
0
0
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
0
1
1
0
0
1
1
0
COPL
STOP
COPD
R
R
R
PS2
PS1
PS0
0
0
0
0
R
ROMSEC LVIRSTD LVIPWRD SSREC
R
R
R
R
Unaffected by Reset
TOF
0
0
TOIE
TSTOP
0
1
0
0
TRST
0
$0021
$0022
0
Reserved
Read:
TIM Counter Register High
Write:
(TCNTH)
Reset:
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
R
= Reserved
= Unimplemented
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 7)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
45
R E Q U I R E D
$0018
Bit 7
A G R E E M E N T
$0017
Register Name
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
$0023
Read:
TIM Counter Register Low
Write:
(TCNTL)
Reset:
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
$0024
A G R E E M E N T
$0025
$0026
$0027
$0028
N O N - D I S C L O S U R E
$0029
$002A
$002B
$002C
$002D
Read:
TIM Modulo Register High
Write:
(TMODH)
Reset:
Read:
TIM Modulo Register Low
Write:
(TMODL)
Reset:
Read:
TIM Channel 0 Status and
Write:
Control Register (TSC0)
Reset:
Read:
TIM Channel 0 Register High
Write:
(TCH0H)
Reset:
Read:
TIM Channel 0 Register Low
Write:
(TCH0L)
Reset:
Read:
TIM Channel 1 Status and
Write:
Control Register (TSC1)
Reset:
Read:
TIM Channel 1 Register High
Write:
(TCH1H)
Reset:
Read:
TIM Channel 1 Register Low
Write:
(TCH1L)
Reset:
Read:
TIM Channel 2 Status and
Write:
Control Register (TSC2)
Reset:
Read:
TIM Channel 2 Register High
Write:
(TCH2H)
Reset:
CH0F
0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH1F
0
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH2F
CH2IE
MS2B
MS2A
ELS2B
ELS2A
TOV2
CH2MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
0
Indeterminate after Reset
= Unimplemented
R
= Reserved
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 7)
Advance Information
46
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
$002F
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
Read:
TIM Channel 3 Status and
Write:
Control Register (TSC3)
Reset:
Read:
TIM Channel 3 Register High
Write:
(TCH3H)
Reset:
Read:
TIM Channel 3 Register Low
Write:
(TCH3L)
Reset:
Read:
TIM Channel 4 Status and
Write:
Control Register (TSC4)
Reset:
Read:
TIM Channel 4 Register High
Write:
(TCH4H)
Reset:
Read:
TIM Channel 4 Register Low
Write:
(TCH4L)
Reset:
Read:
TIM Channel 5 Status and
Write:
Control Register (TSC5)
Reset:
Read:
TIM Channel 5 Register High
Write:
(TCH5H)
Reset:
Read:
TIM Channel 5 Register Low
Write:
(TCH5L)
Reset:
Read:
ADC Status and Control
Write:
Register (ADSCR)
Reset:
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after Reset
CH3F
0
CH3IE
0
MS3A
ELS3B
ELS3A
TOV3
CH3MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH4F
CH4IE
MS4B
MS4A
ELS4B
ELS4A
TOV4
CH4MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH5F
0
CH5IE
0
MS5A
ELS5B
ELS5A
TOV5
CH5MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
COCO
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
0
0
1
1
1
1
1
R
= Reserved
= Unimplemented
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 7)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
$002E
Read:
TIM Channel 2 Register Low
Write:
(TCH2L)
Reset:
Bit 7
A G R E E M E N T
Register Name
Advance Information
47
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
$0039
Read:
ADC Data Register
Write:
(ADR)
Reset:
0
0
0
0
0
0
0
0
BO3
BO2
BO1
BO0
0
1
1
1
0
0
R
R
IE
WCM
$003A
A G R E E M E N T
$003B
$003C
$003D
$003E
Read:
BDLC Analog and Roundtrip
Write:
Delay Register (BARD)
Reset:
Read:
BDLC Control Register 1
Write:
(BCR1)
Reset:
ADIV2
ADIV1
ADIV0
ADICLK
0
0
0
0
ATE
RXPOL
0
0
1
1
0
0
IMSG
CLKS
R1
R0
1
1
1
0
0
0
0
0
DLOOP
RX4XE
NBFS
TEOD
TSIFR
TMIFR1
TMIFR0
1
0
0
0
0
0
0
0
0
I3
I2
I1
I0
0
0
0
0
0
0
0
0
0
0
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
R
SBSW
R
Read:
ALOOP
BDLC Control Register
Write:
(BCR2)
Reset:
1
Read:
BDLC State Vector Register
Write:
(BSVR)
Reset:
Read:
$003F
N O N - D I S C L O S U R E
Read:
ADC Input Clock Register
Write:
(ADICLK)
Reset:
Indeterminate after Reset
BDLC Data Register (BDR) Write:
Reset:
$FE00
$FE01
$FE03
Read:
SIM Break Status Register
Write:
(SBSR)
Reset:
Read:
SIM Reset Status Register
Write:
(SRSR)
Reset:
Read:
SIM Break Flag Control
Write:
Register (SBFCR)
Reset:
Indeterminate after Reset
R
R
R
R
R
0
POR
PIN
COP
ILOP
ILAD
0
LVI
0
1
X
0
0
0
0
X
0
BCFE
R
R
R
R
R
R
R
0
$FE07
Reserved
= Unimplemented
R
= Reserved
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 7)
Advance Information
48
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
$FE0E
Read:
Break Address Register Low
Write:
(BRKL)
Reset:
Read:
Break Status and Control
Write:
Register (BRKSCR)
Reset:
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
Read: LVIOUT
$FE0F
LVI Status Register (LVISR) Write:
Reset:
Read:
EEPROM Nonvolatile Register
Write:
$FE1C
(EENVR)
Reset:
$FE1D
0
EERA
Read:
EEBCLK
EEPROM Control Register
Write:
(EECR)
Reset:
0
0
0
0
EEBP3
EEBP2
EEBP1
EEBP0
0
0
EEOFF
0
EERAS1 EERAS0
0
0
EELAT
EEPGM
0
0
0
0
Reserved
EEPROM Array Control Read:
Register (EEACR) Write:
Reset:
$FFFF
0
Bits 7, 3, 2, 1, and 0 programmed value or 1 in the erased state.
$FE1E
$FE1F
LVISTOP LVILCK
COP Control Register Read:
(COPCTL) Write:
EERA
R
R
R
EEBP3
EEBP2
EEBP1
EEBP0
R
R
R
R
R
R
R
R
All bits load their contents from EENVR at reset.
LOW BYTE OF RESET VECTOR
WRITING TO $FFFF CLEARS COP COUNTER
Reset:
Unaffected by Reset
= Unimplemented
R
= Reserved
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 7)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
$FE0D
Read:
Break Address Register High
Write:
(BRKH)
Reset:
Bit 7
A G R E E M E N T
$FE0C
Register Name
N O N - D I S C L O S U R E
Addr.
Advance Information
49
R E Q U I R E D
Table 2-1. Vector Addresses
High
N O N - D I S C L O S U R E
Priority
A G R E E M E N T
Low
Address
Advance Information
50
Vector
$FFDC
BDLC Vector (High)
$FFDD
BDLC Vector (Low)
$FFDE
ADC Vector (High)
$FFDF
ADC Vector (Low)
$FFE0
SCI Transmit Vector (High)
$FFE1
SCI Transmit Vector (Low)
$FFE2
SCI Receive Vector (High)
$FFE3
SCI Receive Vector (Low)
$FFE4
SCI Error Vector (High)
$FFE5
SCI Error Vector (Low)
$FFE6
SPI Transmit Vector (High)
$FFE7
SPI Transmit Vector (Low)
$FFE8
SPI Receive Vector (High)
$FFE9
SPI Receive Vector (Low)
$FFEA
TIM Overflow Vector (High)
$FFEB
TIM Overflow Vector (Low)
$FFEC
TIM Channel 5 Vector (High)
$FFED
TIM Channel 5 Vector (Low)
$FFEE
TIM Channel 4 Vector (High)
$FFEF
TIM Channel 4 Vector (Low)
$FFF0
TIM Channel 3 Vector (High)
$FFF1
TIM Channel 3 Vector (Low)
$FFF2
TIM Channel 2 Vector (High)
$FFF3
TIM Channel 2 Vector (Low)
$FFF4
TIM Channel 1 Vector (High)
$FFF5
TIM Channel 1 Vector (Low)
$FFF6
TIM Channel 0 Vector (High)
$FFF7
TIM Channel 0 Vector (Low)
$FFF8
PLL Vector (High)
$FFF9
PLL Vector (Low)
$FFFA
IRQ Vector (High)
$FFFB
IRQ Vector (Low)
$FFFC
SWI Vector (High)
$FFFD
SWI Vector (Low)
$FFFE
Reset Vector (High)
$FFFF
Reset Vector (Low)
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.2 Introduction
This section describes the 640 bytes of random-access memory (RAM).
3.3 Functional Description
Addresses $0050–$02CF are RAM locations. The location of the stack
RAM is programmable. The 16-bit stack pointer allows the stack to be
anywhere in the 640-byte memory space.
NOTE:
For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 176 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for input/output (I/O) control and user data or code. When the stack
pointer is moved from its reset location at $00FF, direct addressing
mode instructions can access all page zero RAM locations efficiently.
Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE:
For M68HC05, M6805, and M146805 compatibility, the H register is not
stacked.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
51
R E Q U I R E D
3.1 Contents
A G R E E M E N T
Section 3. Random-Access Memory (RAM)
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
R E Q U I R E D
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
Be careful when using nested subroutines. The CPU could overwrite
data in the RAM during a subroutine or during the interrupt stacking
operation.
N O N - D I S C L O S U R E
A G R E E M E N T
NOTE:
Advance Information
52
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.2 Introduction
This section describes the 20,480 bytes of user read-only memory
(ROM), 224 bytes of monitor ROM, and 36 bytes of user vectors.
4.3 Functional Description
N O N - D I S C L O S U R E
The user ROM consists of 20,480 bytes of ROM from addresses
$AE00–$FDFF. The monitor ROM and vectors are located from
$FE20–$FEFF. See Figure 2-1. Memory Map.
Thirty-six of the user vectors, $FFDC–$FFFF, are dedicated to
user-defined reset and interrupt vectors.
Security has been incorporated into the MC68HC08AS20 to prevent
external viewing of the ROM contents. This feature ensures that
customer-developed software remains proprietary.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
Section 4. Read-Only Memory (ROM)
A G R E E M E N T
Advance Information — MC68HC08AS20
Advance Information
53
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Advance Information
54
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.4
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.2 Introduction
N O N - D I S C L O S U R E
This section describes use of mask options by custom-masked ROMs
and the mask option register in the MC68HC08AS20.
R E Q U I R E D
Section 5. Mask Options
A G R E E M E N T
Advance Information — MC68HC08AS20
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
55
The mask options are hard-wired connections, specified at the same
time as the ROM code, which allow the user to customize the MCU. The
options control the enable or disable ability of the following functions:
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
5.3 Functional Description
•
ROM security1
•
Resets caused by the LVI module
•
Power to the LVI module
•
Stop mode recovery time (32 CGMXCLK cycles or 4096
CGMXCLK cycles)
•
COP timeout period (8,176 CGMXCLK cycles or 262,128
CGMXCLK cycles)
•
STOP instruction
•
Computer operating properly module (COP)
The mask option register ($001F) is used in the initialization of various
options. For error free compatibility with the emulator OTP
(M68HC708AS48CFN), a write to $001F in the MC68HC08AS20 has no
effect in MCU operation.
5.4 Mask Option Register
Address:
$001F
Bit 7
Read:
Write:
R
6
5
4
ROMSEC LVIRSTD LVIPWRD
R
Reset:
R
R
3
2
1
Bit 0
SSREC
COPL
STOP
COPD
R
R
R
R
Unaffected by Reset
R
= Reserved
Figure 5-1. Mask Option Register (MOR)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the ROM data difficult for unauthorized users.
Advance Information
56
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
LVIPWRD— LVI Power Disable Bit
LVIPWRD disables the LVI module. (See Section 10. Low-Voltage
Inhibit (LVI).)
1 = LVI module power disabled
0 = LVI module power enabled
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. (See
Section 10. Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
SSREC — Short Stop Recovery Bit
NOTE:
N O N - D I S C L O S U R E
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. (See
16.6.2 Stop Mode.)
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
If using an external crystal oscillator, do not set the SSREC bit.
COPL— COP Long Timeout Bit
COPL selects the long COP timeout period. (See Section 13.
Computer Operating Properly (COP).)
1 = COP timeout period is 262,128 CGMXCLK cycles
0 = COP timeout period is 8,176 CGMXCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
ROMSEC enables the ROM security feature. Setting the ROMSEC bit
prevents reading of the ROM contents. Access to the ROM is denied
to unauthorized users of customer specified software.
1 = ROM security enabled
0 = ROM security disabled
A G R E E M E N T
ROMSEC — ROM Security Bit
Advance Information
57
R E Q U I R E D
COPD — COP Disable Bit
N O N - D I S C L O S U R E
A G R E E M E N T
COPD disables the COP module. (See Section 13. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
Advance Information
58
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.4.1
EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.4.2
EEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.4.3
EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.4
EEPROM Redundant Mode . . . . . . . . . . . . . . . . . . . . . . . .65
6.4.5
EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.4.6
EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.4.7
EEPROM Nonvolatile Register and EEPROM
Array Configuration Register . . . . . . . . . . . . . . . . . . . . . 68
6.4.8
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.4.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.4.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.2 Introduction
This section describes the 512 bytes of electrically erasable
programmable ROM (EEPROM).
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
59
R E Q U I R E D
6.1 Contents
A G R E E M E N T
Section 6. Electrically Erasable Programmable ROM
(EEPROM)
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
6.3 Features
EEPROM features include:
•
Byte, Block, or Bulk Erasable
•
Nonvolatile Redundant Array Option
•
Nonvolatile Block Protection Option
•
Nonvolatile MCU Configuration Bits
•
On-Chip Charge Pump for Programming/Erasing
6.4 Functional Description
Addresses $0800–$09FF are EEPROM locations. The 512 bytes of
EEPROM can be programmed or erased without an external voltage
supply. The EEPROM has a lifetime of 10,000 write-erase cycles in the
nonredundant mode. Reliability (data retention) is further extended if the
redundancy option is selected. EEPROM cells are protected with a
nonvolatile, 128-byte, block protection option. These options are stored
in the EEPROM nonvolatile register (EENVR) and are loaded into the
EEPROM array configuration register (EEACR) after reset or a read of
EENVR. The EEPROM array can also be disabled to reduce current.
6.4.1 EEPROM Programming
The unprogrammed state is a logic 1. Programming changes the state to
a logic 0. Only valid EEPROM bytes in the nonprotected blocks and
EENVR can be programmed. When the array is configured in the
redundant mode, programming the first 256 bytes ($0800–$08FF) will
also program the last 256 bytes ($0900–$09FF) with the same data.
Programming the EEPROM in the nonredundant mode is
recommended. Program the data to both locations before entering the
redundant mode.
Advance Information
60
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
Follow this procedure to program a byte of EEPROM. Refer to 21.6
Control Timing for timing values.
1. Clear EERAS1 and EERAS0 and set EELAT in the EECR
($FE1D). Set value of tEEPGM. (See Notes a and b.)
2. Write the desired data to any user EEPROM address.
3. Set the EEPGM bit. (See Note c.)
4. Wait for a time, tEEPGM, to program the byte.
7. Clear EELAT bits. (See Note d.)
8. Repeat steps 1 through 7 for more EEPROM programming.
NOTES:
a. EERAS1 and EERAS0 must be cleared for programming.
Otherwise, you will be in erase mode.
b. Setting the EELAT bit configures the address and data buses
to latch data for programming the array. Only data with a valid
EEPROM address will be latched. If another consecutive valid
EEPROM write occurs, this address and data will override the
previous address and data. Any attempts to read other
EEPROM data will read the latched data. If EELAT is set,
other writes to the EECR will be allowed after a valid
EEPROM write.
c.
The EEPGM bit cannot be set if the EELAT bit is cleared and
a non-EEPROM write has occurred. This is to ensure proper
programming sequence. When EEPGM is set, the on-board
charge pump generates the program voltage and applies it to
the user EEPROM array. When the EEPGM bit is cleared, the
program voltage is removed from the array and the internal
charge pump is turned off.
d. Any attempt to clear both EEPGM and EELAT bits with a
single instruction will clear only EEPGM to allow time for
removal of high voltage from the EEPROM array.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
61
N O N - D I S C L O S U R E
6. Wait for the programming voltage time to fall, tEEFPV.
A G R E E M E N T
5. Clear the EEPGM bit.
The unprogrammed state is a logic 1. Only the valid EEPROM bytes in
the nonprotected blocks and EENVR can be erased. When the array is
configured in the redundant mode, erasing the first 256 bytes
($0800–$08FF) will also erase the last 256 bytes ($0900–$09FF).
Follow this procedure to erase EEPROM. Refer to 21.6 Control Timing
for timing values.
1. Clear/set EERAS1 and EERAS0 to select byte/block/bulk erase,
and set EELAT in EECTL. Set value of tEEBYT/tEEBLOCK/tEEBULK.
(See Note a.)
A G R E E M E N T
R E Q U I R E D
6.4.2 EEPROM Erasing
2. Write any data to the desired address for byte erase, to any
address in the desired block for block erase, or to any array
address for bulk erase.
3. Set the EEPGM bit. (See Note b.)
4. Wait for a time, tEEPGM, to program the byte.
5. Clear EEPGM bit.
6. Wait for the erasing voltage time to fall, tEEFPV.
7. Clear EELAT bits. (See Note c.)
N O N - D I S C L O S U R E
8. Repeat steps 1 through 7 for more EEPROM byte/block erasing.
EEBPx bit must be cleared to erase EEPROM data in the corresponding
block. If any EEBPx is set, the corresponding block cannot be erased
and bulk erase mode does not apply.
NOTES:
a. Setting the EELAT bit configures the address and data buses
to latch data for erasing the array. Only valid EEPROM
addresses with their data will be latched. If another
consecutive valid EEPROM write occurs, this address and
data will override the previous address and data. In block
erase mode, any EEPROM address in the block can be used
in step 2. All locations within this block will be erased. In bulk
erase mode, any EEPROM address can be used to erase the
whole EEPROM. EENVR is not affected with block or bulk
Advance Information
62
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
c.
Any attempt to clear both EEPGM and EELAT bits with a
single instruction will clear only EEPGM to allow time for
removal of high voltage from the EEPROM array.
N O N - D I S C L O S U R E
In general, all bits should be erased before being programmed.
However, if program/erase cycling is of concern, the following procedure
can be used to minimize bit cycling in each EEPROM byte. If any bit in
a byte must be changed from a 0 to a 1, the byte needs to be erased
before programming. Table 6-1 summarizes the conditions for erasing
before programming.
Table 6-1. EEPROM Program/Erase Cycling Reduction
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
EEPROM Data To Be
Programmed
EEPROM Data Before
Programming
Erase Before
Programming?
0
0
No
0
1
No
1
0
Yes
1
1
No
R E Q U I R E D
b. To ensure proper erasing sequence, the EEPGM bit cannot
be set if the EELAT bit is cleared and a non-EEPROM write
has occurred. Once EEPGM is set, the type of erase mode
cannot be modified. If EEPGM is set, the on-board charge
pump generates the erase voltage and applies it to the user
EEPROM array. When the EEPGM bit is cleared, the erase
voltage is removed from the array and the internal charge
pump is turned off.
A G R E E M E N T
erase. Any attempts to read other EEPROM data will read the
latched data. If EELAT is set, other writes to the EECR will be
allowed after a valid EEPROM write.
Advance Information
63
R E Q U I R E D
6.4.3 EEPROM Block Protection
The 512 bytes of EEPROM are divided into four 128-byte blocks. Each
of these blocks can be protected separately by the EEBPx bit. Any
attempt to program or erase memory locations within the protected block
will not allow the program/erase voltage to be applied to the array. Table
6-2 shows the address ranges within the blocks.
A G R E E M E N T
Table 6-2. EEPROM Array Address Blocks
Block Number (EEBPx)
Address Range
EEBP0
$0800–$087F
EEBP1
$0880–$08FF
EEBP2
$0900–$097F
EEBP3
$0980–$09FF
N O N - D I S C L O S U R E
If the EEBPx bit is set, that corresponding address block is protected.
These bits are effective after a reset or a read to the EENVR register.
The block protect configuration can be modified by erasing/
programming the corresponding bits in the EENVR register and then
reading the EENVR register.
In redundant mode, EEBP3 and EEBP2 will have no meaning.
Advance Information
64
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
NOTE:
Before entering redundant mode, program the EEPROM in
nonredundant mode.
6.4.5 EEPROM Configuration
The EEPROM nonvolatile register (EENVR) contains configurations
concerning block protection and redundancy. EENVR is physically
located on the bottom of the EEPROM array. The contents are
nonvolatile and are not modified by reset. On reset, this special register
loads the EEPROM configuration into a corresponding volatile EEPROM
array configuration register (EEACR). Thereafter, all reads to the
EENVR will reload EEACR.
The EEPROM configuration can be changed by programming/erasing
the EENVR like a normal EEPROM byte. The new array configuration
will take effect with a system reset or a read of the EENVR.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
65
R E Q U I R E D
A G R E E M E N T
To extend the EEPROM data retention, the array can be placed in
redundant mode. In this mode, the first 256 bytes of user EEPROM array
are mapped to the last 256 bytes. Reading, programming and erasing of
the first 256 EEPROM bytes ($0800–$08FF) will physically affect two
bytes of EEPROM. Addressing the last 256 bytes will not be recognized.
Block protection still applies but EEBP3 and EEBP2 are meaningless.
N O N - D I S C L O S U R E
6.4.4 EEPROM Redundant Mode
R E Q U I R E D
6.4.6 EEPROM Control Register
This read/write register controls programming/erasing of the array.
Address:
$FE1D
Bit 7
Read:
Write:
A G R E E M E N T
Reset:
EEBCLK
0
6
0
0
5
4
3
2
EEOFF
EERAS1
EERAS0
EELAT
0
0
0
0
1
0
0
Bit 0
EEPGM
0
= Unimplemented
Figure 6-1. EEPROM Control Register (EECR)
EEBCLK — EEPROM Bus Clock Enable Bit
This read/write bit determines which clock will be used to drive the
internal charge pump for programming/erasing. Reset clears this bit.
1 = Bus clock drives charge pump.
0 = Internal RC oscillator drives charge pump.
NOTE:
Use the internal RC oscillator for applications in the 3- to 5-V range.
N O N - D I S C L O S U R E
EEOFF — EEPROM Power Down Bit
This read/write bit disables the EEPROM module for lower power
consumption. Any attempts to access the array will give unpredictable
results. Reset clears this bit.
1 = Disable EEPROM array
0 = Enable EEPROM array
NOTE:
Advance Information
66
The EEPROM requires a recovery time, tEEOFF, to stabilize after clearing
the EEOFF bit. Refer to 21.6 Control Timing for timing values.
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
EERAS1–EERAS0 — EEPROM Erase Bits
These read/write bits set the programming/erasing modes. Reset
clears these bits.
EERAS1
EERA0
MODE
0
0
0
Byte Program
0
0
1
Byte Erase
0
1
0
Block Erase
0
1
1
Bulk Erase
1
X
X
No Erase/Program
X = don’t care
EELAT — EEPROM Latch Control Bit
This read/write bit latches the address and data buses for
programming the EEPROM array. EELAT cannot be cleared if
EEPGM is still set. Reset clears this bit.
1 = Buses configured for EEPROM programming
0 = Buses configured for normal read operation
EEPGM — EEPROM Program/Erase Enable Bit
This read/write bit enables the internal charge pump and applies the
programming/erasing voltage to the EEPROM array if the EELAT bit
is set and a write to a valid EEPROM location has occurred. Reset
clears the EEPGM bit.
1 = EEPROM programming/erasing power switched on
0 = EEPROM programming/erasing power switched off
NOTE:
Writing logic 0s to both the EELAT and EEPGM bits with a single
instruction will clear only EEPGM. This is to allow time for the removal of
high voltage.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
67
N O N - D I S C L O S U R E
EEBPx
A G R E E M E N T
Table 6-3. EEPROM Program/Erase Mode Select
These registers configure the EEPROM array blocks for programming
purposes. EEACR loads its contents from the EENVR register at reset
and upon any read of the EENVR register.
Address:
A G R E E M E N T
R E Q U I R E D
6.4.7 EEPROM Nonvolatile Register and EEPROM Array Configuration Register
$FE1F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
EERA
R
R
R
EEBP3
EEBP2
EEBP1
EEBP0
Write:
R
R
R
R
R
R
R
R
EENVR
R
R
R
EENVR
EENVR
EENVR
EENVR
R
= Reserved
Figure 6-2. EEPROM Array Control Register (EEACR)
Address:
$FE1C
Bit 7
Read:
Write:
Reset:
EERA
PV
6
5
4
R
R
R
R
R
R
3
2
1
Bit 0
EEBP3
EEBP2
EEBP1
EEBP0
PV
PV
PV
PV
= Unimplemented
N O N - D I S C L O S U R E
R
= Reserved
PV = Programmed value or 1 in the erased state.
Figure 6-3. EEPROM Nonvolatile Register (EENVR)
EERA — EEPROM Redundant Array Bit
This programmable/eraseable/readable bit in EENVR and read-only
bit in EEACR configures the array in redundant mode. Reset loads
EERA from EENVR to EEACR.
1 = EEPROM array in redundant mode configuration
0 = EEPROM array in normal mode configuration
EEBP3–EEBP0 — EEPROM Block Protection Bits
These programmable/eraseable/readable bits in EENVR and
read-only bits in EEACR select blocks of EEPROM array from being
programmed or erased. Reset loads EEBP[3:0] from EENVR to
EEACR. See 6.4.3 EEPROM Block Protection.
1 = EEPROM array block protected
0 = EEPROM array block unprotected
Advance Information
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The WAIT instruction does not affect the EEPROM. It is possible to
program the EEPROM while the MCU is in wait mode. However, if the
EEPROM is inactive, power can be reduced by setting the EEOFF bit
before executing the WAIT instruction.
6.4.8.2 Stop Mode
The STOP instruction reduces the EEPROM power consumption to a
minimum. The STOP instruction should not be executed while the high
voltage is turned on (EEPGM = 1).
If stop mode is entered while program/erase is in progress, high voltage
will be turned off automatically. However, the EEPGM bit will remain set.
When stop mode is terminated and if EEPGM is still set, the high voltage
will be turned back on automatically. Program/erase time will need to be
extended if program/erase is interrupted by entering stop mode.
The module requires a recovery time, tEESTOP, to stabilize after leaving
stop mode (see 21.6 Control Timing). Attempts to access the array
during the recovery time will result in unpredictable behavior.
MC68HC08AS20 — Rev. 4.1
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69
R E Q U I R E D
6.4.8.1 Wait Mode
A G R E E M E N T
The following subsections describe the low-power modes.
N O N - D I S C L O S U R E
6.4.8 Low-Power Modes
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
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7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.4.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.4.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.4.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.4.4
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.4.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.6
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.7
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.8
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.2 Introduction
This section describes the central processor unit (CPU). The M68HC08
CPU is an enhanced and fully object-code-compatible version of the
M68HC05 CPU. The CPU08 Reference Manual (Freescale document
number CPU08RM/AD) contains a description of the CPU instruction
set, addressing modes, and architecture.
MC68HC08AS20 — Rev. 4.1
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Advance Information
71
R E Q U I R E D
7.1 Contents
A G R E E M E N T
Section 7. Central Processor Unit (CPU)
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
Features of the CPU include:
•
Fully Upward, Object-Code Compatibility with the M68HC05
Family
•
16-Bit Stack Pointer with Stack Manipulation Instructions
•
16-Bit Index Register with X-Register Manipulation Instructions
•
8-MHz CPU Internal Bus Frequency
•
64-Kbyte Program/Data Memory Space
•
16 Addressing Modes
•
Memory-to-Memory Data Moves without Using Accumulator
•
Fast 8-Bit by 8-Bit Multiply and 16-Bit by 8-Bit Divide Instructions
•
Enhanced Binary Coded Decimal (BCD) Data Handling
•
Modular Architecture with Expandable Internal Bus Definition for
Extension of Addressing Range beyond 64 Kbytes
•
Low-Power Stop Mode and Wait Mode
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
7.3 Features
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Figure 7-1 shows the five CPU registers. CPU registers are not part of
the memory map.
0
7
ACCUMULATOR (A)
0
15
H
X
INDEX REGISTER (H:X)
15
0
0
PROGRAM COUNTER (PC)
7
0
V 1 1 H I N Z C
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 7-1. CPU Registers
7.4.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by Reset
Figure 7-2. Accumulator (A)
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N O N - D I S C L O S U R E
15
A G R E E M E N T
STACK POINTER (SP)
Bit 7
R E Q U I R E D
7.4 CPU Registers
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
A G R E E M E N T
R E Q U I R E D
7.4.2 Index Register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Read:
Write:
Reset:
X = Indeterminate
Figure 7-3. Index Register (H:X)
N O N - D I S C L O S U R E
The index register can serve also as a temporary data storage location.
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In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Figure 7-4. Stack Pointer (SP)
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct
address (page zero) space. For correct operation, the stack pointer must
point only to RAM locations.
MC68HC08AS20 — Rev. 4.1
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Advance Information
75
R E Q U I R E D
A G R E E M E N T
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
N O N - D I S C L O S U R E
7.4.3 Stack Pointer
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
A G R E E M E N T
R E Q U I R E D
7.4.4 Program Counter
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
Read:
Write:
Reset:
Loaded with vector from $FFFE and $FFFF
N O N - D I S C L O S U R E
Figure 7-5. Program Counter (PC)
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The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Read:
Bit 7
6
5
4
3
2
1
Bit 0
V
1
1
H
I
N
Z
C
X
1
1
X
1
X
X
X
R E Q U I R E D
7.4.5 Condition Code Register
Reset:
X = Indeterminate
Figure 7-6. Condition Code Register (CCR)
V — Overflow Flag Bit
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
A G R E E M E N T
Write:
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an ADD or ADC operation. The
half-carry flag is required for binary coded decimal (BCD) arithmetic
operations. The DAA instruction uses the states of the H and C flags
to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask Bit
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
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Advance Information
77
N O N - D I S C L O S U R E
H — Half-Carry Flag Bit
R E Q U I R E D
NOTE:
To maintain M68HC05 compatibility, the upper byte of the index register
(H) is not stacked automatically. If the interrupt service routine modifies
H, then the user must stack and unstack H using the PSHH and PULH
instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A G R E E M E N T
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative Flag Bit
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag Bit
N O N - D I S C L O S U R E
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Nonzero result
C — Carry/Borrow Flag Bit
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
Advance Information
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Refer to the CPU08 Reference Manual (Freescale document number
CPU08RM/AD) for a description of the instructions and addressing
modes and more detail about CPU architecture.
7.6 CPU During Break Interrupts
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. See Section 11. Break Module (Break). The
program counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor
mode).
N O N - D I S C L O S U R E
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
R E Q U I R E D
The ALU performs the arithmetic and logic operations defined by the
instruction set.
A G R E E M E N T
7.5 Arithmetic/Logic Unit (ALU)
MC68HC08AS20 — Rev. 4.1
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Advance Information
79
Table 7-1 provides a summary of the M68HC08 instruction set.
Description
V H I N Z C
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
A ← (A) + (M) + (C)
Add with Carry
↕ ↕
IMM
DIR
EXT
– ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
ii
dd
hh ll
ee ff
ff
IMM
DIR
EXT
IX2
– ↕ ↕ ↕
IX1
IX
SP1
SP2
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
Add without Carry
AIS #opr
Add Immediate Value (Signed) to SP
SP ← (SP) + (16 « M)
– – – – – – IMM
AIX #opr
Add Immediate Value (Signed) to H:X
H:X ← (H:X) + (16 « M)
– – – – – – IMM
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
Arithmetic Shift Left
(Same as LSL)
C
BCC rel
Branch if Carry Bit Clear
b0
PC ← (PC) + 2 + rel ? (C) = 0
IMM
DIR
EXT
– IX2
IX1
IX
SP1
SP2
2
3
4
4
3
2
4
5
ff
ee ff
2
3
4
4
3
2
4
5
A7
ii
2
AF
ii
2
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
A4
B4
C4
D4
E4
F4
9EE4
9ED4
ff
ee ff
↕
DIR
INH
– – ↕ ↕ ↕ INH
IX1
IX
SP1
38 dd
48
58
68 ff
78
9E68 ff
4
1
1
4
3
5
↕
DIR
INH
INH
– – ↕ ↕ ↕
IX1
IX
SP1
37 dd
47
57
67 ff
77
9E67 ff
4
1
1
4
3
5
b0
C
b7
Advance Information
0 – – ↕ ↕
0
b7
Arithmetic Shift Right
↕ ↕
A ← (A) & (M)
Logical AND
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
80
A ← (A) + (M)
ff
ee ff
Cycles
Operation
Effect on
CCR
Opcode
Source
Form
Operand
Table 7-1. Instruction Set Summary (Sheet 1 of 8)
Address
Mode
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
7.7 Instruction Set Summary
– – – – – – REL
24
rr
3
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? (Z) = 1
– – – – – – REL
27
rr
3
BGE opr
Branch if Greater Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0
– – – – – – REL
90
rr
3
BGT opr
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 – – – – – – REL
92
rr
3
BHCC rel
Branch if Half Carry Bit Clear
PC ← (PC) + 2 + rel ? (H) = 0
– – – – – – REL
28
rr
3
BHCS rel
Branch if Half Carry Bit Set
PC ← (PC) + 2 + rel ? (H) = 1
– – – – – – REL
29
rr
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
– – – – – – REL
22
rr
3
BHS rel
Branch if Higher or Same
(Same as BCC)
PC ← (PC) + 2 + rel ? (C) = 0
– – – – – – REL
24
rr
3
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
– – – – – – REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
– – – – – – REL
2E
rr
3
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
93
rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test
BLE opr
Branch if Less Than or Equal To
(Signed Operands)
BLO rel
Branch if Lower (Same as BCS)
BLS rel
(A) & (M)
0 – – ↕ ↕
IMM
DIR
EXT
– IX2
IX1
IX
SP1
SP2
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1 – – – – – – REL
A5
B5
C5
D5
E5
F5
9EE5
9ED5
3
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
– – – – – – REL
23
rr
3
BLT opr
Branch if Less Than (Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) =1
– – – – – – REL
91
rr
3
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? (I) = 0
– – – – – – REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? (N) = 1
– – – – – – REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? (I) = 1
– – – – – – REL
2D
rr
3
MC68HC08AS20 — Rev. 4.1
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Advance Information
81
R E Q U I R E D
11
13
15
17
19
1B
1D
1F
A G R E E M E N T
Mn ← 0
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – – DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
N O N - D I S C L O S U R E
V H I N Z C
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 7-1. Instruction Set Summary (Sheet 2 of 8)
V H I N Z C
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Table 7-1. Instruction Set Summary (Sheet 3 of 8)
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? (Z) = 0
– – – – – – REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? (N) = 0
– – – – – – REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel
– – – – – – REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – ↕ DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
– – – – – – REL
21
rr
3
PC ← (PC) + 3 + rel ? (Mn) = 1
DIR (b0)
DIR (b1)
DIR (b2)
– – – – – ↕ DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – – DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
– – – – – – REL
AD
rr
4
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
IMM
IMM
– – – – – – IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
BRCLR n,opr,rel Branch if Bit n in M Clear
BRN rel
Branch Never
BRSET n,opr,rel Branch if Bit n in M Set
BSET n,opr
Set Bit n in M
BSR rel
Branch to Subroutine
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel Compare and Branch if Equal
CBEQ X+,rel
CBEQ opr,SP,rel
PC ← (PC) + 3 + rel ? (Mn) = 0
PC ← (PC) + 2
CLC
Clear Carry Bit
C←0
– – – – – 0 INH
98
1
CLI
Clear Interrupt Mask
I←0
– – 0 – – – INH
9A
2
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
0 – – 0 1 – INH
IX1
IX
SP1
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
Clear
Advance Information
82
3F dd
4F
5F
8C
6F ff
7F
9E6F ff
3
1
1
1
3
2
4
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
Complement (One’s Complement)
CPHX #opr
CPHX opr
Compare H:X with M
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
Compare X with M
DAA
Decimal Adjust A
DBNZ opr,rel
DBNZA rel
DBNZX rel
Decrement and Branch if Not Zero
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
Decrement
DIV
Divide
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
Exclusive OR M with A
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
(A) – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(H:X) – (M:M + 1)
(X) – (M)
(A)10
↕
0 – – ↕ ↕
DIR
INH
INH
1 IX1
IX
SP1
A ← (H:A)/(X)
H ← Remainder
A ← (A ⊕ M)
ii
dd
hh ll
ee ff
ff
ff
ee ff
33 dd
43
53
63 ff
73
9E63 ff
2
3
4
4
3
2
4
5
4
1
1
4
3
5
↕
IMM
– – ↕ ↕ ↕ DIR
65
75
ii ii+1
dd
3
4
↕
IMM
DIR
EXT
– – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
9EE3
9ED3
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
U – – ↕ ↕ ↕ INH
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
DIR
PC ← (PC) + 2 + rel ? (result) ≠ 0
INH
PC ← (PC) + 2 + rel ? (result) ≠ 0
– – – – – – INH
PC ← (PC) + 3 + rel ? (result) ≠ 0
IX1
PC ← (PC) + 2 + rel ? (result) ≠ 0
IX
PC ← (PC) + 4 + rel ? (result) ≠ 0
SP1
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
A1
B1
C1
D1
E1
F1
9EE1
9ED1
↕
– – ↕ ↕
DIR
INH
– INH
IX1
IX
SP1
– – – – ↕ ↕ INH
0 – – ↕ ↕
IMM
DIR
EXT
IX2
– IX1
IX
SP1
SP2
ff
ee ff
72
3B
4B
5B
6B
7B
9E6B
2
dd rr
rr
rr
ff rr
rr
ff rr
3A dd
4A
5A
6A ff
7A
9E6A ff
52
A8
B8
C8
D8
E8
F8
9EE8
9ED8
5
3
3
5
4
6
4
1
1
4
3
5
7
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
Advance Information
83
R E Q U I R E D
Compare A with M
IMM
DIR
EXT
IX2
– – ↕ ↕ ↕ IX1
IX
SP1
SP2
A G R E E M E N T
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
N O N - D I S C L O S U R E
V H I N Z C
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 7-1. Instruction Set Summary (Sheet 4 of 8)
V H I N Z C
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Increment
Jump to Subroutine
Load A from M
LDHX #opr
LDHX opr
Load H:X from M
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
Logical Shift Right
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
Move
MUL
Unsigned multiply
84
4
1
1
4
3
5
PC ← Jump Address
dd
hh ll
ee ff
ff
2
3
4
3
2
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
DIR
EXT
– – – – – – IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
IMM
DIR
EXT
– IX2
IX1
IX
SP1
SP2
A6
B6
C6
D6
E6
F6
9EE6
9ED6
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
0 – – ↕ ↕
IMM
– DIR
45
55
ii jj
dd
3
4
0 – – ↕ ↕
IMM
DIR
EXT
IX2
–
IX1
IX
SP1
SP2
AE
BE
CE
DE
EE
FE
9EEE
9EDE
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
A ← (M)
0 – – ↕ ↕
H:X ← (M:M + 1)
X ← (M)
C
0
b7
C
b0
(M)Destination ← (M)Source
H:X ← (H:X) + 1 (IX+D, DIX+)
X:A ← (X) × (A)
ff
ee ff
↕
DIR
INH
INH
– – ↕ ↕ ↕
IX1
IX
SP1
38 dd
48
58
68 ff
78
9E68 ff
4
1
1
4
3
5
↕
DIR
INH
INH
– – 0 ↕ ↕ IX1
IX
SP1
34 dd
44
54
64 ff
74
9E64 ff
4
1
1
4
3
5
b0
0
b7
Advance Information
– – ↕ ↕
3C dd
4C
5C
6C ff
7C
9E6C ff
BC
CC
DC
EC
FC
Load X from M
Logical Shift Left
(Same as ASL)
↕
DIR
INH
– INH
IX1
IX
SP1
DIR
EXT
– – – – – – IX2
IX1
IX
Jump
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Table 7-1. Instruction Set Summary (Sheet 5 of 8)
0 – – ↕ ↕
–
DD
DIX+
IMD
IX+D
– 0 – – – 0 INH
4E
5E
6E
7E
42
dd dd
dd
ii dd
dd
5
4
4
4
5
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
4
1
1
4
3
5
NOP
No Operation
None
– – – – – – INH
9D
1
NSA
Nibble Swap A
A ← (A[3:0]:A[7:4])
– – – – – – INH
62
3
↕
IMM
DIR
EXT
– IX2
IX1
IX
SP1
SP2
AA
BA
CA
DA
EA
FA
9EEA
9EDA
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Inclusive OR A and M
PSHA
Push A onto Stack
Push (A); SP ← (SP) – 1
– – – – – – INH
87
2
PSHH
Push H onto Stack
Push (H); SP ← (SP) – 1
– – – – – – INH
8B
2
PSHX
Push X onto Stack
Push (X); SP ← (SP) – 1
– – – – – – INH
89
2
PULA
Pull A from Stack
SP ← (SP + 1); Pull (A)
– – – – – – INH
86
2
PULH
Pull H from Stack
SP ← (SP + 1); Pull (H)
– – – – – – INH
8A
2
PULX
Pull X from Stack
SP ← (SP + 1); Pull (X)
– – – – – – INH
88
2
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
Rotate Left through Carry
A ← (A) | (M)
0 – – ↕ ↕
C
b7
ff
ee ff
↕
DIR
INH
INH
– – ↕ ↕ ↕ IX1
IX
SP1
39 dd
49
59
69 ff
79
9E69 ff
4
1
1
4
3
5
↕
DIR
INH
– – ↕ ↕ ↕ INH
IX1
IX
SP1
36 dd
46
56
66 ff
76
9E66 ff
4
1
1
4
3
5
b0
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
Rotate Right through Carry
RSP
Reset Stack Pointer
SP ← $FF
– – – – – – INH
9C
1
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕ ↕ ↕ ↕ ↕ ↕ INH
80
7
RTS
Return from Subroutine
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
– – – – – – INH
81
4
C
b7
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
b0
Advance Information
85
R E Q U I R E D
30 dd
40
50
60 ff
70
9E60 ff
Negate (Two’s Complement)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
A G R E E M E N T
DIR
INH
– – ↕ ↕ ↕ INH
IX1
IX
SP1
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
N O N - D I S C L O S U R E
V H I N Z C
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 7-1. Instruction Set Summary (Sheet 6 of 8)
V H I N Z C
IMM
DIR
EXT
IX2
– – ↕ ↕ ↕ IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
ii
dd
hh ll
ee ff
ff
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Table 7-1. Instruction Set Summary (Sheet 7 of 8)
2
3
4
4
3
2
4
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
Subtract with Carry
SEC
Set Carry Bit
C←1
– – – – – 1 INH
99
1
SEI
Set Interrupt Mask
I←1
– – 1 – – – INH
9B
2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
STHX opr
Store H:X in M
STOP
Enable IRQ Pin; Stop Oscillator
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Store X in M
Subtract
A ← (A) – (M) – (C)
M ← (A)
(M:M + 1) ← (H:X)
I ← 0; Stop Oscillator
M ← (X)
A ← (A) – (M)
↕
DIR
EXT
IX2
– IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
– DIR
35
– – 0 – – – INH
8E
0 – – ↕ ↕
0 – – ↕ ↕
ff
ee ff
3
4
4
3
2
4
5
dd
4
dd
hh ll
ee ff
ff
1
DIR
EXT
IX2
– IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
dd
hh ll
ee ff
ff
IMM
DIR
EXT
– – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9EE0
9ED0
ii
dd
hh ll
ee ff
ff
0 – – ↕ ↕
↕
ff
ee ff
ff
ee ff
ff
ee ff
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
SWI
Software Interrupt
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
Transfer A to CCR
CCR ← (A)
↕ ↕ ↕ ↕ ↕ ↕ INH
84
2
TAX
Transfer A to X
X ← (A)
– – – – – – INH
97
1
TPA
Transfer CCR to A
A ← (CCR)
– – – – – – INH
85
1
Advance Information
86
– – 1 – – – INH
83
9
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
TSX
Transfer SP to H:X
TXA
Transfer X to A
TXS
Transfer H:X to SP
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
(A) – $00 or (X) – $00 or (M) – $00
0 – – ↕ ↕
3D dd
4D
5D
6D ff
7D
9E6D ff
3
1
1
3
2
4
H:X ← (SP) + 1
– – – – – – INH
95
2
A ← (X)
– – – – – – INH
9F
1
(SP) ← (H:X) – 1
– – – – – – INH
94
2
Accumulator
Carry/borrow bit
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
n
opr
PC
PCH
PCL
REL
rel
rr
SP1
SP2
SP
U
V
X
Z
&
|
⊕
()
–( )
#
«
←
?
:
↕
—
Any bit
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
7.8 Opcode Map
The opcode map is provided in Table 7-2.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
Test for Negative or Zero
DIR
INH
– INH
IX1
IX
SP1
N O N - D I S C L O S U R E
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
A G R E E M E N T
V H I N Z C
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 7-1. Instruction Set Summary (Sheet 8 of 8)
Advance Information
87
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Advance Information
88
Table 7-2. Opcode Map
Bit Manipulation
DIR
DIR
MSB
Branch
REL
DIR
INH
3
4
0
2
3
4
5
6
7
8
9
A
B
C
D
MC68HC08AS20 — Rev. 4.1
1
2
5
BRSET0
3 DIR
5
BRCLR0
3 DIR
5
BRSET1
3 DIR
5
BRCLR1
3 DIR
5
BRSET2
3 DIR
5
BRCLR2
3 DIR
5
BRSET3
3 DIR
5
BRCLR3
3 DIR
5
BRSET4
3 DIR
5
BRCLR4
3 DIR
5
BRSET5
3 DIR
5
BRCLR5
3 DIR
5
BRSET6
3 DIR
5
BRCLR6
3 DIR
5
BRSET7
3 DIR
5
BRCLR7
3 DIR
4
BSET0
2 DIR
4
BCLR0
2 DIR
4
BSET1
2 DIR
4
BCLR1
2 DIR
4
BSET2
2 DIR
4
BCLR2
2 DIR
4
BSET3
2 DIR
4
BCLR3
2 DIR
4
BSET4
2 DIR
4
BCLR4
2 DIR
4
BSET5
2 DIR
4
BCLR5
2 DIR
4
BSET6
2 DIR
4
BCLR6
2 DIR
4
BSET7
2 DIR
4
BCLR7
2 DIR
3
BRA
2 REL
3
BRN
2 REL
3
BHI
2 REL
3
BLS
2 REL
3
BCC
2 REL
3
BCS
2 REL
3
BNE
2 REL
3
BEQ
2 REL
3
BHCC
2 REL
3
BHCS
2 REL
3
BPL
2 REL
3
BMI
2 REL
3
BMC
2 REL
3
BMS
2 REL
3
BIL
2 REL
3
BIH
2 REL
5
6
1
NEGX
1 INH
4
CBEQX
3 IMM
7
DIV
1 INH
1
COMX
1 INH
1
LSRX
1 INH
4
LDHX
2 DIR
1
RORX
1 INH
1
ASRX
1 INH
1
LSLX
1 INH
1
ROLX
1 INH
1
DECX
1 INH
3
DBNZX
2 INH
1
INCX
1 INH
1
TSTX
1 INH
4
MOV
2 DIX+
1
CLRX
1 INH
4
NEG
2
IX1
5
CBEQ
3 IX1+
3
NSA
1 INH
4
COM
2 IX1
4
LSR
2 IX1
3
CPHX
3 IMM
4
ROR
2 IX1
4
ASR
2 IX1
4
LSL
2 IX1
4
ROL
2 IX1
4
DEC
2 IX1
5
DBNZ
3 IX1
4
INC
2 IX1
3
TST
2 IX1
4
MOV
3 IMD
3
CLR
2 IX1
SP1
IX
9E6
7
Control
INH
INH
8
9
Register/Memory
IX2
SP2
IMM
DIR
EXT
A
B
C
D
9ED
4
SUB
3 EXT
4
CMP
3 EXT
4
SBC
3 EXT
4
CPX
3 EXT
4
AND
3 EXT
4
BIT
3 EXT
4
LDA
3 EXT
4
STA
3 EXT
4
EOR
3 EXT
4
ADC
3 EXT
4
ORA
3 EXT
4
ADD
3 EXT
3
JMP
3 EXT
5
JSR
3 EXT
4
LDX
3 EXT
4
STX
3 EXT
4
SUB
3 IX2
4
CMP
3 IX2
4
SBC
3 IX2
4
CPX
3 IX2
4
AND
3 IX2
4
BIT
3 IX2
4
LDA
3 IX2
4
STA
3 IX2
4
EOR
3 IX2
4
ADC
3 IX2
4
ORA
3 IX2
4
ADD
3 IX2
4
JMP
3 IX2
6
JSR
3 IX2
4
LDX
3 IX2
4
STX
3 IX2
5
SUB
4 SP2
5
CMP
4 SP2
5
SBC
4 SP2
5
CPX
4 SP2
5
AND
4 SP2
5
BIT
4 SP2
5
LDA
4 SP2
5
STA
4 SP2
5
EOR
4 SP2
5
ADC
4 SP2
5
ORA
4 SP2
5
ADD
4 SP2
IX1
SP1
IX
E
9EE
F
LSB
1
Freescale Semiconductor
0
Read-Modify-Write
INH
IX1
E
F
4
1
NEG
NEGA
2 DIR 1 INH
5
4
CBEQ CBEQA
3 DIR 3 IMM
5
MUL
1 INH
4
1
COM
COMA
2 DIR 1 INH
4
1
LSR
LSRA
2 DIR 1 INH
4
3
STHX
LDHX
2 DIR 3 IMM
4
1
ROR
RORA
2 DIR 1 INH
4
1
ASR
ASRA
2 DIR 1 INH
4
1
LSL
LSLA
2 DIR 1 INH
4
1
ROL
ROLA
2 DIR 1 INH
4
1
DEC
DECA
2 DIR 1 INH
5
3
DBNZ DBNZA
3 DIR 2 INH
4
1
INC
INCA
2 DIR 1 INH
3
1
TST
TSTA
2 DIR 1 INH
5
MOV
3 DD
3
1
CLR
CLRA
2 DIR 1 INH
INH Inherent
REL Relative
IMM Immediate
IX
Indexed, No Offset
DIR Direct
IX1 Indexed, 8-Bit Offset
EXT Extended
IX2 Indexed, 16-Bit Offset
DD Direct-Direct
IMD Immediate-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
5
3
NEG
NEG
3 SP1 1 IX
6
4
CBEQ
CBEQ
4 SP1 2 IX+
2
DAA
1 INH
5
3
COM
COM
3 SP1 1 IX
5
3
LSR
LSR
3 SP1 1 IX
4
CPHX
2 DIR
5
3
ROR
ROR
3 SP1 1 IX
5
3
ASR
ASR
3 SP1 1 IX
5
3
LSL
LSL
3 SP1 1 IX
5
3
ROL
ROL
3 SP1 1 IX
5
3
DEC
DEC
3 SP1 1 IX
6
4
DBNZ
DBNZ
4 SP1 2 IX
5
3
INC
INC
3 SP1 1 IX
4
2
TST
TST
3 SP1 1 IX
4
MOV
2 IX+D
4
2
CLR
CLR
3 SP1 1 IX
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
7
3
RTI
BGE
1 INH 2 REL
4
3
RTS
BLT
1 INH 2 REL
3
BGT
2 REL
9
3
SWI
BLE
1 INH 2 REL
2
2
TAP
TXS
1 INH 1 INH
1
2
TPA
TSX
1 INH 1 INH
2
PULA
1 INH
2
1
PSHA
TAX
1 INH 1 INH
2
1
PULX
CLC
1 INH 1 INH
2
1
PSHX
SEC
1 INH 1 INH
2
2
PULH
CLI
1 INH 1 INH
2
2
PSHH
SEI
1 INH 1 INH
1
1
CLRH
RSP
1 INH 1 INH
1
NOP
1 INH
1
STOP
*
1 INH
1
1
WAIT
TXA
1 INH 1 INH
2
SUB
2 IMM
2
CMP
2 IMM
2
SBC
2 IMM
2
CPX
2 IMM
2
AND
2 IMM
2
BIT
2 IMM
2
LDA
2 IMM
2
AIS
2 IMM
2
EOR
2 IMM
2
ADC
2 IMM
2
ORA
2 IMM
2
ADD
2 IMM
3
SUB
2 DIR
3
CMP
2 DIR
3
SBC
2 DIR
3
CPX
2 DIR
3
AND
2 DIR
3
BIT
2 DIR
3
LDA
2 DIR
3
STA
2 DIR
3
EOR
2 DIR
3
ADC
2 DIR
3
ORA
2 DIR
3
ADD
2 DIR
2
JMP
2 DIR
4
4
BSR
JSR
2 REL 2 DIR
2
3
LDX
LDX
2 IMM 2 DIR
2
3
AIX
STX
2 IMM 2 DIR
MSB
0
3
SUB
2 IX1
3
CMP
2 IX1
3
SBC
2 IX1
3
CPX
2 IX1
3
AND
2 IX1
3
BIT
2 IX1
3
LDA
2 IX1
3
STA
2 IX1
3
EOR
2 IX1
3
ADC
2 IX1
3
ORA
2 IX1
3
ADD
2 IX1
3
JMP
2 IX1
5
JSR
2 IX1
5
3
LDX
LDX
4 SP2 2 IX1
5
3
STX
STX
4 SP2 2 IX1
4
SUB
3 SP1
4
CMP
3 SP1
4
SBC
3 SP1
4
CPX
3 SP1
4
AND
3 SP1
4
BIT
3 SP1
4
LDA
3 SP1
4
STA
3 SP1
4
EOR
3 SP1
4
ADC
3 SP1
4
ORA
3 SP1
4
ADD
3 SP1
2
SUB
1 IX
2
CMP
1 IX
2
SBC
1 IX
2
CPX
1 IX
2
AND
1 IX
2
BIT
1 IX
2
LDA
1 IX
2
STA
1 IX
2
EOR
1 IX
2
ADC
1 IX
2
ORA
1 IX
2
ADD
1 IX
2
JMP
1 IX
4
JSR
1 IX
4
2
LDX
LDX
3 SP1 1 IX
4
2
STX
STX
3 SP1 1 IX
High Byte of Opcode in Hexadecimal
LSB
Low Byte of Opcode in Hexadecimal
0
5
Cycles
BRSET0 Opcode Mnemonic
3 DIR Number of Bytes / Addressing Mode
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
8.4.1
Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.4.2
Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . . 93
8.4.2.1
Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.4.2.2
Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . 95
8.4.2.3
Manual and Automatic PLL Bandwidth Modes . . . . . . . . 95
8.4.2.4
Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.4.2.5
Special Programming Exceptions . . . . . . . . . . . . . . . . . . 99
8.4.3
Base Clock Selector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . 99
8.4.4
CGM External Connections. . . . . . . . . . . . . . . . . . . . . . . . 100
8.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8.5.1
Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . 101
8.5.2
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . 101
8.5.3
External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . 101
8.5.4
Analog Power Pin (VDDA/VDDAREF). . . . . . . . . . . . . . . . . . 102
8.5.5
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . 102
8.5.6
Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . 102
8.5.7
CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . 102
8.5.8
CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . 102
8.6
CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8.6.1
PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
8.6.2
PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .106
8.6.3
PLL Programming Register . . . . . . . . . . . . . . . . . . . . . . . . 108
8.7
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Advance Information
89
R E Q U I R E D
8.1 Contents
A G R E E M E N T
Section 8. Clock Generator Module (CGM)
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
8.8
Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.9
CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 111
8.10.1
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . 111
8.10.2
Parametric Influences on Reaction Time . . . . . . . . . . . . . 113
8.10.3
Choosing a Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . . 114
8.10.4
Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . 115
8.2 Introduction
This section describes the clock generator module (CGM). The CGM
generates the crystal clock signal, CGMXCLK, which operates at the
frequency of the crystal. The CGM also generates the base clock signal,
CGMOUT, from which the system integration module (SIM) derives the
system clocks. CGMOUT is based on either the crystal clock divided by
two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two.
The PLL is a frequency generator designed for use with 1-MHz to
8.4-MHz crystals or ceramic resonators. The PLL can generate an
8-MHz bus frequency without using a 32-MHz crystal.
8.3 Features
Features of the CGM include:
Advance Information
90
•
Phase-Locked Loop with Output Frequency in Integer Multiples of
the Crystal Reference
•
Programmable Hardware Voltage-Controlled Oscillator (VCO) for
Low-Jitter Operation
•
Automatic Bandwidth Control Mode for Low-Jitter Operation
•
Automatic Frequency Lock Detector
•
CPU Interrupt on Entry or Exit from Locked Condition
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Crystal oscillator circuit — The crystal oscillator circuit generates
the constant crystal frequency clock, CGMXCLK.
•
Phase-locked loop (PLL) — The PLL generates the
programmable VCO frequency clock CGMVCLK.
•
Base clock selector circuit — This software-controlled circuit
selects either CGMXCLK divided by two or the VCO clock,
CGMVCLK, divided by two as the base clock, CGMOUT. The SIM
derives the system clocks from CGMOUT.
Figure 8-1 shows the structure of the CGM.
8.4.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an
external crystal. The OSC1 pin is the input to the amplifier and the OSC2
pin is the output. The SIMOSCEN signal from the system integration
module (SIM) enables the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and
runs at a rate equal to the crystal frequency. CGMXCLK is then buffered
to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing
for operation. The duty cycle of CGMXCLK is not guaranteed to be 50%
and depends on external factors, including the crystal and related
external components.
An externally generated clock also can feed the OSC1 pin of the crystal
oscillator circuit. Connect the external clock to the OSC1 pin and let the
OSC2 pin float.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
91
R E Q U I R E D
•
A G R E E M E N T
The CGM consists of three major submodules:
N O N - D I S C L O S U R E
8.4 Functional Description
R E Q U I R E D
CRYSTAL OSCILLATOR
OSC2
CGMXCLK
CLOCK
SELECT
CIRCUIT
OSC1
÷2
A
SIMOSCEN
TO SIM
*When S = 1, CGMOUT = B
CGMRDV
CGMRCLK
VDDA
A G R E E M E N T
CGMOUT
B S*
TO SIM, SCI, ADC, BDLC
BCS
CGMXFC
USER MODE
VSS
VRS[7:4]
PTC3
MONITOR MODE
PHASE
DETECTOR
VOLTAGE
CONTROLLED
OSCILLATOR
LOOP
FILTER
PLL ANALOG
LOCK
DETECTOR
LOCK
BANDWIDTH
CONTROL
AUTO
ACQ
INTERRUPT
CONTROL
PLLIE
CGMINT
PLLF
N O N - D I S C L O S U R E
MUL[7:4]
CGMVDV
FREQUENCY
DIVIDER
CGMVCLK
Figure 8-1. CGM Block Diagram
Advance Information
92
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Bit 7
$001C
Read:
PLL Control Register
Write:
(PCTL)
Reset:
Read:
$001D
PLL Bandwidth Control
Write:
Register (PBWC)
Reset:
Read:
$001E
PLL Programming Register
Write:
(PPG)
Reset:
PLLIE
6
PLLF
0
AUTO
0
LOCK
5
4
PLLON
BCS
1
0
ACQ
XLD
3
2
1
Bit 0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
0
1
1
0
0
1
1
0
= Unimplemented
8.4.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually. Refer to 21.9 CGM Operating
Conditions for operating frequencies while reading this section.
8.4.2.1 Circuits
The PLL consists of these circuits:
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
•
Voltage-controlled oscillator (VCO)
•
Modulo VCO frequency divider
•
Phase detector
•
Loop filter
•
Lock detector
Advance Information
93
R E Q U I R E D
Register Name
A G R E E M E N T
Addr.
N O N - D I S C L O S U R E
Table 8-1. CGM I/O Register Summary
R E Q U I R E D
A G R E E M E N T
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. (For maximum immunity guidelines, refer to
document numbers AN1050/D and AN1263/D on electromagnetic
compatibility available from your Freescale sales office.) The VCO
frequency is bound to a range from roughly one-half to twice the
center-of-range frequency, fVRS. Modulating the voltage on the CGMXFC
pin changes the frequency within this range. By design, fVRS is equal to
the nominal center-of-range frequency, fNOM, 4.9152 MHz times a linear
factor (L) or fNOM.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a crystal frequency, fRCLK, and is fed to the PLL
through a buffer. The buffer output is the final reference clock,
CGMRDV, running at a frequency equal to fRCLK.
N O N - D I S C L O S U R E
The VCO’s output clock, CGMVCLK, running at a frequency fVCLK is fed
back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor, N (see 8.4.2.4 Programming the
PLL). The divider’s output is the VCO feedback clock, CGMVDV,
running at a frequency equal to fVCLK/N. See 21.9 CGM Operating
Conditions for more information.
The phase detector then compares the VCO feedback clock (CGMVDV)
with the final reference clock (CGMRDV). A correction pulse is
generated based on the phase difference between the two signals. The
loop filter then slightly alters the dc voltage on the external capacitor
connected to CGMXFC, based on the width and direction of the
correction pulse. The filter can make fast or slow corrections, depending
on its mode, described in 8.4.2.2 Acquisition and Tracking Modes.
The value of the external capacitor and the reference frequency
determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, fRD. The circuit determines the mode of the PLL and the lock
condition based on this comparison.
Advance Information
94
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Acquisition mode — In acquisition mode, the filter can make large
(see 21.11 CGM Acquisition/Lock Time Information) frequency
corrections to the VCO. This mode is used at PLL startup or when
the PLL has suffered a severe noise hit and the VCO frequency is
far off the desired frequency. When in acquisition mode, the ACQ
bit is clear in the PLL bandwidth control register (See 8.6.2 PLL
Bandwidth Control Register.)
•
Tracking mode — In tracking mode, the filter makes only small
(see 21.11 CGM Acquisition/Lock Time Information)
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. (See 8.4.3 Base Clock Selector Circuit.) The PLL is
automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
8.4.2.3 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. (See 8.6.2 PLL Bandwidth Control Register.) If PLL
interrupts are enabled, the software can wait for a PLL interrupt request
and then check the LOCK bit. If interrupts are disabled, software can poll
the LOCK bit continuously (during PLL startup, usually) or at periodic
intervals. In either case, when the LOCK bit is set, the VCO clock is safe
to use as the source for the base clock. (See 8.4.3 Base Clock Selector
Circuit.) If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
95
R E Q U I R E D
•
A G R E E M E N T
The PLL filter is manually or automatically configurable into one of two
operating modes:
N O N - D I S C L O S U R E
8.4.2.2 Acquisition and Tracking Modes
R E Q U I R E D
software must take appropriate action, depending on the application.
(See 8.7 Interrupts for information and precautions on using interrupts.)
N O N - D I S C L O S U R E
A G R E E M E N T
The following conditions apply when the PLL is in automatic bandwidth
control mode:
•
The ACQ bit (see 8.6.2 PLL Bandwidth Control Register) is a
read-only indicator of the mode of the filter. (See 8.4.2.2
Acquisition and Tracking Modes.)
•
The ACQ bit is set when the VCO frequency is within a certain
tolerance, ∆TRK, and is cleared when the VCO frequency is out of
a certain tolerance, ∆UNT. (See 8.10 Acquisition/Lock Time
Specifications for more information.)
•
The LOCK bit is a read-only indicator of the locked state of the
PLL.
•
The LOCK bit is set when the VCO frequency is within a certain
tolerance, ∆LOCK, and is cleared when the VCO frequency is out of
a certain tolerance, ∆UNL. (See 8.10 Acquisition/Lock Time
Specifications for more information.)
•
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See 8.6.1 PLL
Control Register.)
The PLL also can operate in manual mode (AUTO = 0). Manual mode is
used by systems that do not require an indicator of the lock condition for
proper operation. Such systems typically operate well below fBUSMAX and
require fast startup.
The following conditions apply when in manual mode:
Advance Information
96
•
ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
•
Before entering tracking mode (ACQ = 1), software must wait a
given time, tACQ (see 8.10 Acquisition/Lock Time
Specifications), after turning on the PLL by setting PLLON in the
PLL control register (PCTL).
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Software must wait a given time, tAL, after entering tracking mode
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
•
The LOCK bit is disabled.
•
CPU interrupts from the CGM are disabled.
8.4.2.4 Programming the PLL
R E Q U I R E D
•
1. Choose the desired bus frequency, fBUSDES.
Example: fBUSDES = 8 MHz
2. Calculate the desired VCO frequency, fVCLKDES.
fVCLKDES = 4 × fBUSDES
Example: fVCLKDES = 4 × 8 MHz = 32 MHz
3. Using a reference frequency, fRCLK, equal to the crystal frequency,
calculate the VCO frequency multiplier, N.
The round function means that the result is rounded to the nearest
integer.
N O N - D I S C L O S U R E
NOTE:
f VCLKDES
N = round  -------------------- fRCLK 
32 MHz
Example: N = -------------------- = 8
4 MHz
4. Calculate the VCO frequency, fVCLK.
f VCLK = N × f RCLK
Example: fVCLK = 8 × 4 MHz = 32 MHz
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
A G R E E M E N T
Use this procedure to program the PLL:
Advance Information
97
R E Q U I R E D
5. Calculate the bus frequency, fBUS, and compare fBUS with fBUSDES.
If the calculated fBUS is not within the tolerance limits of your
application, select another fBUSDES or another fRCLK.
f VCLK
f BUS = ----------4
32 MHz
Example: f BUS = -------------------- = 8 MHz
4
A G R E E M E N T
6. Using the value 4.9152 MHz for fNOM, calculate the VCO linear
range multiplier, L. The linear range multiplier controls the
frequency range of the PLL.
f VCLK
L = round  ----------- f NOM 
Example: L
=
32 MHz
-------------------------------- = 7
4.9152 MHz
7. Calculate the VCO center-of-range frequency, fVRS. The
center-of-range frequency is the midpoint between the minimum
and maximum frequencies attainable by the PLL.
fVRS = L × fNOM
N O N - D I S C L O S U R E
Example: fVRS = 7 × 4.9152 MHz = 34.4 MHz
NOTE:
Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.
For proper operation,
f NOM
f VRS – f VCLK ≤ --------------2
8. Program the PLL registers accordingly:
a. In the upper four bits of the PLL programming register (PPG),
program the binary equivalent of N.
b. In the lower four bits of the PLL programming register (PPG),
program the binary equivalent of L.
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A zero value for N is interpreted exactly the same as a value of
one.
•
A zero value for L disables the PLL and prevents its selection as
the source for the base clock. (See 8.4.3 Base Clock Selector
Circuit.)
8.4.3 Base Clock Selector Circuit
This circuit is used to select either the crystal clock (CGMXCLK) or the
VCO clock (CGMVCLK) as the source of the base clock (CGMOUT).
The two input clocks go through a transition control circuit that waits up
to three CGMXCLK cycles and three CGMVCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in
stasis. The output of the transition control circuit is then divided by two
to correct the duty cycle. Therefore, the bus clock frequency, which is
one-half of the base clock frequency, is one-fourth the frequency of the
selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the VCO clock. The VCO clock also cannot
be selected as the base clock source if the factor L is programmed to a
zero. This value would set up a condition inconsistent with the operation
of the PLL, so that the PLL would be disabled and the crystal clock would
be forced as the source of the base clock.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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R E Q U I R E D
•
A G R E E M E N T
The programming method described in 8.4.2.4 Programming the PLL
does not account for two possible exceptions. A value of zero for N or L
is meaningless when used in the equations given. To account for these
exceptions:
N O N - D I S C L O S U R E
8.4.2.5 Special Programming Exceptions
In its typical configuration, the CGM requires seven external
components. Five of these are for the crystal oscillator and two are for
the PLL.
The crystal oscillator is normally connected in a Pierce oscillator
configuration, as shown in Figure 8-2. Figure 8-2 shows only the logical
representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
A G R E E M E N T
R E Q U I R E D
8.4.4 CGM External Connections
•
Crystal, X1
•
Fixed capacitor, C1
•
Tuning capacitor, C2, can also be a fixed capacitor
•
Feedback resistor, RB
•
Series resistor, RS, optional
N O N - D I S C L O S U R E
The series resistor (RS) is included in the diagram to follow strict Pierce
oscillator guidelines and may not be required for all ranges of operation,
especially with high-frequency crystals. Refer to the crystal
manufacturer’s data for more information.
Figure 8-2 also shows the external components for the PLL:
•
Bypass capacitor, CBYP
•
Filter capacitor, CF
Routing should be done with great care to minimize signal cross talk and
noise. (See 8.10 Acquisition/Lock Time Specifications for routing
information and more information on the filter capacitor’s value and its
effects on PLL performance.)
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R E Q U I R E D
CGMXCLK
OSC1
OSC2
VSS
RS *
CGMXFC
VDDA/VDDAREF
VDD
CF
RB
CBYP
C1
A G R E E M E N T
X1
C2
*RS can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data.
Figure 8-2. CGM External Connections
8.5 I/O Signals
The following paragraphs describe the CGM I/O signals.
8.5.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
8.5.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
8.5.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase
corrections. A small external capacitor is connected to this pin.
NOTE:
To prevent noise problems, CF should be placed as close to the
CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the CF connection.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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N O N - D I S C L O S U R E
SIMOSCEN
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
8.5.4 Analog Power Pin (VDDA/VDDAREF)
VDDA/VDDAREF is a power pin used by the analog portions of the PLL.
Connect the VDDA/VDDAREF pin to the same voltage potential as the VDD
pin.
NOTE:
Route VDDA/VDDAREF carefully for maximum noise immunity and place
bypass capacitors as close as possible to the package.
8.5.5 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator and PLL.
8.5.6 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal, fXCLK, and comes directly from the crystal oscillator circuit.
Figure 8-2 shows only the logical relation of CGMXCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
8.5.7 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM,
which generates the MCU clocks. CGMOUT is a 50% duty cycle clock
running at twice the bus frequency. CGMOUT is software programmable
to be either the oscillator output, CGMXCLK, divided by two or the VCO
clock, CGMVCLK, divided by two.
8.5.8 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
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PLL control register (PCTL) (See 8.6.1 PLL Control Register.)
•
PLL bandwidth control register (PBWC) (See 8.6.2 PLL
Bandwidth Control Register.)
•
PLL programming register (PPG) (See 8.6.3 PLL Programming
Register.)
Table 8-2 is a summary of the CGM registers.
Table 8-2. CGM I/O Register Summary
Addr.
Register Name
Bit 7
Read:
$001C
$001D
$001E
PLL Control Register
Write:
(PCTL)
Reset:
Read:
PLL Bandwidth Control
Write:
Register (PBWC)
Reset:
Read:
PLL Programming Register
Write:
(PPG)
Reset:
PLLIE
0
AUTO
6
PLLF
0
LOCK
5
4
PLLON
BCS
1
0
ACQ
XLD
3
2
1
Bit 0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
0
1
1
0
0
1
1
0
= Unimplemented
NOTES:
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
MC68HC08AS20 — Rev. 4.1
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R E Q U I R E D
•
A G R E E M E N T
These registers control and monitor operation of the CGM:
N O N - D I S C L O S U R E
8.6 CGM Registers
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, and the base clock selector bit.
Address:
$001C
Bit 7
Read:
Write:
A G R E E M E N T
R E Q U I R E D
8.6.1 PLL Control Register
Reset:
PLLIE
0
6
PLLF
0
5
4
PLLON
BCS
1
0
3
2
1
Bit 0
1
1
1
1
1
1
1
1
= Unimplemented
Figure 8-3. PLL Control Register (PCTL)
PLLIE — PLL Interrupt Enable Bit
N O N - D I S C L O S U R E
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE:
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Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). (See 8.4.3 Base Clock Selector
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU
is powering up.
1 = PLL on
0 = PLL off
R E Q U I R E D
PLLON — PLL On Bit
NOTE:
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. (See 8.4.3 Base Clock Selector Circuit.)
PCTL[3:0] — Unimplemented bits
These bits provide no function and always read as logic 1s.
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N O N - D I S C L O S U R E
This read/write bit selects either the crystal oscillator output,
CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM
output, CGMOUT. CGMOUT frequency is one-half the frequency of
the selected clock. BCS cannot be set while the PLLON bit is clear.
After toggling BCS, it may take up to three CGMXCLK and three
CGMVCLK cycles to complete the transition from one source clock to
the other. During the transition, CGMOUT is held in stasis. (See 8.4.3
Base Clock Selector Circuit.) Reset and the STOP instruction clear
the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
A G R E E M E N T
BCS — Base Clock Select Bit
The PLL bandwidth control register:
A G R E E M E N T
R E Q U I R E D
8.6.2 PLL Bandwidth Control Register
•
Selects automatic or manual (software-controlled) bandwidth
control mode
•
Indicates when the PLL is locked
•
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking mode.
Address:
$001D
Bit 7
Read:
Write:
Reset:
AUTO
0
6
LOCK
0
5
4
ACQ
XLD
0
0
3
2
1
Bit 0
0
0
0
0
0
0
0
0
= Unimplemented
N O N - D I S C L O S U R E
Figure 8-4. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
logic 0 and has no meaning. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
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XLD — Crystal Loss Detect Bit
When the VCO output (CGMVCLK) is driving CGMOUT, this
read/write bit can indicate whether the crystal reference frequency is
active or not. To check the status of the crystal reference, follow these
steps:
1. Write a logic 1 to XLD.
2. Wait N × 4 cycles. (N is the VCO frequency multiplier.)
3. Read XLD.
1 = Crystal reference not active
0 = Crystal reference active
The crystal loss detect function works only when the BCS bit is set,
selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD
always reads as logic 0.
PBWC[3:0] — Reserved for Test
These bits enable test functions not available in user mode. To ensure
software portability from development systems to user applications,
software should write 0s to PBWC[3:0] whenever writing to PBWC.
MC68HC08AS20 — Rev. 4.1
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R E Q U I R E D
In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
A G R E E M E N T
When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the
PLL is in acquisition or tracking mode.
N O N - D I S C L O S U R E
ACQ — Acquisition Mode Bit
R E Q U I R E D
8.6.3 PLL Programming Register
The PLL programming register contains the programming information for
the modulo feedback divider and the programming information for the
hardware configuration of the VCO.
Address:
A G R E E M E N T
Read:
Write:
Reset:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
0
1
1
0
0
1
1
0
Figure 8-5. PLL Programming Register (PPG)
MUL[7:4] — Multiplier Select Bits
N O N - D I S C L O S U R E
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See 8.4.2 Phase-Locked Loop
Circuit (PLL).) A value of $0 in the multiplier select bits configures the
modulo feedback divider the same as a value of $1. Reset initializes
these bits to $6 to give a default multiply value of 6.
Table 8-3. VCO Frequency Multiplier (N) Selection
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MUL7:MUL6:MUL5:MUL4
VCO Frequency Multiplier (N)
0000
1
0001
1
0010
2
0011
3
1101
13
1110
14
1111
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency,
fVRS, (see 8.4.2 Phase-Locked Loop Circuit (PLL).) VRS[7:4] cannot
be written when the PLLON bit in the PLL control register (PCTL) is
set. (See 8.4.2.5 Special Programming Exceptions.) A value of $0
in the VCO range selects bits, disables the PLL, and clears the BCS
bit in the PCTL. (See 8.4.3 Base Clock Selector Circuit and 8.4.2.5
Special Programming Exceptions for more information.) Reset
initializes the bits to $6 to give a default range multiply value of 6.
NOTE:
The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
8.7 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL,
becomes set whether interrupts are enabled or not. When the AUTO bit
is clear, CPU interrupts from the PLL are disabled and PLLF reads as
logic 0.
Software should read the LOCK bit after a PLL interrupt request to see
if the request was due to an entry into lock or an exit from lock. When the
PLL enters lock, the VCO clock, CGMVCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not frequency sensitive,
MC68HC08AS20 — Rev. 4.1
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R E Q U I R E D
VRS[7:4] — VCO Range Select Bits
A G R E E M E N T
The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
N O N - D I S C L O S U R E
NOTE:
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
interrupts should be disabled to prevent PLL interrupt service routines
from impeding software performance or from exceeding stack
limitations.
NOTE:
Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
8.8 Special Modes
The WAIT and STOP instructions put the MCU in low-power standby
modes.
8.8.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait
mode, software can disengage and turn off the PLL by clearing the BCS
and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
8.8.2 Stop Mode
When the STOP instruction executes, the SIM drives the SIMOSCEN
signal low, disabling the CGM and holding low all CGM outputs
(CGMXCLK, CGMOUT, and CGMINT).
If the STOP instruction is executed with the VCO clock (CGMVCLK)
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock
(CGMXCLK) divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
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To protect the PLLF bit during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
the PLL control register during the break state without affecting the
PLLF bit.
8.10 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensures the highest stability and lowest acquisition/lock times.
8.10.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the
reaction time, within specified tolerances, of the system to a step input.
In a PLL, the step input occurs when the PLL is turned on or when it
suffers a noise hit. The tolerance is usually specified as a percent of the
step input or when the output settles to the desired value plus or minus
a percent of the frequency change. Therefore, the reaction time is
constant in this definition, regardless of the size of the step input. For
example, consider a system with a 5% acquisition time tolerance. If a
command instructs the system to change from 0 Hz to 1 MHz, the
acquisition time is the time taken for the frequency to reach
1 MHz ±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is
operating at 1 MHz and suffers a –100 kHz noise hit, the acquisition time
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R E Q U I R E D
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
A G R E E M E N T
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 9.8.3 SIM Break Flag Control
Register.)
N O N - D I S C L O S U R E
8.9 CGM During Break Interrupts
R E Q U I R E D
is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5%
of the 100-kHz step input.
A G R E E M E N T
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.
N O N - D I S C L O S U R E
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are as follows:
•
Acquisition time, tACQ, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance, ∆TRK.
Acquisition time is based on an initial frequency error, [(fDES –
fORIG)/fDES], of not more than ±100%. In automatic bandwidth
control mode (see 8.4.2.3 Manual and Automatic PLL
Bandwidth Modes), acquisition time expires when the ACQ bit
becomes set in the PLL bandwidth control register (PBWC).
•
Lock time, tLOCK, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance, ∆LOCK. Lock
time is based on an initial frequency error, [(fDES – fORIG)/fDES], of
not more than ±100%. In automatic bandwidth control mode, lock
time expires when the LOCK bit becomes set in the PLL
bandwidth control register (PBWC). (See 8.4.2.3 Manual and
Automatic PLL Bandwidth Modes.)
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many cases.
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Another critical parameter is the external filter capacitor. The PLL
modifies the voltage on the VCO by adding or subtracting charge from
this capacitor. Therefore, the rate at which the voltage changes for a
given frequency error (thus change in charge) is proportional to the
capacitor size. The size of the capacitor also is related to the stability of
the PLL. If the capacitor is too small, the PLL cannot make small enough
adjustments to the voltage and the system cannot lock. If the capacitor
is too large, the PLL may not be able to adjust the voltage in a
reasonable time. (See 8.10.3 Choosing a Filter Capacitor.)
Also important is the operating voltage potential applied to the PLL
analog portion potential (VDDA/VDDAREF). Typically VDDA/VDDAREF is at
the same potential as VDD. The power supply potential alters the
characteristics of the PLL. A fixed value is best. Variable supplies, such
as batteries, are acceptable if they vary within a known range at very
slow speeds. Noise on the power supply is not acceptable, because it
causes small frequency errors which continually change the acquisition
time of the PLL.
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R E Q U I R E D
The most critical parameter which affects the PLL reaction times is the
reference frequency, fRDV. This frequency is the input to the phase
detector and controls how often the PLL makes corrections. For stability,
the corrections must be small compared to the desired frequency, so
several corrections are required to reduce the frequency error.
Therefore, the slower the reference the longer it takes to make these
corrections. This parameter is also under user control via the choice of
an external crystal frequency, fXCLK.
A G R E E M E N T
Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
N O N - D I S C L O S U R E
8.10.2 Parametric Influences on Reaction Time
R E Q U I R E D
8.10.3 Choosing a Filter Capacitor
As described in 8.10.2 Parametric Influences on Reaction Time, the
external filter capacitor, CF, is critical to the stability and reaction time of
the PLL. The PLL is also dependent on reference frequency, fRDV, and
supply voltage, VDD. The value of the capacitor, therefore, must be
chosen with supply potential and reference frequency in mind. For
proper operation, the external filter capacitor must be chosen according
to the following equation. Refer to 8.4.2 Phase-Locked Loop Circuit
(PLL) for the value of fRDV and 21.11 CGM Acquisition/Lock Time
Information for the value of CFACT.
V DDA
C F = C FACT  -----------f RDV 
N O N - D I S C L O S U R E
A G R E E M E N T
Temperature and processing also can affect acquisition time because
the electrical characteristics of the PLL change. The part operates as
specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of
the PLL. These factors include noise injected into the PLL through the
filter capacitor, filter capacitor leakage, stray impedances on the circuit
board, and even humidity or circuit board contamination.
For the value of VDDA, choose the voltage potential at which the MCU is
operating. If the power supply is variable, choose a value near the middle
of the range of possible supply values.
This equation does not always yield a commonly available capacitor
size, so round to the nearest available size. If the value is between two
different sizes, choose the higher value for better stability. Choosing the
lower size may seem attractive for acquisition time improvement, but the
PLL can become unstable. Also, always choose a capacitor with a tight
tolerance (±20% or better) and low dissipation.
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Freescale Semiconductor
Correct selection of filter capacitor, CF (See 8.10.3 Choosing a
Filter Capacitor.)
•
Room temperature operation
•
Negligible external leakage on CGMXFC
•
Negligible noise
The K factor in the equations is derived from internal PLL parameters.
KACQ is the K factor when the PLL is configured in acquisition mode, and
KTRK is the K factor when the PLL is configured in tracking mode. (See
8.4.2.2 Acquisition and Tracking Modes.)
V DDA  8 
- -----------t ACQ =  ---------- f RDV   K ACQ
V DDA  4 
- ----------t AL =  ---------- f RDV   K TRK
t LOCK = t ACQ + t AL
NOTE:
There is an inverse proportionality between the lock time and the
reference frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See 8.4.2.3
Manual and Automatic PLL Bandwidth Modes.) A certain number of
clock cycles, nACQ, is required to ascertain that the PLL is within the
tracking mode entry tolerance, ∆TRK, before exiting acquisition mode.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
115
R E Q U I R E D
•
A G R E E M E N T
The actual acquisition and lock times can be calculated using the
equations in this subsection. These equations yield nominal values
under the following conditions:
N O N - D I S C L O S U R E
8.10.4 Reaction Time Calculation
R E Q U I R E D
Additionally, a certain number of clock cycles, nTRK, is required to
ascertain that the PLL is within the lock mode entry tolerance, ∆LOCK.
Therefore, the acquisition time, tACQ, is an integer multiple of nACQ/fRDV,
and the acquisition to lock time, tAL, is an integer multiple of nTRK/fRDV.
Refer to 8.4.2 Phase-Locked Loop Circuit (PLL) for the value of fRDV.
Also, since the average frequency over the entire measurement period
must be within the specified tolerance, the total time usually is longer
than tLock as calculated above.
N O N - D I S C L O S U R E
A G R E E M E N T
In manual mode, it is usually necessary to wait considerably longer than
tLock before selecting the PLL clock (see 8.4.3 Base Clock Selector
Circuit), because the factors described in 8.10.2 Parametric
Influences on Reaction Time can slow the lock time considerably.
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Section 9. System Integration Module (SIM)
9.1 Contents
9.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 121
9.3.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.3.2
Clock Startup from POR or LVI Reset. . . . . . . . . . . . . . . . 121
9.3.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . 122
9.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 122
9.4.1
External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.4.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . 124
9.4.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
9.4.2.2
Computer Operating Properly (COP) Reset. . . . . . . . . . 126
9.4.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.4.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .126
9.4.2.5
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . 126
9.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.5.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 127
9.5.2
SIM Counter During Stop Mode Recovery . . . . . . . . . . . . 127
9.5.3
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . 127
9.6
Program Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . .128
9.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.6.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.6.1.2
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.6.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
9.6.3
Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9.6.4
Status Flag Protection in Break Mode. . . . . . . . . . . . . . . . 132
9.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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117
A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
N O N - D I S C L O S U R E
9.2
R E Q U I R E D
Advance Information — MC68HC08AS20
9.2 Introduction
This section describes the system integration module (SIM), which
supports up to 24 external and/or internal interrupts. The SIM is a system
state controller that coordinates CPU and exception timing. Together
with the central processor unit (CPU), the SIM controls all MCU
activities. A block diagram of the SIM is shown in Figure 9-1. Table 9-1
is a summary of the SIM input/output (I/O) registers.
A G R E E M E N T
R E Q U I R E D
9.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
9.8.1
SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . 136
9.8.2
SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . 138
9.8.3
SIM Break Flag Control Register. . . . . . . . . . . . . . . . . . . .139
The SIM is responsible for:
•
Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
N O N - D I S C L O S U R E
– Internal clock control
•
Master reset control, including power-on reset (POR) and
computer operating properly (COP) timeout
•
Interrupt control
– Acknowledge timing
– Arbitration control timing
– Vector address generation
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118
•
CPU enable/disable timing
•
Modular architecture expandable to 128 interrupt sources
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
MODULE STOP
MODULE WAIT
CPU STOP FROM CPU
CPU WAIT FROM CPU
STOP/WAIT
CONTROL
SIMOSCEN TO CGM
SIM
COUNTER
COP CLOCK
CGMXCLK FROM CGM
A G R E E M E N T
CGMOUT FROM CGM
÷2
CLOCK
CONTROL
RESET
PIN LOGIC
CLOCK GENERATORS
INTERNAL CLOCKS
LVI FROM LVI MODULE
POR CONTROL
MASTER
RESET
CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
ILLEGAL OPCODE FROM CPU
ILLEGAL ADDRESS FROM ADDRESS
MAP DECODERS
COP FROM COP MODULE
INTERRUPT CONTROL
AND PRIORITY DECODE
N O N - D I S C L O S U R E
RESET
INTERRUPT SOURCES
CPU INTERFACE
Figure 9-1. SIM Block Diagram
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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R E Q U I R E D
Table 9-1. SIM I/O Register Summary
Addr.
Register Name
$FE00
Read:
SIM Break Status Register
Write:
(SBSR)
Reset:
6
5
4
3
2
1
Bit 0
R
R
R
R
R
R
SBSW
R
0
Read:
$FE01
Read:
$FE03
POR
PIN
COP
ILOP
ILAD
0
LVI
0
1
X
0
0
0
0
X
0
BCFE
R
R
R
R
R
R
R
SIM Reset Status Register
Write:
(SRSR)
Reset:
SIM Break Flag Control Register
Write:
(SBFCR)
Reset:
0
R
= Reserved
= Unimplemented
X = Indeterminate
Table 9-2 shows the internal signal names used in this section.
Table 9-2. Signal Name Conventions
N O N - D I S C L O S U R E
A G R E E M E N T
Bit 7
Signal Name
Description
CGMXCLK
Buffered version of OSC1 from clock generator module (CGM)
CGMVCLK
PLL output
CGMOUT
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
IAB
Internal address bus
IDB
Internal data bus
PORRST
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Signal from the power-on reset module to the SIM
IRST
Internal reset signal
R/W
Read/write signal
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 9-2. This clock can come
from either an external oscillator or from the on-chip PLL. (See Section
8. Clock Generator Module (CGM).)
R E Q U I R E D
9.3 SIM Bus Clock Control and Generation
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. (See Section 8. Clock Generator Module (CGM).)
9.3.2 Clock Startup from POR or LVI Reset
CGMXCLK
OSC1
CGMVCLK
PLL
CLOCK
SELECT
CIRCUIT
÷2
A
CGMOUT
B S*
*When S = 1,
CGMOUT = B
N O N - D I S C L O S U R E
When the power-on reset (POR) module or the low-voltage inhibit (LVI)
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after 4096 CGMXCLK cycles.
The RST pin is driven low by the SIM during this entire period. The bus
clocks start upon completion of the timeout.
SIM COUNTER
BUS CLOCK
GENERATORS
÷2
SIM
BCS
PTC3
MONITOR MODE
USER MODE
CGM
Figure 9-2. CGM Clock Signals
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
A G R E E M E N T
9.3.1 Bus Timing
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121
R E Q U I R E D
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. (See 9.7.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. However, some modules can
be programmed to be active in wait mode. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode.
9.4 Reset and System Initialization
The MCU has these reset sources:
N O N - D I S C L O S U R E
A G R E E M E N T
9.3.3 Clocks in Stop Mode and Wait Mode
•
Power-on reset module (POR)
•
External reset pin (RST)
•
Computer operating properly module (COP)
•
Low-voltage inhibit module (LVI)
•
Illegal opcode
•
Illegal address
Each of these resets produces the vector $FFFE–FFFF ($FEFE–FEFF
in monitor mode) and asserts the internal reset signal (IRST). IRST
causes all registers to be returned to their default values and all modules
to be returned to their reset states.
An internal reset clears the SIM counter (see 9.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR). (See 9.8 SIM Registers.)
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Pulling the asynchronous RST pin low halts all processing. The PIN bit
of the SIM reset status register (SRSR) is set as long as RST is held low
for a minimum of 67 CGMXCLK cycles, assuming that neither the POR
nor the LVI was the source of the reset. See Table 9-3 for details. Figure
9-3 shows the relative timing.
Reset Type
Number of Cycles Required to Set PIN
POR/LVI
4163 (4096 + 64 + 3)
All Others
67 (64 + 3)
A G R E E M E N T
Table 9-3. PIN Bit Set Timing
CGMOUT
RST
IAB
PC
VECT H
R E Q U I R E D
9.4.1 External Pin Reset
VECT L
N O N - D I S C L O S U R E
Figure 9-3. External Reset Timing
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
123
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles. See Figure
9-4. An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, LVI, or POR. See Figure 9-5. Note that for LVI or
POR resets, the SIM cycles through 4096 CGMXCLK cycles during
which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in Figure 9-4.
A G R E E M E N T
R E Q U I R E D
9.4.2 Active Resets from Internal Sources
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
IRST
RST
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
N O N - D I S C L O S U R E
CGMXCLK
IAB
VECTOR HIGH
Figure 9-4. Internal Reset Timing
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
Figure 9-5. Sources of Internal Reset
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Another 64 CGMXCLK cycles later, the CPU
and memories are released from reset to allow the reset vector
sequence to occur.
R E Q U I R E D
9.4.2.1 Power-On Reset
A POR pulse is generated.
•
The internal reset signal is asserted.
•
The SIM enables CGMOUT.
•
Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
•
The RST pin is driven low during the oscillator stabilization time.
•
The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
N O N - D I S C L O S U R E
•
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
CGMXCLK
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 9-6. POR Recovery
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
A G R E E M E N T
At power-on, these events occur:
Advance Information
125
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
9.4.2.2 Computer Operating Properly (COP) Reset
The overflow of the COP counter causes an internal reset and sets the
COP bit in the SIM reset status register (SRSR) if the COPD bit in the
MOR register is at logic 0. (See Section 13. Computer Operating
Properly (COP).)
9.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
NOTE:
A $9E opcode (pre-byte for SP instructions) followed by an $8E opcode
(stop instruction) generates a stop mode recovery reset.
If the stop enable bit, STOP, in the MOR register is logic 0, the SIM treats
the STOP instruction as an illegal opcode and causes an illegal opcode
reset.
9.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset.
9.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit (LVI) module asserts its output to the SIM when
the VDD voltage falls to the VLVII voltage. The LVI bit in the SIM reset
status register (SRSR) is set and a chip reset is asserted if the LVIPWRD
and LVIRSTD bits in the CONFIG register are at logic 0. The RST pin will
be held low until the SIM counts 4096 CGMXCLK cycles after VDD rises
above VLVIR. Another 64 CGMXCLK cycles later, the CPU is released
from reset to allow the reset vector sequence to occur. (See Section 10.
Low-Voltage Inhibit (LVI).)
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
9.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the clock generation module (CGM) to drive the
bus clock state machine.
9.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the MOR
register. If the SSREC bit is a logic 1, then the stop recovery is reduced
from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK
cycles. This is ideal for applications using canned oscillators that do not
require long startup times from stop mode. External crystal applications
should use the full stop recovery time, that is, with SSREC cleared.
9.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 9.7.2 Stop Mode
for details.) The SIM counter is free-running after all reset states. (See
9.4.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
127
R E Q U I R E D
A G R E E M E N T
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly (COP) module. The SIM
counter overflow supplies the clock for the COP module. The SIM
counter is 12 bits long and is clocked by the falling edge of CGMXCLK.
N O N - D I S C L O S U R E
9.5 SIM Counter
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
9.6 Program Exception Control
Normal, sequential program execution can be changed in three different
ways:
•
Interrupts
– Maskable hardware CPU interrupts
– Nonmaskable software interrupt instruction (SWI)
•
Reset
•
Break interrupts
9.6.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 9-7 shows interrupt entry timing.
Figure 9-9 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced or the I bit is cleared.
(See Figure 9-8.)
MODULE
INTERRUPT
IAB
LAST
ADDRESS
IDB
SP
SP – 1
SP – 2
PC – 1
END OF
PC – 1
LAST INSTR. LOW BYTE HIGH BYTE
SP – 3
X
SP – 4
A
VECTOR
VECTOR
ADDR. HIGH ADDR. LOW
CCR
VECTOR
HIGH
NEW PC
VECTOR
LOW
NEW PC
+1
OPCODE
R/W
Figure 9-7. Hardware Interrupt Entry Timing
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
FROM RESET
BREAK
INTERRUPT?
I BIT
SET?
YES
NO
I BIT SET?
A G R E E M E N T
YES
NO
HARDWARE
INTERRUPT?
YES
NO
STACK CPU REGISTERS.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
SWI
INSTRUCTION?
N O N - D I S C L O S U R E
FETCH NEXT
INSTRUCTION.
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CPU REGISTERS.
NO
EXECUTE INSTRUCTION.
Figure 9-8. Interrupt Processing
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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R E Q U I R E D
MODULE
INTERRUPT
IAB
RTI
ADDRESS
RTI
ADDR. + 1
RTI
OPCODE
IDB
SP – 4
IRRELEVANT
DATA
SP – 3
CCR
SP – 2
A
SP – 1
X
SP
PC
PC – 1
PC – 1
HIGH BYTE LOW BYTE
PC + 1
OPCODE
OPERAND
R/W
9.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register) and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 9-10
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
N O N - D I S C L O S U R E
A G R E E M E N T
Figure 9-9. Hardware Interrupt Recovery Timing
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE:
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130
To maintain compatibility with the M68HC05, M6805, and M146805
Families, the H register is not pushed on the stack during interrupt entry.
If the interrupt service routine modifies the H register or uses the indexed
addressing mode, software should save the H register and then restore
it prior to exiting the routine.
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
BACKGROUND
ROUTINE
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
INT2
A G R E E M E N T
PULH
RTI
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 9-10. Interrupt Recognition Example
9.6.1.2 SWI Instruction
The SWI instruction is a nonmaskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE:
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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N O N - D I S C L O S U R E
LDA #$FF
R E Q U I R E D
CLI
R E Q U I R E D
All reset sources always have higher priority than interrupts and cannot
be arbitrated.
9.6.3 Break Interrupts
The break module can stop normal program flow at a
software-programmable break point by asserting its break interrupt
output. (See Section 11. Break Module (Break).) The SIM puts the
CPU into the break state by forcing it to the SWI vector location. Refer to
the break interrupt subsection of each module to see how the break state
affects each module.
9.6.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select to protect flags from
being cleared by properly initializing the break clear flag enable bit
(BCFE) in the SIM break flag control register (SBFCR). (See 9.8.3 SIM
Break Flag Control Register.)
N O N - D I S C L O S U R E
A G R E E M E N T
9.6.2 Reset
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a two-step clearing mechanism — for example, a read
of one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the flag
as usual.
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Executing the WAIT or STOP instruction puts the MCU in a low-power
mode for standby situations. The SIM holds the CPU in a non-clocked
state. The operation of each of these modes is described below. Both
STOP and WAIT clear the interrupt mask (I) in the condition code
register, allowing interrupts to occur.
R E Q U I R E D
9.7 Low-Power Modes
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module
is active or inactive in wait mode. Some modules can be programmed to
be active in wait mode.
Wait mode also can be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM
break status register (SBSR). If the COP disable bit, COPD, in the mask
option register (MOR $001F) is logic 0, then the computer operating
properly module (COP) is enabled and remains active in wait mode.
IAB
IDB
WAIT ADDR
WAIT ADDR + 1
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 9-11. Wait Mode Entry Timing
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
133
N O N - D I S C L O S U R E
In wait mode, the CPU clocks are inactive while one set of peripheral
clocks continues to run. Figure 9-11 shows the timing for wait mode
entry.
A G R E E M E N T
9.7.1 Wait Mode
R E Q U I R E D
Figure 9-12 and Figure 9-13 show the timing for WAIT recovery.
IAB
IDB
$A6
$A6
$6E0C
$A6
$01
$00FF
$00FE
$0B
$00FD
$00FC
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin or CPU interrupt or break interrupt
A G R E E M E N T
N O N - D I S C L O S U R E
$6E0B
Figure 9-12. Wait Recovery from Interrupt or Break
32
CYCLES
$6E0B
IAB
IDB
$A6
$A6
32
CYCLES
RSTVCT H
RSTVCTL
$A6
RST
CGMXCLK
Figure 9-13. Wait Recovery from Internal Reset
9.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and
CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop
recovery time is selectable using the short stop recovery (SSREC) bit in
the MOR register ($001F). If SSREC is set, stop recovery is reduced
from the normal delay of 4096 CGMXCLK cycles down to 32. This is
Advance Information
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External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 9-14 shows stop mode entry timing.
CPUSTOP
IAB
IDB
STOP ADDR
STOP ADDR + 1
PREVIOUS DATA
SAME
NEXT OPCODE
SAME
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
N O N - D I S C L O S U R E
Figure 9-14. Stop Mode Entry Timing
STOP RECOVERY PERIOD
CGMXCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 9-15. Stop Mode Recovery from Interrupt or Break
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
NOTE:
A G R E E M E N T
ideal for applications using canned oscillators that do not require long
startup times from stop mode.
Advance Information
135
The SIM has three memory mapped registers.
9.8.1 SIM Break Status Register
The SIM break status register contains a flag to indicate that a break
caused an exit from stop mode or wait mode.
A G R E E M E N T
R E Q U I R E D
9.8 SIM Registers
Address:
Read:
Write:
$FE00
Bit 7
6
5
4
3
2
1
Bit 0
R
R
R
R
R
R
SBSW
R
Reset:
0
R
= Reserved
Figure 9-16. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
N O N - D I S C L O S U R E
This status bit is useful in applications requiring a return to wait mode
or stop mode after exiting from a break interrupt. Clear SBSW by
writing a logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode exited by break interrupt
0 = Stop mode or wait mode not exited by break interrupt
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
HIBYTE
EQU
5
LOBYTE
EQU
6
;
If not SBSW, do RTI
BRCLR
SBSW,SBSR, RETURN
; See if wait mode or stop mode was exited by
; break.
TST
LOBYTE,SP
;If RETURNLO is not zero,
BNE
DOLO
;then just decrement low byte.
DEC
HIBYTE,SP
;Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
;Point to WAIT/STOP opcode.
RETURN
PULH
RTI
N O N - D I S C L O S U R E
;Restore H register.
R E Q U I R E D
; This code works if the H register has been pushed onto the stack in the break service routine
;
software. This code should be executed at the end of the break service routine software.
;
A G R E E M E N T
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this. Writing 0 to the SBSW bit
clears it.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
137
This read-only register contains flags to show reset sources. A power-on
reset sets the POR flag and clears all other flags. Reset sources other
than power-on reset do not clear all other flags.
Reading the reset status register clears all reset flags. Reset service can
read the reset status register to clear the register after power-on reset
and to determine the source of any subsequent reset.
NOTE:
A G R E E M E N T
R E Q U I R E D
9.8.2 SIM Reset Status Register
Only a read of the reset status register clears all reset flags. After
multiple resets from different sources without reading the register,
multiple flags remain set.
Address:
Read:
$FE01
Bit 7
6
5
4
3
2
1
Bit 0
POR
PIN
COP
ILOP
ILAD
0
LVI
0
1
X
0
0
0
0
X
0
Write:
Reset:
= Unimplemented
X = Indeterminate
N O N - D I S C L O S U R E
Figure 9-17. SIM Reset Status Register (SRSR)
POR — Power-On Reset Flag
1 = Power-on reset since last read of RSR
0 = Read of RSR since last power-on reset
PIN — External Reset Flag
1 = External reset since last read of RSR
0 = Power-on reset or read of RSR since last external reset
COP — COP Reset Flag
1 = COP reset since last read of RSR
0 = Power-on reset or read of RSR since last COP reset
ILOP — Illegal Opcode Reset Flag
1 = Illegal opcode reset since last read of RSR
0 = Power-on reset or read of RSR since last illegal opcode reset
Advance Information
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MC68HC08AS20 —Rev. 4.1
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LVI — Low-Voltage Inhibit Reset Flag
1 = LVI reset since last read of RSR
0 = Power-on reset or read of RSR since last LVI reset
R E Q U I R E D
ILAD — Illegal Address Reset Flag
1 = Illegal address reset since last read of RSR
0 = Power-on reset or read of RSR since last illegal address reset
The SIM break control register contains a bit that enables software to
clear status bits while the MCU is in a break state.
Address:
Read:
Write:
Reset:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
0
R
= Reserved
A G R E E M E N T
9.8.3 SIM Break Flag Control Register
BCFE — Break Clear Flag Enable Bit
In some module registers, this read/write bit will enable software to
clear status bits by accessing status registers only while the MCU is
in a break state. To clear status bits during the break state, the BCFE
bit must be set.This operation is important for modules with status bits
which can be cleared only by being read. See the register descriptions
in each module for additional details.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
139
N O N - D I S C L O S U R E
Figure 9-18. SIM Break Flag Control Register (SBFCR)
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
10.4.1
Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
10.4.2
Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 143
10.5
LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
10.6
LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
10.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
10.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
10.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
10.2 Introduction
This section describes the low-voltage inhibit module (LVI), which
monitors the voltage on the VDD pin and can force a reset when the VDD
voltage falls to the LVI trip voltage.
10.3 Features
Features of the LVI module include:
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
•
Programmable LVI Reset
•
Programmable Power Consumption
Advance Information
141
R E Q U I R E D
10.1 Contents
A G R E E M E N T
Section 10. Low-Voltage Inhibit (LVI)
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
Figure 10-1 shows the structure of the LVI module. The LVI module
contains a bandgap reference circuit and comparator. The LVI power
disable bit, LVIPWRD, disables the LVI from monitoring VDD voltage.
The LVI reset disable bit, LVIRSTD, disables the LVI module from
generating a reset when VDD falls below a voltage, VLVII. LVIPWRD and
LVIRSTD are in the MOR register ($001F) (see Section 5. Mask
Options). Once an LVI reset occurs, the MCU remains in reset until VDD
rises above a voltage, VLVIR. The output of the comparator controls the
state of the LVIOUT flag in the LVI status register (LVISR).
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
10.4 Functional Description
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
LVISTOP
VDD
STOP INSTRUCTION
LVIPWRD
FROM MOR
FROM MOR
LVIRSTD
LVI RESET
LOW VDD
DETECTOR
LVIOUT
Figure 10-1. LVI Module Block Diagram
Table 10-1. LVI I/O Register Summary
Addr.
Register Name
Bit 7
Read: LVIOUT
$FE0F
6
5
4
0
0
0
0
0
0
LVI Status Register (LVISR) Write:
Reset:
0
3
2
LVISTOP
LVILCK
0
0
1
Bit 0
0
0
0
0
= Unimplemented
Advance Information
142
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
In applications that require VDD to remain above the VLVII level, enabling
LVI resets allows the LVI module to reset the MCU when VDD falls to the
VLVII level. In the MOR register, the LVIPWRD and LVIRSTD bits must
be at logic 0 to enable the LVI module and to enable LVI resets.
10.5 LVI Status Register
The LVI status register flags VDD voltages below the VLVII level.
Address:
$FE0F
Bit 7
Read: LVIOUT
6
5
4
0
0
0
0
0
0
Write:
Reset:
0
3
2
LVISTOP
LVILCK
0
0
1
Bit 0
0
0
0
0
= Reserved
Figure 10-2. LVI Status Register (LVISR)
LVILCK — LVI Lock Bit
This read/write bit inhibits writing to the LVI status and control register.
When LVILCK is set, writing to the LVI status and control register has
no effect. The LVILCK bit can be cleared only by reset.
1 = LVISCR write-protected
0 = LVISCR not write-protected
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
143
R E Q U I R E D
10.4.2 Forced Reset Operation
A G R E E M E N T
In applications that can operate at VDD levels below the VLVII level,
software can monitor VDD by polling the LVIOUT bit. In the MOR register,
the LVIPWRD bit must be at logic 0 to enable the LVI module, and the
LVIRSTD bit must be at logic 1 to disable LVI resets.
N O N - D I S C L O S U R E
10.4.1 Polled LVI Operation
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
LVISTOP — LVI Disable in Stop Mode Bit
This read/write bit turns off the low-voltage inhibit module (LVI) in stop
mode when clear.
1 = LVI not disabled during stop mode
0 = LVI disabled during stop mode
NOTE:
To meet the stop mode IDD specification, LVISTOP must be at logic 0.
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the
VLVII voltage. (See Table 10-2.) Reset clears the LVIOUT bit.
Table 10-2. LVIOUT Bit Indication
VDD
LVIOUT
VDD > VLVIR
0
VDD < VLVII
1
VLVII < VDD < VLVIR
Previous Value
10.6 LVI Interrupts
The LVI module does not generate interrupt requests.
10.7 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power standby
modes.
10.7.1 Wait Mode
With the LVIPWRD bit in the MOR register programmed to logic 0, the
LVI module is active after a WAIT instruction.
With the LVIRSTD bit in the MOR register programmed to logic 0, the LVI
module can generate a reset and bring the MCU out of wait mode.
Advance Information
144
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
When the LVIPWRD bit in the MOR register is programmed to logic 0
and the LVISTOP bit in the LVISR register is at logic 1, the LVI module
remains active after a STOP instruction.
If the LVIPWRD bit is at logic 0, the LVISTOP bit must be at logic 0 to
meet the minimum stop mode IDD specification.
N O N - D I S C L O S U R E
A G R E E M E N T
NOTE:
R E Q U I R E D
10.7.2 Stop Mode
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
145
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Advance Information
146
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.4.1
Flag Protection During Break Interrupts . . . . . . . . . . . . . . 150
11.4.2
CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . 150
11.4.3
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .150
11.4.4
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . 150
11.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.5.1
Break Status and Control Register . . . . . . . . . . . . . . . . . . 151
11.5.2
Break Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.6.1
Wait or Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.2 Introduction
This section describes the break module (break). The break module can
generate a break interrupt that stops normal program flow at a defined
address to enter a background program.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
147
R E Q U I R E D
11.1 Contents
A G R E E M E N T
Section 11. Break Module (Break)
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
R E Q U I R E D
Features of the break module include:
•
Accessible I/O Registers during the Break Interrupt
•
CPU-Generated Break Interrupts
•
Software-Generated Break Interrupts
•
COP Disabling during Break Interrupts
11.4 Functional Description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal (BKPT)
to the SIM. The SIM then causes the CPU to load the instruction register
with a software interrupt instruction (SWI) after completion of the current
CPU instruction. The program counter vectors to $FFFC and $FFFD
($FEFC and $FEFD in monitor mode).
These events can cause a break interrupt to occur:
N O N - D I S C L O S U R E
A G R E E M E N T
11.3 Features
•
A CPU-generated address (the address in the program counter)
matches the contents of the break address registers
•
Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 11-1 shows the structure of the break module.
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
8-BIT COMPARATOR
IAB[15:0]
BKPT
TO SIM
CONTROL
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB[7:0]
Figure 11-1. Break Module Block Diagram
Table 11-1. Break I/O Register Summary
Addr.
Register Name
Read:
$FE0C
Break Address Register High
(BRKH)
Write:
Reset:
Read:
$FE0D
Break Address Register Low
(BRKL)
Write:
Reset:
Read:
$FE0E
Break Status and Control Register
(BRKSCR)
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
149
A G R E E M E N T
BREAK ADDRESS REGISTER HIGH
N O N - D I S C L O S U R E
IAB[15:8]
R E Q U I R E D
11.4.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether module status
bits can be cleared during the break state. The BCFE bit in the SIM break
flag control register (SBFCR) enables software to clear status bits during
the break state. (See 9.8.3 SIM Break Flag Control Register and the
Break Interrupts subsection for each module.)
A G R E E M E N T
11.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
•
Loading the instruction register with the SWI instruction
•
Loading the program counter with $FFFC–$FFFD
($FEFC–$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
N O N - D I S C L O S U R E
11.4.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
11.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when VDD + VHI is present
on the RST pin. For VHI, see 21.5 5.0 Volt DC Electrical
Characteristics.
11.5 Break Module Registers
Three registers control and monitor operation of the break module:
Advance Information
150
•
Break status and control register (BRKSCR)
•
Break address register high (BRKH)
•
Break address register low (BRKL)
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Address:
Read:
Write:
Reset:
$FE0E
Bit 7
6
BRKE
BRKA
0
0
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-2. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
R E Q U I R E D
The break status and control register contains break module enable and
status bits.
A G R E E M E N T
11.5.1 Break Status and Control Register
This read/write status and control bit is set when a break address
match occurs. Writing a logic 1 to BRKA generates a break interrupt.
Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = Break address match
0 = No break address match
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
151
N O N - D I S C L O S U R E
BRKA — Break Active Bit
R E Q U I R E D
11.5.2 Break Address Registers
The break address registers contain the high and low bytes of the
desired breakpoint address. Reset clears the break address registers.
Address:
Read:
N O N - D I S C L O S U R E
A G R E E M E N T
Write:
Reset:
$FE0C
Bit 7
6
5
4
3
2
1
Bit 0
BIT 15
BIT 13
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
0
0
0
0
0
0
0
0
Figure 11-3. Break Address Register (BRKH)
Address:
Read:
Write:
Reset:
$FE0D
Bit 7
6
5
4
3
2
1
Bit 0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
0
0
Figure 11-4. Break Address Register (BRKL)
11.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby
modes.
11.6.1 Wait or Stop Mode
A break interrupt causes exit from wait or stop mode and sets the SBSW
bit in the SIM break status register. (See 9.8 SIM Registers.)
Advance Information
152
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
12.1 Contents
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
12.4.1
Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.4.2
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.4.3
Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.4.4
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.4.5
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.4.6
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
R E Q U I R E D
Section 12. Monitor ROM (MON)
A G R E E M E N T
Advance Information — MC68HC08AS20
This section describes the monitor ROM (MON). The monitor ROM
allows complete testing of the MCU through a single-wire interface with
a host computer.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
153
N O N - D I S C L O S U R E
12.2 Introduction
R E Q U I R E D
Features of the monitor ROM include:
•
Normal User-Mode Pin Functionality
•
One Pin Dedicated to Serial Communication between Monitor
ROM and Host Computer
•
Standard Mark/Space Non-Return-to-Zero (NRZ) Communication
with Host Computer
•
4800 Baud–28.8 kBaud Communication with Host Computer
•
Execution of Code in RAM or ROM
12.4 Functional Description
Monitor ROM receives and executes commands from a host computer.
Figure 12-1 shows a sample circuit used to enter monitor mode and
communicate with a host computer via a standard RS-232 interface.
While simple monitor commands can access any memory address, the
MC68HC08AS20 has a ROM security feature that requires proper
procedures to be followed before the ROM can be accessed. Access to
the ROM is denied to unauthorized users of customer specified
software.
N O N - D I S C L O S U R E
A G R E E M E N T
12.3 Features
In monitor mode, the MCU can execute host-computer code in RAM
while all MCU pins except PTA0 retain normal operating mode functions.
All communication between the host computer and the MCU is through
the PTA0 pin. A level-shifting and multiplexing interface is required
between PTA0 and the host computer. PTA0 is used in a wired-OR
configuration and requires a pullup resistor.
Advance Information
154
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
10 kΩ
68HC08
RST
0.1 µF
VDD + VHI
10 Ω
IRQ1/VPP
VDDA
VDDA/VDDAREF
CGMXFC
1
10 µF
+
0.1 µF
20
+
3
18
4
17
2
19
DB-25
2
5
16
3
6
15
OSC1
20 pF
+
+
10 µF
10 µF
X1
4.9152 MHz
10 MΩ
OSC2
VDD
20 pF
VSS
VDD
N O N - D I S C L O S U R E
10 µF
MC145407
A G R E E M E N T
VDD
VDD
0.1 µF
7
VDD
1
2
3
6
5
4
7
NOTE: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4
Position B — Bus clock = CGMXCLK ÷ 2
MC74HC125
VDD
14
10 kΩ
PTA0
VDD
VDD
10 kΩ
A
(SEE
NOTE.)
PTC3
10 kΩ
B
PTC0
PTC1
Figure 12-1. Monitor Mode Circuit
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
155
Table 12-1 shows the pin conditions for entering monitor mode.
PTC1 Pin
PTA0 Pin
PTC3 Pin
VDD +
VHI(1)
1
0
1
1
Monitor
CGMXCLK
CGMVCLK
----------------------------- or ----------------------------2
2
CGMOUT
-------------------------2
VDD +
VHI(1)
1
0
1
0
Monitor
CGMXCLK
CGMOUT
-------------------------2
IRQ Pin
PTC0 Pin
Table 12-1. Mode Selection
A G R E E M E N T
R E Q U I R E D
12.4.1 Entering Monitor Mode
Mode
CGMOUT
Bus
Frequency
1. For VHI see 21.5 5.0 Volt DC Electrical Characteristics and 21.2 Maximum Ratings
Enter monitor mode by either
•
Executing a software interrupt instruction (SWI) or
•
Applying a logic 0 and then a logic 1 to the RST pin.
N O N - D I S C L O S U R E
The MCU sends a break signal (10 consecutive logic 0s) to the host
computer, indicating that it is ready to receive a command. The break
signal also provides a timing reference to allow the host to determine the
necessary baud rate.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt.
The alternate vectors are in the $FE page instead of the $FF page and
allow code execution from the internal monitor firmware instead of user
code. The COP module is disabled in monitor mode as long as
VDD + VHI (see 21.5 5.0 Volt DC Electrical Characteristics) is applied
to either the IRQ pin or the VDD pin. (See Section 9. System
Integration Module (SIM) for more information on modes of operation.)
NOTE:
Advance Information
156
Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The CGMOUT frequency is
equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Functions
Modes
COP
Reset
Vector
High
Reset
Vector
Low
Break
Vector
High
Break
Vector
Low
SWI
Vector
High
SWI
Vector
Low
User
Enabled
$FFFE
$FFFF
$FFFC
$FFFD
$FFFC
$FFFD
Monitor
Disabled(1)
$FEFE
$FEFF
$FEFC
$FEFD
$FEFC
$FEFD
1. If the high voltage (VDD + VHI) is removed from the IRQ/VPP pin while in monitor mode, the
SIM asserts its COP enable output. The COP is a mask option enabled or disabled by the
COPD bit in the configuration register. (See 21.5 5.0 Volt DC Electrical Characteristics.)
12.4.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. (See Figure 12-2 and Figure 12-3.)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
N O N - D I S C L O S U R E
The data transmit and receive rate can be anywhere from 4800 baud to
28.8 kBaud. Transmit and receive baud rates must be identical.
NEXT
START
BIT
Figure 12-2. Monitor Data Format
$A5
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BREAK
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
STOP
BIT
NEXT
START
BIT
NEXT
START
BIT
Figure 12-3. Sample Monitor Waveforms
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
Table 12-2. Mode Differences
A G R E E M E N T
Table 12-2 is a summary of the differences between user mode and
monitor mode.
Advance Information
157
R E Q U I R E D
12.4.3 Echoing
As shown in Figure 12-4, the monitor ROM immediately echoes each
received byte back to the PTA0 pin for error checking.
Any result of a command appears after the echo of the last byte of the
command.
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
ECHO
RESULT
Figure 12-4. Read Transaction
12.4.4 Break Signal
A start bit followed by nine low bits is a break signal. (See Figure 12-5.)
When the monitor receives a break signal, it drives the PTA0 pin high for
the duration of two bits before echoing the break signal.
N O N - D I S C L O S U R E
A G R E E M E N T
SENT TO
MONITOR
MISSING STOP BIT
TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 12-5. Break Transaction
Advance Information
158
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
12.4.5 Commands
•
READ, read memory
•
WRITE, write memory
•
IREAD, indexed read
•
IWRITE, indexed write
•
READSP, read stack pointer
•
RUN, run user program
A G R E E M E N T
The monitor ROM uses these commands:
A sequence of IREAD or IWRITE commands can access a block of
memory sequentially over the full 64-Kbyte memory map.
Description
Read byte from memory
Operand
Specifies 2-byte address in high byte:low byte order
Data Returned
Returns contents of specified address
Opcode
$4A
N O N - D I S C L O S U R E
Table 12-3. READ (Read Memory) Command
Command Sequence
SENT TO
MONITOR
READ
ECHO
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
RESULT
Advance Information
159
R E Q U I R E D
Table 12-4. WRITE (Write Memory) Command
Description
Write byte to memory
Operand
Specifies 2-byte address in high byte:low byte order; low byte followed by data byte
Data Returned
None
Opcode
$49
Command Sequence
A G R E E M E N T
SENT TO
MONITOR
WRITE
WRITE
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
DATA
ECHO
N O N - D I S C L O S U R E
Table 12-5. IREAD (Indexed Read) Command
Description
Read next 2 bytes in memory from last address accessed
Operand
Specifies 2-byte address in high byte:low byte order
Data Returned
Returns contents of next two addresses
Opcode
$1A
Command Sequence
SENT TO
MONITOR
IREAD
ECHO
Advance Information
160
IREAD
DATA
DATA
RESULT
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
Table 12-6. IWRITE (Indexed Write) Command
Description
Write to last address accessed + 1
Operand
Specifies single data byte
Data Returned
None
Opcode
$19
Command Sequence
IWRITE
IWRITE
DATA
A G R E E M E N T
SENT TO
MONITOR
DATA
ECHO
Description
Reads stack pointer
Operand
None
Data Returned
Returns stack pointer in high byte:low byte order
Opcode
$0C
N O N - D I S C L O S U R E
Table 12-7. READSP (Read Stack Pointer) Command
Command Sequence
SENT TO
MONITOR
READSP
ECHO
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
READSP
SP HIGH
SP LOW
RESULT
Advance Information
161
R E Q U I R E D
Table 12-8. RUN (Run User Program) Command
Description
Executes RTI instruction
Operand
None
Data Returned
None
Opcode
$28
Command Sequence
RUN
RUN
ECHO
12.4.6 Baud Rate
With a 4.9152-MHz crystal and the PTC3 pin at logic 1 during reset, data
is transferred between the monitor and host at 4800 baud. If the PTC3
pin is at logic 0 during reset, the monitor baud rate is 9600. When the
CGM output, CGMOUT, is driven by the PLL, the baud rate is
determined by the MUL[7:4] bits in the PLL programming register (PPG).
(See Section 8. Clock Generator Module (CGM).)
N O N - D I S C L O S U R E
A G R E E M E N T
SENT TO
MONITOR
Table 12-9. Monitor Baud Rate Selection
VCO Frequency Multiplier (N)
1
2
3
4
5
6
Monitor Baud Rate (4.9152 MHz)
4800
9600
14,400
19,200
24,000
28,800
Monitor Baud Rate (4.194 MHz)
4096
8192
12,288
16,384
20,480
24,576
Advance Information
162
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
13.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
13.4.1
CGMXCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
13.4.2
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
13.4.3
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
13.4.4
Internal Reset Resources . . . . . . . . . . . . . . . . . . . . . . . . . 166
13.4.5
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
13.4.6
COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
13.4.7
COPL (COP Long Timeout) . . . . . . . . . . . . . . . . . . . . . . .167
13.5
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
13.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
13.7
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
13.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
13.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
13.9
COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 168
13.2 Introduction
This section describes the computer operating properly (COP) module,
a free-running counter that generates a reset if allowed to overflow. The
COP module helps software recover from runaway code. Prevent a COP
reset by periodically clearing the COP counter.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
163
R E Q U I R E D
13.1 Contents
A G R E E M E N T
Section 13. Computer Operating Properly (COP)
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
Figure 13-1 shows the structure of the COP module.
SIM
CGMXCLK
N O N - D I S C L O S U R E
SIM RESET CIRCUIT
12-BIT SIM COUNTER
SIM RESET STATUS REGISTER
CLEAR BITS 12–4
CLEAR ALL BITS
A G R E E M E N T
R E Q U I R E D
13.3 Functional Description
STOP INSTRUCTION
INTERNAL RESET SOURCES(1)
RESET VECTOR FETCH
COPCTL WRITE
COP MODULE
COPEN (FROM SIM)
COPD (FROM MOR)
6-BIT COP COUNTER
RESET
CLEAR
COP COUNTER
COPCTL WRITE
COPL
NOTE:
1. See 9.4.2 Active Resets from Internal Sources.
Figure 13-1. COP Block Diagram
Table 13-1. COP I/O Register Summary
Addr.
Register Name
$FFFF
COP Control Register (COPCTL)
Advance Information
164
Bit 7
6
5
4
3
2
Read:
Low Byte of Reset Vector
Write:
Writing to $FFFF Clears COP Counter
Reset:
Unaffected by Reset
1
Bit 0
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
COP timeout period = 8,176 or 262,128 / fosc
With a 4.9152-MHz crystal and the COPL bit in the MOR register
($001F) set to a logic 1, the COP timeout period is approximately
53.3 ms. Writing any value to location $FFFF before overflow occurs
clears the COP counter, clears bits 12 through 4 of the SIM counter, and
prevents reset. A CPU interrupt routine can be used to clear the COP.
NOTE:
The COP should be serviced as soon as possible out of reset and before
entering or after exiting stop mode to guarantee the maximum selected
amount of time before the first timeout.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR) (see 9.8.2 SIM Reset
Status Register).
While the microcontroller is in monitor mode, the COP module is
disabled if the RST pin or the IRQ pin is held at VDD + VHI (see 21.5 5.0
Volt DC Electrical Characteristics). During a break state, VDD + VHI on
the RST pin disables the COP module.
NOTE:
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
165
R E Q U I R E D
A G R E E M E N T
If not cleared by software, the COP counter overflows and generates an
asynchronous reset after 8,176 or 262,128 CGMXCLK cycles,
depending upon COPL bit in the MOR register ($001F) (See Section 5.
Mask Options.)
N O N - D I S C L O S U R E
The COP counter is a free-running 6-bit counter preceded by the 12-bit
system integration module (SIM) counter. COP timeouts are determined
strictly by the CGM crystal oscillator clock signal (CGMXCLK), not the
CGMOUT signal (see Figure 8-1. CGM Block Diagram).
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
13.4 I/O Signals
The following paragraphs describe the signals shown in Figure 13-1.
13.4.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
13.4.2 STOP Instruction
The STOP instruction clears the SIM counter.
13.4.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 13.5 COP
Control Register) clears the COP counter and clears bits 12 through 4
of the SIM counter. Reading the COP control register returns the reset
vector.
13.4.4 Internal Reset Resources
An internal reset clears the SIM counter and the COP counter. (See
9.4.2 Active Resets from Internal Sources.)
13.4.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the SIM counter.
13.4.6 COPD (COP Disable)
The COPD bit reflects the state of the COP disable bit (COPD) in the
MOR register ($001F). This signal disables COP generated resets when
asserted. (See Section 5. Mask Options.)
Advance Information
166
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address:
$FFFF
Bit 7
6
5
4
3
Read:
Low Byte of Reset Vector
Write:
Clear COP Counter
Reset:
Unaffected by Reset
2
1
Bit 0
Figure 13-2. COP Control Register (COPCTL)
13.6 Interrupts
The COP does not generate CPU interrupt requests.
13.7 Monitor Mode
The COP is disabled in monitor mode when VDD + VHI (see 21.5 5.0 Volt
DC Electrical Characteristics) is present on the IRQ pin or on the RST
pin.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
167
R E Q U I R E D
13.5 COP Control Register
A G R E E M E N T
The COPL bit selects the state of the COP long timeout bit (COPL) in the
MOR register ($001F). Timeout periods can be 8,176 or 262,128
CGMXCLK cycles. (See 5.4 Mask Option Register.)
N O N - D I S C L O S U R E
13.4.7 COPL (COP Long Timeout)
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
13.8 Low-Power Modes
The following subsections describe the low-power modes.
13.8.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP
reset during wait mode, periodically clear the COP counter in a CPU
interrupt routine.
NOTE:
If the COP is enabled in wait mode, it must be periodically refreshed.
13.8.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the SIM
counter. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
The STOP bit in the MOR register ($001F) (see Section 5. Mask
Options) enables the STOP instruction. To prevent inadvertently turning
off the COP with a STOP instruction, disable the STOP instruction by
programming the STOP bit to logic 0.
13.9 COP Module During Break Interrupts
The COP is disabled during a break interrupt when VDD + VHI (see 21.5
5.0 Volt DC Electrical Characteristics) is present on the RST pin.
Advance Information
168
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
14.1 Contents
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
14.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
14.5
IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
14.6
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 174
14.7
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 174
14.2 Introduction
R E Q U I R E D
Section 14. External Interrupt (IRQ)
A G R E E M E N T
Advance Information — MC68HC08AS20
14.3 Features
Features include:
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
•
Dedicated External Interrupt Pin (IRQ)
•
Hysteresis Buffer
•
Programmable Edge-Only or Edge and Level Interrupt Sensitivity
•
Automatic Interrupt Acknowledge
Advance Information
169
N O N - D I S C L O S U R E
This section describes the nonmaskable external interrupt (IRQ) input.
A logic 0 applied to the external interrupt pin can latch a CPU interrupt
request. Figure 14-1 shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following actions occurs:
•
Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the latch that caused the vector
fetch.
•
Software clear — Software can clear an interrupt latch by writing
to the appropriate acknowledge bit in the interrupt status and
control register (ISCR). Writing a logic 1 to the ACK bit clears the
IRQ latch.
•
Reset — A reset automatically clears both interrupt latches.
ACK
INTERNAL ADDRESS BUS
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
14.4 Functional Description
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
VDD
IRQF
D
CLR
Q
SYNCHRONIZER
CK
IRQ
IRQ
LATCH
IRQ
INTERRUPT
REQUEST
IMASK
MODE
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
Figure 14-1. IRQ Block Diagram
Advance Information
170
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
$001A
IRQ Status/Control Register (ISCR)
Read:
Bit 7
6
5
4
3
2
0
0
0
0
IRQF
0
Write:
Reset:
ACK
0
0
0
0
0
0
1
Bit 0
IMASK
MODE
0
0
= Unimplemented
The external interrupt pin is falling-edge triggered and is softwareconfigurable to be both falling-edge and low-level triggered. The MODE
bit in the ISCR controls the triggering sensitivity of the IRQ pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains
set until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt latch remains set until both of the following occur:
•
Vector fetch or software clear
•
Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the ISCR masks all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the corresponding IMASK bit is clear.
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
(See Figure 14-2.)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
171
R E Q U I R E D
Register Name
A G R E E M E N T
Addr.
N O N - D I S C L O S U R E
Table 14-1. IRQ I/O Register Summary
R E Q U I R E D
FROM RESET
YES
I BIT SET?
NO
A G R E E M E N T
INTERRUPT?
YES
NO
STACK CPU REGISTERS.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
YES
N O N - D I S C L O S U R E
NO
RTI
INSTRUCTION?
YES
UNSTACK CPU REGISTERS.
NO
EXECUTE INSTRUCTION.
Figure 14-2. IRQ Interrupt Flowchart
Advance Information
172
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
•
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK bit in the interrupt status and control register (ISCR). The
ACK bit is useful in applications that poll the IRQ pin and require
software to clear the IRQ latch. Writing to the ACK bit can also
prevent spurious interrupts due to noise. Setting ACK does not
affect subsequent transitions on the IRQ pin. A falling edge on IRQ
that occurs after writing to the ACK bit latches another interrupt
request. If the IRQ mask bit, IMASK, is clear, the CPU loads the
program counter with the vector address at locations $FFFA and
$FFFB.
•
Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic
0, the IRQ latch remains set.
The vector fetch or software clear and the return of the IRQ pin to logic 1
can occur in any order. The interrupt request remains pending as long
as the IRQ pin is at logic 0. A reset will clear the latch and the MODE
control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge sensitive only. With
MODE clear, a vector fetch or software clear immediately clears the IRQ
latch.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
173
R E Q U I R E D
If the MODE bit is set, the IRQ pin is both falling-edge sensitive and
low-level sensitive. With MODE set, both of the following actions must
occur to clear the IRQ latch:
A G R E E M E N T
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch.
A vector fetch, software clear, or reset clears the IRQ latch.
N O N - D I S C L O S U R E
14.5 IRQ Pin
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
The IRQF bit in the ISCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
14.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ interrupt
latch can be cleared during the break state. The BCFE bit in the SIM
break flag control register (SBFCR) enables software to clear the latches
during the break state. (See 9.8.3 SIM Break Flag Control Register.)
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the
IRQ status and control register during the break state has no effect on
the IRQ latch.
14.7 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. The ISCR has these functions:
Advance Information
174
•
Shows the state of the IRQ interrupt flag
•
Clears the IRQ interrupt latch
•
Masks IRQ interrupt request
•
Controls triggering sensitivity of the IRQ interrupt pin
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
6
5
4
3
2
0
0
0
0
IRQF
0
Write:
Reset:
ACK
0
0
0
0
0
0
1
Bit 0
IMASK
MODE
0
0
= Unimplemented
Figure 14-3. IRQ Status and Control Register (ISCR)
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always
reads as logic 0. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
Reset clears MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
175
R E Q U I R E D
Bit 7
A G R E E M E N T
Read:
$001A
N O N - D I S C L O S U R E
Address:
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
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176
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Section 15. Input/Output (I/O) Ports
15.1 Contents
15.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15.3.2
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . 181
15.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
15.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
15.4.2
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . 184
15.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
15.5.1
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
15.5.2
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . 187
15.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.6.1
Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.6.2
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . 190
15.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
15.7.1
Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
15.7.2
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
15.8.1
Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
15.8.2
Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . . 197
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
177
A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
N O N - D I S C L O S U R E
15.2
R E Q U I R E D
Advance Information— MC68HC08AS20
R E Q U I R E D
A G R E E M E N T
15.2 Introduction
Forty bidirectional input/output (I/O) pins form six parallel ports. All I/O
pins are programmable as inputs or outputs.
NOTE:
Table 15-1. I/O Register Summary
Addr.
$0000
$0001
$0002
N O N - D I S C L O S U R E
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
$0003
$0004
$0005
Register Name
Read:
Port A Data Register
Write:
(PTA)
Reset:
Read:
Port B Data Register
Write:
(PTB)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC2
PTC1
PTC0
PTD2
PTD1
PTD0
DDRA2
DDRA1
DDRA0
Unaffected by Reset
PTB7
PTB6
PTB5
0
Read:
Port D Data Register
Write:
(PTD)
Reset:
0
0
0
PTC4
PTC3
Unaffected by Reset
R
Read:
DDRA7
Data Direction Register A
Write:
(DDRA)
Reset:
Read:
DDRB7
Data Direction Register B
Write:
(DDRB)
Reset:
0
PTD6
PTD5
PTD4
PTD3
Unaffected by Reset
DDRA6
DDRA5
DDRA4
DDRA3
Unaffected by Reset
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
R
= Reserved
= Unimplemented
178
PTB3
Unaffected by Reset
Read:
Port C Data Register
Write:
(PTC)
Reset:
Advance Information
PTB4
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
$0006
Read:
MCLKEN
Data Direction Register C
Write:
(DDRC)
Reset:
0
$0007
$0008
$0009
$000C
$000D
Read:
Data Direction Register D
Write:
(DDRD)
Reset:
Read:
Port E Data Register
Write:
(PTE)
Reset:
Read:
Port F Data Register
Write:
(PTF)
Reset:
Bit 7
4
3
2
1
Bit 0
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDR2
DDRD1
DDRD0
0
0
0
0
0
0
0
0
PTE7
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
PTF2
PTF1
PTF0
0
0
5
0
0
0
Unaffected by Reset
0
0
0
Freescale Semiconductor
PTF3
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
0
0
0
0
0
0
DDRF3
DDRF2
DDRF1
DDRF0
0
0
0
0
0
0
0
0
R
= Reserved
= Unimplemented
MC68HC08AS20 — Rev. 4.1
0
Unaffected by Reset
Read:
DDRE7
Data Direction Register E
Write:
(DDRE)
Reset:
0
Read:
Data Direction Register F
Write:
(DDRF)
Reset:
6
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179
R E Q U I R E D
Register Name
A G R E E M E N T
Addr.
N O N - D I S C L O S U R E
Table 15-1. I/O Register Summary (Continued)
Port A is an 8-bit general-purpose bidirectional I/O port.
15.3.1 Port A Data Register
The port A data register contains a data latch for each of the eight
port A pins.
A G R E E M E N T
R E Q U I R E D
15.3 Port A
Address:
Read:
Write:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Reset:
Unaffected by Reset
Figure 15-1. Port A Data Register (PTA)
PTA[7:0] — Port A Data Bits
N O N - D I S C L O S U R E
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Read:
Write:
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Reset:
Unaffected by Reset
Figure 15-2. Data Direction Register A (DDRA)
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 15-3 shows the port A I/O logic.
READ DDRA ($0004)
INTERNAL DATA BUS
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
DDRAx
PTAx
PTAx
READ PTA ($0000)
Figure 15-3. Port A I/O Circuit
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
181
R E Q U I R E D
Address:
A G R E E M E N T
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for
the corresponding port A pin; a logic 0 disables the output buffer.
N O N - D I S C L O S U R E
15.3.2 Data Direction Register A
R E Q U I R E D
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-2 summarizes
the operation of the port A pins.
Table 15-2. Port A Pin Functions
A G R E E M E N T
DDRA
Bit
PTA
Bit
I/O Pin
Mode
Accesses
to DDRA
Accesses to PTA
Read/Write
Read
Write
0
X
Input, Hi-Z
DDRA[7:0]
Pin
PTA[7:0](1)
1
X
Output
DDRA[7:0]
PTA[7:0]
PTA[7:0]
N O N - D I S C L O S U R E
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
The port B data register contains a data latch for each of the eight port
B pins.
Address:
Read:
Write:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
ATD2
ATD1
ATD0
Reset:
Alternate
Functions:
Unaffected by Reset
ATD7
ATD6
ATD5
ATD4
ATD3
Figure 15-4. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
ATD[7:0] — ADC Channels
PTB7/ATD7–PTB0/ATD0 are eight of the 15 analog-to-digital
converter channels. The ADC channel select bits, CH[4:0], determine
whether the PTB7/ATD7–PTB0/ATD0 pins are ADC channels or
general-purpose I/O pins. If an ADC channel is selected and a read of
this corresponding bit in the port B data register occurs, the data will
be 0 if the data direction for this bit is programmed as an input.
Otherwise, the data will reflect the value in the data latch. (See
Section 19. Analog-to-Digital Converter (ADC).) Data direction
register B (DDRB) does not affect the data direction of port B pins that
are being used by the ADC. However, the DDRB bits always
determine whether reading port B returns to the states of the latches
or logic 0.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
183
R E Q U I R E D
15.4.1 Port B Data Register
A G R E E M E N T
Port B is an 8-bit special function port that shares all of its pins with the
analog-to-digital converter (ADC).
N O N - D I S C L O S U R E
15.4 Port B
R E Q U I R E D
15.4.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for
the corresponding port B pin; a logic 0 disables the output buffer.
Address:
A G R E E M E N T
Read:
Write:
Reset:
$0005
Bit 7
6
5
4
3
2
1
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
Figure 15-5. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
N O N - D I S C L O S U R E
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 15-6 shows the port B I/O logic.
READ DDRB ($0005)
INTERNAL DATA BUS
WRITE DDRB ($0005)
RESET
WRITE PTB ($0001)
DDRBx
PTBx
PTBx
READ PTB ($0001)
Figure 15-6. Port B I/O Circuit
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MC68HC08AS20 —Rev. 4.1
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Table 15-3. Port B Pin Functions
PTB
Bit
Bit in Use
by ADC
I/O Pin
Mode
Accesses
to DDRB
Accesses to PTB
Read/Write
Read
Write
0
X
No
Input, Hi-Z
DDRB[7:0]
Pin
PTB[7:0](1)
1
X
No
Output
DDRB[7:0]
PTB[7:0]
PTB[7:0]
0
X
Yes
Input, Hi-Z
DDRB[7:0]
0
PTB[7:0](1)
1
X
Yes
Input, Hi-Z
DDRB[7:0]
PTB[7:0]
PTB[7:0]
N O N - D I S C L O S U R E
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
A G R E E M E N T
DDRB
Bit
R E Q U I R E D
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx
data latch. When bit DDRBx is a logic 0, reading address $0001 reads
the voltage level on the pin, or logic 0 if that particular bit is in use by the
ADC. The data latch can always be written, regardless of the state of its
data direction bit. Table 15-3 summarizes the operation of the port B
pins.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
185
Port C is an 5-bit general-purpose bidirectional I/O port that shares one
of its pins with the bus clock (MCLK).
15.5.1 Port C Data Register
The port C data register contains a data latch for each of the five port C
pins.
A G R E E M E N T
R E Q U I R E D
15.5 Port C
Address:
Read:
$0002
Bit 7
6
5
0
0
0
Write:
Reset:
4
3
2
1
Bit 0
PTC4
PTC3
PTC2
PTC1
PTC0
Unaffected by Reset
Alternate
Functions:
MCLK
= Unimplemented
N O N - D I S C L O S U R E
Figure 15-7. Port C Data Register (PTC)
PTC[4:0] — Port C Data Bits
These read/write bits are software-programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data.
MCLK — T12 System Bus Clock Bit
The bus clock (MCLK) is driven out of PTC2 when enabled by the
MCLKEN bit in PTCDDR7.
Advance Information
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Freescale Semiconductor
$0006
Bit 7
Read:
Write:
Reset:
MCLKEN
0
6
5
0
0
0
0
4
3
2
1
Bit 0
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
= Unimplemented
Figure 15-8. Data Direction Register C (DDRC)
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTC2. If
MCLK is enabled, PTC2 is under the control of MCLKEN. Reset
clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRC[4:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE:
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 15-9 shows the port C I/O logic.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
187
R E Q U I R E D
Address:
A G R E E M E N T
Data direction register C determines whether each port C pin is an input
or an output. Writing a logic 1 to a DDRC bit enables the output buffer for
the corresponding port C pin; a logic 0 disables the output buffer.
N O N - D I S C L O S U R E
15.5.2 Data Direction Register C
R E Q U I R E D
READ DDRC ($0006)
INTERNAL DATA BUS
WRITE DDRC ($0006)
RESET
WRITE PTC ($0002)
DDRCx
PTCx
PTCx
A G R E E M E N T
READ PTC ($0002)
Figure 15-9. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx
data latch. When bit DDRCx is a logic 0, reading address $0002 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-4 summarizes
the operation of the port C pins.
Table 15-4. Port C Pin Functions
N O N - D I S C L O S U R E
DDRC
Bit
PTC
Bit
I/O Pin
Mode
Accesses to
DDRC
Accesses to PTC
Read/Write
Read
Write
[7] = 0
PTC2
Input, Hi-Z
DDRC[7]
0
PTC2
[7] = 1
PTC2
Output,
MCLK
DDRC[7]
Data Latch
—
0
X
Input, Hi-Z
DDRC[4:0]
Pin
PTC[4:3, 1:0](1)
1
X
Output
DDRC[4:0]
PTC[4:0]
PTC[4:3, 1:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
The port D data register contains a data latch for the seven port D pins.
Address:
$0003
Bit 7
Read:
0
Write:
R
6
5
4
3
2
1
Bit 0
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
ATD10
ATD9
ATD8
Reset:
Alternate
Functions:
Unaffected by Reset
R
ATD14/
TCLK
R
= Reserved
ATD13
ATD12
ATD11
Figure 15-10. Port D Data Register (PTD)
PTD[6:0] — Port D Data Bits
PTD[6:0] are read/write, software programmable bits. Data direction
of PTD[6:0] pins are under the control of the corresponding bit in data
direction register D.
ATD[14:8] — ADC Channel Status Bits
PTD6/ATD14/TCLK–PTD0/ATD8 are seven of the 15
analog-to-digital converter channels. The ADC channel select bits,
CH[4:0], determine whether the PTD6/ATD14/TCLK–PTD0/ATD8
pins are ADC channels or general-purpose I/O pins. If an ADC
channel is selected and a read of this corresponding bit in the port B
data register occurs, the data will be 0 if the data direction for this bit
is programmed as an input. Otherwise, the data will reflect the value
in the data latch. (See Section 19. Analog-to-Digital Converter
(ADC).)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
189
R E Q U I R E D
15.6.1 Port D Data Register
A G R E E M E N T
Port D is an 8-bit special function I/O port that shares all of its pins with
the analog-to-digital converter (ADC).
N O N - D I S C L O S U R E
15.6 Port D
R E Q U I R E D
Data direction register D (DDRD) does not affect the data direction of
port D pins that are being used by the ADC. However, the DDRD bits
always determine whether reading port D returns the states of the
latches or logic 0.
TCLK — Timer Clock Input Bit
The PTD6/ATD14/TCLK pin is the external clock input for the TIM.
The prescaler select bits, PS[2:0], select PTD6/ATD14/TCLK as the
TIM clock input. (See 16.9.1 TIM Status and Control Register.)
When not selected as the TIM clock, PTD6/ATD14/TCLK is available
for general-purpose I/O or as an ADC channel.
NOTE:
Do not use ADC channel ATD14 when using the PTD6/ATD14/TCLK pin
as the clock input for the TIM.
15.6.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for
the corresponding port D pin; a logic 0 disables the output buffer.
Address:
N O N - D I S C L O S U R E
A G R E E M E N T
NOTE:
$0007
Bit 7
Read:
0
Write:
0
Reset:
0
6
5
4
3
2
1
Bit 0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
Figure 15-11. Data Direction Register D (DDRD)
DDRD[6:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[6:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE:
Advance Information
190
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
INTERNAL DATA BUS
WRITE DDRD ($0007)
RESET
DDRDx
WRITE PTD ($0003)
PTDx
PTDx
READ PTD ($0003)
Figure 15-12. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic 0, reading address $0003 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-5 summarizes
the operation of the port D pins.
R E Q U I R E D
READ DDRD ($0007)
A G R E E M E N T
Figure 15-12 shows the port D I/O logic.
DDRD
Bit
PTD
Bit
Bit in Use
by ADC
I/O Pin
Mode
0
X
No
1
X
0
1
Accesses
to DDRD
Accesses to PTD
Read/Write
Read
Write
Input, Hi-Z
DDRD[6:0]
Pin
PTD[6:0](1)
No
Output
DDRD[6:0]
PTD[6:0]
PTD[6:0]
X
Yes
Input, Hi-Z
DDRD[6:0]
0
PTD[6:0](1)
X
Yes
Input, Hi-Z
DDRD[6:0]
PTD[6:0]
PTD[6:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
191
N O N - D I S C L O S U R E
Table 15-5. Port D Pin Functions
Port E is an 8-bit special function port that shares two of its pins with the
timer interface module (TIM), two of its pins with the serial
communications interface module (SCI), and four of its pins with the
serial peripheral interface module (SPI).
15.7.1 Port E Data Register
The port E data register contains a data latch for each of the eight port
E pins.
A G R E E M E N T
R E Q U I R E D
15.7 Port E
Address:
Read:
Write:
$0008
Bit 7
6
5
4
3
2
1
Bit 0
PTE7
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
TCH0
RxD
TxD
Reset:
Alternate
Function:
Unaffected by Reset
SPSCK
MOSI
MISO
SS
TCH1
N O N - D I S C L O S U R E
Figure 15-13. Port E Data Register (PTE)
PTE[7:0] — Port E Data Bits
PTE[7:0] are read/write, software programmable bits. Data direction
of each port E pin is under the control of the corresponding bit in data
direction register E.
SPSCK — SPI Serial Clock Bit
The PTE7/SPSCK pin is the serial clock input of an SPI slave module
and serial clock output of an SPI master module. When the SPE bit is
clear, the PTE7/SPSCK pin is available for general-purpose I/O.
MOSI — Master Out/Slave In Bit
The PTE6/MOSI pin is the master out/slave in terminal of the SPI
module. When the SPE bit is clear, the PTE6/MOSI pin is available for
general-purpose I/O. (See 18.14.1 SPI Control Register.)
Advance Information
192
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
The PTE4/SS pin is the slave select input of the SPI module. When
the SPE bit is clear or when the SPI master bit, SPMSTR, is set and
MODFEN bit is low, the PTE4/SS pin is available for general-purpose
I/O. (See 18.13.4 SS (Slave Select).) When the SPI is enabled as a
slave, the DDRE4 bit in data direction register E (DDRE) has no effect
on the PTE4/SS pin.
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SPI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 15-6.)
TCH[1:0] — Timer Channel I/O Bits
The PTE3/TCH1–PTE2/TCH0 pins are the TIM input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine
whether the PTE3/TCH1–PTE2/TCH0 pins are timer channel I/O pins
or general-purpose I/O pins. (See 16.9.4 TIM Channel Status and
Control Registers.)
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIM. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 15-6.)
RxD — SCI Receive Data Input Bit
The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O. (See 17.9.1
SCI Control Register 1.)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
193
R E Q U I R E D
SS — Slave Select Bit
A G R E E M E N T
The PTE5/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTE5/MISO pin is available for general-purpose
I/O. (See 18.14.1 SPI Control Register.)
N O N - D I S C L O S U R E
MISO — Master In/Slave Out Bit
R E Q U I R E D
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. (See
17.9.1 SCI Control Register 1.)
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SCI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 15-6.)
15.7.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input
or an output. Writing a logic 1 to a DDRE bit enables the output buffer for
the corresponding port E pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
N O N - D I S C L O S U R E
A G R E E M E N T
TxD — SCI Transmit Data Output
Reset:
$000C
Bit 7
6
5
4
3
2
1
Bit 0
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
0
0
0
Figure 15-14. Data Direction Register E (DDRE)
DDRE[7:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE[7:0], configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE:
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 15-15 shows the port E I/O logic.
Advance Information
194
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
WRITE PTE ($0008)
PTEx
PTEx
READ PTE ($0008)
Figure 15-15. Port E I/O Circuit
When bit DDREx is a logic 1, reading address $0008 reads the PTEx
data latch. When bit DDREx is a logic 0, reading address $0008 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-6 summarizes
the operation of the port E pins.
Table 15-6. Port E Pin Functions
DDRE
Bit
PTE
Bit
I/O Pin
Mode
Accesses
to DDRE
Accesses to PTE
Read/Write
Read
Write
0
X
Input, Hi-Z
DDRE[7:0]
Pin
PTE[7:0](1)
1
X
Output
DDRE[7:0]
PTE[7:0]
PTE[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
195
R E Q U I R E D
DDREx
RESET
A G R E E M E N T
INTERNAL DATA BUS
WRITE DDRE ($000C)
N O N - D I S C L O S U R E
READ DDRE ($000C)
Port F is a 4-bit special function port that shares four of its pins with the
timer interface module (TIM).
15.8.1 Port F Data Register
The port F data register contains a data latch for each of the four port F
pins.
A G R E E M E N T
R E Q U I R E D
15.8 Port F
Address:
Read:
$0009
Bit 7
6
5
4
0
0
0
0
Write:
Reset:
3
2
1
Bit 0
PTF3
PTF2
PTF1
PTF0
TCH4
TCH3
TCH2
Unaffected by Reset
Alternate
Function:
TCH5
= Unimplemented
N O N - D I S C L O S U R E
Figure 15-16. Data Direction Register F (DDRF)
PTF[3:0] — Port F Data Bits
These read/write bits are software programmable. Data direction of
each port F pin is under the control of the corresponding bit in data
direction register F. Reset has no effect on PTF[3:0].
TCH[5:2] — Timer Channel I/O Bits
The PTF3/TCH5–PTF0/TCH2 pins are the TIM input capture/output
compare pins. The edge/level select bits, ELSxB–ELSxA, determine
whether the PTF3/TCH5–PTF0/TCH2 pins are timer channel I/O pins
or general-purpose I/O pins. (See 16.9.4 TIM Channel Status and
Control Registers.)
NOTE:
Advance Information
196
Data direction register F (DDRF) does not affect the data direction of port
F pins that are being used by the TIM. However, the DDRF bits always
determine whether reading port F returns the states of the latches or the
states of the pins. (See Table 15-7.)
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Read:
$000D
Bit 7
6
5
4
0
0
0
0
0
0
0
0
Write:
Reset:
3
2
1
Bit 0
DDRF3
DDRF2
DDRF1
DDRF0
0
0
0
0
= Unimplemented
Figure 15-17. Data Direction Register F (DDRF)
DDRF[3:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears
DDRF[3:0], configuring all port F pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE:
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 15-18 shows the port F I/O logic.
READ DDRF ($000D)
INTERNAL DATA BUS
WRITE DDRF ($000D)
RESET
WRITE PTF ($0009)
DDRFx
PTFx
PTFx
READ PTF ($0009)
Figure 15-18. Port F I/O Circuit
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
197
R E Q U I R E D
Address:
A G R E E M E N T
Data direction register F determines whether each port F pin is an input
or an output. Writing a logic 1 to a DDRF bit enables the output buffer for
the corresponding port F pin; a logic 0 disables the output buffer.
N O N - D I S C L O S U R E
15.8.2 Data Direction Register F
R E Q U I R E D
When bit DDRFx is a logic 1, reading address $0009 reads the PTFx
data latch. When bit DDRFx is a logic 0, reading address $0009 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-7 summarizes
the operation of the port F pins.
Table 15-7. Port F Pin Functions
A G R E E M E N T
DDRF
Bit
PTF
Bit
I/O Pin
Mode
Accesses
to DDRF
Accesses to PTF
Read/Write
Read
Write
0
X
Input, Hi-Z
DDRF[3:0]
Pin
PTF[3:0](1)
1
X
Output
DDRF[3:0]
PTF[3:0]
PTF[3:0]
N O N - D I S C L O S U R E
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Advance Information
198
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
16.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
16.4.1
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
16.4.2
Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
16.4.3
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
16.4.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 206
16.4.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .207
16.4.4
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . 208
16.4.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 209
16.4.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 210
16.4.4.3
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
16.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
16.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
16.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
16.7
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 214
16.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
16.8.1
TIM Clock Pin (PTD6/ATD14/TCLK) . . . . . . . . . . . . . . . . . 215
16.8.2
TIM Channel I/O Pins (PTF3/TCH5–PTF0/TCH2 and
PTE3/TCH1–PTE2/TCH0) . . . . . . . . . . . . . . . . . . . . . . 215
16.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
16.9.1
TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .216
16.9.2
TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
16.9.3
TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 220
16.9.4
TIM Channel Status and Control Registers. . . . . . . . . . . . 221
16.9.5
TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
199
R E Q U I R E D
16.1 Contents
A G R E E M E N T
Section 16. Timer Interface (TIM)
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
R E Q U I R E D
16.2 Introduction
This section describes the timer interface module (TIM6). The TIM is a
6-channel timer that provides a timing reference with input capture,
output compare, and pulse-width-modulation functions. Figure 16-1 is a
block diagram of the TIM.
A G R E E M E N T
16.3 Features
Features of the TIM include:
•
Six Input Capture/Output Compare Channels
– Rising-Edge, Falling-Edge, or Any-Edge Input Capture Trigger
– Set, Clear, or Toggle Output Compare Action
•
Buffered and Unbuffered Pulse Width Modulation (PWM) Signal
Generation
•
Programmable TIM Clock Input
– 7-Frequency Internal Bus Clock Prescaler Selection
N O N - D I S C L O S U R E
– External TIM Clock Input (4-MHz Maximum Frequency)
Advance Information
200
•
Free-Running or Modulo Up-Count Operation
•
Toggle Any Channel Pin on Overflow
•
TIM Counter Stop and Reset Bits
•
Modular Architecture Expandable to Eight Channels in Hardware
But Not Expandable in Software
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
INTERNAL
BUS CLOCK
R E Q U I R E D
TCLK
PTD6/ATD14/TCLK
PRESCALER SELECT
PRESCALER
TSTOP
PS2
TRST
PS1
PS0
16-BIT COUNTER
TOF
TOIE
INTERRUPT
LOGIC
16-BIT COMPARATOR
ELS0B
ELS0A
TOV0
CH0MAX
16-BIT COMPARATOR
TCH0H–TCH0L
CH0F
16-BIT LATCH
MS0A
CHANNEL 1
ELS1B
MS0B
ELS1A
TOV1
CH1MAX
16-BIT COMPARATOR
TCH1H–TCH1L
CH1F
16-BIT LATCH
CH1IE
MS1A
CHANNEL 2
ELS2B
ELS2A
TOV2
CH2MAX
16-BIT COMPARATOR
TCH2H–TCH2L
CH2F
16-BIT LATCH
MS2A
CHANNEL 3
ELS3B
MS2B
ELS3A
TCH3H–TCH3L
CH3F
16-BIT LATCH
CH3IE
MS3A
ELS4B
ELS4A
TOV4
CH5MAX
16-BIT COMPARATOR
TCH4H–TCH4L
CH4F
16-BIT LATCH
MS4A
CHANNEL 5
CH2IE
TOV3
CH3MAX
16-BIT COMPARATOR
CHANNEL 4
CH0IE
ELS5B
MS4B
ELS5A
TOV5
CH5MAX
16-BIT COMPARATOR
TCH5H–TCH5L
CH4IE
CH5F
16-BIT LATCH
MS5A
CH5IE
PTE2
LOGIC
PTE2/TCH0
INTERRUPT
LOGIC
PTE3
LOGIC
PTE3/TCH1
INTERRUPT
LOGIC
PTF0
LOGIC
PTF0/TCH2
INTERRUPT
LOGIC
PTF1
LOGIC
N O N - D I S C L O S U R E
CHANNEL 0
A G R E E M E N T
TMODH–TMODL
PTF1/TCH3
INTERRUPT
LOGIC
PTF2
LOGIC
PTF2/TCH4
INTERRUPT
LOGIC
PTF3
LOGIC
PTF3/TCH5
INTERRUPT
LOGIC
Figure 16-1. TIM Block Diagram
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
201
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Table 16-1. TIM I/O Register Summary
Addr.
$0020
$0022
$0023
Register Name
Bit 7
$0025
$0026
$0027
$0029
$002A
$002B
TSTOP
3
0
0
2
1
Bit 0
PS2
PS1
PS0
0
0
1
0
0
0
0
0
Read:
TIM Counter Register High
Write:
(TCNTH)
Reset:
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Read:
TIM Counter Register Low
Write:
(TCNTL)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
TIM Modulo Register High
Write:
(TMODH)
Reset:
Read:
TIM Modulo Register Low
Write:
(TMODL)
Reset:
Read:
TIM Channel 0 Status and
Write:
Control Register (TSC0)
Reset:
Read:
TIM Channel 0 Register High
Write:
(TCH0H)
Reset:
0
CH0F
0
Bit 7
Read:
TIM Channel 1 Status and
Write:
Control Register (TSC1)
Reset:
CH1F
Read:
TIM Channel 1 Register High
Write:
(TCH1H)
Reset:
Read:
TIM Channel 1 Register Low
Write:
(TCH1L)
Reset:
TIM Channel 2 Status and
Write:
Control Register (TSC2)
Reset:
TRST
Indeterminate after Reset
TIM Channel 0 Register Low
Write:
(TCH0L)
Reset:
Read:
$002C
TOIE
4
TOF
Read:
$0028
5
Read:
TIM Status and Control
Write:
Register (TSC)
Reset:
Read:
$0024
6
6
5
4
3
Indeterminate after Reset
0
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH2F
0
0
CH2IE
MS2B
MS2A
ELS2B
ELS2A
TOV2
CH2MAX
0
0
0
0
0
0
0
= Unimplemented
Advance Information
202
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
$002E
$002F
Read:
TIM Channel 2 Register High
Write:
(TCH2H)
Reset:
Read:
TIM Channel 2 Register Low
Write:
(TCH2L)
Reset:
Read:
TIM Channel 3 Status and
Write:
Control Register (TSC3)
Reset:
Read:
$0030
$0031
$0032
$0033
TIM Channel 3 Register High
Write:
(TCH3H)
Reset:
Read:
TIM Channel 3 Register Low
Write:
(TCH3L)
Reset:
Read:
TIM Channel 4 Status and
Write:
Control Register (TSC4)
Reset:
Read:
TIM Channel 4 Register High
Write:
(TCH4H)
Reset:
Read:
$0034
$0035
$0036
$0037
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
CH3F
0
4
3
CH3IE
0
MS3A
ELS3B
ELS3A
TOV3
CH3MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH4F
CH4IE
MS4B
MS4A
ELS4B
ELS4A
TOV4
CH4MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
0
Indeterminate after Reset
Bit 7
Read:
TIM Channel 5 Status and
Write:
Control Register (TSC5)
Reset:
CH5F
Read:
TIM Channel 5 Register Low
Write:
(TCH5L)
Reset:
5
Indeterminate after Reset
TIM Channel 4 Register Low
Write:
(TCH4L)
Reset:
Read:
TIM Channel 5 Register High
Write:
(TCH5H)
Reset:
6
6
5
4
3
Indeterminate after Reset
0
CH5IE
0
MS5A
ELS5B
ELS5A
TOV5
CH5MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
= Unimplemented
MC68HC08AS20 — Rev. 4.1
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R E Q U I R E D
$002D
Register Name
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N O N - D I S C L O S U R E
Addr.
A G R E E M E N T
Table 16-1. TIM I/O Register Summary (Continued)
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
16.4 Functional Description
Figure 16-1 shows the TIM structure. The central component of the TIM
is the 16-bit TIM counter that can operate as a free-running counter or a
modulo up-counter. The TIM counter provides the timing reference for
the input capture and output compare functions. The TIM counter
modulo registers, TMODH–TMODL, control the modulo value of the TIM
counter. Software can read the TIM counter value at any time without
affecting the counting sequence.
The six TIM channels are programmable independently as input capture
or output compare channels.
16.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the
TIM clock pin, PTD6/ATD14/TCLK. The prescaler generates seven
clock rates from the internal bus clock. The prescaler select bits,
PS[2–0], in the TIM status and control register select the TIM clock
source.
16.4.2 Input Capture
An input capture function has three basic parts: edge select logic, an
input capture latch, and a 16-bit counter. Two 8-bit registers, which make
up the 16-bit input capture register, are used to latch the value of the
free-running counter after the corresponding input capture edge detector
senses a defined transition. The polarity of the active edge is
programmable. The level transition which triggers the counter transfer is
defined by the corresponding input edge bits (ELSxB and ELSxA in
TSC0 through TSC5 control registers with x referring to the active
channel number). When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH–TCHxL. Input captures can generate
TIM CPU interrupt requests. Software can determine that an input
capture event has occurred by enabling input capture interrupts or by
polling the status flag bit.
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By recording the times for successive edges on an incoming signal,
software can determine the period and/or pulse width of the signal. To
measure a period, two successive edges of the same polarity are
captured. To measure a pulse width, two alternate polarity edges are
captured. Software should track the overflows at the 16-bit module
counter to extend its range.
Another use for the input capture function is to establish a time
reference. In this case, an input capture function is used in conjunction
with an output compare function. For example, to activate an output
signal a specified number of clock cycles after detecting an input event
(edge), use the input capture function to record the time at which the
edge occurred. A number corresponding to the desired delay is added to
this captured value and stored to an output compare register (see 16.9.5
TIM Channel Registers). Because both input captures and output
compares are referenced to the same 16-bit modulo counter, the delay
can be controlled to the resolution of the counter independent of
software latencies.
Reset does not affect the contents of the input capture register.
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R E Q U I R E D
A G R E E M E N T
The free-running counter contents are transferred to the TIM channel
status and control register (TSC0–TSC5) (see 16.9.4 TIM Channel
Status and Control Registers) on each proper signal transition
regardless of whether the TIM channel flag (CH0F–CH5F in
TSC0–TSC5 registers) is set or clear. When the status flag is set, a CPU
interrupt is generated if enabled. The value of the count latched or
“captured” is the time of the event. Because this value is stored in the
input capture register when the actual event occurs, user software can
respond to this event at a later time and determine the actual time of the
event. However, this must be done prior to another input capture on the
same pin; otherwise, the previous time value will be lost.
N O N - D I S C L O S U R E
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization.
R E Q U I R E D
16.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse
with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIM can set, clear, or toggle the channel pin. Output compares can
generate TIM CPU interrupt requests.
A G R E E M E N T
16.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare
pulses as described in 16.4.3 Output Compare. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
N O N - D I S C L O S U R E
An unsynchronized write to the TIM channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass
the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
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•
When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
•
When changing to a larger output compare value, enable channel
x TIM overflow interrupts and write the new value in the TIM
overflow interrupt routine. The TIM overflow interrupt occurs at the
end of the current counter overflow period. Writing a larger value
in an output compare interrupt routine (at the end of the current
pulse) could cause two output compares to occur in the same
counter overflow period.
MC68HC08AS20 —Rev. 4.1
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Channels 2 and 3 can be linked to form a buffered output compare
channel whose output appears on the PTF0/TCH2 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS2B bit in TIM channel 2 status and control register (TSC2)
links channel 2 and channel 3. The output compare value in the TIM
channel 2 registers initially controls the output on the PTF0/TCH2 pin.
Writing to the TIM channel 3 registers enables the TIM channel 3
registers to synchronously control the output after the TIM overflows. At
each subsequent overflow, the TIM channel registers (2 or 3) that control
the output are the ones written to last. TSC2 controls and monitors the
buffered output compare function, and TIM channel 3 status and control
register (TSC3) is unused. While the MS2B bit is set, the channel 3 pin,
PTF1/TCH3, is available as a general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered output compare
channel whose output appears on the PTF2/TCH4 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS4B bit in TIM channel 4 status and control register (TSC4)
links channel 4 and channel 5. The output compare value in the TIM
channel 4 registers initially controls the output on the PTF2/TCH4 pin.
Writing to the TIM channel 5 registers enables the TIM channel 5
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R E Q U I R E D
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The output compare value in the TIM
channel 0 registers initially controls the output on the PTE2/TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1
registers to synchronously control the output after the TIM overflows. At
each subsequent overflow, the TIM channel registers (0 or 1) that control
the output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control
register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
PTE2/TCH0, is available as a general-purpose I/O pin.
A G R E E M E N T
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the PTE2/TCH0 pin. The TIM channel
registers of the linked pair alternately control the output.
N O N - D I S C L O S U R E
16.4.3.2 Buffered Output Compare
R E Q U I R E D
NOTE:
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output
compares.
16.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel,
the TIM can generate a PWM signal. The value in the TIM counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIM counter
modulo registers. The time between overflows is the period of the PWM
signal.
As Figure 16-2 shows, the output compare value in the TIM channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIM to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIM to set the pin if the state of the PWM
pulse is logic 0.
N O N - D I S C L O S U R E
A G R E E M E N T
registers to synchronously control the output after the TIM overflows. At
each subsequent overflow, the TIM channel registers (4 or 5) that control
the output are the ones written to last. TSC4 controls and monitors the
buffered output compare function, and TIM channel 5 status and control
register (TSC5) is unused. While the MS4B bit is set, the channel 5 pin,
PTF3/TCH5, is available as a general-purpose I/O pin.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 16-2. PWM Period and Pulse Width
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16.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as
described in 16.4.4 Pulse Width Modulation (PWM). The pulses are
unbuffered because changing the pulse width requires writing the new
pulse width value over the value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse
width value could cause incorrect operation for up to two PWM periods.
For example, writing a new value before the counter reaches the old
value but after the counter reaches the new value prevents any compare
during that PWM period. Also, using a TIM overflow interrupt routine to
write a new, smaller pulse width value may cause the compare to be
missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
MC68HC08AS20 — Rev. 4.1
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•
When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
•
When changing to a longer pulse width, enable channel x TIM
overflow interrupts and write the new value in the TIM overflow
interrupt routine. The TIM overflow interrupt occurs at the end of
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R E Q U I R E D
A G R E E M E N T
The value in the TIM channel registers determines the pulse width of the
PWM output. The pulse width of an 8-bit PWM signal is variable in 256
increments. Writing $0080 (128) to the TIM channel registers produces
a duty cycle of 128/256 or 50%.
N O N - D I S C L O S U R E
The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000 (see 16.9.1 TIM Status and Control Register).
R E Q U I R E D
NOTE:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
16.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the PTE2/TCH0 pin. The TIM channel registers of the
linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The TIM channel 0 registers initially
control the pulse width on the PTE2/TCH0 pin. Writing to the TIM
channel 1 registers enables the TIM channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIM channel registers (0 or 1)
that control the pulse width are the ones written to last. TSC0 controls
and monitors the buffered PWM function, and TIM channel 1 status and
control register (TSC1) is unused. While the MS0B bit is set, the channel
1 pin, PTE3/TCH1, is available as a general-purpose I/O pin.
N O N - D I S C L O S U R E
A G R E E M E N T
the current PWM period. Writing a larger value in an output
compare interrupt routine (at the end of the current pulse) could
cause two output compares to occur in the same PWM period.
Channels 2 and 3 can be linked to form a buffered PWM channel whose
output appears on the PTF0/TCH2 pin. The TIM channel registers of the
linked pair alternately control the pulse width of the output.
Setting the MS2B bit in TIM channel 2 status and control register (TSC2)
links channel 2 and channel 3. The TIM channel 2 registers initially
control the pulse width on the PTF0/TCH2 pin. Writing to the TIM
channel 3 registers enables the TIM channel 3 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIM channel registers (2 or 3)
that control the pulse width are the ones written to last. TSC2 controls
and monitors the buffered PWM function, and TIM channel 3 status and
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Setting the MS4B bit in TIM channel 4 status and control register (TSC4)
links channel 4 and channel 5. The TIM channel 4 registers initially
control the pulse width on the PTF2/TCH4 pin. Writing to the TIM
channel 5 registers enables the TIM channel 5 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIM channel registers (4 or 5)
that control the pulse width are the ones written to last. TSC4 controls
and monitors the buffered PWM function, and TIM channel 5 status and
control register (TSC5) is unused. While the MS4B bit is set, the channel
5 pin, PTF3/TCH5, is available as a general-purpose I/O pin.
NOTE:
In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
R E Q U I R E D
Channels 4 and 5 can be linked to form a buffered PWM channel whose
output appears on the PTF2/TCH4 pin. The TIM channel registers of the
linked pair alternately control the pulse width of the output.
A G R E E M E N T
control register (TSC3) is unused. While the MS2B bit is set, the channel
3 pin, PTF1/TCH3, is available as a general-purpose I/O pin.
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter by setting the TIM reset bit, TRST.
2. In the TIM counter modulo registers (TMODH–TMODL), write the
value for the required PWM period.
3. In the TIM channel x registers (TCHxH–TCHxL), write the value for
the required pulse width.
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N O N - D I S C L O S U R E
16.4.4.3 PWM Initialization
R E Q U I R E D
4. In TIM channel x status and control register (TSCx):
a. Write 0–1 (for unbuffered output compare or PWM signals) or
1–0 (for buffered output compare or PWM signals) to the
mode select bits, MSxB–MSxA. (See Table 16-3.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
A G R E E M E N T
c.
NOTE:
Write 1–0 (to clear output on compare) or 1–1 (to set output
on compare) to the edge/level select bits, ELSxB–ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See Table 16-3.)
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit,
TSTOP.
N O N - D I S C L O S U R E
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H–TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels. MS0B
takes priority over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered
PWM operation. The TIM channel 2 registers (TCH2H–TCH2L) initially
control the PWM output. TIM status control register 2 (TSCR2) controls
and monitors the PWM signal from the linked channels. MS2B takes
priority over MS2A.
Setting MS4B links channels 4 and 5 and configures them for buffered
PWM operation. The TIM channel 4 registers (TCH4H–TCH4L) initially
control the PWM output. TIM status control register 4 (TSCR4) controls
and monitors the PWM signal from the linked channels. MS4B takes
priority over MS4A.
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Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. (See 16.9.4 TIM
Channel Status and Control Registers.)
R E Q U I R E D
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
•
TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter value rolls over to $0000 after matching the value in the
TIM counter modulo registers. The TIM overflow interrupt enable
bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and
TOIE are in the TIM status and control register.
•
TIM channel flags (CH5F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
16.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby
modes.
16.6.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait
mode, the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
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N O N - D I S C L O S U R E
The following TIM sources can generate interrupt requests:
A G R E E M E N T
16.5 Interrupts
R E Q U I R E D
16.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIM
counter. TIM operation resumes when the MCU exits stop mode.
16.7 TIM During Break Interrupts
A G R E E M E N T
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 9.8.3 SIM Break Flag Control
Register.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
N O N - D I S C L O S U R E
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
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Port D shares one of its pins with the TIM. Port E shares two of its pins
with the TIM and port F shares four of its pins with the TIM.
PTD6/ATD14/TCLK is an external clock input to the TIM prescaler. The
six TIM channel I/O pins are PTE2/TCH0, PTE3/TCH1, PTF0/TCH2,
PTF1/TCH3, PTF2/TCH4, and PTF3/TCH5.
R E Q U I R E D
16.8 I/O Signals
1
------------------------------------- + t SU
bus frequency
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD6/ATD14/TCLK is available as a general-purpose I/O pin or ADC
channel when not used as the TIM clock input. When the
PTD6/ATD14/TCLK pin is the TIM clock input, it is an input regardless of
the state of the DDRD6 bit in data direction register D.
16.8.2 TIM Channel I/O Pins (PTF3/TCH5–PTF0/TCH2 and PTE3/TCH1–PTE2/TCH0)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE2/TCH0, PTE6/TCH2, and
PTF2/TCH4 can be configured as buffered output compare or buffered
PWM pins.
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N O N - D I S C L O S U R E
PTD6/ATD14/TCLK is an external clock input that can be the clock
source for the TIM counter instead of the prescaled internal bus clock.
Select the PTD6/ATD14/TCLK input by writing logic 1s to the three
prescaler select bits, PS[2–0]. (See 16.9.1 TIM Status and Control
Register.) The minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is:
A G R E E M E N T
16.8.1 TIM Clock Pin (PTD6/ATD14/TCLK)
R E Q U I R E D
These I/O registers control and monitor TIM operation:
•
TIM status and control register (TSC)
•
TIM control registers (TCNTH–TCNTL)
•
TIM counter modulo registers (TMODH–TMODL)
•
TIM channel status and control registers (TSC0, TSC1, TSC2,
TSC3, TSC4, and TSC5)
•
TIM channel registers (TCH0H–TCH0L, TCH1H–TCH1L,
TCH2H–TCH2L, TCH3H–TCH3L, TCH4H–TCH4L and
TCH5H–TCH5L)
16.9.1 TIM Status and Control Register
The TIM status and control register:
N O N - D I S C L O S U R E
A G R E E M E N T
16.9 I/O Registers
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•
Enables TIM overflow interrupts
•
Flags TIM overflows
•
Stops the TIM counter
•
Resets the TIM counter
•
Prescales the TIM counter clock
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Read:
TOF
Write:
0
Reset:
0
6
5
TOIE
TSTOP
0
1
4
3
0
0
TRST
0
0
2
1
Bit 0
PS2
PS1
PS0
0
0
0
= Unimplemented
Figure 16-3. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter resets to $0000 after
reaching the modulo value programmed in the TIM counter modulo
registers. Clear TOF by reading the TIM status and control register
when TOF is set and then writing a logic 0 to TOF. If another TIM
overflow occurs before the clearing sequence is complete, then
writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset
clears the TOF bit. Writing a logic 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
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R E Q U I R E D
Bit 7
A G R E E M E N T
$0020
N O N - D I S C L O S U R E
Address:
R E Q U I R E D
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIM counter is reset and always reads as logic 0. Reset clears the
TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
A G R E E M E N T
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.
PS[2–0] — Prescaler Select Bits
These read/write bits select either the PTD6/ATD14/TCLK pin or one
of the seven prescaler outputs as the input to the TIM counter as
Table 16-2 shows. Reset clears the PS[2–0] bits.
N O N - D I S C L O S U R E
Table 16-2. Prescaler Selection
Advance Information
218
PS[2–0]
TIM Clock Source
000
Internal Bus Clock ÷1
001
Internal Bus Clock ÷ 2
010
Internal Bus Clock ÷ 4
011
Internal Bus Clock ÷ 8
100
Internal Bus Clock ÷ 16
101
Internal Bus Clock ÷ 32
110
Internal Bus Clock ÷ 64
111
PTD6/ATD14/TCLK
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
NOTE:
If TCNTH is read during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Register Name and Address TCNTH — $0022
Read:
Bit 7
6
5
4
3
2
1
Bit 0
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
0
0
0
0
0
0
0
0
Write:
Reset:
Register Name and Address TCNTL — $0023
Read:
Bit 7
6
5
4
3
2
1
Bit 0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 16-4. TIM Counter Registers (TCNTH and TCNTL)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
219
R E Q U I R E D
A G R E E M E N T
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
N O N - D I S C L O S U R E
16.9.2 TIM Counter Registers
R E Q U I R E D
16.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the
TIM counter. When the TIM counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next clock. Writing to the high byte (TMODH) inhibits
the TOF bit and overflow interrupts until the low byte (TMODL) is written.
Reset sets the TIM counter modulo registers.
A G R E E M E N T
Register Name and Address TMODH — $0024
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
1
1
1
1
1
1
1
1
Register Name and Address TMODL — $0025
Read:
Write:
N O N - D I S C L O S U R E
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1
1
1
1
1
1
1
1
Figure 16-5. TIM Counter Modulo Registers (TMODH and TMODL)
NOTE:
Advance Information
220
Reset the TIM counter before writing to the TIM counter modulo registers.
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
•
Flags input captures and output compares
•
Enables input capture and output compare interrupts
•
Selects input capture, output compare, or PWM operation
•
Selects high, low, or toggling output on output compare
•
Selects rising edge, falling edge, or any edge as the active input
capture trigger
•
Selects output toggling on TIM overflow
•
Selects 100% PWM duty cycle
•
Selects buffered or unbuffered output compare/PWM operation
Register Name and Address TSC0 — $0026
Bit 7
Read:
CH0F
Write:
0
Reset:
0
6
5
4
3
2
1
Bit 0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
4
3
2
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
Register Name and Address TSC1 — $0029
Bit 7
Read:
CH1F
Write:
0
Reset:
0
6
CH1IE
0
5
0
0
= Unimplemented
Figure 16-6. TIM Channel Status
and Control Registers (TSC0–TSC5)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
221
A G R E E M E N T
Each of the TIM channel status and control registers:
N O N - D I S C L O S U R E
16.9.4 TIM Channel Status and Control Registers
R E Q U I R E D
Register Name and Address TSC2 — $002C
Bit 7
Read:
CH2F
Write:
0
Reset:
0
6
5
4
3
2
1
Bit 0
CH2IE
MS2B
MS2A
ELS2B
ELS2A
TOV2
CH2MAX
0
0
0
0
0
0
0
4
3
2
1
Bit 0
MS3A
ELS3B
ELS3A
TOV3
CH3MAX
0
0
0
0
0
Register Name and Address TSC3 — $002F
A G R E E M E N T
Bit 7
Read:
CH3F
Write:
0
Reset:
0
6
CH3IE
0
5
0
0
Register Name and Address TSC4 — $0032
N O N - D I S C L O S U R E
Bit 7
Read:
CH4F
Write:
0
Reset:
0
6
5
4
3
2
1
Bit 0
CH4IE
MS4B
MS4A
ELS4B
ELS4A
TOV4
CH4MAX
0
0
0
0
0
0
0
4
3
2
1
Bit 0
MS5A
ELS5B
ELS5A
TOV5
CH5MAX
0
0
0
0
0
Register Name and Address TSC5 — $0035
Bit 7
Read:
CH5F
Write:
0
Reset:
0
6
CH5IE
0
5
0
0
= Unimplemented
Figure 16-6. TIM Channel Status
and Control Registers (TSC0–TSC5) (Continued)
Advance Information
222
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
When CHxIE = 0, clear CHxF by reading TIM channel x status and
control register with CHxF set, and then writing a logic 0 to CHxF. If
another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
R E Q U I R E D
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
A G R E E M E N T
CHxF — Channel x Flag Bit
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM channel 0, TIM channel 2, and TIM
channel 4 status and control registers.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and
reverts TCH3 to general-purpose I/O.
Setting MS4B disables the channel 5 status and control register and
reverts TCH5 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
223
N O N - D I S C L O S U R E
MSxB — Mode Select Bit B
R E Q U I R E D
MSxA — Mode Select Bit A
When ELSxB–ELSxA ≠ 00, this read/write bit selects either input
capture operation or unbuffered output compare/PWM operation.
(See Table 16-3.)
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
A G R E E M E N T
When ELSxB–ELSxA = 00, this read/write bit selects the initial output
level of the TCHx pin. (See Table 16-3.) Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
N O N - D I S C L O S U R E
When ELSxB and ELSxA are both clear, channel x is not connected
to port E or port F, and pin PTEx/TCHx or pin PTFx/TCHx is available
as a general-purpose I/O pin. Table 16-3 shows how ELSxB and
ELSxA work. Reset clears the ELSxB and ELSxA bits.
Advance Information
224
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
ELSxB–ELSxA
X0
00
Mode
Output
Preset
NOTE:
X1
00
00
01
00
10
00
11
01
01
01
10
01
11
1X
01
1X
10
1X
11
Configuration
Pin under Port Control; Initial
Output Level High
Pin under Port Control; Initial
Output Level Low
Capture on Rising Edge Only
Input
Capture
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Output
Compare
or PWM
Buffered
Output
Compare
or Buffered
PWM
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Before enabling a TIM channel register for input capture operation, make
sure that the PTEx/TCHx pin or PTFx/TCHx pin is stable for at least two
bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE:
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
225
A G R E E M E N T
MSxB–MSxA
N O N - D I S C L O S U R E
Table 16-3. Mode, Edge, and Level Selection
R E Q U I R E D
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 16-7 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 16-7. CHxMAX Latency
16.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
N O N - D I S C L O S U R E
A G R E E M E N T
CHxMAX — Channel x Maximum Duty Cycle Bit
In input capture mode (MSxB–MSxA = 0–0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0–0), writing to the high byte
of the TIM channel x registers (TCHxH) inhibits output compares until
the low byte (TCHxL) is written.
Advance Information
226
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
Indeterminate after Reset
Register Name and Address TCH0L — $0028
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
Indeterminate after Reset
Register Name and Address TCH1H — $002A
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
Indeterminate after Reset
Register Name and Address TCH1L — $002B
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
Indeterminate after Reset
Register Name and Address TCH2H — $002D
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Indeterminate after Reset
Figure 16-8. TIM Channel Registers
(TCH0H/L–TCH3H/L) (Sheet 1 of 3)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
227
R E Q U I R E D
Write:
6
A G R E E M E N T
Read:
Bit 7
N O N - D I S C L O S U R E
Register Name and Address TCH0H — $0027
R E Q U I R E D
Register Name and Address TCH2L — $002E
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
Indeterminate after Reset
A G R E E M E N T
Register Name and Address TCH3H — $0030
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
Indeterminate after Reset
Register Name and Address TCH3L — $0031
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N O N - D I S C L O S U R E
Reset:
Indeterminate after Reset
Register Name and Address TCH4H — $0033
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
Indeterminate after Reset
Register Name and Address TCH4L — $0034
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indeterminate after Reset
Figure 16-8. TIM Channel Registers
(TCH0H/L–TCH3H/L) (Sheet 2 of 3)
Advance Information
228
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Write:
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
Indeterminate after Reset
Register Name and Address TCH5L — $0037
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indeterminate after Reset
N O N - D I S C L O S U R E
Figure 16-8. TIM Channel Registers
(TCH0H/L–TCH3H/L) (Sheet 3 of 3)
R E Q U I R E D
Read:
Bit 7
A G R E E M E N T
Register Name and Address TCH5H — $0036
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
229
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Advance Information
230
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
17.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
17.4.1
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
17.4.2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
17.4.3
Character Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
17.4.4
Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . 238
17.4.5
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
17.4.6
Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
17.4.7
Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . 242
17.4.8
Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
17.4.9
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
17.4.10 Character Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
17.4.11 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
17.4.12 Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
17.4.13 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
17.4.14 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
17.5 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
17.5.1
Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
17.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
17.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
17.7
SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .252
17.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
17.8.1
PTE0/TxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . . 253
17.8.2
PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . 253
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
231
R E Q U I R E D
17.1 Contents
A G R E E M E N T
Section 17. Serial Communications Interface (SCI)
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
R E Q U I R E D
17.2 Introduction
This section describes the serial communications interface module (SCI,
Version D), which allows high-speed asynchronous communications
with peripheral devices and other MCUs.
N O N - D I S C L O S U R E
A G R E E M E N T
17.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
17.9.1
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
17.9.2
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
17.9.3
SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
17.9.4
SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
17.9.5
SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
17.9.6
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
17.9.7
SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Advance Information
232
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
17.3 Features
•
Full Duplex Operation
•
Standard Mark/Space Non-Return-to-Zero (NRZ) Format
•
32 Programmable Baud Rates
•
Programmable 8-Bit or 9-Bit Character Length
•
Separately Enabled Transmitter and Receiver
•
Separate Receiver and Transmitter CPU Interrupt Requests
•
Programmable Transmitter Output Polarity
•
Two Receiver Wakeup Methods:
A G R E E M E N T
Features of the SCI module include:
– Idle Line Wakeup
– Address Mark Wakeup
•
Interrupt-Driven Operation with Eight Interrupt Flags:
– Transmitter Empty
– Transmission Complete
– Receiver Full
N O N - D I S C L O S U R E
– Idle Receiver Input
– Receiver Overrun
– Noise Error
– Framing Error
– Parity Error
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
•
Receiver Framing Error Detection
•
Hardware Parity Checking
•
1/16 Bit-Time Noise Detection
Advance Information
233
Figure 17-1 shows the structure of the SCI module. The SCI allows
full-duplex, asynchronous, NRZ serial communication between the MCU
and remote devices, including other MCUs. The transmitter and receiver
of the SCI operate independently, although they use the same baud rate
generator. During normal operation, the CPU monitors the status of the
SCI, writes the data to be transmitted, and processes received data.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
17.4 Functional Description
Advance Information
234
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
ERROR
INTERRUPT
CONTROL
RECEIVE
SHIFT REGISTER
PTE1/RxD
SCI DATA
REGISTER
RECEIVER
INTERRUPT
CONTROL
TRANSMITTER
INTERRUPT
CONTROL
SCI DATA
REGISTER
TRANSMIT
SHIFT REGISTER
PTE0/TxD
TXINV
SCTIE
R8
TCIE
A G R E E M E N T
T8
SCRIE
ILIE
TE
SCTE
RE
TC
RWU
SBK
SCRF
OR
ORIE
IDLE
NF
NEIE
FE
FEIE
PE
PEIE
LOOPS
WAKEUP
CONTROL
FLAG
CONTROL
RECEIVE
CONTROL
ENSCI
ENSCI
TRANSMIT
CONTROL
BKF
M
RPF
WAKE
N O N - D I S C L O S U R E
LOOPS
ILTY
CGMXCLK
R E Q U I R E D
INTERNAL BUS
÷4
PRESCALER
BAUD RATE
GENERATOR
÷ 16
PEN
PTY
DATA SELECTION
CONTROL
Figure 17-1. SCI Module Block Diagram
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
235
R E Q U I R E D
A G R E E M E N T
Table 17-1. SCI I/O Register Summary
Addr.
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
Reset:
0
0
0
0
0
0
0
0
Read:
R8
T8
R
R
ORIE
NEIE
FEIE
PEIE
Read:
$0013
SCI Control Register 1
(SCC1)
Write:
Reset:
Read:
$0014
$0015
$0016
$0017
$0018
N O N - D I S C L O S U R E
Register Name
SCI Control Register 2
(SCC2)
SCI Control Register 3
(SCC3)
SCI Status Register 1
(SCS1)
SCI Status Register 2
(SCS2)
SCI Data Register
(SCDR)
Write:
Write:
Reset:
U
U
0
0
0
0
0
0
Read:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
Write:
R
R
R
R
R
R
R
R
Reset:
1
1
0
0
0
0
0
0
Read:
0
0
0
0
0
0
BKF
RPF
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
SCR2
SCR1
SCR0
0
0
0
Reset:
Read:
$0019
SCI Baud Rate Register
(SCBR)
Unaffected by Reset
0
0
0
0
Write:
Reset:
SCP1
SCP0
0
0
= Unimplemented
Advance Information
236
R
0
= Reserved
U = Unaffected
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
The SCI uses the standard non-return-to-zero mark/space data format
illustrated in Figure 17-2.
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
POSSIBLE
PARITY
BIT
BIT 6
BIT 7
9-BIT DATA FORMAT
(BIT M IN SCC1 SET)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
NEXT
START
BIT
STOP
BIT
POSSIBLE
PARITY
BIT
BIT 6
BIT 7
BIT 8
STOP
BIT
A G R E E M E N T
8-BIT DATA FORMAT
(BIT M IN SCC1 CLEAR)
R E Q U I R E D
17.4.1 Data Format
NEXT
START
BIT
Figure 17-2. SCI Data Formats
17.4.2 Transmitter
Figure 17-3 shows the structure of the SCI transmitter.
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCC1) determines character length.
When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is
the ninth bit (bit 8).
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
237
N O N - D I S C L O S U R E
17.4.3 Character Length
During an SCI transmission, the transmit shift register shifts a character
out to the PTE0/TxD pin. The SCI data register (SCDR) is the write-only
buffer between the internal data bus and the transmit shift register. To
initiate an SCI transmission:
1. Initialize the Tx and Rx rate in the SCI baud register (SCBR)
($0019) see 17.9.7 SCI Baud Rate Register.
2. Enable the SCI by writing a logic 1 to ENSCI in SCI control register
1 (SCC1) ($0013).
A G R E E M E N T
R E Q U I R E D
17.4.4 Character Transmission
3. Enable the transmitter by writing a logic 1 to the transmitter enable
bit (TE) in SCI control register 2 (SCC2) ($0014).
4. Clear the SCI transmitter empty bit (SCTE) by first reading SCI
status register (SCS1) ($0016) and then writing to the SCDR
($0018).
5. Repeat step 3 for each subsequent transmission.
N O N - D I S C L O S U R E
At the start of a transmission, transmitter control logic automatically
loads the transmit shift register with a preamble of 10 or 11 logic 1s. After
the preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes
into the most significant bit position.
The SCI transmitter empty bit, SCTE in the SCI status control register
(SCS1), becomes set when the SCDR transfers a byte to the transmit
shift register. The SCTE bit indicates that the SCDR can accept new
data from the internal data bus. If the SCI transmit interrupt enable bit,
SCTI E (SCC2), is also set, the SCTE bit generates a transmitter CPU
interrupt request.
When the transmit shift register is not transmitting a character, the
PTE0/TxD pin goes to the idle condition, logic 1. If at any time software
clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and
receiver relinquish control of the port E pins.
Advance Information
238
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
INTERNAL BUS
÷ 16
SCI DATA REGISTER
SCP1
11-BIT
TRANSMIT
SHIFT REGISTER
STOP
CGMXCLK
BAUD
DIVIDER
SCP0
SCR1
H
SCR2
8
7
6
5
4
3
2
START
PRESCALER
÷4
1
0
L
PTE0/TxD
TXINV
A G R E E M E N T
MSB
PARITY
GENERATION
T8
BREAK
ALL ZEROS
PTY
PREAMBLE
ALL ONES
PEN
SHIFT ENABLE
M
LOAD FROM SCDR
TRANSMITTER CPU INTERRUPT REQUEST
SCR0
TRANSMITTER
CONTROL LOGIC
SCTE
SBK
SCTE
TC
TCIE
LOOPS
SCTIE
ENSCI
TC
TE
N O N - D I S C L O S U R E
SCTIE
TCIE
Figure 17-3. SCI Transmitter
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
239
R E Q U I R E D
A G R E E M E N T
Table 17-2. SCI Transmitter I/O Register Summary
Addr.
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
Reset:
0
0
0
0
0
0
0
0
Read:
R8
T8
R
R
ORIE
NEIE
FEIE
PEIE
Read:
$0013
SCI Control Register 1
(SCC1)
Write:
Reset:
Read:
$0014
$0015
$0016
$0017
$0018
N O N - D I S C L O S U R E
Register Name
SCI Control Register 2
(SCC2)
SCI Control Register 3
(SCC3)
SCI Status Register 1
(SCS1)
SCI Status Register 2
(SCS2)
SCI Data Register
(SCDR)
Write:
Write:
Reset:
U
U
0
0
0
0
0
0
Read:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
Write:
R
R
R
R
R
R
R
R
Reset:
1
1
0
0
0
0
0
0
Read:
0
0
0
0
0
0
BKF
RPF
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
$0019
SCI Baud Rate Register
(SCBR)
Unaffected by Reset
Read:
0
0
Write:
R
R
Reset:
0
0
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
= Unimplemented
Advance Information
240
R
= Reserved
U = Unaffected
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
The SCI recognizes a break character when a start bit is followed by
eight or nine logic 0 data bits and a logic 0 where the stop bit should be.
Receiving a break character has the following effects on SCI registers:
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
•
Sets the framing error bit (FE) in SCS1
•
Sets the SCI receiver full bit (SCRF) in SCS1
•
Clears the SCI data register (SCDR)
•
Clears the R8 bit in SCC3
•
Sets the break flag bit (BKF) in SCS2
•
May set the overrun (OR), noise flag (NF), parity error (PE), or
reception in progress flag (RPF) bits
Advance Information
241
R E Q U I R E D
A G R E E M E N T
Writing a logic 1 to the send break bit, SBK (SCC2), loads the transmit
shift register with a break character. A break character contains all logic
0s and has no start, stop, or parity bit. Break character length depends
on the M bit (SCC1). As long as SBK is at logic 1, transmitter logic
continuously loads break characters into the transmit shift register. After
software clears the SBK bit, the shift register finishes transmitting the
last break character and then transmits at least one logic 1. The
automatic logic 1 at the end of a break character guarantees the
recognition of the start bit of the next character.
N O N - D I S C L O S U R E
17.4.5 Break Characters
An idle character contains all logic 1s and has no start, stop, or parity bit.
Idle character length depends on the M bit (mode character length) in
SCC1. The preamble is a synchronizing idle character that begins every
transmission.
If the TE bit (transmitter enable) is cleared during a transmission, the
PTE0/TxD pin becomes idle after completion of the transmission in
progress. Clearing and then setting the TE bit during a transmission
queues an idle character to be sent after the character currently being
transmitted.
A G R E E M E N T
R E Q U I R E D
17.4.6 Idle Characters
NOTE:
When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the PTE0/TxD pin. Setting
TE after the stop bit appears on PTE0/TxD causes data previously
written to the SCDR to be lost.
A good time to toggle the TE bit is when the SCTE bit becomes set and
just before writing the next byte to the SCDR.
N O N - D I S C L O S U R E
17.4.7 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)
reverses the polarity of transmitted data. All transmitted values, including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
(See 17.9.1 SCI Control Register 1.)
Advance Information
242
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
•
SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE (SCC2),
enables the SCTE bit to generate transmitter CPU interrupt
requests.
•
Transmission complete (TC) — The TC bit in SCS1 indicates that
the transmit shift register and the SCDR are empty and that no
break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE (SCC2), enables the TC bit to
generate transmitter CPU interrupt requests.
17.4.9 Receiver
N O N - D I S C L O S U R E
Figure 17-4 shows the structure of the SCI receiver.
R E Q U I R E D
The following conditions can generate CPU interrupt requests from the
SCI transmitter:
A G R E E M E N T
17.4.8 Transmitter Interrupts
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
243
R E Q U I R E D
INTERNAL BUS
SCR1
SCR0
BAUD
DIVIDER
÷ 16
CGMXCLK
DATA
RECOVERY
PTE1/RxD
A G R E E M E N T
BKF
ALL ZEROS
CPU INTERRUPT REQUEST
ERROR CPU INTERRUPT REQUEST
RPF
M
WAKE
ILTY
PEN
PTY
H
8
7
6
5
4
3
SCRF
WAKEUP
LOGIC
PARITY
CHECKING
IDLE
ILIE
SCRF
SCRIE
N O N - D I S C L O S U R E
11-BIT
RECEIVE SHIFT REGISTER
STOP
PRESCALER
ALL ONES
÷4
SCI DATA REGISTER
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
START
SCR2
SCP0
2
1
0
L
MSB
SCP1
RWU
IDLE
R8
ILIE
SCRIE
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
Figure 17-4. SCI Receiver Block Diagram
Advance Information
244
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
Reset:
0
0
0
0
0
0
0
0
Read:
R8
Write:
R
T8
R
R
ORIE
NEIE
FEIE
PEIE
Reset:
U
U
0
0
0
0
0
0
Read:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
Write:
R
R
R
R
R
R
R
R
Reset:
1
1
0
0
0
0
0
0
Read:
0
0
0
0
0
0
BKF
RPF
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
SCR2
SCR1
SCR0
0
0
0
Read:
$0013
SCI Control Register 1
(SCC1)
Write:
Reset:
Read:
$0014
$0015
SCI Control Register 2
(SCC2)
SCI Control Register 3
(SCC3)
$0016 SCI Status Register 1 (SCS1)
$0017 SCI Status Register 2 (SCS2)
$0018
SCI Data Register
(SCDR)
Write:
Reset:
Read:
$0019
SCI Baud Rate Register
(SCBR)
Unaffected by Reset
0
0
0
0
Write:
Reset:
SCP1
SCP0
0
0
= Unimplemented
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R
0
= Reserved
U = Unaffected
Advance Information
245
R E Q U I R E D
Register Name
A G R E E M E N T
Addr.
N O N - D I S C L O S U R E
Table 17-3. SCI Receiver I/O Register Summary
R E Q U I R E D
17.4.10 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCC1) determines character length.
When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the
ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth
bit (bit 7).
A G R E E M E N T
17.4.11 Character Reception
During an SCI reception, the receive shift register shifts characters in
from the PTE1/RxD pin. The SCI data register (SCDR) is the read-only
buffer between the internal data bus and the receive shift register.
N O N - D I S C L O S U R E
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The SCI receiver full bit,
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the SCI receive interrupt enable bit, SCRIE
(SCC2), is also set, the SCRF bit generates a receiver CPU interrupt
request.
Advance Information
246
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
•
After every start bit
•
After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
LSB
START BIT
PTE1/RxD
START BIT
VERIFICATION
DATA
SAMPLING
N O N - D I S C L O S U R E
START BIT
QUALIFICATION
SAMPLES
RT4
RT3
RT2
RT16
RT1
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
Figure 17-5. Receiver Data Sampling
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
The receiver samples the PTE1/RxD pin at the RT clock rate. The RT
clock is an internal signal with a frequency 16 times the baud rate. To
adjust for baud rate mismatch, the RT clock is resynchronized at the
following times (see Figure 17-5):
A G R E E M E N T
17.4.12 Data Sampling
Advance Information
247
R E Q U I R E D
To verify the start bit and to detect noise, data recovery logic takes
samples at RT3, RT5, and RT7. Table 17-4 summarizes the results of
the start bit verification samples.
A G R E E M E N T
Table 17-4. Start Bit Verification
RT3, RT5, and RT7
Samples
Start Bit
Verification
Noise Flag
000
Yes
0
001
Yes
1
010
Yes
1
011
No
0
100
Yes
1
101
No
0
110
No
0
111
No
0
If start bit verification is not successful, the RT clock is reset and a new
search for a start bit begins.
N O N - D I S C L O S U R E
To determine the value of a data bit and to detect noise, recovery logic
takes samples at RT8, RT9, and RT10. Table 17-5 summarizes the
results of the data bit samples.
Table 17-5. Data Bit Recovery
Advance Information
248
RT8, RT9, and RT10
Samples
Data Bit
Determination
Noise Flag
000
0
0
001
0
1
010
0
1
011
1
1
100
0
1
101
1
1
110
1
1
111
1
0
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
The RT8, RT9, and RT10 samples do not affect start bit verification. If
any or all of the RT8, RT9, and RT10 start bit samples are logic 1s
following a successful start bit verification, the noise flag (NF) is set and
the receiver assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at
RT8, RT9, and RT10. Table 17-6 summarizes the results of the stop bit
samples.
R E Q U I R E D
NOTE:
Framing
Error Flag
Noise Flag
000
1
0
001
1
1
010
1
1
011
0
1
100
1
1
101
0
1
110
0
1
111
0
0
17.4.13 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error bit, FE, in
SCS1. The FE flag is set at the same time that the SCRF bit (SCS1) is
set. A break character that has no stop bit also sets the FE bit.
17.4.14 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup bit, RWU (SCC2), puts the
receiver into a standby state during which receiver interrupts are
disabled.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
249
N O N - D I S C L O S U R E
RT8, RT9, and RT10
Samples
A G R E E M E N T
Table 17-6. Stop Bit Recovery
R E Q U I R E D
N O N - D I S C L O S U R E
A G R E E M E N T
Depending on the state of the WAKE bit in SCC1, either of two
conditions on the PTE1/RxD pin can bring the receiver out of the standby
state:
NOTE:
•
Address mark — An address mark is a logic 1 in the most
significant bit position of a received character. When the WAKE bit
is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI
receiver full bit, SCRF. Software can then compare the character
containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and
processes the characters that follow. If they are not the same,
software can set the RWU bit and put the receiver back into the
standby state.
•
Idle input line condition — When the WAKE bit is clear, an idle
character on the PTE1/RxD pin wakes the receiver from the
standby state by clearing the RWU bit. The idle character that
wakes the receiver does not set the receiver idle bit, IDLE, or the
SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines
whether the receiver begins counting logic 1s as idle character bits
after the start bit or after the stop bit.
Clearing the WAKE bit after the PTE1/RxD pin has been idle may cause
the receiver to wake up immediately.
17.5 Receiver Interrupts
The following sources can generate CPU interrupt requests from the SCI
receiver:
•
Advance Information
250
SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that
the receive shift register has transferred a character to the SCDR.
SCRF can generate a receiver CPU interrupt request. Setting the
SCI receive interrupt enable bit, SCRIE (SCC2), enables the
SCRF bit to generate receiver CPU interrupts.
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
The following receiver error flags in SCS1 can generate CPU interrupt
requests:
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
•
Receiver overrun (OR) — The OR bit indicates that the receive
shift register shifted in a new character before the previous
character was read from the SCDR. The previous character
remains in the SCDR, and the new character is lost. The overrun
interrupt enable bit, ORIE (SCC3), enables OR to generate SCI
error CPU interrupt requests.
•
Noise flag (NF) — The NF bit is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE (SCC3), enables
NF to generate SCI error CPU interrupt requests.
•
Framing error (FE) — The FE bit in SCS1 is set when a logic 0
occurs where the receiver expects a stop bit. The framing error
interrupt enable bit, FEIE (SCC3), enables FE to generate SCI
error CPU interrupt requests.
•
Parity error (PE) — The PE bit in SCS1 is set when the SCI
detects a parity error in incoming data. The parity error interrupt
enable bit, PEIE (SCC3), enables PE to generate SCI error CPU
interrupt requests.
Advance Information
251
R E Q U I R E D
17.5.1 Error Interrupts
A G R E E M E N T
Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11
consecutive logic 1s shifted in from the PTE1/RxD pin. The idle
line interrupt enable bit, ILIE (SCC2), enables the IDLE bit to
generate CPU interrupt requests.
N O N - D I S C L O S U R E
•
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
17.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby
modes.
17.6.1 Wait Mode
The SCI module remains active after the execution of a WAIT
instruction. In wait mode, the SCI module registers are not accessible by
the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.
17.6.2 Stop Mode
The SCI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect SCI register states. SCI module
operation resumes after an external interrupt.
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
17.7 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during interrupts generated by the break
module. The BCFE bit in the SIM break flag control register (SBFCR)
enables software to clear status bits during the break state.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
Advance Information
252
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Port E shares two of its pins with the SCI module. The two SCI I/O pins
are:
•
PTE0/TxD — Transmit data
•
PTE1/RxD — Receive data
17.8.1 PTE0/TxD (Transmit Data)
The PTE0/TxD pin is the serial data output from the SCI transmitter. The
SCI shares the PTE0/TxD pin with port E. When the SCI is enabled, the
PTE0/TxD pin is an output regardless of the state of the DDRE0 bit in
data direction register E (DDRE).
17.8.2 PTE1/RxD (Receive Data)
The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI
shares the PTE1/RxD pin with port E. When the SCI is enabled, the
PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data
direction register E (DDRE).
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
253
R E Q U I R E D
A G R E E M E N T
17.8 I/O Signals
N O N - D I S C L O S U R E
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
R E Q U I R E D
These I/O registers control and monitor SCI operation:
•
SCI control register 1 (SCC1)
•
SCI control register 2 (SCC2)
•
SCI control register 3 (SCC3)
•
SCI status register 1 (SCS1)
•
SCI status register 2 (SCS2)
•
SCI data register (SCDR)
•
SCI baud rate register (SCBR)
17.9.1 SCI Control Register 1
SCI control register 1:
N O N - D I S C L O S U R E
A G R E E M E N T
17.9 I/O Registers
Advance Information
254
•
Enables loop mode operation
•
Enables the SCI
•
Controls output polarity
•
Controls character length
•
Controls SCI wakeup method
•
Controls idle character detection
•
Enables parity function
•
Controls parity type
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Read:
Write:
Reset:
$0013
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
0
Figure 17-6. SCI Control Register 1 (SCC1)
R E Q U I R E D
Address:
ENSCI — Enable SCI Bit
This read/write bit enables the SCI and the SCI baud rate generator.
Clearing ENSCI sets the SCTE and TC bits in SCI status register 1
and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled
TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset
clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE:
Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
255
N O N - D I S C L O S U R E
This read/write bit enables loop mode operation. In loop mode the
PTE1/RxD pin is disconnected from the SCI, and the transmitter
output goes into the receiver input. Both the transmitter and the
receiver must be enabled to use loop mode. Reset clears the LOOPS
bit.
1 = Loop mode enabled
0 = Normal operation enabled
A G R E E M E N T
LOOPS — Loop Mode Select Bit
R E Q U I R E D
M — Mode (Character Length) Bit
This read/write bit determines whether SCI characters are eight or
nine bits long. (See Table 17-7.) The ninth bit can serve as an extra
stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Condition Bit
A G R E E M E N T
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
character or an idle condition on the PTE1/RxD pin. Reset clears the
WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
N O N - D I S C L O S U R E
This read/write bit determines when the SCI starts counting logic 1s
as idle character bits. The counting begins either after the start bit or
after the stop bit. If the count begins after the start bit, then a string of
logic 1s preceding the stop bit can cause false recognition of an idle
character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
PEN — Parity Enable Bit
This read/write bit enables the SCI parity function. (See Table 17-7.)
When enabled, the parity function inserts a parity bit in the most
significant bit position. (See Figure 17-2.) Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
Advance Information
256
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
NOTE:
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 17-7. Character Format Selection
Control Bits
Character Format
PEN:PTY
Start Bits
Data Bits
Parity
Stop Bits
Character
Length
0
0X
1
8
None
1
10 Bits
1
0X
1
9
None
1
11 Bits
0
10
1
7
Even
1
10 Bits
0
11
1
7
Odd
1
10 Bits
1
10
1
8
Even
1
11 Bits
1
11
1
8
Odd
1
11 Bits
N O N - D I S C L O S U R E
M
R E Q U I R E D
This read/write bit determines whether the SCI generates and checks
for odd parity or even parity. (See Table 17-7.) Reset clears the PTY
bit.
1 = Odd parity
0 = Even parity
A G R E E M E N T
PTY — Parity Bit
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
257
SCI control register 2:
•
Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt
requests
– Enables the TC bit to generate transmitter CPU interrupt
requests
– Enables the SCRF bit to generate receiver CPU interrupt
requests
A G R E E M E N T
R E Q U I R E D
17.9.2 SCI Control Register 2
– Enables the IDLE bit to generate receiver CPU interrupt
requests
•
Enables the transmitter
•
Enables the receiver
•
Enables SCI wakeup
•
Transmits SCI break characters
N O N - D I S C L O S U R E
Address:
Read:
Write:
Reset:
$0014
Bit 7
6
5
4
3
2
1
Bit 0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
Figure 17-7. SCI Control Register 2 (SCC2)
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter
CPU interrupt requests. Reset clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt requests
0 = SCTE not enabled to generate CPU interrupt requests
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU
interrupt requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
Advance Information
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MC68HC08AS20 —Rev. 4.1
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This read/write bit enables the IDLE bit to generate SCI receiver CPU
interrupt requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
PTE0/TxD pin. If software clears the TE bit, the transmitter completes
any transmission in progress before the PTE0/TxD returns to the idle
condition (logic 1). Clearing and then setting TE during a transmission
queues an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE:
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver but does not affect receiver interrupt flag bits.
Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
NOTE:
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
259
R E Q U I R E D
ILIE — Idle Line Interrupt Enable Bit
A G R E E M E N T
This read/write bit enables the SCRF bit to generate SCI receiver
CPU interrupt requests. Reset clears the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt requests
0 = SCRF not enabled to generate CPU interrupt requests
N O N - D I S C L O S U R E
SCRIE — SCI Receive Interrupt Enable Bit
R E Q U I R E D
RWU — Receiver Wakeup Bit
This read/write bit puts the receiver in a standby state during which
receiver interrupts are disabled. The WAKE bit in SCC1 determines
whether an idle input or an address mark brings the receiver out of the
standby state and clears the RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
N O N - D I S C L O S U R E
A G R E E M E N T
Setting and then clearing this read/write bit transmits a break
character followed by a logic 1. The logic 1 after the break character
guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic 1s
between them. Reset clears the SBK bit.
1 = Transmit break characters
0 = No break characters transmitted
NOTE:
Do not toggle the SBK bit immediately after setting the SCTE bit because
toggling SBK too early causes the SCI to send a break character instead
of a preamble.
17.9.3 SCI Control Register 3
SCI control register 3:
•
Stores the ninth SCI data bit received and the ninth SCI data bit to
be transmitted
•
Enables these interrupts:
– Receiver overrun interrupts
– Noise error interrupts
– Framing error interrupts
– Parity error interrupts
Advance Information
260
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Bit 7
Read:
R8
Write:
Reset:
U
6
5
4
3
2
1
Bit 0
T8
R
R
ORIE
NEIE
FEIE
PEIE
U
0
0
0
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 17-8. SCI Control Register 3 (SCC3)
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth
bit (bit 8) of the received character. R8 is received at the same time
that the SCDR receives the other eight bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth
bit (bit 7). Reset has no effect on the R8 bit.
T8 — Transmitted Bit 8
N O N - D I S C L O S U R E
When the SCI is transmitting 9-bit characters, T8 is the read/write
ninth bit (bit 8) of the transmitted character. T8 is loaded into the
transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the noise error bit, NE. Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
$0015
A G R E E M E N T
Address:
Advance Information
261
R E Q U I R E D
This read/write bit enables SCI error CPU interrupt requests
generated by the framing error bit, FE. Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI receiver CPU interrupt requests
generated by the parity error bit, PE. (See Figure 17-9.) Reset clears
PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
17.9.4 SCI Status Register 1
SCI status register 1 contains flags to signal the following conditions:
N O N - D I S C L O S U R E
A G R E E M E N T
FEIE — Receiver Framing Error Interrupt Enable Bit
•
Transfer of SCDR data to transmit shift register complete
•
Transmission complete
•
Transfer of receive shift register data to SCDR complete
•
Receiver input idle
•
Receiver overrun
•
Noisy data
•
Framing error
•
Parity error
Address:
$0016
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
Write:
R
R
R
R
R
R
R
R
Reset:
1
1
0
0
0
0
0
0
R
= Reserved
Figure 17-9. SCI Status Register 1 (SCS1)
Advance Information
262
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
NOTE:
Setting the TE bit for the first time also sets the SCTE bit. Setting the TE
and SCTIE bits generates an SCI transmitter CPU request.
TC — Transmission Complete Bit
This read-only bit is set when the SCTE bit is set and no data,
preamble, or break character is being transmitted. TC generates an
SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also
set. TC is cleared automatically when data, preamble, or break
character is queued and ready to be sent. There may be up to 1.5
transmitter clocks of latency between queueing data, preamble, and
break character and the transmission actually starting. Reset sets the
TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. SCRF can generate an SCI
receiver CPU interrupt request. In normal operation, clear the SCRF
bit by reading SCS1 with SCRF set and then reading the SCDR.
Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an SCI error CPU
interrupt request if the ILIE bit in SCC2 is also set and the DMARE bit
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
263
R E Q U I R E D
A G R E E M E N T
This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal
operation, clear the SCTE bit by reading SCS1 with SCTE set and
then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
N O N - D I S C L O S U R E
SCTE — SCI Transmitter Empty Bit
R E Q U I R E D
in SCC3 is clear. Clear the IDLE bit by reading SCS1 with IDLE set
and then reading the SCDR. After the receiver is enabled, it must
receive a valid character that sets the SCRF bit before an idle
condition can set the IDLE bit. Also, after the IDLE bit has been
cleared, a valid character must again set the SCRF bit before an idle
condition can set the IDLE bit. Reset clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
A G R E E M E N T
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the
SCDR before the receive shift register receives the next character.
The OR bit generates an SCI error CPU interrupt request if the ORIE
bit in SCC3 is also set. The data in the shift register is lost, but the data
already in the SCDR is not affected. Clear the OR bit by reading SCS1
with OR set and then reading the SCDR. Reset clears the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
N O N - D I S C L O S U R E
Software latency may allow an overrun to occur between reads of
SCS1 and SCDR in the flag-clearing sequence. Figure 17-10 shows
the normal flag-clearing sequence and an example of an overrun
caused by a delayed flag-clearing sequence. The delayed read of
SCDR does not clear the OR bit because OR was not set when SCS1
was read. Byte 2 caused the overrun and is lost. The next
flag-clearing sequence reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is
important to know which byte is lost due to an overrun, the
flag-clearing routine can check the OR bit in a second read of SCS1
after reading the data register.
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the
PTE1/RxD pin. NF generates an NF CPU interrupt request if the NEIE
bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then
reading the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected
Advance Information
264
MC68HC08AS20 —Rev. 4.1
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PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
BYTE 3
SCRF = 0
SCRF = 1
SCRF = 0
SCRF = 1
BYTE 2
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCDR
BYTE 2
READ SCDR
BYTE 3
N O N - D I S C L O S U R E
BYTE 1
SCRF = 0
SCRF = 1
NORMAL FLAG CLEARING SEQUENCE
BYTE 2
BYTE 3
SCRF = 0
OR = 0
SCRF = 1
OR = 1
SCRF = 0
OR = 1
SCRF = 1
OR = 1
SCRF = 1
DELAYED FLAG CLEARING SEQUENCE
BYTE 1
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
Figure 17-10. Flag Clearing Sequence
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
This clearable, read-only bit is set when a logic 0 is accepted as the
stop bit. FE generates an SCI error CPU interrupt request if the FEIE
bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
A G R E E M E N T
FE — Receiver Framing Error Bit
Advance Information
265
SCI status register 2 contains flags to signal two conditions:
1. Break character detected
2. Incoming data
Address:
A G R E E M E N T
R E Q U I R E D
17.9.5 SCI Status Register 2
$0017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
BKF
RPF
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 17-11. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
N O N - D I S C L O S U R E
This clearable, read-only bit is set when the SCI detects a break
character on the PTE1/RxD pin. In SCS1, the FE and SCRF bits are
also set. In 9-bit character transmissions, the R8 bit in SCC3 is
cleared. BKF does not generate a CPU interrupt request. Clear BKF
by reading SCS2 with BKF set and then reading the SCDR. Once
cleared, BKF can become set again only after logic 1s again appear
on the PTE1/RxD pin followed by another break character. Reset
clears the BKF bit.
1 = Break character detected
0 = No break character detected
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the
RT1 time period of the start bit search. RPF does not generate an
interrupt request. RPF is reset after the receiver detects false start
bits, usually from noise or a baud rate mismatch or when the receiver
detects an idle character. Polling RPF before disabling the SCI
module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
Advance Information
266
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Address:
$0018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Unaffected by Reset
Figure 17-12. SCI Data Register (SCDR)
R7/T7–R0/T0 — Receive/Transmit Data Bits
N O N - D I S C L O S U R E
Reading address $0018 accesses the read-only received data bits,
R7–R0. Writing to address $0018 writes the data to be transmitted,
T7–T0. Reset has no effect on the SCI data register.
R E Q U I R E D
The SCI data register is the buffer between the internal data bus and the
receive and transmit shift registers. Reset has no effect on data in the
SCI data register.
A G R E E M E N T
17.9.6 SCI Data Register
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
267
The baud rate register selects the baud rate for both the receiver and the
transmitter.
Address:
Read:
$0019
Bit 7
6
0
0
0
0
Write:
A G R E E M E N T
R E Q U I R E D
17.9.7 SCI Baud Rate Register
Reset:
5
4
SCP1
SCP0
0
0
3
2
1
Bit 0
SCR2
SCR1
SCR0
0
0
0
0
= Unimplemented
Figure 17-13. SCI BAUD Rate Register (SCBR)
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown
in Table 17-8. Reset clears SCP1 and SCP0.
N O N - D I S C L O S U R E
Table 17-8. SCI Baud Rate Prescaling
SCP1:SCP0
Prescaler Divisor (PD)
00
1
01
3
10
4
11
13
SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate divisor as shown in
Table 17-9. Reset clears SCR2:SCR0.
Advance Information
268
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
SCR2:SCR1:SCR0
Baud Rate Divisor (BD)
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
A G R E E M E N T
Table 17-9. SCI Baud Rate Selection
Use the following formula to calculate the SCI baud rate:
CGMXCLK
Baud rate = -----------------------------------64 × PD × BD
PD = Prescale divisor (see Table 17-8)
N O N - D I S C L O S U R E
BD = Baud rate divisor (see Table 17-9)
MC68HC08AS20 — Rev. 4.1
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Advance Information
269
Table 17-10. SCI Baud Rate Selection Examples
SCP1:SCP0
Prescaler Divisor
(PD)
SCR2:SCR1:SCR0
Baud Rate Divisor
(BD)
Baud Rate
(fXCLK = 4.194 MHz)
00
1
000
1
65,531
00
1
001
2
32,766
00
1
010
4
16,383
00
1
011
8
8191
00
1
100
16
4095
00
1
101
32
2048
00
1
110
64
1024
00
1
111
128
512
01
3
000
1
21,844
01
3
001
2
10,922
01
3
010
4
5461
01
3
011
8
2730
01
3
100
16
1365
01
3
101
32
683
01
3
110
64
341
01
3
111
128
171
10
4
000
1
16,383
10
4
001
2
8191
10
4
010
4
4096
10
4
011
8
2048
10
4
100
16
1024
10
4
101
32
512
10
4
110
64
256
10
4
111
128
128
11
13
000
1
5041
11
13
001
2
1664
11
13
010
4
1260
11
13
011
8
630
11
13
100
16
315
11
13
101
32
158
11
13
110
64
78.8
11
13
111
128
39.4
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Table 17-10 shows the SCI baud rates that can be generated with a
4.194-MHz crystal.
Advance Information
270
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
18.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
18.4
Pin Name and Register Name Conventions . . . . . . . . . . . . . . 273
18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
18.5.1
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
18.5.2
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
18.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
18.6.1
Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . 278
18.6.2
Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . 279
18.6.3
Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . 280
18.6.4
Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . 282
18.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
18.7.1
Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
18.7.2
Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
18.8
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
18.9
Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 289
18.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
18.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
18.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
18.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
18.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 293
18.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
18.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . .294
18.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . .295
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
271
R E Q U I R E D
18.1 Contents
A G R E E M E N T
Section 18. Serial Peripheral Interface (SPI)
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
R E Q U I R E D
SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
VSS (Clock Ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
18.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
18.14.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
18.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .300
18.14.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
18.2 Introduction
This section describes the serial peripheral interface (SPI) module,
which allows full-duplex, synchronous, serial communications with
peripheral devices.
18.3 Features
Features of the SPI module include:
N O N - D I S C L O S U R E
A G R E E M E N T
18.13.3
18.13.4
18.13.5
•
Full-Duplex Operation
•
Master and Slave Modes
•
Double-Buffered Operation with Separate Transmit and Receive
Registers
•
Four Master Mode Frequencies (Maximum = Bus Frequency ÷ 2)
•
Maximum Slave Mode Frequency = Bus Frequency
•
Serial Clock with Programmable Polarity and Phase
•
Two Separately Enabled Interrupts with CPU Service:
– SPRF (SPI Receiver Full)
– SPTE (SPI Transmitter Empty)
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•
Mode Fault Error Flag with CPU Interrupt Capability
•
Overflow Error Flag with CPU Interrupt Capability
•
Programmable Wired-OR Mode
•
I2C (Inter-Integrated Circuit) Compatibility
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
•
SS (slave select)
•
SPSCK (SPI serial clock)
•
MOSI (master out slave in)
•
MISO (master in slave out)
The SPI shares four I/O pins with a parallel I/O port. The full name of an
SPI pin reflects the name of the shared port pin. Table 18-1 shows the
full names of the SPI I/O pins. The generic pin names appear in the text
that follows.
Table 18-1. Pin Name Conventions
SPI Generic Pin Name:
Full SPI Pin Name:
MISO
MOSI
SS
SPSCK
PTE5/MISO
PTE6/MOSI
PTE4/SS
PTE7/SPSCK
The generic names of the SPI I/O registers are:
•
SPI control register (SPCR)
•
SPI status and control register (SPSCR)
•
SPI data register (SPDR)
Table 18-2 shows the names and the addresses of the SPI I/O registers.
Table 18-2. I/O Register Addresses
Register Name
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Address
SPI Control Register
$0010
SPI Status and Control Register
$0011
SPI Data Register
$0012
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273
A G R E E M E N T
The generic names of the SPI input/output (I/O) pins are:
N O N - D I S C L O S U R E
18.4 Pin Name and Register Name Conventions
R E Q U I R E D
18.5 Functional Description
Table 18-3 summarizes the SPI I/O registers and Figure 18-1 shows the
structure of the SPI module.
Table 18-3. SPI I/O Register Summary
Addr
Bit 7
6
5
4
3
2
1
Bit 0
SPI Control Register Read:
SPRIE
(SPCR) Write:
R
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
0
1
0
1
0
0
0
OVRF
MODF
SPTE
MODFEN
SPR1
SPR0
Reset:
$0011
SPI Status and Control Register Read:
(SPSCR) Write:
Reset:
$0012
SPI Data Register Read:
(SPDR) Write:
0
SPRF
ERRIE
0
0
0
0
1
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
N O N - D I S C L O S U R E
A G R E E M E N T
$0010
Register Name
Unaffected by Reset
R
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274
= Reserved
= Unimplemented
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
INTERNAL BUS
TRANSMIT DATA REGISTER
SHIFT REGISTER
7
6
5
4
3
2
1
MISO
0
÷2
MOSI
÷8
RECEIVE DATA REGISTER
÷ 32
PIN
CONTROL
LOGIC
÷ 128
SPMSTR
CLOCK
SELECT
SPE
SPR1
A G R E E M E N T
CLOCK
DIVIDER
SPSCK
M
CLOCK
LOGIC
S
SPR0
SPMSTR
TRANSMITTER CPU INTERRUPT REQUEST
CPHA
MODFEN
SS
CPOL
SPWOM
ERRIE
SPI
CONTROL
SPTIE
RECEIVER/ERROR CPU INTERRUPT REQUEST
SPRIE
SPE
SPRF
SPTE
OVRF
MODF
Figure 18-1. SPI Module Block Diagram
The SPI module allows full-duplex, synchronous, serial communication
between the MCU and peripheral devices, including other MCUs.
Software can poll the SPI status flags or SPI operation can be
interrupt-driven. All SPI interrupts can be serviced by the CPU.
The following paragraphs describe the operation of the SPI module.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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N O N - D I S C L O S U R E
BUS CLOCK
The SPI operates in master mode when the SPI master bit, SPMSTR
(SPCR $0010), is set.
NOTE:
Configure the SPI modules as master and slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave
SPI before disabling the master SPI. (See 18.14.1 SPI Control
Register.)
Only a master SPI module can initiate transmissions. Software begins
the transmission from a master SPI module by writing to the SPI data
register. If the shift register is empty, the byte immediately transfers to
the shift register, setting the SPI transmitter empty bit, SPTE (SPSCR
$0011). The byte begins shifting out on the MOSI pin under the control
of the serial clock. (See Figure 18-2.)
A G R E E M E N T
R E Q U I R E D
18.5.1 Master Mode
N O N - D I S C L O S U R E
The SPR1 and SPR0 bits control the baud rate generator and determine
the speed of the shift register. (See 18.14.2 SPI Status and Control
Register.) Through the SPSCK pin, the baud rate generator of the
master also controls the shift register of the slave peripheral.
MASTER MCU
SHIFT REGISTER
SLAVE MCU
MISO
MISO
MOSI
MOSI
SPSCK
BAUD RATE
GENERATOR
SS
SHIFT REGISTER
SPSCK
VDD
SS
Figure 18-2. Full-Duplex Master-Slave Connections
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276
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
The SPI operates in slave mode when the SPMSTR bit (SPCR $0010)
is clear. In slave mode the SPSCK pin is the input for the serial clock
from the master MCU. Before a data transmission occurs, the SS pin of
the slave MCU must be at logic 0. SS must remain low until the
transmission is complete. (See 18.7.2 Mode Fault Error.)
In a slave SPI module, data enters the shift register under the control of
the serial clock from the master SPI module. After a byte enters the shift
register of a slave SPI, it is transferred to the receive data register, and
the SPRF bit (SPSCR) is set. To prevent an overflow condition, slave
software then must read the SPI data register before another byte enters
the shift register.
The maximum frequency of the SPSCK for an SPI configured as a slave
is the bus clock speed, which is twice as fast as the fastest master
SPSCK clock that can be generated. The frequency of the SPSCK for an
SPI configured as a slave does not have to correspond to any SPI baud
rate. The baud rate only controls the speed of the SPSCK generated by
an SPI configured as a master. Therefore, the frequency of the SPSCK
for an SPI configured as a slave can be any frequency less than or equal
to the bus speed.
When the master SPI starts a transmission, the data in the slave shift
register begins shifting out on the MISO pin. The slave can load its shift
register with a new byte for the next transmission by writing to its transmit
data register. The slave must write to its transmit data register at least
one bus cycle before the master starts the next transmission. Otherwise,
the byte already in the slave shift register shifts out on the MISO pin.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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R E Q U I R E D
A G R E E M E N T
18.5.2 Slave Mode
N O N - D I S C L O S U R E
As the byte shifts out on the MOSI pin of the master, another byte shifts
in from the slave on the master’s MISO pin. The transmission ends when
the receiver full bit, SPRF (SPSCR), becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data
register. In normal operation, SPRF signals the end of a transmission.
Software clears SPRF by reading the SPI status and control register and
then reading the SPI data register. Writing to the SPI data register clears
the SPTIE bit.
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Data written to the slave shift register during a a transmission remains in
a buffer until the end of the transmission.
When the clock phase bit (CPHA) is set, the first edge of SPSCK starts
a transmission. When CPHA is clear, the falling edge of SS starts a
transmission. (See 18.6 Transmission Formats.)
If the write to the data register is late, the SPI transmits the data already
in the shift register from the previous transmission.
NOTE:
To prevent SPSCK from appearing as a clock edge, SPSCK must be in
the proper idle state before the slave is enabled.
18.6 Transmission Formats
During an SPI transmission, data is simultaneously transmitted (shifted
out serially) and received (shifted in serially). A serial clock line
synchronizes shifting and sampling on the two serial data lines. A slave
select line allows individual selection of a slave SPI device; slave
devices that are not selected do not interfere with SPI bus activities. On
a master SPI device, the slave select line can be used optionally to
indicate a multiple-master bus contention.
18.6.1 Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SCK) phase
and polarity using two bits in the SPI control register (SPCR). The clock
polarity is specified by the CPOL control bit, which selects an active high
or low clock and has no significant effect on the transmission format.
The clock phase (CPHA) control bit (SPCR) selects one of two
fundamentally different transmission formats. The clock phase and
polarity should be identical for the master SPI device and the
communicating slave device. In some cases, the phase and polarity are
changed between transmissions to allow a master device to
communicate with peripheral slaves having different requirements.
NOTE:
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278
Before writing to the CPOL bit or the CPHA bit (SPCR), disable the SPI
by clearing the SPI enable bit (SPE).
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
SCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
SCK CPOL = 0
SCK CPOL = 1
MOSI
FROM MASTER
MISO
FROM SLAVE
MSB
SS TO SLAVE
CAPTURE STROBE
Figure 18-3. Transmission Format (CPHA = 0)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
N O N - D I S C L O S U R E
Figure 18-3 shows an SPI transmission in which CPHA (SPCR) is
logic 0. The figure should not be used as a replacement for data sheet
parametric information.Two waveforms are shown for SCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted
as a master or slave timing diagram since the serial clock (SCK), master
in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the
output from the slave, and the MOSI signal is the output from the master.
The SS line is the slave select input to the slave. The slave SPI drives
its MISO output only when its slave select input (SS) is at logic 0, so that
only the selected slave drives to the master. The SS pin of the master is
not shown but is assumed to be inactive. The SS pin of the master must
be high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See 18.7.2 Mode Fault Error.) When CPHA = 0, the first SPSCK
edge is the MSB capture strobe. Therefore, the slave must begin driving
its data before the first SPSCK edge, and a falling edge on the SS pin is
used to start the transmission. The SS pin must be toggled high and then
low again between each byte transmitted as shown in Figure 18-4.
A G R E E M E N T
18.6.2 Transmission Format When CPHA = 0
Advance Information
279
R E Q U I R E D
BYTE 1
BYTE 2
BYTE 3
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 18-4. CPHA/SS Timing
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the falling edge of SS. Any data
written after the falling edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
18.6.3 Transmission Format When CPHA = 1
Figure 18-5 shows an SPI transmission in which CPHA (SPCR) is
logic 1. The figure should not be used as a replacement for data sheet
parametric information. Two waveforms are shown for SCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted
as a master or slave timing diagram since the serial clock (SCK), master
in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the
output from the slave, and the MOSI signal is the output from the master.
The SS line is the slave select input to the slave. The slave SPI drives
its MISO output only when its slave select input (SS) is at logic 0, so that
only the selected slave drives to the master. The SS pin of the master is
not shown but is assumed to be inactive. The SS pin of the master must
be high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See 18.7.2 Mode Fault Error.) When CPHA = 1, the master
N O N - D I S C L O S U R E
A G R E E M E N T
MISO/MOSI
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
3
4
5
6
7
8
MOSI
FROM MASTER
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MISO
FROM SLAVE
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
R E Q U I R E D
2
SCK CPOL = 0
SCK CPOL =1
LSB
SS TO SLAVE
CAPTURE STROBE
Figure 18-5. Transmission Format (CPHA = 1)
begins driving its MOSI pin on the first SPSCK edge. Therefore, the
slave uses the first SPSCK edge as a start transmission signal. The SS
pin can remain low between transmissions. This format may be
preferable in systems having only one master and only one slave driving
the MISO data line.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the first edge of SPSCK. Any
data written after the first edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
281
A G R E E M E N T
1
N O N - D I S C L O S U R E
SCK CYCLE #
FOR REFERENCE
When the SPI is configured as a master (SPMSTR = 1), transmissions
are started by a software write to the SPDR ($0012). CPHA has no effect
on the delay to the start of the transmission, but it does affect the initial
state of the SCK signal. When CPHA = 0, the SCK signal remains
inactive for the first half of the first SCK cycle. When CPHA = 1, the first
SCK cycle begins with an edge on the SCK line from its inactive to its
active level. The SPI clock rate (selected by SPR1–SPR0) affects the
delay from the write to SPDR and the start of the SPI transmission. (See
Figure 18-6.) The internal SPI clock in the master is a free-running
derivative of the internal MCU clock. It is only enabled when both the
SPE and SPMSTR bits (SPCR) are set to conserve power. SCK edges
occur halfway through the low time of the internal MCU clock. Since the
SPI clock is free-running, it is uncertain where the write to the SPDR will
occur relative to the slower SCK. This uncertainty causes the variation
in the initiation delay shown in Figure 18-6. This delay will be no longer
than a single SPI bit time. That is, the maximum delay between the write
to SPDR and the start of the SPI transmission is two MCU bus cycles for
DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and
128 MCU bus cycles for DIV128.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
18.6.4 Transmission Initiation Latency
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
WRITE
TO SPDR
INITIATION DELAY
BUS
CLOCK
MOSI
MSB
BIT 6
BIT 5
SCK
CPHA = 1
SCK
CPHA = 0
1
2
3
A G R E E M E N T
SCK CYCLE
NUMBER
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN








WRITE
TO SPDR
BUS
CLOCK
BUS
CLOCK
WRITE
TO SPDR
EARLIEST
BUS
CLOCK
WRITE
TO SPDR
EARLIEST
BUS
CLOCK
WRITE
TO SPDR
EARLIEST
SCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
SCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
SCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
LATEST
SCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
LATEST
N O N - D I S C L O S U R E
EARLIEST LATEST
Figure 18-6. Transmission Start Delay (Master)
MC68HC08AS20 — Rev. 4.1
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Advance Information
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R E Q U I R E D
Two flags signal SPI error conditions:
1. Overflow (OVRFin SPSCR) — Failing to read the SPI data register
before the next byte enters the shift register sets the OVRF bit.
The new byte does not transfer to the receive data register, and
the unread byte still can be read by accessing the SPI data
register. OVRF is in the SPI status and control register.
2. Mode fault error (MODF in SPSCR) — The MODF bit indicates
that the voltage on the slave select pin (SS) is inconsistent with the
mode of the SPI. MODF is in the SPI status and control register.
18.7.1 Overflow Error
The overflow flag (OVRF in SPSCR) becomes set if the SPI receive data
register still has unread data from a previous transmission when the
capture strobe of bit 1 of the next transmission occurs. (See Figure 18-3
and Figure 18-5.) If an overflow occurs, the data being received is not
transferred to the receive data register so that the unread data can still
be read. Therefore, an overflow error always indicates the loss of data.
OVRF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE in SPSCR) is also set. MODF and OVRF can
generate a receiver/error CPU interrupt request. (See Figure 18-9.) It is
not possible to enable only MODF or OVRF to generate a receiver/error
CPU interrupt request. However, leaving MODFEN low prevents MODF
from being set.
N O N - D I S C L O S U R E
A G R E E M E N T
18.7 Error Conditions
If an end-of-block transmission interrupt was meant to pull the MCU out
of wait, having an overflow condition without overflow interrupts enabled
causes the MCU to hang in wait mode. If the OVRF is enabled to
generate an interrupt, it can pull the MCU out of wait mode instead.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not,
watch for an overflow condition. Figure 18-7 shows how it is possible to
miss an overflow.
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
BYTE 3
6
BYTE 4
8
SPRF
OVRF
READ SPSCR
READ SPDR
2
5
3
1
BYTE 1 SETS SPRF BIT.
2
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
BYTE 2 SETS SPRF BIT.
3
4
7
5
6
7
8
CPU READS SPSCRW WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS SET. BYTE 4 IS LOST.
Figure 18-7. Missed Read of Overflow Condition
The first part of Figure 18-7 shows how to read the SPSCR and SPDR
to clear the SPRF without problems. However, as illustrated by the
second transmission example, the OVRF flag can be set in between the
time that SPSCR and SPDR are read.
In this case, an overflow can be easily missed. Since no more SPRF
interrupts can be generated until this OVRF is serviced, it will not be
obvious that bytes are being lost as more transmissions are completed.
To prevent this, either enable the OVRF interrupt or do another read of
the SPSCR after the read of the SPDR. This ensures that the OVRF was
not set before the SPRF was cleared and that future transmissions will
complete with an SPRF interrupt. Figure 18-8 illustrates this process.
Generally, to avoid this second SPSCR read, enable the OVRF to the
CPU by setting the ERRIE bit (SPSCR).
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
285
A G R E E M E N T
BYTE 2
4
N O N - D I S C L O S U R E
BYTE 1
1
R E Q U I R E D
BYTE 1
BYTE 2
BYTE 3
BYTE 4
1
5
7
11
SPI RECEIVE
COMPLETE
SPRF
OVRF
2
READ SPSCR
A G R E E M E N T
6
9
3
READ SPDR
N O N - D I S C L O S U R E
4
1
BYTE 1 SETS SPRF BIT.
2
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
3
8
12
10
14
13
8
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
9
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
10 CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
4
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
11 BYTE 4 SETS SPRF BIT.
5
BYTE 2 SETS SPRF BIT.
12 CPU READS SPSCR.
6
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
13 CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
14 CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
Figure 18-8. Clearing SPRF When OVRF Interrupt Is Not Enabled
18.7.2 Mode Fault Error
For the MODF flag (in SPSCR) to be set, the mode fault error enable bit
(MODFEN in SPSCR) must be set. Clearing the MODFEN bit does not
clear the MODF flag but does prevent MODF from being set again after
MODF is cleared.
MODF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE in SPSCR) is also set. The SPRF, MODF,
and OVRF interrupts share the same CPU interrupt vector. MODF and
OVRF can generate a receiver/error CPU interrupt request. (See Figure
18-9.) It is not possible to enable only MODF or OVRF to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
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•
The SPE bit is cleared.
•
The SPTE bit is set.
•
The SPI state counter is cleared.
•
The data direction register of the shared I/O port regains control of
port drivers.
NOTE:
To prevent bus contention with another master SPI after a mode fault
error, clear all data direction register (DDR) bits associated with the SPI
shared port pins.
NOTE:
Setting the MODF flag (SPSCR) does not clear the SPMSTR bit.
Reading SPMSTR when MODF = 1 will indicate a MODE fault error
occurred in either master mode or slave mode.
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS
goes high during a transmission. When CPHA = 0, a transmission begins
when SS goes low and ends once the incoming SPSCK returns to its idle
level after the shift of the eighth data bit. When CPHA = 1, the
transmission begins when the SPSCK leaves its idle level and SS is
already low. The transmission continues until the SPSCK returns to its
IDLE level after the shift of the last data bit. (See 18.6 Transmission
Formats.)
NOTE:
When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0)
and later unselected (SS is at logic 1) even if no SPSCK is sent to that
slave. This happens because SS at logic 0 indicates the start of the
transmission (MISO driven out with the value of MSB) for CPHA = 0.
When CPHA = 1, a slave can be selected and then later unselected with
no transmission occurring. Therefore, MODF does not occur since a
transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
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R E Q U I R E D
If ERRIE = 1, the SPI generates an SPI receiver/error CPU
interrupt request.
A G R E E M E N T
•
N O N - D I S C L O S U R E
In a master SPI with the mode fault enable bit (MODFEN) set, the mode
fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master
SPI causes the following events to occur:
R E Q U I R E D
NOTE:
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK
clocks, even if a transmission has begun.
To clear the MODF flag, read the SPSCR and then write to the SPCR
register. This entire clearing procedure must occur with no MODF
condition existing or else the flag will not be cleared.
18.8 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt
requests:
Table 18-4. SPI Interrupts
Flag
N O N - D I S C L O S U R E
A G R E E M E N T
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by toggling the SPE bit of the slave.
Request
SPTE (Transmitter Empty)
SPI Transmitter CPU Interrupt Request (SPTIE = 1)
SPRF (Receiver Full)
SPI Receiver CPU Interrupt Request (SPRIE = 1)
OVRF (Overflow)
SPI Receiver/Error Interrupt Request (SPRIE = 1,
ERRIE = 1)
MODF (Mode Fault)
SPI Receiver/Error Interrupt Request (SPRIE = 1,
ERRIE = 1, MODFEN = 1)
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests.
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt, provided that the SPI is enabled
(SPE = 1).
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF flags to generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF flag is enabled to generate
receiver/error CPU interrupt requests.
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SPTIE
R E Q U I R E D
SPTE
SPE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPRIE
SPRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
ERRIE
MODF
Two sources in the SPI status and control register can generate CPU
interrupt requests:
1. SPI receiver full bit (SPRF) — The SPRF bit becomes set every
time a byte transfers from the shift register to the receive data
register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF can generate an SPI receiver/error CPU interrupt request.
2. SPI transmitter empty (SPTE) — The SPTE bit becomes set every
time a byte transfers from the transmit data register to the shift
register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE can generate an SPTE CPU interrupt request.
18.9 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE in SPSCR) indicates
when the transmit data buffer is ready to accept new data. Write to the
SPI data register only when the SPTE bit is high. Figure 18-10 shows
the timing associated with doing back-to-back transmissions with the
SPI (SPSCK has CPHA–CPOL = 1–0).
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N O N - D I S C L O S U R E
Figure 18-9. SPI Interrupt Request Generation
A G R E E M E N T
OVRF
R E Q U I R E D
WRITE TO SPDR
SPTE
1
3
8
5
2
10
SPSCK (CPHA:CPOL = 1:0)
MOSI
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT
6 5 4 3 2 1
6 5 4 3 2 1
6 5 4
BYTE 1
BYTE 2
BYTE 3
A G R E E M E N T
6
READ SPSCR
11
7
READ SPDR
N O N - D I S C L O S U R E
9
4
SPRF
1
CPU WRITES BYTE 1 TO SPDR, CLEARING
SPTE BIT.
2
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
3
CPU WRITES BYTE 2 TO SPDR, QUEUEING
BYTE 2 AND CLEARING SPTE BIT.
4
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
5
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
6
CPU READS SPSCR WITH SPRF BIT SET.
12
7
CPU READS SPDR, CLEARING SPRF BIT.
8
CPU WRITES BYTE 3 TO SPDR, QUEUEING
BYTE 3 AND CLEARING SPTE BIT.
9
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
10 BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
Figure 18-10. SPRF/SPTE CPU Interrupt Timing
The transmit data buffer allows back-to-back transmissions without the
slave precisely timing its writes between transmissions as in a system
with a single data buffer. Also, if no new data is written to the data buffer,
the last value contained in the shift register is the next data word to be
transmitted.
For an idle master or idle slave that has no data loaded into its transmit
buffer, the SPTE is set again no more than two bus cycles after the
transmit buffer empties into the shift register. This allows the user to
queue up a 16-bit value to send. For an already active slave, the load of
the shift register cannot occur until the transmission is completed. This
implies that a back-to-back write to the transmit data register is not
possible. The SPTE indicates when the next write can occur.
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The SPTE flag is set.
•
Any transmission currently in progress is aborted.
•
The shift register is cleared.
•
The SPI state counter is cleared, making it ready for a new
complete transmission.
•
All the SPI port logic is defaulted back to being general-purpose
I/O.
The following additional items are reset only by a system reset:
•
All control bits in the SPCR register
•
All control bits in the SPSCR register (MODFEN, ERRIE, SPR1,
and SPR0)
•
The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE
between transmissions without having to reset all control bits when SPE
is set back to high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still
service these interrupts after the SPI has been disabled. The user can
disable the SPI by writing 0 to the SPE bit. The SPI also can be disabled
by a mode fault occurring in an SPI that was configured as a master with
the MODFEN bit set.
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R E Q U I R E D
•
A G R E E M E N T
Any system reset completely resets the SPI. Partial resets occur
whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the
following occurs:
N O N - D I S C L O S U R E
18.10 Resetting the SPI
The WAIT and STOP instructions put the MCU in low-power standby
modes.
18.11.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction.
In wait mode, the SPI module registers are not accessible by the CPU.
Any enabled CPU interrupt request from the SPI module can bring the
MCU out of wait mode.
A G R E E M E N T
R E Q U I R E D
18.11 Low-Power Modes
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF
bit to generate CPU interrupt requests by setting the error interrupt
enable bit (ERRIE). (See 18.8 Interrupts.)
N O N - D I S C L O S U R E
18.11.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect register conditions. SPI operation
resumes after the MCU exits stop mode. If stop mode is exited by reset,
any transfer in progress is aborted and the SPI is reset.
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To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit
cleared, a write to the data register in break mode will not initiate a
transmission nor will this data be transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared
has no effect.
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R E Q U I R E D
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
A G R E E M E N T
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR, $FE03) enables software to
clear status bits during the break state. (See 9.8.3 SIM Break Flag
Control Register.)
N O N - D I S C L O S U R E
18.12 SPI During Break Interrupts
The SPI module has five I/O pins and shares four of them with a parallel
I/O port.
A G R E E M E N T
R E Q U I R E D
18.13 I/O Signals
•
MISO — Data received
•
MOSI — Data transmitted
•
SPSCK — Serial clock
•
SS — Slave select
•
VSS — Clock ground
The SPI has limited inter-integrated circuit (I2C) capability (requiring
software support) as a master in a single-master environment. To
communicate with I2C peripherals, MOSI becomes an open-drain output
when the SPWOM bit in the SPI control register is set. In I2C
communication, the MOSI and MISO pins are connected to a
bidirectional pin from the I2C peripheral and through a pullup resistor
to VDD.
N O N - D I S C L O S U R E
18.13.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmit serial data. In full
duplex operation, the MISO pin of the master SPI module is connected
to the MISO pin of the slave SPI module. The master SPI simultaneously
receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is
configured as a slave. The SPI is configured as a slave when its
SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a
multiple-slave system, a logic 1 on the SS pin puts the MISO pin in a
high-impedance state.
When enabled, the SPI controls data direction of the MISO pin
regardless of the state of the data direction register of the shared I/O
port.
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When enabled, the SPI controls data direction of the MOSI pin
regardless of the state of the data direction register of the shared I/O
port.
18.13.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and
slave devices. In a master MCU, the SPSCK pin is the clock output. In a
slave MCU, the SPSCK pin is the clock input. In full duplex operation, the
master and slave MCUs exchange a byte of data in eight serial clock
cycles.
N O N - D I S C L O S U R E
When enabled, the SPI controls data direction of the SPSCK pin
regardless of the state of the data direction register of the shared I/O
port.
R E Q U I R E D
MOSI is one of the two SPI module pins that transmit serial data. In full
duplex operation, the MOSI pin of the master SPI module is connected
to the MOSI pin of the slave SPI module. The master SPI simultaneously
transmits data from its MOSI pin and receives data on its MISO pin.
A G R E E M E N T
18.13.2 MOSI (Master Out/Slave In)
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The SS pin has various functions depending on the current state of the
SPI. For an SPI configured as a slave, the SS is used to select a slave.
For CPHA = 0, the SS is used to define the start of a transmission. (See
18.6 Transmission Formats.) Since it is used to indicate the start of a
transmission, the SS must be toggled high and low between each byte
transmitted for the CPHA = 0 format. However, it can remain low
throughout the transmission for the CPHA = 1 format. See Figure 18-11.
A G R E E M E N T
R E Q U I R E D
18.13.4 SS (Slave Select)
MISO/MOSI
BYTE 1
BYTE 2
BYTE 3
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 18-11. CPHA/SS Timing
N O N - D I S C L O S U R E
When an SPI is configured as a slave, the SS pin is always configured
as an input. It cannot be used as a general-purpose I/O regardless of the
state of the MODFEN control bit. However, the MODFEN bit can still
prevent the state of the SS from creating a MODF error. (See 18.14.2
SPI Status and Control Register.)
NOTE:
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK
clocks, even if a transmission already has begun.
When an SPI is configured as a master, the SS input can be used in
conjunction with the MODF flag to prevent multiple masters from driving
MOSI and SPSCK. (See 18.7.2 Mode Fault Error.) For the state of the
SS pin to set the MODF flag, the MODFEN bit in the SPSCK register
must be set. If the MODFEN bit is low for an SPI master, the SS pin can
be used as a general-purpose I/O under the control of the data direction
register of the shared I/O port. With MODFEN high, it is an input-only pin
to the SPI regardless of the state of the data direction register of the
shared I/O port.
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SPE SPMSTR MODFEN
SPI Configuration
State of SS Logic
0
X
X
Not Enabled
General-Purpose I/O;
SS Ignored by SPI
1
0
X
Slave
Input-Only to SPI
1
1
0
Master without MODF
General-Purpose I/O;
SS Ignored by SPI
1
1
1
Master with MODF
Input-Only to SPI
X = don’t care
18.13.5 VSS (Clock Ground)
N O N - D I S C L O S U R E
VSS is the ground return for the serial clock pin, SPSCK, and the ground
for the port output buffers. To reduce the ground return path loop and
minimize radio frequency (RF) emissions, connect the ground pin of the
slave to the VSS pin.
18.14 I/O Registers
Three registers control and monitor SPI operation:
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•
SPI control register (SPCR, $0010)
•
SPI status and control register (SPSCR, $0011)
•
SPI data register (SPDR, $0012)
R E Q U I R E D
Table 18-5. SPI Configuration
A G R E E M E N T
The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the data register.
(See Table 18-5.)
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The SPI control register:
A G R E E M E N T
R E Q U I R E D
18.14.1 SPI Control Register
•
Enables SPI module interrupt requests
•
Selects CPU interrupt requests
•
Configures the SPI module as master or slave
•
Selects serial clock polarity and phase
•
Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
•
Enables the SPI module
Address:
Read:
Write:
Reset:
$0010
Bit 7
6
5
4
3
2
1
Bit 0
SPRIE
R
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
0
0
1
0
1
0
0
0
R
= Reserved
N O N - D I S C L O S U R E
Figure 18-12. SPI Control Register (SPCR)
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
1 = Master mode
0 = Slave mode
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This read/write bit controls the timing relationship between the serial
clock and SPI data. (See Figure 18-3 and Figure 18-5.) To transmit
data between SPI modules, the SPI modules must have identical
CPHA bits. When CPHA = 0, the SS pin of the slave SPI module must
be set to logic 1 between bytes. (See Figure 18-11.) Reset sets the
CPHA bit.
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle
state and begin driving the MISO pin with the MSB of its data. Once
the transmission begins, no new data is allowed into the shift register
from the data register. Therefore, the slave data register must be
loaded with the desired transmit data before the falling edge of SS.
Any data written after the falling edge is stored in the data register and
transferred to the shift register at the current transmission.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the
beginning of the transmission. The same applies when SS is high for
a slave. The MISO pin is held in a high-impedance state, and the
incoming SPSCK is ignored. In certain cases, it may also cause the
MODF flag to be set. (See 18.7.2 Mode Fault Error.) A logic 1 on the
SS pin does not in any way affect the state of the SPI state machine.
SPWOM — SPI Wired-OR Mode Bit
This read/write bit disables the pullup devices on pins SPSCK, MOSI,
and MISO so that those pins become open-drain outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
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R E Q U I R E D
CPHA — Clock Phase Bit
A G R E E M E N T
This read/write bit determines the logic state of the SPSCK pin
between transmissions. (See Figure 18-3 and Figure 18-5.) To
transmit data between SPI modules, the SPI modules must have
identical CPOL bits. Reset clears the CPOL bit.
N O N - D I S C L O S U R E
CPOL — Clock Polarity Bit
R E Q U I R E D
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI. (See 18.10 Resetting the SPI.) Reset clears
the SPE bit.
1 = SPI module enabled
0 = SPI module disabled
SPTIE— SPI Transmit Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
18.14.2 SPI Status and Control Register
The SPI status and control register contains flags to signal the following
conditions:
N O N - D I S C L O S U R E
A G R E E M E N T
SPE — SPI Enable Bit
•
Receive data register full
•
Failure to clear SPRF bit before next byte is received (overflow
error)
•
Inconsistent logic level on SS pin (mode fault error)
•
Transmit data register empty
The SPI status and control register also contains bits that perform these
functions:
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•
Enable error interrupts
•
Enable mode fault error detection
•
Select master SPI baud rate
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Read:
SPRF
Write:
Reset:
0
6
ERRIE
0
5
4
3
OVRF
MODF
SPTE
0
0
1
2
1
Bit 0
MODFEN
SPR1
SPR0
0
0
0
= Unimplemented
Figure 18-13. SPI Status and Control Register (SPSCR)
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the
SPI status and control register with SPRF set and then reading the
SPI data register. Any read of the SPI data register clears the SPRF
bit.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable Bit
This read-only bit enables the MODF and OVRF flags to generate
CPU interrupt requests. Reset clears the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte
in the receive data register before the next byte enters the shift
register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the
OVRF bit by reading the SPI status and control register with OVRF set
and then reading the SPI data register. Reset clears the OVRF flag.
1 = Overflow
0 = No overflow
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R E Q U I R E D
Bit 7
A G R E E M E N T
$0011
N O N - D I S C L O S U R E
Address:
R E Q U I R E D
MODF — Mode Fault Bit
This clearable, ready-only flag is set in a slave SPI if the SS pin goes
high during a transmission. In a master SPI, the MODF flag is set if
the SS pin goes low at any time. Clear the MODF bit by reading the
SPI status and control register with MODF set and then writing to the
SPI data register. Reset clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
A G R E E M E N T
SPTE — SPI Transmitter Empty Bit
This clearable, read-only flag is set each time the transmit data
register transfers a byte into the shift register. SPTE generates an
SPTE CPU interrupt request if the SPTIE bit in the SPI control register
is set also.
NOTE:
Do not write to the SPI data register unless the SPTE bit is high.
N O N - D I S C L O S U R E
For an idle master or idle slave that has no data loaded into its
transmit buffer, the SPTE will be set again within two bus cycles since
the transmit buffer empties into the shift register. This allows the user
to queue up a 16-bit value to send. For an already active slave, the
load of the shift register cannot occur until the transmission is
completed. This implies that a back-to-back write to the transmit data
register is not possible. The SPTE indicates when the next write can
occur.
Reset sets the SPTE bit.
1 = Transmit data register empty
0 = Transmit data register not empty
MODFEN — Mode Fault Enable Bit
This read/write bit, when set to 1, allows the MODF flag to be set. If
the MODF flag is set, clearing the MODFEN does not clear the MODF
flag. If the SPI is enabled as a master and the MODFEN bit is low,
then the SS pin is available as a general-purpose I/O.
If the MODFEN bit is set, then this pin is not available as a
general-purpose I/O. When the SPI is enabled as a slave, the SS pin
is not available as a general-purpose I/O regardless of the value of
MODFEN. (See 18.13.4 SS (Slave Select).)
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SPR1 and SPR0 — SPI Baud Rate Select Bits
Table 18-6. SPI Master Baud Rate Selection
SPR1:SPR0
Baud Rate Divisor (BD)
00
2
01
8
10
32
11
128
Use the following formula to calculate the SPI baud rate:
CGMOUT
Bus clock
Baud rate = -------------------------- = ------------------------2 × BD
BD
where:
CGMOUT = base clock output of the clock generator module (CGM),
see Section 8. Clock Generator Module (CGM).
BD = baud rate divisor
MC68HC08AS20 — Rev. 4.1
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N O N - D I S C L O S U R E
A G R E E M E N T
In master mode, these read/write bits select one of four baud rates as
shown in Table 18-6. SPR1 and SPR0 have no effect in slave mode.
Reset clears SPR1 and SPR0.
R E Q U I R E D
If the MODFEN bit is low, the level of the SS pin does not affect the
operation of an enabled SPI configured as a master. For an enabled
SPI configured as a slave, having MODFEN low only prevents the
MODF flag from being set. It does not affect any other part of SPI
operation. (See 18.7.2 Mode Fault Error.)
The SPI data register is the read/write buffer for the receive data register
and the transmit data register. Writing to the SPI data register writes data
into the transmit data register. Reading the SPI data register reads data
from the receive data register. The transmit data and receive data
registers are separate buffers that can contain different values. See
Figure 18-1.
Address:
A G R E E M E N T
R E Q U I R E D
18.14.3 SPI Data Register
$0012
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Indeterminate after Reset
Figure 18-14. SPI Data Register (SPDR)
R7–R0/T7–T0 — Receive/Transmit Data Bits
Do not use read-modify-write instructions on the SPI data register since
the buffer read is not the same as the buffer written.
N O N - D I S C L O S U R E
NOTE:
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19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
19.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
19.4.1
ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
19.4.2
Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
19.4.3
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
19.4.4
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .309
19.4.5
Accuracy and Precision. . . . . . . . . . . . . . . . . . . . . . . . . . .309
19.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
19.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
19.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
19.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
19.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
19.7.1
ADC Analog Power Pin (VDDA/VDDAREF)/ADC
Voltage Reference Pin (VREFH) . . . . . . . . . . . . . . . . . . 310
19.7.2
ADC Analog Ground Pin (VSSA)/ADC
Voltage Reference Low Pin (VREFL). . . . . . . . . . . . . . . 310
19.7.3
ADC Voltage In (ADCVIN). . . . . . . . . . . . . . . . . . . . . . . . . 311
19.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
19.8.1
ADC Status and Control Register . . . . . . . . . . . . . . . . . . . 311
19.8.2
ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
19.8.3
ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 314
MC68HC08AS20 — Rev. 4.1
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Advance Information
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R E Q U I R E D
19.1 Contents
A G R E E M E N T
Section 19. Analog-to-Digital Converter (ADC)
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
R E Q U I R E D
This section describes the analog-to-digital converter (ADC). The ADC
is an 8-bit analog-to-digital converter.
19.3 Features
Features of the ADC module include:
•
15 Channels (52-PLCC) with Multiplexed Input
•
Linear Successive Approximation
•
8-Bit Resolution
•
Single or Continuous Conversion
•
Conversion Complete Flag or Conversion Complete Interrupt
•
Selectable ADC Clock
19.4 Functional Description
Fifteen ADC channels are available for sampling external sources at
pins PTD6/ATD14/TCLK–PTD0/ATD8 and PTB7/ATD7–PTB0/ATD0.
An analog multiplexer allows the single ADC converter to select one of
the 15 ADC channels as ADC voltage input (ADCVIN). ADCVIN is
converted by the successive approximation register-based counters.
When the conversion is completed, ADC places the result in the ADC
data register and sets a flag or generates an interrupt.
(See Figure 19-1.)
N O N - D I S C L O S U R E
A G R E E M E N T
19.2 Introduction
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R E Q U I R E D
INTERNAL
DATA BUS
READ DDRB/DDRB
RESET
WRITE PTB/PTD
DISABLE
DDRBx/DDRDx
PTBx/PTDx
PTBx/PTDx
ADC CHANNEL x
READ PTB/PTD
A G R E E M E N T
DISABLE
ADC DATA REGISTER
INTERRUPT
LOGIC
AIEN
CONVERSION
COMPLETE
ADC VOLTAGE IN
ADCVIN
ADC
CHANNEL
SELECT
ADCH[4:0]
COCO
ADC CLOCK
CGMXCLK
BUS CLOCK
CLOCK
GENERATOR
ADIV[2:0]
ADICLK
Figure 19-1. ADC Block Diagram
19.4.1 ADC Port I/O Pins
PTD6/ATD14/TCLK–PTD0/ATD8 and PTB7/ATD7–PTB0/ATD0 are
general-purpose I/O pins that are shared with the ADC channels.
The channel select bits (ADC status control register, $0038), define
which ADC channel/port pin will be used as the input signal. The ADC
overrides the port I/O logic by forcing that pin as input to the ADC. The
remaining ADC channels/port pins are controlled by the port I/O logic
and can be used as general-purpose I/O. Writes to the port register or
DDR will not have any affect on the port pin that is selected by the ADC.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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N O N - D I S C L O S U R E
WRITE DDRB/DDRD
R E Q U I R E D
NOTE:
Do not use ADC channel ATD14 when using the PTD6/ATD14/TCLK pin
as the clock input for the TIM.
19.4.2 Voltage Conversion
When the input voltage to the ADC equals VREFH (see 21.7 ADC
Characteristics), the ADC converts the signal to $FF (full scale). If the
input voltage equals VSSA/VREFL, the ADC converts it to $00. Input
voltages between VREFH and VSSA/VREFL are a straight-line linear
conversion. All other input voltages will result in $FF if greater than
VREFH and $00 if less than VSSA/VREFL.
NOTE:
Input voltage should not exceed the analog supply voltages.
19.4.3 Conversion Time
Sixteen ADC internal clocks are required to perform one conversion. The
ADC starts a conversion on the first rising edge of the ADC internal clock
immediately following a write to the ADSCR. If the ADC internal clock is
selected to run at 1 MHz, then one conversion will take 16 µs to
complete. But since the ADC can run almost completely asynchronously
to the bus clock, (for example, the ADC is configured to derive its internal
clock from CGMXCLK and the bus clock is being derived from the PLL
within the CGM [CGMOUT]), this 16 µs conversion can take up to 17 µs
to complete. This worst-case could occur if the write to the ADSCR
happened directly after the rising edge of the ADC internal clock causing
the conversion to wait until the next rising edge of the ADC internal clock.
With a 1 MHz ADC internal clock the maximum sample rate is 59 kHz to
62 kHz. Refer to 21.7 ADC Characteristics.
N O N - D I S C L O S U R E
A G R E E M E N T
Read of a port pin which is in use by the ADC will return a logic 0 if the
corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value
in the port data latch is read.
16 to 17 ADC Clock Cycles
Conversion Time = 
ADC Clock Frequency
Number of Bus Cycles = Conversion Time x Bus Frequency
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19.4.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes. See
21.7 ADC Characteristics for accuracy information.
19.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. A CPU interrupt is generated
if the COCO bit is at logic 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.
19.6 Low-Power Modes
The following subsections describe the low-power modes.
19.6.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting the ADCH[4–0] bits in the ADC status
and control register to logic 1s before executing the WAIT instruction.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
309
R E Q U I R E D
A G R E E M E N T
In the continuous conversion mode, the ADC continuously converts the
selected channel filling the ADC data register with new data after each
conversion. Data from the previous conversion will be overwritten
whether that data has been read or not. Conversions will continue until
the ADCO bit is cleared. The COCO bit (ADC status control register,
$0038) is set after each conversion and can be cleared by writing the
ADC status and control register or reading of the ADC data register.
N O N - D I S C L O S U R E
19.4.4 Continuous Conversion
R E Q U I R E D
19.6.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode. Allow one conversion cycle to stabilize the analog
circuitry before attempting a new ADC conversion after exiting stop
mode.
N O N - D I S C L O S U R E
A G R E E M E N T
19.7 I/O Signals
The ADC module has 15 channels that are shared with I/O ports B and
D and one channel with an input-only port bit on port D. Refer to 21.7
ADC Characteristics for voltages referenced in the next three
subsections.
19.7.1 ADC Analog Power Pin (VDDA/VDDAREF)/ADC Voltage Reference Pin (VREFH)
The ADC analog portion uses VDDA/VDDAREF as its power pin. Connect
the VDDA/VDDAREF pin to the same voltage potential as VDD. External
filtering may be necessary to ensure clean VDDA/VDDAREF for good
results.
VREFH is the high reference voltage for all analog-to-digital conversions.
Connect the VREFH pin to a voltage potential between 1.5 volts and
VDDAREF/VDDA depending on the desired upper conversion boundary.
NOTE:
Route VDDA/VDDAREF carefully for maximum noise immunity and place
bypass capacitors as close as possible to the package.
19.7.2 ADC Analog Ground Pin (VSSA)/ADC Voltage Reference Low Pin (VREFL)
The ADC analog portion uses VSSA as its ground pin. Connect the VSSA
pin to the same voltage potential as VSS.
VREFL is the lower reference supply for the ADC. Connect the VREFL pin
to a voltage potential between VSSA and 0.5 volts depending on the
desired lower conversion boundary.
Advance Information
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These I/O registers control and monitor ADC operation:
•
ADC status and control register (ADSCR)
•
ADC data register (ADR)
•
ADC clock register (ADICLK)
19.8.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and
control register.
Address:
$0038
Bit 7
Read:
COCO
Write:
R
Reset:
0
R
6
5
4
3
2
1
Bit 0
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
0
1
1
1
1
1
= Reserved
Figure 19-2. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
the ADC status and control register is written or whenever the ADC
data register is read. Reset clears this bit.
1 = conversion completed (AIEN = 0)
0 = conversion not completed (AIEN = 0)
or
0 = CPU interrupt enabled (AIEN = 1)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
311
R E Q U I R E D
19.8 I/O Registers
A G R E E M E N T
ADCVIN is the input voltage signal from one of the 15 ADC channels to
the ADC module.
N O N - D I S C L O S U R E
19.7.3 ADC Voltage In (ADCVIN)
R E Q U I R E D
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
A G R E E M E N T
When set, the ADC will convert samples continuously and update the
ADR register at the end of each conversion. Only one conversion is
allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field
which is used to select one of the ADC channels. The five channel
select bits are detailed in the following table. Care should be taken
when using a port pin as both an analog and a digital input
simultaneously to prevent switching noise from corrupting the analog
signal. (See Table 19-1.)
N O N - D I S C L O S U R E
The ADC subsystem is turned off when the channel select bits are all
set to one. This feature allows for reduced power consumption for the
MCU when the ADC is not used. Reset sets all of these bits to a
logic 1.
NOTE:
Advance Information
312
Recovery from the disabled state requires one conversion cycle to
stabilize.
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
0
0
0
0
0
PTB0/ATD0
0
0
0
0
1
PTB1/ATD1
0
0
0
1
0
PTB2/ATD2
0
0
0
1
1
PTB3/ATD3
0
0
1
0
0
PTB4/ATD4
0
0
1
0
1
PTB5/ATD5
0
0
1
1
0
PTB6/ATD6
0
0
1
1
1
PTB7/ATD7
0
1
0
0
0
PTD0/ATD8
0
1
0
0
1
PTD1/ATD9
0
1
0
1
0
PTD2/ATD10
0
1
0
1
1
PTD3/ATD11
0
1
1
0
0
PTD4/ATD12
0
1
1
0
1
PTD5/ATD13
0
1
1
1
0
PTD6/ATD14/TCLK
Range 01111 ($0F) to 11010 ($1A)
Unused (see Note 1)
1
1
0
1
1
Reserved
1
1
1
0
0
VDDAREF/VDDA
(see Note 2)
1
1
1
0
1
VREFH
(see Note 2)
1
1
1
1
0
VSSA/VREFL (see Note 2)
1
1
1
1
1
ADC power off
NOTES:
1. If any unused channels are selected, the resulting ADC conversion will be
unknown.
2. The voltage levels supplied from internal reference nodes as specified in the
table are used to verify the operation of the ADC converter both in production
test and for user applications.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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A G R E E M E N T
ADCH4
N O N - D I S C L O S U R E
Table 19-1. Mux Channel Select
R E Q U I R E D
One 8-bit result register is provided. This register is updated each time
an ADC conversion completes.
Address:
Read:
$0039
Bit 7
6
5
4
3
2
1
Bit 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Indeterminate after Reset
= Unimplemented
Figure 19-3. ADC Data Register (ADR)
19.8.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address:
N O N - D I S C L O S U R E
A G R E E M E N T
19.8.2 ADC Data Register
Read:
Write:
Reset:
$003A
Bit 7
6
5
4
ADIV2
ADIV1
ADIV0
ADICLK
0
0
0
0
3
2
1
Bit 0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 19-4. ADC Input Clock Register (ADICLK)
ADIV2:ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 19-2
shows the available clock configurations. The ADC clock should be
set to approximately 1 MHz.
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
Table 19-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
0
0
0
ADC Input Clock / 1
0
0
1
ADC Input Clock / 2
0
1
0
ADC Input Clock / 4
0
1
1
ADC Input Clock / 8
1
X
X
ADC Input Clock / 16
ADICLK selects either bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz,
CGMXCLK can be used as the clock source for the ADC. If
CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as
the clock source. As long as the internal ADC clock is at
approximately 1 MHz, correct operation can be guaranteed. (See
21.7 ADC Characteristics.)
1 = Internal bus clock
0 = External clock (CGMXCLK)
fXCLK or Bus Frequency
1 MHz = 
ADIV[2:0]
NOTE:
During the conversion process, changing the ADC clock will result in an
incorrect conversion.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
315
N O N - D I S C L O S U R E
ADICLK — ADC Input Clock Register Bit
A G R E E M E N T
X = don’t care
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
20.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
20.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
20.4.1
BDLC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 322
20.4.1.1
Power Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
20.4.1.2
Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
20.4.1.3
Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
20.4.1.4
BDLC Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
20.4.1.5
BDLC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
20.4.1.6
Digital Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . 324
20.4.1.7
Analog Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . 324
20.5 BDLC MUX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
20.5.1
Rx Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
20.5.1.1
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
20.5.1.2
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
20.5.2
J1850 Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
20.5.3
J1850 VPW Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
20.5.4
J1850 VPW Valid/Invalid Bits and Symbols . . . . . . . . . . . 334
20.5.5
Message Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
20.6 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
20.6.1
Protocol Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
20.6.2
Rx and Tx Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . 341
20.6.3
Rx and Tx Shadow Registers . . . . . . . . . . . . . . . . . . . . . . 342
20.6.4
Digital Loopback Multiplexer . . . . . . . . . . . . . . . . . . . . . . . 342
20.6.5
State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
20.6.5.1
4X Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
20.6.5.2
Receiving a Message in Block Mode . . . . . . . . . . . . . . . 343
20.6.5.3
Transmitting a Message in Block Mode . . . . . . . . . . . . . 343
20.6.5.4
J1850 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
317
R E Q U I R E D
20.1 Contents
A G R E E M E N T
Section 20. Byte Data Link Controller–Digital (BDLC–D)
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
R E Q U I R E D
20.6.5.5
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
20.7 BDLC CPU Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
20.7.1
BDLC Analog and Roundtrip Delay. . . . . . . . . . . . . . . . . . 346
20.7.2
BDLC Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . 348
20.7.3
BDLC Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . 351
20.7.4
BDLC State Vector Register . . . . . . . . . . . . . . . . . . . . . . .358
20.7.5
BDLC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
N O N - D I S C L O S U R E
A G R E E M E N T
20.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
20.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
20.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
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Freescale Semiconductor
The byte data link controller (BDLC) provides access to an external
serial communication multiplex bus, operating according to the SAE
J1850 protocol.
20.3 Features
R E Q U I R E D
20.2 Introduction
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
SAE J1850 Class B Data Communications Network Interface
Compatible and ISO Compatible for Low-Speed (<125 kbps)
Serial Data Communications in Automotive Applications
•
10.4 kbps Variable Pulse Width (VPW) Bit Format
•
Digital Noise Filter
•
Collision Detection
•
Hardware Cyclical Redundancy Check (CRC) Generation and
Checking
•
Two Power-Saving Modes with Automatic Wakeup on Network
Activity
•
Polling or CPU Interrupts
•
Block Mode Receive and Transmit Supported
•
4X Receive Mode, 41.6 kbps, Supported
•
Digital Loopback Mode
•
Analog Loopback Mode
•
In-Frame Response (IFR) Types 0, 1, 2, and 3 Supported
N O N - D I S C L O S U R E
•
A G R E E M E N T
Features of the BDLC module include:
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Figure 20-1 shows the organization of the BDLC module. The CPU
interface contains the software addressable registers and provides the
link between the CPU and the buffers. The buffers provide storage for
data received and data to be transmitted onto the J1850 bus. The
protocol handler is responsible for the encoding and decoding of data
bits and special message symbols during transmission and reception.
The MUX interface provides the link between the BDLC digital section
and the analog physical interface. The wave shaping, driving, and
digitizing of data is performed by the physical interface.
A G R E E M E N T
R E Q U I R E D
20.4 Functional Description
Use of the BDLC module in message networking fully implements the
SAE Standard J1850 Class B Data Communication Network Interface
specification.
NOTE:
It is recommended that the reader be familiar with the SAE J1850
document and ISO Serial Communication document prior to proceeding
with this section of the MC68HC08AS20 specification.
N O N - D I S C L O S U R E
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 20-1. BDLC Block Diagram
.
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Freescale Semiconductor
BDLC Analog and Roundtrip Read:
Delay Register (BARD) Write:
Reset:
$003C
BDLC Control Register 1 Read:
(BCR1) Write:
Reset:
$003D
$003E
$003F
Bit 7
6
5
4
ATE
RXPOL
1
0
0
1
0
0
IMSG
CLKS
R1
R0
1
1
1
DLOOP
BDLC Control Register 2 Read:
ALOOP
(BCR2) Write:
3
2
1
Bit 0
BO3
BO2
BO1
BO0
0
1
1
1
0
0
R
R
IE
WCM
0
0
0
0
0
RX4XE
NBFS
TEOD
TSIFR
TMIFR1
TMIFR0
Reset:
1
1
0
0
0
0
0
0
BDLC State Vector Register Read:
(BSVR) Write:
0
0
I3
I2
I1
I0
0
0
Reset:
0
0
0
0
0
0
0
0
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
BDLC Data Register (BDR)
Read:
Write:
Reset:
Indeterminate after Reset
= Unimplemented
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R
R E Q U I R E D
$003B
Name
N O N - D I S C L O S U R E
Addr.
A G R E E M E N T
Table 20-1. BDLC Input/Output (I/O) Register Summary
= Reserved
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R E Q U I R E D
20.4.1 BDLC Operating Modes
The BDLC has five main modes of operation which interact with the
power supplies, pins, and rest of the MCU as shown in Figure 20-2.
POWER OFF
VDD > VDD (MINIMUM) AND
ANY MCU RESET SOURCE ASSERTED
N O N - D I S C L O S U R E
A G R E E M E N T
VDD ≤ VDD (MINIMUM)
RESET
ANY MCU RESET SOURCE ASSERTED
FROM ANY MODE
(COP, ILLADDR, PU, RESET, LVR, POR)
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
RUN
BDLC STOP
NO MCU RESET SOURCE ASSERTED
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
BDLC WAIT
STOP INSTRUCTION OR
WAIT INSTRUCTION AND WCM = 1
WAIT INSTRUCTION AND WCM = 0
Figure 20-2. BDLC Operating Modes State Diagram
20.4.1.1 Power Off Mode
For the BDLC to guarantee operation, this mode is entered from reset
mode whenever the BDLC supply voltage, VDD, drops below its
minimum specified value. The BDLC will be placed in reset mode by
low-voltage reset (LVR) before being powered down. In power off mode,
the pin input and output specifications are not guaranteed.
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In reset mode, the internal BDLC voltage references are operative, VDD
is supplied to the internal circuits which are held in their reset state, and
the internal BDLC system clock is running. Registers will assume their
reset condition. Because outputs are held in their programmed reset
state, inputs and network activity are ignored.
20.4.1.3 Run Mode
This mode is entered from reset mode after all MCU reset sources are
no longer asserted. Run mode is entered from the BDLC wait mode
whenever activity is sensed on the J1850 bus.
Run mode is entered from the BDLC stop mode whenever network
activity is sensed, although messages will not be received properly until
the clocks have stabilized and the CPU is also in run mode.
In this mode, normal network operation takes place. The user should
ensure that all BDLC transmissions have ceased before exiting this
mode.
20.4.1.4 BDLC Wait Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a WAIT instruction and if the WCM bit in the
BCR1 register is cleared previously.
In this mode, the BDLC internal clocks continue to run. The first
passive-to-active transition of the bus generates a CPU interrupt request
from the BDLC, which wakes up the BDLC and the CPU. In addition, if
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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R E Q U I R E D
A G R E E M E N T
This mode is entered from power off mode whenever the BDLC supply
voltage, VDD, rises above its minimum specified value
(VDD –10%) and some MCU reset source is asserted. The internal MCU
reset must be asserted while powering up the BDLC or an unknown state
will be entered and correct operation cannot be guaranteed. Reset mode
is also entered from any other mode as soon as one of the MCU’s
possible reset sources (such as LVR, POR, COP watchdog, reset pin,
etc.) is asserted.
N O N - D I S C L O S U R E
20.4.1.2 Reset Mode
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
the BDLC receives a valid end-of-frame (EOF) symbol while operating in
wait mode, then the BDLC also will generate a CPU interrupt request,
which wakes up the BDLC and the CPU. See 20.8.1 Wait Mode.
20.4.1.5 BDLC Stop Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a STOP instruction or if the CPU executes
a WAIT instruction and the WCM bit in the BCR1 is set previously.
In this mode, the BDLC internal clocks are stopped but the physical
interface circuitry is placed in a low-power mode and awaits network
activity. If network activity is sensed, then a CPU interrupt request will be
generated, restarting the BDLC internal clocks. See 20.8.2 Stop Mode.
20.4.1.6 Digital Loopback Mode
When a bus fault has been detected, the digital loopback mode is used
to determine if the fault condition is caused by failure in the node’s
internal circuits or elsewhere in the network, including the node’s analog
physical interface. In this mode, the transmit digital output pin (BDTxD)
and the receive digital input pin (BDRxD) of the digital interface are
disconnected from the analog physical interface and tied together to
allow the digital portion of the BDLC to transmit and receive its own
messages without driving the J1850 bus.
20.4.1.7 Analog Loopback Mode
Analog loopback mode is used to determine if a bus fault has been
caused by a failure in the node’s off-chip analog transceiver or
elsewhere in the network. The BDLC analog loopback mode does not
modify the digital transmit or receive functions of the BDLC. It does,
however, ensure that once analog loopback mode is exited, the BDLC
will wait for an idle bus condition before participation in network
communication resumes. If the off-chip analog transceiver has a
loopback mode, it usually causes the input to the output drive stage to
be looped back into the receiver, allowing the node to receive messages
it has transmitted without driving the J1850 bus. In this mode, the output
to the J1850 bus typically is high impedance. This allows the
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The MUX interface is responsible for bit encoding/decoding and digital
noise filtering between the protocol handler and the physical interface.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
R E Q U I R E D
20.5 BDLC MUX Interface
A G R E E M E N T
communication path through the analog transceiver to be tested without
interfering with network activity. Using the BDLC analog loopback mode
in conjunction with the analog transceiver’s loopback mode ensures that,
once the off-chip analog transceiver has exited loopback mode, the
BCLD will not begin communicating before a known condition exists on
the J1850 bus.
PHYSICAL INTERFACE
N O N - D I S C L O S U R E
BDLC
TO J1850 BUS
Figure 20-3. BDLC Block Diagram
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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R E Q U I R E D
The receiver section of the BDLC includes a digital low pass filter to
remove narrow noise pulses from the incoming message. An outline of
the digital filter is shown in Figure 20-4.
RX DATA
FROM
PHYSICAL
INTERFACE
(BDRxD)
INPUT
SYNC
D
Q
4-BIT UP/DOWN COUNTER
UP/DOWN
OUT
DATA
LATCH
D
Q
FILTERED
RX DATA OUT
MUX
INTERFACE
CLOCK
Figure 20-4. BDLC Rx Digital Filter Block Diagram
20.5.1.1 Operation
The clock for the digital filter is provided by the MUX interface clock (see
fBDLC parameter in Table 20-4). At each positive edge of the clock
signal, the current state of the receiver physical interface (BDRxD) signal
is sampled. The BDRxD signal state is used to determine whether the
counter should increment or decrement at the next negative edge of the
clock signal.
N O N - D I S C L O S U R E
A G R E E M E N T
20.5.1 Rx Digital Filter
The counter will increment if the input data sample is high but decrement
if the input sample is low. Therefore, the counter will thus progress either
up toward 15 if, on average, the BDRxD signal remains high or progress
down toward 0 if, on average, the BDRxD signal remains low.
When the counter eventually reaches the value 15, the digital filter
decides that the condition of the BDRxD signal is at a stable logic level
1 and the data latch is set, causing the filtered Rx data signal to become
a logic level 1. Furthermore, the counter is prevented from overflowing
and can be decremented only from this state.
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The data latch will retain its value until the counter next reaches the
opposite end point, signifying a definite transition of the signal.
R E Q U I R E D
Alternatively, should the counter eventually reach the value 0, the digital
filter decides that the condition of the BDRxD signal is at a stable logic
level 0 and the data latch is reset, causing the filtered Rx data signal to
become a logic level 0. Furthermore, the counter is prevented from
underflowing and can only be incremented from this state.
If the signal on the BDRxD signal transitions, then there will be a delay
before that transition appears at the filtered Rx data output signal. This
delay will be between 15 and 16 clock periods, depending on where the
transition occurs with respect to the sampling points. This filter delay
must be taken into account when performing message arbitration.
For example, if the frequency of the MUX interface clock (fBDLC) is
1.0486 MHz, then the period (tBDLC) is 954 ns and the maximum filter
delay in the absence of noise will be 15.259 µs.
The effect of random noise on the BDRxD signal depends on the
characteristics of the noise itself. Narrow noise pulses on the BDRxD
signal will be ignored completely if they are shorter than the filter delay.
This provides a degree of low pass filtering.
If noise occurs during a symbol transition, the detection of that transition
can be delayed by an amount equal to the length of the noise burst. This
is just a reflection of the uncertainty of where the transition is truly
occurring within the noise.
Noise pulses that are wider than the filter delay, but narrower than the
shortest allowable symbol length, will be detected by the next stage of
the BDLC’s receiver as an invalid symbol.
Noise pulses that are longer than the shortest allowable symbol length
will be detected normally as an invalid symbol or as invalid data when
the frame’s CRC is checked.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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N O N - D I S C L O S U R E
The performance of the digital filter is best described in the time domain
rather than the frequency domain.
A G R E E M E N T
20.5.1.2 Performance
All messages transmitted on the J1850 bus are structured using the
format shown in Figure 20-5.
J1850 states that each message has a maximum length of 101 PWM bit
times or 12 VPW bytes, excluding SOF, EOD, NB, and EOF, with each
byte transmitted most significant bit (MSB) first.
All VPW symbol lengths in the following descriptions are typical values
at a 10.4-kbps bit rate.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
20.5.2 J1850 Frame Format
SOF — Start-of-Frame Symbol
All messages transmitted onto the J1850 bus must begin with a
long-active 200 µs period SOF symbol. This indicates the start of a
new message transmission. The SOF symbol is not used in the CRC
calculation.
Data — In-Message Data Bytes
The data bytes contained in the message include the message
priority/type, message ID byte (typically the physical address of the
responder), and any actual data being transmitted to the receiving
node. The message format used by the BDLC is similar to the 3-byte
consolidated header message format outlined by the SAE J1850
document. See SAE J1850 Class B Data Communications Network
Interface for more information about 1- and 3-byte headers.
Messages transmitted by the BDLC onto the J1850 bus must contain
at least one data byte, and, therefore, can be as short as one data
byte and one CRC byte. Each data byte in the message is eight bits
in length and is transmitted MSB to LSB (least significant bit).
DATA
IDLE
SOF
PRIORITY
(DATA0)
MESSAGE ID
(DATA1)
DATAN
CRC
E
O
D
OPTIONAL
N
B
IFR
EOF
I
F
S
IDLE
Figure 20-5. J1850 Bus Message Format (VPW)
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CRC generation uses the divisor polynomial X8 + X4 + X3 + X2 + 1.
The remainder polynomial initially is set to all ones. Each byte in the
message after the start-of-frame (SOF) symbol is processed serially
through the CRC generation circuitry. The one’s complement of the
remainder then becomes the 8-bit CRC byte, which is appended to
the message after the data bytes, in MSB-to-LSB order.
When receiving a message, the BDLC uses the same divisor
polynomial. All data bytes, excluding the SOF and end of data
symbols (EOD) but including the CRC byte, are used to check the
CRC. If the message is error free, the remainder polynomial will equal
X7 + X6 + X2 = $C4, regardless of the data contained in the message.
If the calculated CRC does not equal $C4, the BDLC will recognize
this as a CRC error and set the CRC error flag in the BSVR.
R E Q U I R E D
This byte is used by the receiver(s) of each message to determine if
any errors have occurred during the transmission of the message.
The BDLC calculates the CRC byte and appends it onto any
messages transmitted onto the J1850 bus. It also performs CRC
detection on any messages it receives from the J1850 bus.
A G R E E M E N T
CRC — Cyclical Redundancy Check Byte
The EOD symbol is a long 200-µs passive period on the J1850 bus
used to signify to any recipients of a message that the transmission
by the originator has completed. No flag is set upon reception of the
EOD symbol.
IFR — In-Frame Response Bytes
The IFR section of the J1850 message format is optional. Users
desiring further definition of in-frame response should review the SAE
J1850 Class B Data Communications Network Interface specification.
EOF — End-of-Frame Symbol
This symbol is a long 280-µs passive period on the J1850 bus and is
longer than an end-of-data (EOD) symbol, which signifies the end of
a message. Since an EOF symbol is longer than a 200-µs EOD
MC68HC08AS20 — Rev. 4.1
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N O N - D I S C L O S U R E
EOD — End-of-Data Symbol
R E Q U I R E D
symbol, if no response is transmitted after an EOD symbol, it
becomes an EOF, and the message is assumed to be completed. The
EOF flag is set upon receiving the EOF symbol.
IFS — Inter-Frame Separation Symbol
A G R E E M E N T
The IFS symbol is a 20-µs passive period on the J1850 bus which
allows proper synchronization between nodes during continuous
message transmission. The IFS symbol is transmitted by a node after
the completion of the end-of-frame (EOF) period and, therefore is
seen as a 300-µs passive period.
When the last byte of a message has been transmitted onto the J1850
bus and the EOF symbol time has expired, all nodes then must wait
for the IFS symbol time to expire before transmitting a start-of-frame
(SOF) symbol, marking the beginning of another message.
However, if the BDLC is waiting for the IFS period to expire before
beginning a transmission and a rising edge is detected before the IFS
time has expired, it will synchronize internally to that edge.
N O N - D I S C L O S U R E
A rising edge may occur during the IFS period because of varying
clock tolerances and loading of the J1850 bus, causing different
nodes to observe the completion of the IFS period at different times.
To allow for individual clock tolerances, receivers must synchronize to
any SOF occurring during an IFS period.
BREAK — Break
The BDLC cannot transmit a BREAK symbol.
If the BDLC is transmitting at the time a BREAK is detected, it treats
the BREAK as if a transmission error had occurred and halts
transmission.
If the BDLC detects a BREAK symbol while receiving a message, it
treats the BREAK as a reception error and sets the invalid symbol flag
in the BSVR, also ignoring the frame it was receiving. If while
receiving a message in 4X mode, the BDLC detects a BREAK
symbol, it treats the BREAK as a reception error, sets the invalid
symbol flag, and exits 4X mode (for example, the RX4XE bit in BCR2
is cleared automatically). If bus control is required after the BREAK
symbol is received and the IFS time has elapsed, the programmer
must resend the transmission byte using highest priority.
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Freescale Semiconductor
The J1850 protocol BREAK symbol is not related to the HC08 Break
Module (See Section 11. Break Module (Break).)
IDLE — Idle Bus
An idle condition exists on the bus during any passive period after
expiration of the IFS period (for example, > 300 µs). Any node sensing
an idle bus condition can begin transmission immediately.
R E Q U I R E D
NOTE:
Each logic 1 or logic 0 contains a single transition and can be at either
the active or passive level and one of two lengths, either 64 µs or 128 µs
(tNOM at 10.4 kbps baud rate), depending upon the encoding of the
previous bit. The start-of-frame (SOF), end-of-data (EOD), end-of-frame
(EOF), and inter-frame separation (IFS) symbols always will be encoded
at an assigned level and length. See Figure 20-6.
Each message will begin with an SOF symbol, an active symbol, and,
therefore, each data byte (including the CRC byte) will begin with a
passive bit, regardless of whether it is a logic 1 or a logic 0.
All VPW bit lengths stated in the following descriptions are typical values
at a 10.4-kbps bit rate. EOF, EOD, IFS, and IDLE, however, are not
driven J1850 bus states. They are passive bus periods observed by
each node’s CPU.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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N O N - D I S C L O S U R E
Huntsinger’s variable pulse width modulation (VPW) is an encoding
technique in which each bit is defined by the time between successive
transitions and by the level of the bus between transitions, (for instance,
active or passive). Active and passive bits are used alternately. This
encoding technique is used to reduce the number of bus transitions for
a given bit rate.
A G R E E M E N T
20.5.3 J1850 VPW Symbols
R E Q U I R E D
Logic 0
A logic 0 is defined as either:
– An active-to-passive transition followed by a passive period
64 µs in length, or
– A passive-to-active transition followed by an active period
128 µs in length
A G R E E M E N T
See Figure 20-6(a).
ACTIVE
128 µs
OR
64 µs
OR
64 µs
PASSIVE
(A) LOGIC 0
ACTIVE
128 µs
PASSIVE
N O N - D I S C L O S U R E
(B) LOGIC 1
ACTIVE
≥ 240 µs
200 µs
200 µs
PASSIVE
(C) BREAK
(D) START OF FRAME
(E) END OF DATA
300 µs
ACTIVE
280 µs
20 µs
IDLE > 300 µs
PASSIVE
(F) END OF FRAME
(G) INTER-FRAME
SEPARATION
(H) IDLE
Figure 20-6. J1850 VPW Symbols with Nominal Symbol Times
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A logic 1 is defined as either:
– An active-to-passive transition followed by a passive period
128 µs in length, or
– A passive-to-active transition followed by an active period
64 µs in length
See Figure 20-6(b).
R E Q U I R E D
Logic 1
Break Signal (BREAK)
The BREAK signal is defined as a passive-to-active transition
followed by an active period of at least 240 µs (see Figure 20-6(c)).
Start-of-Frame Symbol (SOF)
The SOF symbol is defined as passive-to-active transition followed by
an active period 200 µs in length (see Figure 20-6(d)). This allows the
data bytes which follow the SOF symbol to begin with a passive bit,
regardless of whether it is a logic 1 or a logic 0.
End-of-Data Symbol (EOD)
The EOD symbol is defined as an active-to-passive transition
followed by a passive period 200 µs in length (see Figure 20-6(e)).
End-of-Frame Symbol (EOF)
The EOF symbol is defined as an active-to-passive transition followed
by a passive period 280 µs in length (see Figure 20-6(f)). If no IFR
byte is transmitted after an EOD symbol is transmitted, after another
80 µs the EOD becomes an EOF, indicating completion of the
message.
Inter-Frame Separation Symbol (IFS)
The IFS symbol is defined as a passive period 300 µs in length. The
20-µs IFS symbol contains no transition, since when it is used it
always appends to a 280-µs EOF symbol (see Figure 20-6(g)).
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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N O N - D I S C L O S U R E
The NB symbol has the same property as a logic 1 or a logic 0. It is
only used in IFR message responses.
A G R E E M E N T
Normalization Bit (NB)
An idle is defined as a passive period greater than 300 µs in length.
20.5.4 J1850 VPW Valid/Invalid Bits and Symbols
The timing tolerances for receiving data bits and symbols from the
J1850 bus have been defined to allow for variations in oscillator
frequencies. In many cases, the maximum time allowed to define a data
bit or symbol is equal to the minimum time allowed to define another data
bit or symbol.
A G R E E M E N T
R E Q U I R E D
Idle
Since the minimum resolution of the BDLC for determining what symbol
is being received is equal to a single period of the MUX interface clock
(tBDLC), an apparent separation in these maximum time/minimum time
concurrences equals one cycle of tBDLC.
This one clock resolution allows the BDLC to differentiate properly
between the different bits and symbols. This is done without reducing the
valid window for receiving bits and symbols from transmitters onto the
J1850 bus, which has varying oscillator frequencies.
N O N - D I S C L O S U R E
In Huntsinger’s variable pulse width (VPW) modulation bit encoding, the
tolerances for both the passive and active data bits received and the
symbols received are defined with no gaps between definitions. For
example, the maximum length of a passive logic 0 is equal to the
minimum length of a passive logic 1, and the maximum length of an
active logic 0 is equal to the minimum length of a valid SOF symbol.
Invalid Passive Bit
See Figure 20-7(1). If the passive-to-active received transition
beginning the next data bit or symbol occurs between the
active-to-passive transition beginning the current data bit (or symbol)
and a, the current bit would be invalid.
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64 µs
ACTIVE
(1) INVALID PASSIVE BIT
PASSIVE
a
ACTIVE
(2) VALID PASSIVE LOGIC 0
PASSIVE
(3) VALID PASSIVE LOGIC 1
PASSIVE
b
c
ACTIVE
(4) VALID EOD SYMBOL
PASSIVE
c
d
Figure 20-7. J1850 VPW Received Passive Symbol Times
Valid Passive Logic 0
See Figure 20-7(2). If the passive-to-active received transition
beginning the next data bit (or symbol) occurs between a and b, the
current bit would be considered a logic 0.
Valid Passive Logic 1
See Figure 20-7(3). If the passive-to-active received transition
beginning the next data bit (or symbol) occurs between b and c, the
current bit would be considered a logic 1.
Valid EOD Symbol
See Figure 20-7(4). If the passive-to-active received transition
beginning the next data bit (or symbol) occurs between c and d, the
current symbol would be considered a valid end-of-data symbol
(EOD).
MC68HC08AS20 — Rev. 4.1
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A G R E E M E N T
b
ACTIVE
N O N - D I S C L O S U R E
a
R E Q U I R E D
200 µs
128 µs
R E Q U I R E D
300 µs
280 µs
ACTIVE
(1) VALID EOF SYMBOL
PASSIVE
a
b
ACTIVE
(2) VALID EOF+
IFS SYMBOL
A G R E E M E N T
PASSIVE
c
d
Figure 20-8. J1850 VPW Received Passive
EOF and IFS Symbol Times
Valid EOF and IFS Symbols
In Figure 20-8(1), if the passive-to-active received transition
beginning the SOF symbol of the next message occurs between a
and b, the current symbol will be considered a valid end-of-frame
(EOF) symbol.
N O N - D I S C L O S U R E
See Figure 20-8(2). If the passive-to-active received transition
beginning the SOF symbol of the next message occurs between c
and d, the current symbol will be considered a valid EOF symbol
followed by a valid inter-frame separation symbol (IFS). All nodes
must wait until a valid IFS symbol time has expired before beginning
transmission. However, due to variations in clock frequencies and bus
loading, some nodes may recognize a valid IFS symbol before others
and immediately begin transmitting. Therefore, any time a node
waiting to transmit detects a passive-to-active transition once a valid
EOF has been detected, it should immediately begin transmission,
initiating the arbitration process.
Idle Bus
In Figure 20-8(2), if the passive-to-active received transition
beginning the start-of-frame (SOF) symbol of the next message does
not occur before d, the bus is considered to be idle, and any node
wishing to transmit a message may do so immediately.
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128 µs
64 µs
ACTIVE
(1) INVALID ACTIVE BIT
PASSIVE
a
ACTIVE
(2) VALID ACTIVE LOGIC 1
R E Q U I R E D
200 µs
b
(3) VALID ACTIVE LOGIC 0
PASSIVE
b
c
ACTIVE
(4) VALID SOF SYMBOL
PASSIVE
c
d
Figure 20-9. J1850 VPW Received Active Symbol Times
Invalid Active Bit
In Figure 20-9(1), if the active-to-passive received transition
beginning the next data bit (or symbol) occurs between the
passive-to-active transition beginning the current data bit (or symbol)
and a, the current bit would be invalid.
Valid Active Logic 1
In Figure 20-9(2), if the active-to-passive received transition
beginning the next data bit (or symbol) occurs between a and b, the
current bit would be considered a logic 1.
Valid Active Logic 0
In Figure 20-9(3), if the active-to-passive received transition
beginning the next data bit (or symbol) occurs between b and c, the
current bit would be considered a logic 0.
MC68HC08AS20 — Rev. 4.1
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N O N - D I S C L O S U R E
a
ACTIVE
A G R E E M E N T
PASSIVE
R E Q U I R E D
Valid SOF Symbol
In Figure 20-9(4), if the active-to-passive received transition
beginning the next data bit (or symbol) occurs between c and d, the
current symbol would be considered a valid SOF symbol.
Valid BREAK Symbol
N O N - D I S C L O S U R E
A G R E E M E N T
In Figure 20-10, if the next active-to-passive received transition does
not occur until after e, the current symbol will be considered a valid
BREAK symbol. A BREAK symbol should be followed by a
start-of-frame (SOF) symbol beginning the next message to be
transmitted onto the J1850 bus. See 20.5.2 J1850 Frame Format for
BDLC response to BREAK symbols.
240 µs
ACTIVE
(2) VALID BREAK SYMBOL
PASSIVE
e
Figure 20-10. J1850 VPW Received BREAK Symbol Times
20.5.5 Message Arbitration
Message arbitration on the J1850 bus is accomplished in a
non-destructive manner, allowing the message with the highest priority
to be transmitted, while any transmitters which lose arbitration simply
stop transmitting and wait for an idle bus to begin transmitting again.
If the BDLC wants to transmit onto the J1850 bus, but detects that
another message is in progress, it waits until the bus is idle. However, if
multiple nodes begin to transmit in the same synchronization window,
message arbitration will occur beginning with the first bit after the SOF
symbol and continue with each bit thereafter. If a write to the BDR (for
instance, to initiate transmission) occurred on or before
104 • tBDLC from the received rising edge, then the BDLC will transmit
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Whenever a node detects a dominant bit on BDRxD when it transmitted
a recessive bit, it loses arbitration and immediately stops transmitting.
This is known as bitwise arbitration.
Since a logic 0 dominates a logic 1, the message with the lowest value
will have the highest priority and will always win arbitration. For instance,
a message with priority 000 will win arbitration over a message with
priority 011.
0
1
1
0
1
1
N O N - D I S C L O S U R E
This method of arbitration will work no matter how many bits of priority
encoding are contained in the message.
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS AND STOPS
TRANSMITTING
1
ACTIVE
TRANSMITTER A
PASSIVE
0
0
ACTIVE
TRANSMITTER B
PASSIVE
0
1
1
0
0
DATA
DATA
DATA
DATA
DATA
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
TRANSMITTER B WINS
ARBITRATION AND
CONTINUES
TRANSMITTING
ACTIVE
J1850 BUS
PASSIVE
SOF
Figure 20-11. J1850 VPW Bitwise Arbitrations
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
The variable pulse width modulation (VPW) symbols and J1850 bus
electrical characteristics are chosen carefully so that a logic 0 (active or
passive type) will always dominate over a logic 1 (active or passive type)
simultaneously transmitted. Hence, logic 0s are said to be dominant and
logic 1s are said to be recessive.
A G R E E M E N T
and arbitrate for the bus. If a CPU write to the BDR occurred after
104 • tBDLC from the detection of the rising edge, then the BDLC will not
transmit, but will wait for the next IFS period to expire before attempting
to transmit the byte.
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R E Q U I R E D
20.6 BDLC Protocol Handler
The protocol handler is responsible for framing, arbitration, CRC
generation/checking, and error detection. The protocol handler
conforms to SAE J1850 Class B Data Communications Network
Interface.
NOTE:
N O N - D I S C L O S U R E
A G R E E M E N T
During arbitration, or even throughout the transmitting message, when
an opposite bit is detected, transmission is stopped immediately unless
it occurs on the 8th bit of a byte. In this case, the BDLC automatically will
append up to two extra logic 1 bits and then stop transmitting. These two
extra bits will be arbitrated normally and thus will not interfere with
another message. The second logic 1 bit will not be sent if the first loses
arbitration. If the BDLC has lost arbitration to another valid message,
then the two extra logic 1s will not corrupt the current message.
However, if the BDLC has lost arbitration due to noise on the bus, then
the two extra logic 1s will ensure that the current message will be
detected and ignored as a noise-corrupted message.
Freescale assumes that the reader is familiar with the J1850
specification before reading this protocol handler description.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 20-12. BDLC Block Diagram
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The protocol handler contains the state machine, Rx shadow register, Tx
shadow register, Rx shift register, Tx shift register, and loopback
multiplexer as shown in Figure 20-13.
TO PHYSICAL INTERFACE
A G R E E M E N T
ALOOP
BDTxD
CONTROL
LOOPBACK
MULTIPLEXER
RxD
DLOOP FROM BCR2
LOOPBACK CONTROL
BDTxD
STATE MACHINE
Tx SHADOW REGISTER
8
Tx DATA
Rx SHADOW REGISTER
CONTROL
Tx SHIFT REGISTER
Rx DATA
Rx SHIFT REGISTER
8
TO CPU INTERFACE AND Rx/Tx BUFFERS
Figure 20-13. BDLC Protocol Handler Outline
20.6.2 Rx and Tx Shift Registers
The Rx shift register gathers received serial data bits from the J1850 bus
and makes them available in parallel form to the Rx shadow register. The
Tx shift register takes data, in parallel form, from the Tx shadow register
and presents it serially to the state machine so that it can be transmitted
onto the J1850 bus.
MC68HC08AS20 — Rev. 4.1
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N O N - D I S C L O S U R E
BDRxD
R E Q U I R E D
20.6.1 Protocol Architecture
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
20.6.3 Rx and Tx Shadow Registers
Immediately after the Rx shift register has completed shifting in a byte of
data, this data is transferred to the Rx shadow register and RDRF or
RXIFR is set (see 20.7.4 BDLC State Vector Register). An interrupt is
generated if the interrupt enable bit (IE) in BCR1 is set. After the transfer
takes place, this new data byte in the Rx shadow register is available to
the CPU interface, and the Rx shift register is ready to shift in the next
byte of data. Data in the Rx shadow register must be retrieved by the
CPU before it is overwritten by new data from the Rx shift register.
Once the Tx shift register has completed its shifting operation for the
current byte, the data byte in the Tx shadow register is loaded into the
Tx shift register. After this transfer takes place, the Tx shadow register is
ready to accept new data from the CPU when the TDRE flag in the BSVR
is set.
20.6.4 Digital Loopback Multiplexer
The digital loopback multiplexer connects RxD to either BDTxD or
BDRxD, depending on the state of the DLOOP bit in the BCR2 (See
20.7.3 BDLC Control Register 2).
20.6.5 State Machine
All functions associated with performing the protocol are executed or
controlled by the state machine. The state machine is responsible for
framing, collision detection, arbitration, CRC generation/checking, and
error detection. The following sections describe the BDLC’s actions in a
variety of situations.
20.6.5.1 4X Mode
The BDLC can exist on the same J1850 bus as modules which use a
special 4X (41.6 kbps) mode of J1850 variable pulse width modulation
(VPW) operation. The BDLC cannot transmit in 4X mode, but it can
receive messages in 4X mode, if the RX4XE bit is set in BCR2. If the
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Another node wishing to send a block mode transmission must first
inform all other nodes on the network that this is about to happen. This
is usually accomplished by sending a special predefined message.
20.6.5.3 Transmitting a Message in Block Mode
A block mode message is transmitted inherently by simply loading the
bytes one by one into the BDR until the message is complete. The
programmer should wait until the TDRE flag (see 20.7.4 BDLC State
Vector Register) is set prior to writing a new byte of data into the BDR.
The BDLC does not contain any predefined maximum J1850 message
length requirement.
20.6.5.4 J1850 Bus Errors
The BDLC detects several types of transmit and receive errors which
can occur during the transmission of a message onto the J1850 bus.
Transmission Error
If the message transmitted by the BDLC contains invalid bits or
framing symbols on non-byte boundaries, this constitutes a
transmission error. When a transmission error is detected, the BDLC
immediately will cease transmitting. The error condition is reflected in
the BSVR (see Table 20-6). If the interrupt enable bit (IE in BCR1) is
set, a CPU interrupt request from the BDLC is generated.
MC68HC08AS20 — Rev. 4.1
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R E Q U I R E D
Although not a part of the SAE J1850 protocol, the BDLC does allow for
a special block mode of operation of the receiver. As far as the BDLC is
concerned, a block mode message is simply a long J1850 frame that
contains an indefinite number of data bytes. All other features of the
frame remain the same, including the SOF, CRC, and EOD symbols.
A G R E E M E N T
20.6.5.2 Receiving a Message in Block Mode
N O N - D I S C L O S U R E
RX4XE bit is not set in the BCR2, any 4X message on the J1850 bus is
treated as noise by the BDLC and is ignored.
R E Q U I R E D
CRC Error
A cyclical redundancy check (CRC) error is detected when the data
bytes and CRC byte of a received message are processed and the
CRC calculation result is not equal. The CRC code will detect any
single and 2-bit errors, as well as all 8-bit burst errors and almost all
other types of errors. The CRC error flag (in BSVR) is set when a CRC
error is detected. (See 20.7.4 BDLC State Vector Register.)
Symbol Error
A G R E E M E N T
A symbol error is detected when an abnormal (invalid) symbol is
detected in a message being received from the J1850 bus. The invalid
symbol is set when a symbol error is detected. (See 20.7.4 BDLC
State Vector Register.)
Framing Error
N O N - D I S C L O S U R E
A framing error is detected if an EOD or EOF symbol is detected on a
non-byte boundary from the J1850 bus. A framing error also is
detected if the BDLC is transmitting the EOD and instead receives an
active symbol. The symbol invalid, or the out-of-range flag, is set
when a framing error is detected. (See 20.7.4 BDLC State Vector
Register.)
Bus Fault
If a bus fault occurs, the response of the BDLC will depend upon the
type of bus fault.
If the bus is shorted to battery, the BDLC will wait for the bus to fall to
a passive state before it will attempt to transmit a message. As long
as the short remains, the BDLC will never attempt to transmit a
message onto the J1850 bus.
If the bus is shorted to ground, the BDLC will see an idle bus, begin
to transmit the message, and then detect a transmission error (in
BSVR), since the short to ground would not allow the bus to be driven
to the active (dominant) SOF state. The BDLC will abort that
transmission and wait for the next CPU command to transmit.
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The BDLC cannot transmit a BREAK symbol. It only can receive a
BREAK symbol from the J1850 bus.
20.6.5.5 Summary
Table 20-2. BDLC J1850 Bus Error Summary
Error Condition
BDLC Function
Transmission Error
For invalid bits or framing symbols on non-byte boundaries, invalid
symbol interrupt will be generated. BDLC stops transmission.
Cyclical Redundancy Check (CRC) Error
CRC error interrupt will be generated. The BDLC will wait for EOF.
Invalid Symbol: BDLC transmits, but
Receives Invalid Bits (Noise)
The BDLC will abort transmission immediately. Invalid symbol
interrupt will be generated.
Framing Error
Invalid symbol interrupt will be generated. The BDLC will wait for end
of frame (EOF).
Bus Short to VDD
The BDLC will not transmit until the bus is idle. Invalid symbol
interrupt will be generated. EOF interrupt also must be seen before
another transmission attempt. Depending on length of the short,
LOA flag also may be set.
Bus Short to GND
Thermal overload will shut down physical interface. Fault condition is
seen as invalid symbol flag. EOF interrupt must also be seen
before another transmission attempt.
BDLC Receives BREAK Symbol
Invalid symbol interrupt will be generated. The BDLC will wait for the
next valid SOF.
MC68HC08AS20 — Rev. 4.1
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R E Q U I R E D
If a BREAK symbol is received while the BDLC is transmitting or
receiving, an invalid symbol (in BSVR) interrupt will be generated.
Reading the BSVR (see 20.7.4 BDLC State Vector Register) will
clear this interrupt condition. The BDLC will wait for the bus to idle,
then wait for a start-of-frame (SOF) symbol.
A G R E E M E N T
BREAK — Break
N O N - D I S C L O S U R E
In any case, if the bus fault is temporary, as soon as the fault is
cleared, the BDLC will resume normal operation. If the bus fault is
permanent, it may result in permanent loss of communication on the
J1850 bus. (See 20.7.4 BDLC State Vector Register.)
R E Q U I R E D
20.7 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the
BDLC and consists of five user registers.
TO CPU
N O N - D I S C L O S U R E
A G R E E M E N T
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 20-14. BDLC Block Diagram
20.7.1 BDLC Analog and Roundtrip Delay
This register programs the BDLC to compensate for various delays of
different external transceivers. The default delay value is 16 µs. Timing
adjustments from 9 µs to 24 µs in steps of 1 µs are available. The BARD
register can be written only once after each reset, after which they
become read-only bits. The register may be read at any time.
Address:
Read:
Write:
Reset:
$003B
Bit 7
6
ATE
RXPOL
1
1
5
4
0
0
0
0
3
2
1
Bit 0
BO3
BO2
BO1
BO0
0
1
1
1
= Unimplemented
Figure 20-15. BDLC Analog and Roundtrip Delay Register (BARD)
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The analog transceiver enable (ATE) bit is used to select either the
on-board or an off-chip analog transceiver.
1 = Select on-board analog transceiver
0 = Select off-chip analog transceiver
NOTE:
This device does not contain an on-board transceiver. This bit should be
programmed to a logic 0 for proper operation.
R E Q U I R E D
ATE — Analog Transceiver Enable Bit
The receive pin polarity (RXPOL) bit is used to select the polarity of
an incoming signal on the receive pin. Some external analog
transceivers invert the receive signal from the J1850 bus before
feeding it back to the digital receive pin.
1 = Select normal/true polarity; true non-inverted signal from the
J1850 bus; for example, the external transceiver does not
invert the receive signal
0 = Select inverted polarity, where an external transceiver inverts
the receive signal from the J1850 bus
BO3–BO0 — BARD Offset Bits
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
N O N - D I S C L O S U R E
Table 20-3 shows the expected transceiver delay with respect to
BARD offset values.
A G R E E M E N T
RXPOL — Receive Pin Polarity Bit
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R E Q U I R E D
Table 20-3. BDLC Transceiver Delay
Corresponding Expected
Transceiver’s Delays (µs)
0000
9
0001
10
0010
11
0011
12
0100
13
0101
14
0110
15
0111
16
1000
17
1001
18
1010
19
1011
20
1100
21
1101
22
1110
23
1111
24
N O N - D I S C L O S U R E
A G R E E M E N T
BARD Offset Bits BO[3:0]
20.7.2 BDLC Control Register 1
This register is used to configure and control the BDLC.
Address:
Read:
Write:
Reset:
$003C
Bit 7
6
5
4
IMSG
CLKS
R1
R0
1
1
1
0
R
= Reserved
3
2
0
0
R
R
0
0
1
Bit 0
IE
WCM
0
0
Figure 20-16. BDLC Control Register 1 (BCR1)
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CLKS — Clock Bit
For J1850 bus communications to take place, the nominal BDLC
operating frequency (fBDLC) must always be 1.048576 MHz or 1 MHz.
The CLKS register bit allows the user to select the frequency
(1.048576 MHz or 1 MHz) used to automatically adjust symbol timing.
1 = Binary frequency (1.048576 MHz) selected for fBDLC
0 = Integer frequency (1 MHz) selected for fBDLC
R E Q U I R E D
This bit is used to disable the receiver until a new start-of-frame (SOF)
is detected.
1 = Disable receiver. When set, all BDLC interrupt requests will be
masked (except $20 in BSVR) and the status bits will be held
in their reset state. If this bit is set while the BDLC is receiving
a message, the rest of the incoming message will be ignored.
0 = Enable receiver. This bit is cleared automatically by the
reception of an SOF symbol or a BREAK symbol. It will then
generate interrupt requests and will allow changes of the
status register to occur. However, these interrupts may still be
masked by the interrupt enable (IE) bit.
A G R E E M E N T
IMSG — Ignore Message Bit
These bits determine the amount by which the frequency of the MCU
CGMXCLK signal is divided to form the MUX interface clock (fBDLC)
which defines the basic timing resolution of the MUX interface. They
may be written only once after reset, after which they become
read-only bits.
The nominal frequency of fBDLC must always be 1.048576 MHz or 1.0
MHz for J1850 bus communications to take place. Hence, the value
programmed into these bits is dependent on the chosen MCU system
clock frequency per Table 20-4.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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N O N - D I S C L O S U R E
R1 and R0 — Rate Select Bits
R E Q U I R E D
A G R E E M E N T
Table 20-4. BDLC Rate Selection
fXCLK Frequency
R1
R0
Division
fBDLC
1.049 MHz
0
0
1
1.049 MHz
2.097 MHz
0
1
2
1.049 MHz
4.194 MHz
1
0
4
1.049 MHz
8.389 MHz
1
1
8
1.049 MHz
1.000 MHz
0
0
1
1.00 MHz
2.000 MHz
0
1
2
1.00 MHz
4.000 MHz
1
0
4
1.00 MHz
8.000 MHz
1
1
8
1.00 MHz
IE— Interrupt Enable Bit
N O N - D I S C L O S U R E
This bit determines whether the BDLC will generate CPU interrupt
requests in run mode. It does not affect CPU interrupt requests when
exiting the BDLC stop or BDLC wait modes. Interrupt requests will be
maintained until all of the interrupt request sources are cleared by
performing the specified actions upon the BDLC’s registers. Interrupts
that were pending at the time that this bit is cleared may be lost.
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
If the programmer does not wish to use the interrupt capability of the
BDLC, the BDLC state vector register (BSVR) can be polled
periodically by the programmer to determine BDLC states. See 20.7.4
BDLC State Vector Register for a description of the BSVR.
WCM — Wait Clock Mode Bit
This bit determines the operation of the BDLC during CPU wait mode.
See 20.8.2 Stop Mode and 20.8.1 Wait Mode for more details on its
use.
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
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Read:
Write:
Reset:
$003D
Bit 7
6
5
4
3
2
1
Bit 0
ALOOP
DLOOP
RX4XE
NBFS
TEOD
TSIFR
TMIFR1
TMIFR0
1
1
0
0
0
0
0
0
Figure 20-17. BDLC Control Register 2 (BCR2)
ALOOP — Analog Loopback Mode Bit
This bit determines whether the J1850 bus will be driven by the
analog physical interface’s final drive stage. The programmer can use
this bit to reset the BDLC state machine to a known state after the
off-chip analog transceiver is placed in loopback mode. When the
user clears ALOOP, to indicate that the off-chip analog transceiver is
no longer in loopback mode, the BDLC waits for an EOF symbol
before attempting to transmit. Most transceivers have the ALOOP
feature available.
1 = Input to the analog physical interface’s final drive stage is
looped back to the BDLC receiver. The J1850 bus is not driven.
0 = The J1850 bus will be driven by the BDLC. After the bit is
cleared, the BDLC requires the bus to be idle for a minimum of
end-of-frame symbol time (tTRV4) before message reception or
a minimum of inter-frame symbol time (tTRV6) before message
transmission. (See 21.15 BDLC Receiver VPW Symbol
Timings.)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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R E Q U I R E D
Address:
A G R E E M E N T
This register controls transmitter operations of the BDLC. It is
recommended that BSET and BCLR instructions be used to manipulate
data in this register to ensure that the register’s content does not change
inadvertently.
N O N - D I S C L O S U R E
20.7.3 BDLC Control Register 2
R E Q U I R E D
DLOOP — Digital Loopback Mode Bit
A G R E E M E N T
This bit determines the source to which the digital receive input
(BDRxD) is connected and can be used to isolate bus fault conditions
(see Figure 20-13). If a fault condition has been detected on the bus,
this control bit allows the programmer to connect the digital transmit
output to the digital receive input. In this configuration, data sent from
the transmit buffer will be reflected back into the receive buffer. If no
faults exist in the BDLC, the fault is in the physical interface block or
elsewhere on the J1850 bus.
1 = When set, BDRxD is connected to BDTxD. The BDLC is now
in digital loopback mode.
0 = When cleared, BDTxD is not connected to BDRxD. The BDLC
is taken out of digital loopback mode and can now drive or
receive the J1850 bus normally (given ALOOP is not set). After
writing DLOOP to 0, the BDLC requires the bus to be idle for a
minimum of end-of-frame symbol (ttv4) time before allowing a
reception of a message. The BDLC requires the bus to be idle
for a minimum of inter-frame separator symbol (ttv6) time
before allowing any message to be transmitted.
RX4XE — Receive 4X Enable Bit
N O N - D I S C L O S U R E
This bit determines if the BDLC operates at normal transmit and
receive speed (10.4 kbps) or receive only at 41.6 kbps. This feature
is useful for fast downloading of data into a J1850 node for diagnostic
or factory programming of the node.
1 = When set, the BDLC is put in 4X receive-only operation.
0 = When cleared, the BDLC transmits and receives at 10.4 kbps.
Reception of a BREAK symbol automatically clears this bit and
sets BDLC state vector register (BSVR) to $001C.
NBFS — Normalization Bit Format Select Bit
This bit controls the format of the normalization bit (NB). (See Figure
20-18.) SAE J1850 strongly encourages using an active long (logic 0)
for in-frame responses containing cyclical redundancy check (CRC)
and an active short (logic 1) for in-frame responses without CRC.
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
1 = NB that is received or transmitted is a 0 when the response part
of an in-frame response (IFR) ends with a CRC byte. NB that
is received or transmitted is a 1 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
0 = NB that is received or transmitted is a 1 when the response part
of an in-frame response (IFR) ends with a CRC byte. NB that
is received or transmitted is a 0 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
TSIFR, TMIFR1, and TMIFR0 — Transmit In-Frame Response
Control Bits
These three bits control the type of in-frame response being sent. The
programmer should not set more than one of these control bits to a 1
at any given time. However, if more than one of these three control
bits are set to 1, the priority encoding logic will force these register bits
to a known value as shown in Table 20-5. For example, if 011 is
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
353
N O N - D I S C L O S U R E
This bit is set by the programmer to indicate the end of a message is
being sent by the BDLC. It will append an 8-bit CRC after completing
transmission of the current byte. This bit also is used to end an
in-frame response (IFR). If the transmit shadow register is full when
TEOD is set, the CRC byte will be transmitted after the current byte in
the Tx shift register and the byte in the Tx shadow register have been
transmitted. (See 20.6.3 Rx and Tx Shadow Registers for a
description of the transmit shadow register.) Once TEOD is set, the
transmit data register empty flag (TDRE) in the BDLC state vector
register (BSVR) is cleared to allow lower priority interrupts to occur.
(See 20.7.4 BDLC State Vector Register.)
1 = Transmit end-of-data (EOD) symbol
0 = The TEOD bit will be cleared automatically at the rising edge of
the first CRC bit that is sent or if an error is detected. When
TEOD is used to end an IFR transmission, TEOD is cleared
when the BDLC receives back a valid EOD symbol or an error
condition occurs.
A G R E E M E N T
TEOD — Transmit End-of-Data Bit
R E Q U I R E D
written to TSIFR, TMIFR1, and TMIFR0, then internally they will be
encoded as 010. However, when these bits are read back, they will
read 011.
A G R E E M E N T
Table 20-5. BDLC Transmit In-Frame Response
Control Bit Priority Encoding
Write/Read
TSIFR
Write/Read
TMIFR1
Write/Read
TMIFR0
Actual
TSIFR
Actual
TMIFR1
Actual
TMIFR0
0
0
0
0
0
0
1
X
X
1
0
0
0
1
X
0
1
0
0
0
1
0
0
1
N O N - D I S C L O S U R E
The BDLC supports the in-frame response (IFR) feature of J1850 by
setting these bits correctly. The four types of J1850 IFR are shown in
the following figure. The purpose of the in-frame response modes is
to allow multiple nodes to acknowledge receipt of the data by
responding with their personal ID or physical address in a
concatenated manner after they have seen the EOD symbol. If
transmission arbitration is lost by a node while sending its response,
it continues to transmit its ID/address until observing its unique byte
in the response stream. For VPW modulation, the first bit of the IFR is
always passive; therefore, an active normalization bit must be
generated by the responder and sent prior to its ID/address byte.
When there are multiple responders on the J1850 bus, only one
normalization bit is sent which assists all other transmitting nodes to
sync their responses.
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
DATA FIELD
NB
EOF
EOD
SOF
HEADER
ID
TYPE 1 — SINGLE BYTE TRANSMITTED FROM A SINGLE RESPONDER
CRC
NB
ID1
ID N
EOF
EOD
DATA FIELD
EOD
SOF
HEADER
TYPE 2 — SINGLE BYTE TRANSMITTED FROM MULTIPLE RESPONDERS
CRC
NB
IFR DATA FIELD
CRC
(OPTIONAL)
EOF
EOD
DATA FIELD
EOD
SOF
HEADER
TYPE 3 — MULTIPLE BYTES TRANSMITTED FROM A SINGLE RESPONDER
NB = Normalization Bit
ID = Identifier, usually the physical address of the responder(s)
Figure 20-18. Types of In-Frame Response (IFR)
TSIFR — Transmit Single Byte IFR with No CRC (Type 1 or 2) Bit
The TSIFR bit is used to request the BDLC to transmit the byte in the
BDLC data register (BDR) as a single byte IFR with no CRC.
Typically, the byte transmitted is a unique identifier or address of the
transmitting (responding) node. See Figure 20-18.
1 = If this bit is set prior to a valid EOD being received with no CRC
error, once the EOD symbol has been received the BDLC will
attempt to transmit the appropriate normalization bit followed
by the byte in the BDR.
0 = The TSIFR bit will be cleared automatically, once the BDLC
has successfully transmitted the byte in the BDR onto the
bus, or TEOD is set, or an error is detected on the bus.
If the programmer attempts to set the TSIFR bit immediately after the
EOD symbol has been received from the bus, the TSIFR bit will remain
in the reset state and no attempt will be made to transmit the IFR byte.
If a loss of arbitration occurs when the BDLC attempts to transmit and
after the IFR byte winning arbitration completes transmission, the BDLC
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
355
A G R E E M E N T
CRC
TYPE 0 — NO IFR
N O N - D I S C L O S U R E
CRC
EOD
DATA FIELD
EOF
EOD
SOF
HEADER
R E Q U I R E D
will again attempt to transmit the BDR (with no normalization bit). The
BDLC will continue transmission attempts until an error is detected on
the bus, or TEOD is set, or the BDLC transmission is successful.
If loss of arbitration occurs in the last two bits of the IFR byte, two
additional 1 bits will not be sent out because the BDLC will attempt to
retransmit the byte in the transmit shift register after the IRF byte winning
arbitration completes transmission.
A G R E E M E N T
TMIFR1 — Transmit Multiple Byte IFR with CRC (Type 3) Bit
N O N - D I S C L O S U R E
The TMIFR1 bit requests the BDLC to transmit the byte in the BDLC
data register (BDR) as the first byte of a multiple byte IFR with CRC
or as a single byte IFR with CRC. Response IFR bytes are still subject
to J1850 message length maximums (see 20.5.2 J1850 Frame
Format). See Figure 20-18
1 = If this bit is set prior to a valid EOD being received with no CRC
error, once the EOD symbol has been received, the BDLC will
attempt to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last
IFR byte has been written into the BDR. After TEOD has been
set and the last IFR byte has been transmitted, the CRC byte
is transmitted.
0 = The TMIFR1 bit will be cleared automatically, once the BDLC
has successfully transmitted the CRC byte and EOD symbol,
by the detection of an error on the multiplex bus or by a
transmitter underrun caused when the programmer does not
write another byte to the BDR after the TDRE interrupt.
If the TMIFR1 bit is set, the BDLC will attempt to transmit the
normalization symbol followed by the byte in the BDR. After the byte
in the BDR has been loaded into the transmit shift register, a TDRE
interrupt (see 20.7.4 BDLC State Vector Register) will occur similar
to the main message transmit sequence. The programmer should
then load the next byte of the IFR into the BDR for transmission.
When the last byte of the IFR has been loaded into the BDR, the
programmer should set the TEOD bit in the BDLC control register 2
(BCR2). This will instruct the BDLC to transmit a CRC byte once the
byte in the BDR is transmitted, and then transmit an EOD symbol,
indicating the end of the IFR portion of the message frame.
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
If a loss of arbitration occurs when the BDLC is transmitting any byte
of a multiple byte IFR, the BDLC will go to the loss of arbitration state,
set the appropriate flag, and cease transmission.
If the BDLC loses arbitration during the IFR, the TMIFR1 bit will be
cleared and no attempt will be made to retransmit the byte in the
BDR. If loss of arbitration occurs in the last two bits of the IFR byte,
two additional 1 bits will be sent out.
NOTE:
The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
on the J1850 bus from corrupting a message.
TMIFR0 — Transmit Multiple Byte IFR without CRC (Type 3) Bit
The TMIFR0 bit is used to request the BDLC to transmit the byte in
the BDLC data register (BDR) as the first byte of a multiple byte IFR
without CRC. Response IFR bytes are still subject to J1850 message
length maximums (see 20.5.2 J1850 Frame Format). See Figure
20-18.
1 = If this bit is set prior to a valid EOD being received with no CRC
error, once the EOD symbol has been received, the BDLC will
attempt to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last
IFR byte has been written into the BDR. After TEOD has been
set, the last IFR byte to be transmitted will be the last byte
which was written into the BDR.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
357
R E Q U I R E D
A G R E E M E N T
If the programmer attempts to set the TMIFR1 bit immediately after
the EOD symbol has been received from the bus, the TMIFR1 bit will
remain in the reset state, and no attempt will be made to transmit an
IFR byte.
N O N - D I S C L O S U R E
However, if the programmer wishes to transmit a single byte followed
by a CRC byte, the programmer should load the byte into the BDR
before the EOD symbol has been received, and then set the TMIFR1
bit. Once the TDRE interrupt occurs, the programmer should then set
the TEOD bit in the BCR2. This will result in the byte in the BDR being
the only byte transmitted before the IFR CRC byte, and no TDRE
interrupt will be generated.
R E Q U I R E D
0 = The TMIFR0 bit will be cleared automatically, once the BDLC
has successfully transmitted the EOD symbol, by the detection
of an error on the multiplex bus or by a transmitter underrun
caused when the programmer does not write another byte to
the BDR after the TDRE interrupt.
N O N - D I S C L O S U R E
A G R E E M E N T
If the TMIFR0 bit is set, the BDLC will attempt to transmit the
normalization symbol followed by the byte in the BDR. After the byte
in the BDR has been loaded into the transmit shift register, a TDRE
interrupt (see 20.7.4 BDLC State Vector Register) will occur similar
to the main message transmit sequence. The programmer should
then load the next byte of the IFR into the BDR for transmission.
When the last byte of the IFR has been loaded into the BDR, the
programmer should set the TEOD bit in the BCR2. This will instruct
the BDLC to transmit an EOD symbol once the byte in the BDR is
transmitted, indicating the end of the IFR portion of the message
frame. The BDLC will not append a CRC when the TMIFR0 is set.
If the programmer attempts to set the TMIFR0 bit after the EOD
symbol has been received from the bus, the TMIFR0 bit will remain in
the reset state, and no attempt will be made to transmit an IFR byte.
If a loss of arbitration occurs when the BDLC is transmitting, the
TMIFR0 bit will be cleared, and no attempt will be made to retransmit
the byte in the BDR. If loss of arbitration occurs in the last two bits of
the IFR byte, two additional 1 bits (active short bits) will be sent out.
NOTE:
The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
on to the J1850 bus from a corrupted message.
20.7.4 BDLC State Vector Register
This register is provided to substantially decrease the CPU overhead
associated with servicing interrupts while under operation of a multiplex
protocol. It provides an index offset that is directly related to the BDLC’s
current state, which can be used with a user-supplied jump table to
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Bit 7
6
5
4
3
2
1
Bit 0
0
0
I3
I2
I1
I0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 20-19. BDLC State Vector Register (BSVR)
I0, I1, I2, and I3 — Interrupt Source Bits
These bits indicate the source of the interrupt request that currently is
pending. The encoding of these bits are listed in Table 20-6.
Table 20-6. BDLC Interrupt Sources
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
BSVR
I3
I2
I1
I0
Interrupt Source
Priority
$00
0
0
0
0
No Interrupts Pending
0 (Lowest)
$04
0
0
0
1
Received EOF
1
$08
0
0
1
0
Received IFR Byte (RXIFR)
2
$0C
0
0
1
1
BDLC Rx Data Register Full (RDRF)
3
$10
0
1
0
0
BDLC Tx Data Register Empty (TDRE)
4
$14
0
1
0
1
Loss of Arbitration
5
$18
0
1
1
0
Cyclical Redundancy Check (CRC) Error
6
$1C
0
1
1
1
Symbol Invalid or Out of Range
7
$20
1
0
0
0
Wakeup
8 (Highest)
Advance Information
359
R E Q U I R E D
Read:
$003E
A G R E E M E N T
Address:
N O N - D I S C L O S U R E
rapidly enter an interrupt service routine. This eliminates the need for the
user to maintain a duplicate state machine in software.
R E Q U I R E D
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR except when the
BDLC data register needs servicing (RDRF, RXIFR, or TDRE
conditions). RXIFR and RDRF can be cleared only by a read of the
BSVR followed by a read of the BDLC data register (BDR). TDRE can
either be cleared by a read of the BSVR followed by a write to the BDLC
BDR or by setting the TEOD bit in BCR2.
A G R E E M E N T
Upon receiving a BDLC interrupt, the user can read the value within the
BSVR, transferring it to the CPU’s index register. The value can then be
used to index into a jump table, with entries four bytes apart, to quickly
enter the appropriate service routine. For example:
Service
*
*
JMPTAB
LDX
JMP
BSVR
JMPTAB,X
Fetch State Vector Number
Enter service routine,
(must end in RTI)
JMP
NOP
JMP
NOP
JMP
NOP
SERVE0
Service condition #0
SERVE1
Service condition #1
SERVE2
Service condition #2
JMP
END
SERVE8
Service condition #8
N O N - D I S C L O S U R E
*
NOTE:
The NOPs are used only to align the JMPs onto 4-byte boundaries so
that the value in the BSVR can be used intact. Each of the service
routines must end with an RTI instruction to guarantee correct continued
operation of the device. Note also that the first entry can be omitted since
it corresponds to no interrupt occurring.
The service routines should clear all of the sources that are causing the
pending interrupts. Note that the clearing of a high priority interrupt may
still leave a lower priority interrupt pending, in which case bits I0, I1, and
I2 of the BSVR will then reflect the source of the remaining interrupt
request.
If fewer states are used or if a different software approach is taken, the
jump table can be made smaller or omitted altogether.
Advance Information
360
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Address:
Read:
Write:
Reset:
$003F
Bit 7
6
5
4
3
2
1
Bit 0
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
Indeterminate after Reset
R E Q U I R E D
20.7.5 BDLC Data Register
Data read from this register will be the last data byte received from the
J1850 bus. This received data should only be read after an Rx data
register full (RDRF) interrupt has occurred. (See 20.7.4 BDLC State
Vector Register.)
The BDR is double buffered via a transmit shadow register and a receive
shadow register. After the byte in the transmit shift register has been
transmitted, the byte currently stored in the transmit shadow register is
loaded into the transmit shift register. Once the transmit shift register has
shifted the first bit out, the TDRE flag is set, and the shadow register is
ready to accept the next data byte. The receive shadow register works
similarly. Once a complete byte has been received, the receive shift
register stores the newly received byte into the receive shadow register.
The RDRF flag is set to indicate that a new byte of data has been
received. The programmer has one BDLC byte reception time to read
the shadow register and clear the RDRF flag before the shadow register
is overwritten by the newly received byte.
To abort an in-progress transmission, the programmer should stop
loading data into the BDR. This will cause a transmitter underrun error
and the BDLC automatically will disable the transmitter on the next
non-byte boundary. This means that the earliest a transmission can be
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
361
N O N - D I S C L O S U R E
This register is used to pass the data to be transmitted to the J1850 bus
from the CPU to the BDLC. It is also used to pass data received from the
J1850 bus to the CPU. Each data byte (after the first one) should be
written only after a Tx data register empty (TDRE) state is indicated in
the BSVR.
A G R E E M E N T
Figure 20-20. BDLC Data Register (BDR)
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
halted is after at least one byte plus two extra logic 1s have been
transmitted. The receiver will pick this up as an error and relay it in the
state vector register as an invalid symbol error.
NOTE:
The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
on the J1850 bus from corrupting a message.
20.8 Low-Power Modes
The following information concerns wait mode and stop mode.
20.8.1 Wait Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a WAIT instruction and the WCM bit in
BDLC control register 1 (BCR1) is previously clear. In BDLC wait mode,
the BDLC cannot drive any data.
A subsequent successfully received message, including one that is in
progress at the time that this mode is entered, will cause the BDLC to
wake up and generate a CPU interrupt request if the interrupt enable (IE)
bit in the BDLC control register 1 (BCR1) is previously set (see 20.7.2
BDLC Control Register 1 for a better understanding of IE). This results
in less of a power saving, but the BDLC is guaranteed to receive
correctly the message which woke it up, since the BDLC internal
operating clocks are kept running.
NOTE:
Ensuring that all transmissions are complete or aborted before putting
the BDLC into wait mode is important.
20.8.2 Stop Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a STOP instruction or if the CPU executes
a WAIT instruction and the WCM bit in the BDLC control register 1
(BCR1) is previously set. This is the lowest power mode that the BDLC
can enter.
Advance Information
362
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
If this mode is entered while the BDLC is receiving a message, the first
subsequent received edge will cause the BDLC to wake up immediately,
generate a CPU interrupt request, and wait for the BDLC internal
operating clocks to restart and stabilize before normal communications
can resume. Therefore, the BDLC is not guaranteed to receive that
message correctly.
It is important to ensure all transmissions are complete or aborted prior
to putting the BDLC into stop mode.
R E Q U I R E D
N O N - D I S C L O S U R E
NOTE:
A G R E E M E N T
A subsequent passive-to-active transition on the J1850 bus will cause
the BDLC to wake up and generate a non-maskable CPU interrupt
request. When a STOP instruction is used to put the BDLC in stop mode,
the BDLC is not guaranteed to correctly receive the message which
woke it up, since it may take some time for the BDLC internal operating
clocks to restart and stabilize. If a WAIT instruction is used to put the
BDLC in stop mode, the BDLC is guaranteed to correctly receive the
byte which woke it up, if and only if an end-of-frame (EOF) has been
detected prior to issuing the WAIT instruction by the CPU. Otherwise,
the BDLC will not correctly receive the byte that woke it up.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
363
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Advance Information
364
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
21.1 Contents
21.2
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
21.3
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 367
21.4
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
21.5
5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 368
21.6
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
21.7
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
21.8
5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing . . . . . 371
21.9
CGM Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .374
R E Q U I R E D
Section 21. Electrical Specifications
A G R E E M E N T
Advance Information — MC68HC08AS20
21.11 CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . . 375
21.12 Timer Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 376
21.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
21.14 BDLC Transmitter VPW Symbol Timings . . . . . . . . . . . . . . . . 376
21.15 BDLC Receiver VPW Symbol Timings . . . . . . . . . . . . . . . . . . 377
21.16 BDLC Transmitter DC Electrical Characteristics . . . . . . . . . . 378
21.17 BDLC Receiver DC Electrical Characteristics . . . . . . . . . . . . 378
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
365
N O N - D I S C L O S U R E
21.10 CGM Component Information. . . . . . . . . . . . . . . . . . . . . . . . . 374
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 21.5 5.0 Volt DC Electrical Characteristics for
guaranteed operating conditions.
Rating
A G R E E M E N T
R E Q U I R E D
21.2 Maximum Ratings
Symbol
Value
Unit
Supply Voltage
VDD
–0.3 to +6.0
V
Input Voltage
VIN
VSS –0.3 to VDD +0.3
V
I
± 25
mA
TSTG
–55 to +150
°C
Maximum Current out of VSS
IMVSS
100
mA
Maximum Current into VDD
IMVDD
100
mA
VHI
VDD to VDD + 2
V
Maximum Current Per Pin
Excluding VDD and VSS
Storage Temperature
Reset IRQ Input Voltage
N O N - D I S C L O S U R E
NOTE: Voltages are referenced to VSS.
NOTE:
Advance Information
366
This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIN and VOUT be constrained to the
range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD.)
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Symbol
Value
Unit
TA
–40 to 105
°C
VDD
5.0 ± 10%
V
Symbol
Value
Unit
Thermal Resistance
PLCC (52 Pins)
θJA
50
°C/W
I/O Pin Power Dissipation
PI/O
User Determined
W
Power Dissipation (see Note 1)
PD
PD = (IDD x VDD) +
PI/O = K/(TJ + 273 °C)
W
Constant (see Note 2)
K
PD x (TA + 273 °C)
+ (PD2 x θJA)
W/°C
Average Junction Temperature
TJ
Operating Temperature Range
Operating Voltage Range
21.4 Thermal Characteristics
Characteristic
Maximum Junction Temperature
TJM
TA = PD
x θJA
150
°C
°C
N O N - D I S C L O S U R E
NOTES:
1. Power dissipation is a function of temperature.
2. K is a constant unique to the device. K can be determined from a known TA and measured PD. With
this value of K, PD and TJ can be determined for any value of TA.
R E Q U I R E D
Rating
A G R E E M E N T
21.3 Functional Operating Range
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
367
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
21.5 5.0 Volt DC Electrical Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
Output High Voltage
(ILoad = –2.0 mA) All Ports, RESET
VOH
VDD –0.8
—
—
V
Output Low Voltage
(ILoad = 1.6 mA) All Ports, RESET
VOL
—
—
0.4
V
Input High Voltage
All Ports, IRQs, RESET, OSC1
VIH
0.7 x VDD
—
VDD
V
Input Low Voltage
All Ports, IRQs, RESET, OSC1
VIL
VSS
—
0.3 x VDD
V
—
—
—
—
30
15
mA
mA
—
—
—
—
—
—
—
—
5
50
400
500
µA
µA
µA
µA
VDD + VDDA/VDDAREF Supply Current
Run (see Note 3)
Wait (see Note 4)
Stop (see Note 5)
25 °C
–40 °C to +105 °C
25 °C with LVI Enabled
–40 °C to +105 °C with LVI Enabled
IDD
I/O Ports Hi-Z Leakage Current
IL
—
—
±1
µA
Input Current
IIN
—
—
±1
µA
Capacitance
Ports (As Input or Output)
COUT
CIN
—
—
—
—
12
8
pF
Low-Voltage Reset Inhibit
VLVII
3.8
4.0
4.2
V
Low-Voltage Reset Recover
VLVIR
4.0
4.2
4.4
V
Low-Voltage Reset Inhibit/Recover Hysteresis
HLVI
100
200
500
mV
POR ReArm Voltage (see Note 6)
VPOR
0
—
200
mV
POR Reset Voltage (see Note 7)
VPORRST
0
—
800
mV
RPOR
0.02
—
—
V/ms
VHI
VDD
VDD + 2
V
POR Rise Time Ramp Rate (see Note 8)
High COP Disable Voltage (see Note 9)
NOTES:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +105 °C, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (Operating) IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 V from rail.
No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 Vdc from rail. No dc
loads. Less than 100 pF on all outputs, CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance
linearly affects wait IDD. Measured with all modules enabled.
5. Stop IDD measured with OSC1 = VSS.
6. Maximum is highest voltage that POR is guaranteed.
7. Maximum is highest voltage that POR is possible.
8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until
minimum VDD is reached.
9. See 13.9 COP Module During Break Interrupts.
Advance Information
368
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Symbol
Min
Max
Unit
fBUS
—
8.4
M Hz
RESET Pulse Width Low
tRL
1.5
—
tcyc
IRQ Interrupt Pulse Width Low (Edge-Triggered)
tILHI
1.5
—
tcyc
IRQ Interrupt Pulse Period
tILIL
Note 3
—
tcyc
EEPROM Programming Time per Byte
tEEPGM
10
—
ms
EEPROM Erasing Time per Byte
tEBYTE
10
—
ms
EEPROM Erasing Time per Block
tEBLOCK
10
—
ms
EEPROM Erasing Time per Bulk
tEBULK
10
—
ms
EEPROM Programming Voltage Discharge Period
tEEFPV
100
—
µs
16-Bit Timer (see Note 2)
Input Capture Pulse Width (see Note 3)
Input Capture Period
tTH, tTL
tTLTL
2
Note 4
—
—
tcyc
Bus Operating Frequency (4.5–5.5 V — VDD Only)
N O N - D I S C L O S U R E
NOTES:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +105 °C, unless otherwise noted.
2. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
3. Refer to Table 16-3. Mode, Edge, and Level Selection and supporting note.
4. The minimum period tTLTL or tILIL should not be less than the number of cycles it takes to execute the capture interrupt
service routine plus TBD tcyc.
R E Q U I R E D
Characteristic
A G R E E M E N T
21.6 Control Timing
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
369
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
21.7 ADC Characteristics
Characteristic
Min
Max
Unit
Resolution
8
8
Bits
Absolute Accuracy
(VREFL = 0 V, VDDA = VREFH = 5 V ± 10%)
–1
+1
LSB
Includes
Quantization
VREFL
VREFH
V
VREFL = VSSA
Power-Up Time
16
17
µs
Conversion Time
Period
Input Leakage (see Note 3)
Ports B and D
—
±1
µA
Conversion Time
16
17
ADC
Clock
Cycles
Conversion Range (see Note 1)
Monotonicity
Comments
Includes Sampling
Time
Inherent within Total Error
Zero Input Reading
00
01
Hex
VIN = VREFL
Full-Scale Reading
FE
FF
Hex
VIN = VREFH
Sample Time (see Note 2)
5
—
ADC
Clock
Cycles
Input Capacitance
—
8
pF
Not Tested
ADC Internal Clock
500 k
1.048 M
Hz
Tested Only at 1 MHz
Analog Input Voltage
–0.3
VDD + 0.3
V
NOTES:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, VDDA/VDDAREF = 5.0 Vdc ± 10%, VSSA = 0 Vdc, VREFH = 5.0 Vdc ± 10%
2. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
3. The external system error caused by input leakage current is approximately equal to the product of R
source and input current.
Advance Information
370
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Min
Max
Operating Frequency (see Note 3)
Master
Slave
fBUS(M)
fBUS(S)
fBUS/128 dc
fBUS/2 fBUS
1
Cycle Time
Master
Slave
tcyc(M)
tcyc(S)
2
1
128
—
tcyc
2
Enable Lead Time
tLEAD
15
—
ns
3
Enable Lag Time
tLAG
15
—
ns
4
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
100
50
—
—
ns
5
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
100
50
—
—
ns
6
Data Setup Time, Inputs
Master
Slave
tSU(M)
tSU(S)
45
5
—
—
ns
7
Data Hold Time, Inputs
Master
Slave
tH(M)
tH(S)
0
15
—
—
ns
tA(CP0)
tA(CP1)
0
0
40
20
ns
ns
Access Time, Slave (see Note 4)
CPHA = 0
CPHA = 1
Unit
MHz
9
Slave Disable Time, Hold Time to High-Impedance
State (see Note 5)
tDIS
—
25
ns
10
Data Valid Time after Enable Edge (see Note 6)
Master
Slave
tV(M)
tV(S)
—
—
10
40
ns
ns
11
Data Hold Time, Outputs, after Enable Edge
Master
Slave
tHO(M)
tHO(S)
0
5
—
—
ns
ns
NOTES:
1. All timing is shown with respect to 30% VDD and 70% VDD, unless otherwise noted; assumes 100 pF load on all SPI
pins.
2. Item numbers refer to dimensions in Figure 21-1 and Figure 21-2.
3. fBUS = the currently active bus frequency for the microcontroller.
4. Time to data active from high-impedance state
5. Hold time to high-impedance state
6. With 100 pF on all SPI pins
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
371
R E Q U I R E D
Symbol
8
Characteristic
A G R E E M E N T
Num
N O N - D I S C L O S U R E
21.8 5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing
R E Q U I R E D
SS
(INPUT)
SS pin of master held high.
1
SCK (CPOL = 0)
(OUTPUT)
NOTE
SCK (CPOL = 1)
(OUTPUT)
NOTE
5
4
5
4
6
A G R E E M E N T
MISO
(INPUT)
MSB IN
BITS 6–1
10
11
MOSI
(OUTPUT)
MASTER MSB OUT
7
LSB IN
10
11
BITS 6–1
MASTER LSB OUT
NOTE: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
(INPUT)
SS pin of master held high.
N O N - D I S C L O S U R E
1
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
5
NOTE
4
5
NOTE
4
6
MISO
(INPUT)
10
MOSI
(OUTPUT)
MSB IN
BITS 6–1
11
MASTER MSB OUT
7
LSB IN
10
BITS 6–1
11
MASTER LSB OUT
NOTE: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 21-1. SPI Master Timing
Advance Information
372
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
SS
(INPUT)
3
1
SCK (CPOL = 0)
(INPUT)
11
5
4
2
SCK (CPOL = 1)
(INPUT)
5
4
9
8
SLAVE
MSB OUT
6
MOSI
(OUTPUT)
BITS 6–1
7
NOTE
11
11
10
MSB IN
SLAVE LSB OUT
A G R E E M E N T
MISO
(INPUT)
BITS 6–1
LSB IN
NOTE: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
SCK (CPOL = 0)
(INPUT)
5
4
2
8
MISO
(OUTPUT)
N O N - D I S C L O S U R E
3
SCK (CPOL = 1)
(INPUT)
5
4
10
NOTE
MOSI
(INPUT)
9
SLAVE
MSB OUT
6
7
BITS 6–1
11
10
MSB IN
SLAVE LSB OUT
BITS 6–1
LSB IN
NOTE: Not defined but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 21-2. SPI Slave Timing
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
373
R E Q U I R E D
21.9 CGM Operating Conditions
Characteristic
Crystal Reference Frequency
Crystal Cycle Speed
Range Nominal Multiplier
A G R E E M E N T
VCO Center-of-Range Frequency(1)
Min
Typ
Max
Unit
fxclk
1
—
8
MHz
CGMXCLK
1/fXCLK
—
1/fXCLK
MHz
fnom
—
4.9152
—
MHz
4.9152
—
36.1
MHz
4.9152
—
16.4
MHz
fvrs
Medium Voltage VCO Center-of-Range Frequency
VCO Frequency Multiplier
N
1
—
15
—
VCO Center-of-Range Multiplier
L
1
—
15
—
fvclk
fvrsmin
—
fvrsmax
MHz
VCO Operating Frequency
1. 5.0 V ±10% VDD only
21.10 CGM Component Information
Characteristic
N O N - D I S C L O S U R E
Symbol
Symbol
Min
Typ
Max
Unit
fxclk
1
4.9152
8
MHz
Crystal Load Capacitance(2)
CL
—
—
—
pF
Crystal Fixed Capacitance(2)
C1
—
2 × CL
—
pF
Crystal Tuning Capacitance(2)
C2
—
2 × CL
—
pF
Feedback Bias Resistor
RB
—
1
—
MΩ
Series Resistor(3)
RS
0
—
3.3
kΩ
Filter Capacitor
CF
—
Cfact × (VDDA/fxclk)
—
pF
Cbyp
—
0.1
—
µF
Crystal (X1) Frequency (MHz)(1)
Bypass Capacitor(4)
1. Fundamental mode crystals only
2. Consult crystal manufacturer’s data.
3. Not required
4. Cbyp must provide low AC impedance from f = fxclk/100 to 100 × fvclk, so series resistance must be considered.
Advance Information
374
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Min
Typ
Max
Unit
Filter Capacitor Multiply Factor
Cfact
—
0.0154
—
F/sV
Acquisition Mode Time Factor
Kacq
—
0.1135
—
V
Tracking Mode Time Factor
Ktrk
—
0.0174
—
V
Manual Mode Time to Stable(1)
tacq
—
8 × V DDA
----------------------------f xclk × K acq
—
s
Manual Stable to Lock Time(1)
tal
—
4 × V DDA
--------------------------f xclk × K trk
—
s
Manual Acquisition Time
tLock
—
tacq + tal
—
s
Tracking Mode Entry Frequency Tolerance
∆trk
0
—
± 3.6%
—
Acquisition Mode Entry Frequency Tolerance
∆acq
±6.3
—
± 7.2%
—
LOCK Entry Frequency Tolerance
∆Lock
0
—
± 0.9%
—
LOCK Exit Frequency Tolerance
∆unl
±0.9
—
± 1.8%
—
Reference Cycles per Acquisition Mode Measurement
nacq
—
32
—
Cyc.
Reference Cycles per Tracking Mode Measurement
ntrk
—
128
—
Cyc.
Automatic Mode Time to Stable(1)
tacq
n acq
----------f xclk
8 × V DDA
----------------------------f xclk × K acq
—
s
Automatic Stable to Lock Time(1)
tal
n trk
---------f xclk
4 × V DDA
--------------------------f xclk × K trk
—
s
Automatic Lock Time
tLock
—
tacq+tal
—
s
(2)
fJ
0
—
PLL Jitter
%
%
± fcrys ×
0.025%
× N/4
Hz
1. If CF chosen correctly
2. Deviation of average bus frequency over 2 ms. This parameter is guaranteed but not tested. N = VCO frequency multiplier.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
375
R E Q U I R E D
Symbol
A G R E E M E N T
Description
N O N - D I S C L O S U R E
21.11 CGM Acquisition/Lock Time Information
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
21.12 Timer Module Characteristics
Characteristic
Symbol
Min
Max
Unit
tTIH, tTIL
125
—
ns
tTCH, tTCL
(1/fOP) + 5
—
ns
Symbol
Min
Max
Unit
VRDR
0.7
—
V
10,000
—
Cycles
10
—
Years
Input Capture Pulse Width
Input Clock Pulse Width
21.13 Memory Characteristics
Characteristic
RAM Data Retention Voltage
EEPROM Write/Erase Cycles
@ 10 ms Write Time + 85 °C
EEPROM Data Retention
After 10,000 Write/Erase Cycles
21.14 BDLC Transmitter VPW Symbol Timings
Characteristic
Number
Symbol
Min
Typ
Max
Unit
Passive Logic 0
10
tTVP1
62
64
66
µs
Passive Logic 1
11
tTVP2
126
128
130
µs
Active Logic 0
12
tTVA1
126
128
130
µs
Active Logic 1
13
tTVA2
62
64
66
µs
Start of Frame (SOF)
14
tTVA3
198
200
202
µs
End of Data (EOD)
15
tTVP3
198
200
202
µs
End of Frame (EOF)
16
tTV4
278
280
282
µs
Inter-Frame Separator (IFS)
17
tTV6
298
300
302
µs
NOTES:
1. fBDLC = 1.048576 or 1.0 MHz, VDD = 5.0 V ± 10%, VSS = 0 V
2. See Figure 21-3.
Advance Information
376
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
Number
Symbol
Min
Typ
Max
Unit
Passive Logic 0
10
tTRVP1
34
64
96
µs
Passive Logic 1
11
tTRVP2
96
128
163
µs
Active Logic 0
12
tTRVA1
96
128
163
µs
Active Logic 1
13
tTRVA2
34
64
96
µs
Start of Frame (SOF)
14
tTRVA3
163
200
239
µs
End of Data (EOD)
15
tTRVP3
163
200
239
µs
End of Frame (EOF)
16
tTRV4
239
280
320
µs
Break
18
tTRV6
240
—
—
µs
13
11
1
1
14
10
12
SOF
0
0
N O N - D I S C L O S U R E
NOTES:
1. fBDLC = 1.048576 or 1.0 MHz, VDD = 5.0 V ± 10%, VSS = 0 V
2. The receiver symbol timing boundaries are subject to an uncertainty of 1 tBDLC µs due to sampling considerations.
3. See Figure 21-3.
15
0
EOD
16
EOF
18
BRK
Figure 21-3. BDLC Variable Pulse Width Modulation (VPW) Symbol Timing
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
R E Q U I R E D
Characteristic
A G R E E M E N T
21.15 BDLC Receiver VPW Symbol Timings
Advance Information
377
R E Q U I R E D
21.16 BDLC Transmitter DC Electrical Characteristics
Characteristic
Symbol
Min
Max
Unit
BDTxD Output Low Voltage
(IBDTxD = 1.6 mA)
VOLTX
—
0.4
V
BDTxD Output High Voltage
(IBDTxD = –800 µA)
VOHTX
VDD –0.8
—
V
N O N - D I S C L O S U R E
A G R E E M E N T
NOTE:
1. VDD = 5.0 Vdc + 10%, VSS = 0 Vdc, TA = –40 oC to +125 oC, unless otherwise noted
21.17 BDLC Receiver DC Electrical Characteristics
Characteristic
Symbol
Min
Max
Unit
BDRxD Input Low Voltage
VILRX
VSS
0.3 x VDD
V
BDRxD Input High Voltage
VIHRX
0.7 x VDD
VDD
V
BDRxD Input Low Current
IILBDRXI
–1
+1
µA
BDRxD Input High Current
IHBDRX
–1
+1
µA
NOTE:
1. VDD = 5.0 Vdc + 10%, VSS = 0 Vdc, TA = –40 oC to +125 oC, unless otherwise noted
Advance Information
378
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
22.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
22.3
52-Pin Plastic Leaded Chip Carrier Package
(Case 778) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
22.2 Introduction
This section describes the dimensions of the 52-pin plastic leaded chip
carrier package.
The following figure shows the latest package at the time of this
publication. To make sure that you have the latest package
specifications, please visit the Freescale website at http://freescale.com.
Follow wwweb on-line instructions to retrieve the current mechanical
specifications.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
379
R E Q U I R E D
22.1 Contents
A G R E E M E N T
Section 22. Mechanical Specifications
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
0.007 (0.18)
B
Y BRK
–N–
M
T L–M
0.007 (0.18)
U
M
S
N
S
T L–M
S
N
S
D
Z
–M–
–L–
A G R E E M E N T
R E Q U I R E D
22.3 52-Pin Plastic Leaded Chip Carrier Package (Case 778)
W
D
52
1
V
A
0.007 (0.18)
M
T L–M
S
N
S
R
0.007 (0.18)
M
T L–M
S
N
S
E
C
0.004 (0.100)
–T– SEATING
J
VIEW S
G
PLANE
N O N - D I S C L O S U R E
G1
S
T L–M
S
H
N
S
0.007 (0.18)
M
T L–M
S
N
S
K1
K
F
VIEW S
Advance Information
380
S
T L–M
S
N
S
VIEW D–D
Z
0.010 (0.25)
G1
0.010 (0.25)
X
0.007 (0.18)
M
T L–M
S
N
S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE
TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT
MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED
AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE
BURRS AND INTERLEAD FLASH, BUT INCLUDING
ANY MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE
H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.785
0.795
0.785
0.795
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
–––
0.025
–––
0.750
0.756
0.750
0.756
0.042
0.048
0.042
0.048
0.042
0.056
–––
0.020
2_
10 _
0.710
0.730
0.040
–––
MILLIMETERS
MIN
MAX
19.94
20.19
19.94
20.19
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
–––
0.64
–––
19.05
19.20
19.05
19.20
1.07
1.21
1.07
1.21
1.07
1.42
–––
0.50
2_
10 _
18.04
18.54
1.02
–––
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
23.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
23.3
MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
23.4
Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .382
23.5
ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
23.6
ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . . 384
23.7
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
23.2 Introduction
This section contains instructions for ordering custom-masked ROM
MCUs.
23.3 MCU Ordering Forms
To initiate an order for a ROM-based MCU, first obtain the current
ordering form for the MCU from a Freescale representative. Submit the
following items when ordering MCUs:
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
•
A current MCU ordering form that is completely filled out
(Contact your Freescale sales office for assistance.)
•
A copy of the customer specification if the customer specification
deviates from the Freescale specification for the MCU
•
Customer’s application program on one of the media listed in 23.4
Application Program Media.
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381
R E Q U I R E D
23.1 Contents
A G R E E M E N T
Section 23. Ordering Information
N O N - D I S C L O S U R E
Advance Information — MC68HC08AS20
Please deliver the application program to Freescale in one of the
following media:
A G R E E M E N T
R E Q U I R E D
23.4 Application Program Media
•
Macintosh®1 3 1/2-inch diskette (double-sided 800 K or
double-sided high-density 1.4 M)
•
MS-DOS®2 or PC-DOSTM3 3 1/2-inch diskette (double-sided
720 K or double-sided high-density 1.44 M)
•
MS-DOS® or PC-DOSTM 5 1/4-inch diskette (double-sided
double-density 360 K or double-sided high-density 1.2 M)
Use positive logic for data and addresses.
N O N - D I S C L O S U R E
When submitting the application program on a diskette, clearly label the
diskette with the following information:
•
Customer name
•
Customer part number
•
Project or product name
•
File name of object code
•
Date
•
Name of operating system that formatted diskette
•
Formatted capacity of diskette
1. Macintosh is a registered trademark of Apple Computer, Inc.
2. MS-DOS is a registered trademark of Microsoft Corporation.
3. PC-DOS is a trademark of International Business Machines Corporation.
Advance Information
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Freescale Semiconductor
If the memory map has two user ROM areas with the same addresses,
then write the two areas in separate files on the diskette. Label the
diskette with both filenames.
In addition to the object code, a file containing the source code can be
included. Freescale keeps this code confidential and uses it only to
expedite ROM pattern generation in case of any difficulty with the object
code. Label the diskette with the filename of the source code.
R E Q U I R E D
Begin the application program at the first user ROM location. Program
addresses must correspond exactly to the available on-chip user ROM
addresses as shown in the memory map. Write $00 in all non-user
ROM locations or leave all non-user ROM locations blank. Refer to
the current MCU ordering form for additional requirements. Freescale
may request pattern resubmission if nonuser areas contain any non-zero
code.
A G R E E M E N T
On diskettes, the application program must be in Freescale’s S-record
format (S1 and S9 records), a character-based object file format
generated by M6805 cross assemblers and linkers.
The primary use for the on-chip ROM is to hold the customer’s
application program. The customer develops and debugs the application
program and then submits the MCU order along with the application
program.
Freescale enters the customer’s application program code into a
computer program that generates a listing verify file. The listing verify file
represents the memory map of the MCU. The listing verify file contains
the user ROM code and may also contain non-user ROM code, such as
selfcheck code. Freescale sends the customer a computer printout of
the listing verify file along with a listing verify form.
To aid the customer in checking the listing verify file, Freescale
programs the listing verify file into customer-supplied blank preformatted
Macintosh or DOS disks. All original pattern media are filed for
contractual purposes and are not returned.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
383
N O N - D I S C L O S U R E
23.5 ROM Program Verification
23.6 ROM Verification Units (RVUs)
After receiving the signed listing verify form, Freescale manufactures a
custom photographic mask. The mask contains the customer’s
application program and is used to process silicon wafers. The
application program cannot be changed after the manufacture of the
mask begins. Freescale then produces 10 MCUs, called RVUs, and
sends the RVUs to the customer. RVUs are usually packaged in
unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are
not tested to environmental extremes because their sole purpose is to
demonstrate that the customer’s user ROM pattern was properly
implemented. The 10 RVUs are free of charge with the minimum order
quantity. These units are not to be used for qualification or production.
RVUs are not guaranteed by Freescale Quality Assurance.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Check the listing verify file thoroughly, then complete and sign the listing
verify form and return the listing verify form to Freescale. The signed
listing verify form constitutes the contractual agreement for the creation
of the custom mask.
23.7 MC Order Numbers
Table 23-1. MC Order Numbers
MC Order Number
Operating
Temperature Range
MC68HC08AS20FN(1)
0 °C to + 70 °C
MC68HC08AS20CFN
– 40 °C to + 85 °C
MC68HC08AS20VFN
– 40 °C to + 105 °C
1. FN = plastic leaded chip carrier
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor
How to Reach Us:
Home Page:
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For Literature Requests Only:
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P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
[email protected]
Rev. 4.1
MC68HC08AS20/D
July 13, 2005
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