CY25702 Programmable High-Frequency Crystal Oscillator (XO) Features Benefits • Programmable High-frequency Crystal Oscillator (XO) • Wide output (CLK) range from: • Eliminates the need for external crystal oscillator. • Internal PLL to generate up to 125-MHz output. — 1.0 to 125 MHz (VDD = 5.0V) • Suitable for most PC, consumer and networking applications. — 1.0 to 90 MHz (VDD = 3.3V) • Application compatibility in standard and low-power systems. • Integrated phase-locked loop (PLL) • Low cycle-to-cycle Jitter • CY25701 can be used as a direct replacement in 3.3V applications if Spread Spectrum Clock (SSC) is required for EMI reduction without any PCB modification. • 3.3/5.0V operation • Output Enable function • Power-down function • In-house programming of samples and prototype quantities is available using the CY3672 programming kit and CY36xx socket adapter. Sample and production quantities are available through Cypress’s value-added distribution partners. • Refer to CY25701 for SSCG function • Lead-free package Pin Configuration Logic Block Diagram CY25702 4-pin Plastic SMD RFB PLL 1 OE/PD# VDD 4 2 VSS CLK 3 C XIN PROGRAMMABLE CONFIGURATION C XOUT OUTPUT DIVIDERS and MUX 3 CLK 1 OE/PD# 4 2 VDD VSS Cypress Semiconductor Corporation Document #: 38-07721 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised December 09, 2004 CY25702 Pin Definition Pin Name 1 Description OE/PD# Output Enable pin: Active HIGH. If OE = 1, CLK is enabled. Power Down pin: Active LOW. If PD# = 0, Power Down is enabled. 2 VSS Power supply ground. 3 CLK Clock output. 4 VDD 3.3V or 5.0V power supply. Functional Description The CY25702 uses a programmable configuration memory array to synthesize output frequency. The CY25702 is a Crystal Oscillator (XO). The device uses a Cypress proprietary PLL to synthesize the frequency of the embedded input crystal. The frequency CLK output can be programmed from 10–125 MHz. The CY25702 is available in a 4-pin plastic SMD packages with operating temperature range of –20 to 70°C. Table 1. Programming Data Requirement Pin Function Output Frequency Output Enable/Power Down Power Supply Pin Name CLK OE/PD# VDD Pin# 3 1 4 Units MHz N/A V Program Value ENTER DATA ENTER DATA ENTER DATA Programming Description synthesized clock is from 1–125MHz when VDD= 5V and 1–90MHz when VDD = 3.3V. Field/Factory-Programmable CY25702 Field/Factory programming is available for samples and manufacturing by Cypress and its distributors. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. Once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. This part number will be used for additional sample requests and production orders. Output Enable or Power Down (OE/PD#, pin 1) Pin 1 can be programmed as either output enable (OE) or Power Down (PD#). Absolute Maximum Rating Supply Voltage (VDD).....................................–0.5V to +7.0V DC Input Voltage ................................... –0.5V to VDD + 0.5V Additional information on the CY25702 can be obtained from the Cypress web site at www.cypress.com. Storage Temperature (Non-condensing) .... –55°C to +100°C Output Frequency, CLK Output (CLK, pin 3) Data Retention @ Tj = 125°C................................> 10 years The frequency at the CLK output is produced by synthesizing the embedded crystal oscillator frequency input. The range of Package Power Dissipation...................................... 350 mW Junction Temperature ................................ –40°C to +125°C Operating Conditions Min. Typ. Max. Unit VDD1 Parameter Supply Voltage Range Description 3.00 3.30 3.60 V VDD2 Supply Voltage Range 4.50 5.00 5.50 V TA Ambient Temperature –20 – 70 °C CLOAD Max. Load Capacitance @ pin 3 – – 15 pF FCLK1 CLK output frequency, CLOAD = 15 pF, VDD = 5.0V 1.0 – 125 MHz FCLK2 CLK output frequency, CLOAD = 15 pF, , VDD = 3.3V 1.0 – 90 MHz TPU Power-up time for VDD to reach minimum specified voltage (power ramp must be monotonic) 0.05 – 500 ms DC Electrical Characteristics Parameter Description Condition VOH1 High Output Voltage VDD = 5.0V, IOH = –16mA VOL1 Low Output Voltage VDD= 5.0V , IOL= 16mA Document #: 38-07721 Rev. ** Min. Typ. Max. Unit VDD-0.4 – – – V – 0.4 V Page 2 of 7 CY25702 DC Electrical Characteristics Parameter Description Condition VOH2 High Output Voltage VDD = 3.3V , IOH = –8mA VOL2 Low Output Voltage VDD= 3.3V , IOL = 8mA VIH1 Input High Voltage (pin 1) VDD = 5.0V VIL1 Input Low Voltage (pin 1) VIH2 Input High Voltage (pin 1) VIL2 Input Low Voltage (pin 1) IIH Input High Current (pin 1) IIL Input Low Current (pin 1) Vin = VSS IOZ Output Leakage Current (pin 3) Three-state output, OE = 0 CIN Input Capacitance (pin 1) IVDD1 Supply Current IVDD2 Supply Current IVDD3 Min. Typ. Max. Unit VDD-0.4 – – V – – 0.4 V 2.0 – – V VDD = 5.0V – – 0.8 V VDD = 3.3V 0.7VDD – – V VDD = 3.3V – – 0.2VDD V Vin = VDD – – 10 µA – – 10 µA –10 – 10 µA Pin 1, OE or PD# – 5 7 pF VDD = 3.3V, CLK = 1 to 90 MHz, CLOAD = 0, OE = VDD – – 28 mA VDD = 3.3V, CLK = 1 to 90 MHz, CLOAD = 0, OE = GND – – 16 mA Supply Current VDD = 5.0V, CLK = 1 to 125 MHz, CLOAD = 0, OE = VDD – – 45 mA IVDD4 Supply Current VDD = 5.0V, CLK = 1 to 125 MHz, CLOAD = 0, OE = GND – – 30 mA IPD# Power Down Current PD# = GND – – 50 µA FS Frequency Stability –20 to +70°C –50 – 50 ppm AG Aging Ta = 25°C, First Year –5 – 5 ppm SR Shock Resistance Three drops on a hard board from 750 mm or excitation test with 29.400m/s2 x 0.3ms x 1/2 sinewave in three directions –20 – 20 ppm Max. Unit AC Electrical Characteristics Parameter Description Condition Min. Typ. DC Output Duty Cycle CLK, Measured at VDD/2 40 50 60 % tR Output Rise Time 20%–80% of VDD, CL = 15 pF – – 4.0 ns tF Output Fall Time 20%–80% of VDD, CL = 15 pF – – 4.0 ns TOE1 Output Disable Time (pin1 = OE) Time from falling edge on OE to stopped outputs (Asynchronous) – 150 350 ns TOE2 Output Enable Time (pin1 = OE) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) – 150 350 ns TLOCK PLL Lock Time – – 10 ms TSU Start-up time out of Power Down PD# pin Low to High – – 5 ms TPDD Power Down Delay Time – – 25 ns Time for CLK to reach valid frequency PD# pin Low to CLK Low (Asynchronous) Application Circuit Power VDD (GND if PD#) 1 OE/PD# VDD 4 0.1uF CY25702 2 VSS Document #: 38-07721 Rev. ** CLK 3 Page 3 of 7 CY25702 Switching Waveforms Duty Cycle Timing (DC = t1A/t1B) t1A CLK t1B Output Rise/Fall Time VDD CLK 0V Tr Tf Output Rise time (Tr) = 20 to 80% of VDD Output Fall time (Tf) = 80 to 20% of VDD Output Enable/Disable Timing OUTPUT ENABLE VDD 0V VIH VIL TOE2 High Impedance CLK TOE1 Document #: 38-07721 Rev. ** Page 4 of 7 CY25702 Ordering Information Part Number[1,2] Package description Product Flow CY25702JXCZZZZ 4-Lead Plastic JE04A SMD – Lead-free Commercial, –20° to 70°C CY25702JXCZZZZT 4-Lead Plastic JE04A SMD, Tape and Reel – Lead-free Commercial, –20° to 70°C CY25702FJXC 4-Lead Plastic JE04A SMD – Lead-free Commercial, –20° to 70°C CY25702FJXCT 4-Lead Plastic JE04A SMD, Tape and Reel – Lead-free Commercial, –20° to 70°C CY25702XZZZ 4-Lead Plastic JE04B SMD – Lead-free Commercial, –20° to 70°C CY25702XZZZT 4-Lead Plastic JE04B SMD, Tape and Reel – Lead-free Commercial, –20° to 70°C CY25702FX 4-Lead Plastic JE04B SMD – Lead-free Commercial, –20° to 70°C CY25702FXT 4-Lead Plastic JE04B SMD, Tape and Reel – Lead-free Commercial, –20° to 70°C Package Drawings and Dimensions 4-Lead JEC JE04A 10.2±0.3 (10.5 MAX) 4 1.0±0.2 (1.0) 3.6 5.0 5.6±0.2 (5.8 MAX) 1.0±0.2 (1.0) 1 1.3 2.1 2.4 +0.2 -0.1 2.5 (2.7 MAX) 4.6 0.1 0.15±0.1 (0.05 MIN) 0.51 5.08±0.1 DIMENSIONS IN MILLIMETERS REFERENCE JEDEC: N/A PKG. WEIGHT: 0.24 gms 5.08 RECOMMENDED SOLDERING PATTERN 51-85204-*A Notes: 1. “ZZZZ” or “ZZZ” denotes the assigned product dash number. This number will be assigned by factory after the output frequency and spread percent programming data is received from the customer. 2. “FJXC” or “FX” suffix is used for products programmed in field by Cypress distributors. Document #: 38-07721 Rev. ** Page 5 of 7 CY25702 Package Drawings and Dimensions (continued) 4-Lead JE (5.0 x 2.8 MM) JE04B 5.0±0.2 4 0.35 MIN. 2.8 3.2±0.2 2.5±0.2 0.35 MIN. 1 0.5 1.0 1.6 1.1±0.1 1.2 MAX. 1.5 0.1 2.54±0.1 0.05±0.05 (0 MIN.) 2.2 DIMENSIONS IN MILLIMETERS REFERENCE JEDEC: N/A PKG. WEIGHT: 0.034 gms 2.54 RECOMMENDED SOLDERING PATTERN 51-85212-** All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07721 Rev. ** Page 6 of 7 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY25702 Document History Page Document Title: CY25702 Programmable High-Frequency Crystal Oscillator (XO) Document Number: 38-07721 REV. ECN NO. Issue Date Orig. of Change ** 296081 See ECN RGL Document #: 38-07721 Rev. ** Description of Change New data sheet Page 7 of 7