Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators ADCMP600/ADCMP601/ADCMP602 Fully specified rail to rail at VCC = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCC + 0.2 V Low glitch CMOS-/TTL-compatible output stage 3.5 ns propagation delay 10 mW at 3.3 V Shutdown pin Single-pin control for programmable hysteresis and latch Power supply rejection > 50 dB Improved replacement for MAX999 −40°C to +125°C operation FUNCTIONAL BLOCK DIAGRAM NONINVERTING INPUT INVERTING INPUT ADCMP600/ ADCMP601/ ADCMP602 LE/HYS (EXCEPT ADCMP600) SDN (ADCMP602 ONLY) Q OUTPUT 05914-001 FEATURES Figure 1. APPLICATIONS High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current/voltage-controlled oscillators Automatic test equipment (ATE) GENERAL DESCRIPTION The ADCMP600, ADCMP601, and ADCMP602 are very fast comparators fabricated on XFCB2, an Analog Devices, Inc. proprietary process. These comparators are exceptionally versatile and easy to use. Features include an input range from VEE − 0.5 V to VCC + 0.2 V, low noise, TTL-/CMOS-compatible output drivers, and latch inputs with adjustable hysteresis and/or shutdown inputs. The device offers 5 ns propagation delay with 10 mV overdrive on 3 mA typical supply current. A flexible power supply scheme allows the devices to operate with a single +2.5 V positive supply and a −0.5 V to +2.8 V input signal range up to a +5.5 V positive supply with a −0.5 V to +5.8 V input signal range. Split input/output supplies with no sequencing restrictions on the ADCMP602 support a wide input signal range while still allowing independent output swing control and power savings. The TTL-/CMOS-compatible output stage is designed to drive up to 5 pF with full timing specs and to degrade in a graceful and linear fashion as additional capacitance is added. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. Latch and programmable hysteresis features are also provided with a unique single-pin control option. The ADCMP600 is available in 5-lead SC70 and SOT-23 packages, the ADCMP601 is available in a 6-lead SC70 package, and the ADCMP602 is available in an 8-lead MSOP package. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADCMP600/ADCMP601/ADCMP602 TABLE OF CONTENTS Features .............................................................................................. 1 Power/Ground Layout and Bypassing..................................... 10 Applications....................................................................................... 1 TTL-/CMOS-Compatible Output Stage ................................. 10 Functional Block Diagram .............................................................. 1 Using/Disabling the Latch Feature........................................... 10 General Description ......................................................................... 1 Optimizing Performance........................................................... 11 Revision History ............................................................................... 2 Comparator Propagation Delay Dispersion ........................... 11 Specifications..................................................................................... 3 Comparator Hysteresis .............................................................. 11 Electrical Characteristics............................................................. 3 Crossover Bias Point .................................................................. 12 Timing Information ......................................................................... 5 Minimum Input Slew Rate Requirement ................................ 12 Absolute Maximum Ratings............................................................ 6 Typical Application Circuits ......................................................... 13 Thermal Resistance ...................................................................... 6 Outline Dimensions ....................................................................... 14 Pin Configuration and Function Descriptions............................. 7 Ordering Guide .......................................................................... 14 Typical Performance Characteristics ............................................. 8 Application Information................................................................ 10 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADCMP600/ADCMP601/ADCMP602 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VCCI = VCCO = 2.5 V, TA = 25°C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Voltage Range Common-Mode Range Differential Voltage Offset Voltage Bias Current Offset Current Capacitance Resistance, Differential Mode Resistance, Common Mode Active Gain Common-Mode Rejection Ratio Hysteresis (ADCMP600) Hysteresis (ADCMP601/ADCMP602) LATCH ENABLE PIN CHARACTERISTICS (ADCMP601/ADCMP602 Only) VIH VIL IIH IOL HYSTERESIS MODE AND TIMING (ADCMP601/ADCMP602 Only) Hysteresis Mode Bias Voltage Resistor Value Hysteresis Current Latch Setup Time Latch Hold Time Latch-to-Output Delay Latch Minimum Pulse Width SHUTDOWN PIN CHARACTERISTICS (ADCMP602 Only) VIH VIL IIH IOL Sleep Time Wake-Up Time DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level Output Voltage High Level at −40°C Output Voltage Low Level at− 40°C Symbol Conditions Min VP, VN VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V −0.5 −0.2 VOS IP, IN −5.0 −5.0 −2.0 CP, CN AV CMRR −0.1 V to VCC −0.5 V to VCC + 0.5 V 200 100 VCCI = 2.5 V, VCCO = 2.5 V, VCM = −0.2 V to +2.7 V VCCI = 2.5 V, VCCO = 5.5 V 50 tSD tH VOH VOL VOH VOL Unit VCC + 0.2 VCC + 0.2 VCC + 0.8 +5.0 +5.0 +2.0 V V V mV μA μA pF kΩ kΩ dB dB 1 700 350 85 dB mV mV 2 0.1 Hysteresis is shut off Latch mode guaranteed VIH = VCC VIL = 0.4 V 2.0 −0.2 −6 −0.1 Current −1 μA Hysteresis = 120 mV Hysteresis = 120 mV VOD = 50 mV VOD = 50 mV VOD = 50 mV VOD = 50 mV 1.145 65 −18 Comparator is operating Shutdown guaranteed VIH = VCC VIL = 0 V ICCO < 500 μA VOD = 100 mV, output valid VCCO = 2.5 V to 5.5 V IOH = 8 mA, VCCO = 2.5 V IOL = 8 mA, VCCO = 2.5 V IOH = 6 mA, VCCO = 2.5 V IOL = 6 mA, VCCO = 2.5 V 2.0 −0.2 −6 Rev. 0 | Page 3 of 16 ±2 ±2 Max 50 RHYS = ∞ tS tH tPLOH, tPLOL tPL Typ +0.4 1.25 80 −12 −2 2.6 27 21 +0.4 VCC +0.8 +6 +0.1 V V μA mA 1.35 120 −7 V kΩ μA ns ns ns ns VCCO +0.6 6 V V μA μA ns ns −100 20 50 VCC − 0.4 0.4 VCC − 0.4 0.4 V V V V ADCMP600/ADCMP601/ADCMP602 Parameter AC PERFORMANCE 1 Rise Time /Fall Time Propagation Delay Symbol Conditions tR tF 10% to 90%, VCCO = 2.5 V 10% to 90%, VCCO = 5.5 V VOD = 50 mV, VCCO = 2.5 V VOD = 50 mV, VCCO = 5.5 V VOD = 10 mV, VCCO = 2.5 V VCCO = 2.5 V to 5.5 V VOD = 50 mV 10 mV < VOD < 125 mV −0.2 V < VCM < VCCI + 2 V VOD = 50 mV VCCI = VCCO = 2.5 V PWOUT = 90% of PWIN VCCI = VCCO = 5.5 V PWOUT = 90% of PWIN tPD Propagation Delay Skew—Rising to Falling Transition Overdrive Dispersion Common-Mode Dispersion Minimum Pulse Width POWER SUPPLY Input Supply Voltage Range Output Supply Voltage Range Positive Supply Differential (ADCMP602 Only) Positive Supply Current (ADCMP600/ADCMP601) Input Section Supply Current (ADCMP602 Only) Output Section Supply Current (ADCMP602 Only) Power Dissipation Power Supply Rejection Ratio Shutdown Mode ICCI (ADCMP602 Only) Shutdown Mode ICCO (ADCMP602 Only) 1 PWMIN VCCI VCCO VCCI − VCCO VCCI − VCCO IVCC IVCCI IVCCO PD PD PSRR Operating Nonoperating VCC = 2.5 V VCC = 5.5 V VCCI = 2.5 V VCCI = 5.5 V VCCO = 2.5 V VCCO = 5.5 V VCC = 2.5 V VCC = 5.5 V VCCI = 2.5 V to 5 V VCC = 2.5 V VCC =2.5 V VIN = 100 mV square input at 50 MHz, VCM = 0 V, CL = 5 pF, VCCI = VCCO =2.5 V, unless otherwise noted. Rev. 0 | Page 4 of 16 Min Typ Max Unit 2.2 4 3.5 4.3 5 500 ns ns ns ns ns ps 1.2 200 ns ps 3 ns 4.5 ns 2.5 2.5 −3.0 5.5 5.5 +3.0 V V V 3 3.5 0.9 1.2 1.45 2.1 7 20 +5.5 3.5 4.0 1.4 2.0 3.0 3.5 9 23 V mA 240 400 mA mA mA mA mW mW dB μA 30 μA −5.5 −50 ADCMP600/ADCMP601/ADCMP602 TIMING INFORMATION Figure 2 illustrates the ADCMP600/ADCMP601/ADCMP602 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2. 1.1V LATCH ENABLE tS tPL tH DIFFERENTIAL INPUT VOLTAGE VIN VN ± VOS VOD tPDL tPLOH Q OUTPUT tF 05914-025 50% Figure 2. System Timing Diagram Table 2. Timing Descriptions Symbol tPDH Timing Input to output high delay tPDL Input to output low delay tPLOH Latch enable to output high delay tPLOL Latch enable to output low delay tH Minimum hold time tPL tS Minimum latch enable pulse width Minimum setup time tR Output rise time tF Output fall time VOD Voltage overdrive Description Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum time that the latch enable signal must be high to acquire an input signal change. Minimum time before the negative transition of the latch enable signal occurs that an input signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Difference between the input voltages VA and VB. Rev. 0 | Page 5 of 16 ADCMP600/ADCMP601/ADCMP602 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Parameter Supply Voltages Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Positive Supply Differential (VCCI − VCCO) Input Voltages Input Voltage Differential Input Voltage Maximum Input/Output Current Shutdown Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Latch/Hysteresis Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Output Current Temperature Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Rating −0.5 V to +6.0 V −0.5 V to +6.0 V −6.0 V to +6.0 V THERMAL RESISTANCE −0.5 V to VCCI + 0.5 V ±(VCCI + 0.5 V) ±50 mA −0.5 V to VCCO + 0.5 V ±50 mA −0.5 V to VCCO + 0.5 V ±50 mA ±50 mA θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type ADCMP600 SC70 5-Lead ADCMP600 SOT-23 5-Lead ADCMP601 SC70 6-Lead ADCMP602 MSOP 5-Lead 1 Measurement in still air. ESD CAUTION −40°C to +125°C 150°C −65°C to +150°C Rev. 0 | Page 6 of 16 θJA1 426 302 426 130 Unit °C/W °C/W °C/W °C/W ADCMP600/ADCMP601/ADCMP602 5 4 VN 6 VCCI /VCCO 5 LE/HYS VCCI 1 ADCMP601 VEE 2 TOP VIEW (Not to Scale) VP 3 Q 1 VCCI /VCCO Figure 3. ADCMP600 Pin Configuration TOP VIEW (Not to Scale) VP 3 4 VN VP 2 05914-003 VEE 2 ADCMP600 05914-002 Q 1 Figure 4. ADCMP601 Pin Configuration VN 3 SDN 4 ADCMP602 TOP VIEW (Not to Scale) 8 VCCO 7 Q 6 VEE 5 LE/HYS 05914-004 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. ADCMP602 Pin Configuration Table 5. ADCMP600 (SOT-23-5 and SC70-5) Pin Function Descriptions Pin No. 1 Mnemonic Q 2 3 4 5 VEE VP VN VCCI/VCCO Description Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN. Negative Supply Voltage. Noninverting Analog Input. Inverting Analog Input. Input Section Supply/Output Section Supply. Shared pin. Table 6. ADCMP601 (SC70-6) Pin Function Descriptions Pin No. 1 Mnemonic Q 2 3 4 5 6 VEE VP VN LE/HYS VCCI/VCCO Description Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. Negative Supply Voltage. Noninverting Analog Input. Inverting Analog Input. Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch. Input Section Supply/Output Section Supply. Shared pin. Table 7. ADCMP602 (MSOP-8) Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 Mnemonic VCCI VP VN SDN LE/HYS VEE Q 8 VCCO Description Input Section Supply. Noninverting Analog Input. Inverting Analog Input. Shutdown. Drive this pin low to shut down the device. Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch. Negative Supply Voltage. Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. Output Section Supply. Rev. 0 | Page 7 of 16 ADCMP600/ADCMP601/ADCMP602 TYPICAL PERFORMANCE CHARACTERISTICS VCCI = VCCO = 2.5 V, TA = 25°C, unless otherwise noted. 800 20 600 15 IOL VS VOL IOH VS VOH VCC = 5.5V VCC = 2.5V 10 0 –200 5 0 –5 –400 –10 –600 –15 –800 –1 0 1 2 3 4 LE/HYS (V) 5 6 –20 –1.0 –0.6 –0.2 0.2 7 1.4 1.8 2.2 2.6 3.0 3.4 250 VCC = 2.5V 100 VCC = 5.5V 200 50 HYSTERESIS (mV) 0 –50 VCC = 5.5V 150 100 50 –100 05914-027 VCC = 2.5V –150 –1 0 1 2 3 4 5 6 05914-008 CURRENT (µA) 1.0 Figure 9. VOH/VOL vs. Current Load 150 0 7 50 SHUTDOWN PIN VOLTAGE (V) Figure 7. SDN Pin I/V Characteristics 150 250 350 450 HYSTERESIS RESISTOR (kΩ) 550 650 Figure 10. Hysteresis vs. RHYS Control Resistor 450 VCC = 2.5V 400 15 350 HYSTERESIS (mV) 10 5 0 –5 IB @ +125°C IB @ –40°C –0.5 0 0.5 1.0 1.5 2.0 2.5 COMMON-MODE VOLTAGE (V) 250 LOT 2 200 150 100 IB @ +25°C –15 –20 –1.0 LOT 1 300 50 3.0 0 3.5 05914-026 –10 05914-005 IB (µA) 0.6 VOUT (V) Figure 6. LE/HYS Pin I/V Characteristics 20 09514-011 LOAD CURRENT (mA) 200 05914-007 CURRENT (µA) 400 0 –5 –10 –15 PIN CURRENT (µA) Figure 11. Hysteresis vs. Pin Current Figure 8. Input Bias Current vs. Input Common Mode Rev. 0 | Page 8 of 16 –20 ADCMP600/ADCMP601/ADCMP602 4.8 4.4 4.2 4.0 3.8 3.6 3.4 3.0 05914-009 3.2 05914-012 PROPAGATION DELAY (ns) 4.6 0 10 20 30 40 50 60 70 80 1.00V/DIV 90 100 110 120 130 140 M4.00ns OVERDRIVE (mV) Figure 12. Propagation Delay vs. Input Overdrive at VCC = 2.5 V Figure 15. 50 MHz Output Waveform VCC = 5.5 V 4.0 PROPAGATION DELAY (ns) VCM AT VCC = 2.5V 3.8 3.6 RISE 3.4 FALL 0 0.6 1.2 1.8 2.4 05914-013 3.0 –0.6 05914-028 3.2 3.0 COMMON-MODE VOLTAGE (V) 500mV/DIV 5.0 4.6 4.4 4.2 4.0 RISE 3.6 FALL 3.4 05914-029 PROPAGATION DELAY (ns) 4.8 3.8 3.2 3.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 M4.00ns Figure16. 50 MHz Output Waveforms @ 2.5 V Figure 13. Propagation Delay vs. Input Common-Mode Voltage at VCC = 2.5 V 6.0 VCCO (V) Figure 14. Propagation Delay vs. VCCO Rev. 0 | Page 9 of 16 ADCMP600/ADCMP601/ADCMP602 APPLICATION INFORMATION The ADCMP600/ADCMP601/ADCMP602 comparators are very high speed devices. Despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. Multiple high quality 0.01 μF bypass capacitors should be placed as close as possible to each of the VCCI and VCCO supply pins and should be connected to the GND plane with redundant vias. At least one of these should be placed to provide a physically short return path for output currents flowing back from ground to the VCC pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. If the package allows and the input and output supplies have been connected separately such that VCCI ≠ VCCO, care should be taken to bypass each of these supplies separately to the GND plane. A bypass capacitor should never be connected between them. It is recommended that the GND plane separate the VCCI and VCCO planes when the circuit board layout is designed to minimize coupling between the two supplies and to take advantage of the additional bypass capacitance from each respective supply to the ground plane. This enhances the performance when split input/output supplies are used. If the input and output supplies are connected together for single-supply operation such that VCCI = VCCO, coupling between the two supplies is unavoidable; however, careful board placement can help keep output return currents away from the inputs. TTL-/CMOS-COMPATIBLE OUTPUT STAGE Specified propagation delay performance can be achieved only by keeping the capacitive load at or below the specified minimums. The outputs of the devices are designed to directly drive one Schottky TTL or three low power Schottky TTL loads or the equivalent. For large fan outputs, buses, or transmission lines, use an appropriate buffer to maintain the excellent speed and stability of the comparator. With the rated 5 pF load capacitance applied, more than half of the total device propagation delay is output stage slew time, even at 2.5 V VCC. Because of this, the total prop delay decreases as VCCO decreases, and instability in the power supply may appear as excess delay dispersion. This delay is measured to the 50% point for the supply in use; therefore, the fastest times are observed with the VCC supply at 2.5 V, and larger values are observed when driving loads that switch at other levels. When duty cycle accuracy is critical, the logic being driven should switch at 50% of VCC and load capacitance should be minimized. When in doubt, it is best to power VCCO or the entire device from the logic supply and rely on the input PSRR and CMRR to reject noise. Overdrive and input slew rate dispersions are not significantly affected by output loading and VCC variations. The TTL-/CMOS-compatible output stage is shown in the simplified schematic diagram (Figure 17). Because of its inherent symmetry and generally good behavior, this output stage is readily adaptable for driving various filters and other unusual loads. VLOGIC A1 Q1 +IN –IN OUTPUT AV A2 GAIN STAGE Q2 OUTPUT STAGE 05914-014 POWER/GROUND LAYOUT AND BYPASSING Figure 17. Simplified Schematic Diagram of TTL-/CMOS-Compatible Output Stage USING/DISABLING THE LATCH FEATURE The latch input is designed for maximum versatility. It can safely be left floating for fixed hysteresis or be tied to VCC to remove the hysteresis, or it can be driven low by any standard TTL/CMOS device as a high speed latch. In addition, the pin can be operated as a hysteresis control pin with a bias voltage of 1.25 V nominal and an input resistance of approximately 7000 Ω. This allows the comparator hysteresis to be easily and accurately controlled by either a resistor or an inexpensive CMOS DAC. Hysteresis control and latch mode can be used together if an open drain, an open collector, or a three-state driver is connected parallel to the hysteresis control resistor or current source. Due to the programmable hysteresis feature, the logic threshold of the latch pin is approximately 1.1 V regardless of VCC. Rev. 0 | Page 10 of 16 ADCMP600/ADCMP601/ADCMP602 OPTIMIZING PERFORMANCE INPUT VOLTAGE 1V/ns COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP600/ADCMP601/ADCMP602 comparators are designed to reduce propagation delay dispersion over a wide input overdrive range. Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (that is, how far or how fast the input signal exceeds the switching threshold). Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instrumentation. It is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (Figure 18 and Figure 19). VN ± VOS 10V/ns 05914-016 DISPERSION Q/Q OUTPUT Figure 19. Propagation Delay—Slew Rate Dispersion COMPARATOR HYSTERESIS The addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. Figure 20 shows the transfer function for a comparator with hysteresis. As the input voltage approaches the threshold (0.0 V, in this example) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +VH/2, and the new switching threshold becomes −VH/2. The comparator remains in the high state until the new threshold, −VH/2, is crossed from below the threshold region in a negative direction. In this manner, noise or feedback output signals centered on 0.0 V input cannot cause the comparator to switch states unless it exceeds the region bounded by ±VH/2. OUTPUT VOH VOL The device dispersion is typically < 2 ns as the overdrive varies from 10 mV to 125 mV. This specification applies to both positive and negative signals because the device has very closely matched delays both positive-going and negative-going inputs. –VH 2 500mV OVERDRIVE 0 +VH 2 INPUT 05914-017 As with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. Stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. Large discontinuities along input and output transmission lines can also limit the specified pulsewidth dispersion performance. The source impedance should be minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. Thermal noise from large resistances can easily cause extra jitter with slowly slewing input signals; higher impedances encourage undesired coupling. Figure 20. Comparator Hysteresis Transfer Function INPUT VOLTAGE 10mV OVERDRIVE DISPERSION Q/Q OUTPUT 05914-015 VN ± VOS Figure 18. Propagation Delay—Overdrive Dispersion The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. One limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that reduce high speed performance and induce oscillation in some cases. These ADCMP600 features a fixed hysteresis of approximately 2 mV. The ADCMP601 and ADCMP602 comparators offer a programmable Hysteresis feature that can significantly improve accuracy and stability. Connecting an external pull-down resistor or a current source from the LE/HYS pin to GND, varies the amount of hysteresis in a predictable, stable manner. Rev. 0 | Page 11 of 16 ADCMP600/ADCMP601/ADCMP602 200 VCC = 5.5V 150 100 50 VCC = 2.5V 05914-030 The hysteresis control pin appears as a 1.25 V bias voltage seen through a series resistance of 7 kΩ ± 20% throughout the hysteresis control range. The advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. An external bypass capacitor is not recommended on the HYS pin because it impairs the latch function and often degrades the jitter performance of the device. As described in the Using/Disabling the Latch Feature section, hysteresis control need not compromise the latch function. 250 HYSTERESIS (mV) Leaving the LE/HYS pin disconnected results in a fixed hysteresis of 2 mV; driving this pin high removes hysteresis. The maximum hysteresis that can be applied using this pin is approximately 160 mV. Figure 21 illustrates the amount of hysteresis applied as a function of the external resistor value, and Figure 11 illustrates hysteresis as a function of the current. 0 50 150 250 350 450 HYSTERESIS RESISTOR (kΩ) 550 650 Figure 21. Hysteresis vs. RHYS Control Resistor MINIMUM INPUT SLEW RATE REQUIREMENT CROSSOVER BIAS POINT In both op amps and comparators, rail-to-rail inputs of this type have a dual front-end design. Certain devices are active near the VCC rail and others are active near the VEE rail. At some predetermined point in the common-mode range, a crossover occurs. At this point, normally VCC/2, the direction of the bias current reverses and the measured offset voltages and currents change. The ADCMP600/ADCMP601/ADCMP602 comparators slightly elaborate on this scheme. Crossover points can be found at approximately 0.8 V and 1.6 V. With the rated load capacitance and normal good PC Board design practice, as discussed in the Optimizing Performance section, these comparators should be stable at any input slew rate with no hysteresis. Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. With additional capacitive loading or poor bypassing, oscillation is observed. This oscillation is due to the high gain bandwidth of the comparator in combination with feedback parasitics in the package and PC board. In many applications, chattering is not harmful. Rev. 0 | Page 12 of 16 ADCMP600/ADCMP601/ADCMP602 TYPICAL APPLICATION CIRCUITS 5V 0.1µF 2.5V ADCMP600 OUTPUT 0.1µF ADCMP600 Figure 22. Self-Biased, 50% Slicer INPUT 1.25V ±50mV INPUT 1.25V REF CMOS VDD 2.5V TO 5V ADCMP600 10kΩ 10kΩ ADCMP601 CMOS 10kΩ 82pF LE/HYS 40kΩ 05914-020 100Ω CMOS PWM OUTPUT Figure 23. LVDS-to-CMOS Receiver 05914-022 2kΩ 05914-019 2kΩ Figure 25. Oscillator and Pulse-Width Modulator 2.5V TO 5V 2.5V ADCMP601 ADCMP601 CONTROL VOLTAGE 0V TO 2.5V 82pF 100kΩ DIGITAL INPUT LE/HYS 100kΩ 05914-021 20kΩ OUTPUT 1.5MHz TO 30MHz HYSTERESIS CURRENT Figure 24. Voltage-Controlled Oscillator 74 AHC 1G07 LE/HYS 10kΩ Figure 26. Hysteresis Adjustment with Latch Rev. 0 | Page 13 of 16 05914-023 10kΩ 20kΩ ADCMP600/ADCMP601/ADCMP602 OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 1.25 1.15 5 1 2.20 2.00 1.80 2.40 2.10 1.80 4 2 3 PIN 1 1.35 1.25 1.15 0.40 0.10 1.10 0.80 0.30 0.15 0.10 MAX 5 4 1 2 3 2.40 2.10 1.80 PIN 1 0.65 BSC 1.00 0.90 0.70 6 1.00 0.90 0.70 0.46 0.36 0.26 0.22 0.08 SEATING PLANE 0.65 BSC 1.30 BSC 1.10 0.80 0.30 0.15 0.10 MAX 0.10 COPLANARITY 0.40 0.10 SEATING PLANE 0.46 0.36 0.26 0.22 0.08 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203-AA COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 27. 5-Lead Thin Shrink Small Outline Transistor Package (SC70) (KS-5) Dimensions shown in millimeters Figure 29. 6-Lead Thin Shrink Small Outline Transistor Package (SC70) (KS-6) Dimensions shown in millimeters 3.20 3.00 2.80 2.90 BSC 5 4 2.80 BSC 1.60 BSC 1 2 8 3.20 3.00 2.80 3 1 PIN 1 0.95 BSC 4 0.65 BSC 1.45 MAX 0.15 MAX 5.15 4.90 4.65 PIN 1 1.90 BSC 1.30 1.15 0.90 5 0.50 0.30 SEATING PLANE 0.95 0.85 0.75 0.22 0.08 10° 5° 0° 1.10 MAX 0.15 0.00 0.60 0.45 0.30 0.38 0.22 COPLANARITY 0.10 0.23 0.08 0.80 0.60 0.40 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-178-AA COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 28. 5-Lead Small Outline Transistor Package (SOT-23) (RJ-5) Dimensions shown in millimeters Figure 30. 8-Lead Mini Small Outline Package (MSOP) (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model ADCMP600BRJZ-R2 1 ADCMP600BRJZ-RL1 ADCMP600BRJZ-REEL71 ADCMP600BKSZ-R21 ADCMP600BKSZ-RL1 ADCMP600BKSZ-REEL71 ADCMP601BKSZ-R21 ADCMP601BKSZ-RL1 ADCMP601BKSZ-REEL71 ADCMP602BRMZ1 ADCMP602BRMZ-REEL1 ADCMP602BRMZ-REEL71 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 5-Lead SOT23 5-Lead SOT23 5-Lead SOT23 5-Lead SC70 5-Lead SC70 5-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Z = Pb-free part. Rev. 0 | Page 14 of 16 Package Option RJ-5 RJ-5 RJ-5 KS-5 KS-6 KS-6 KS-6 KS-6 KS-6 RM-8 RM-8 RM-8 Branding G0C G0C G0C G0C G0C G0C G0N G0N G0N GF GF GF ADCMP600/ADCMP601/ADCMP602 NOTES Rev. 0 | Page 15 of 16 ADCMP600/ADCMP601/ADCMP602 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05914-0-10/06(0) Rev. 0 | Page 16 of 16