MC74HC4066A Quad Analog Switch/ Multiplexer/Demultiplexer High−Performance Silicon−Gate CMOS The MC74HC4066A utilizes silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low O F F −c h a n n e l l e a k a g e c u r r e n t . T h i s b i l a t e r a l s w i t c h / multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power−supply range (from VCC to GND). The HC4066A is identical in pinout to the metal−gate CMOS MC14016 and MC14066. Each device has four independent switches. The device has been designed so the ON resistances (RON) are more linear over input voltage than RON of metal−gate CMOS analog switches. The ON/OFF control inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. For analog switches with voltage−level translators, see the HC4316A. Features • • • • • • • • • • http://onsemi.com MARKING DIAGRAMS 14 PDIP−14 MC74HC4066AN N SUFFIX AWLYYWWG CASE 646 14 1 1 14 SOIC−14 D SUFFIX CASE 751A 14 Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Wide Power−Supply Voltage Range (VCC − GND) = 2.0 to 12.0 V Analog Input Voltage Range (VCC − GND) = 2.0 to 12.0 V Improved Linearity and Lower ON Resistance over Input Voltage than the MC14016 or MC14066 Low Noise Chip Complexity: 44 FETs or 11 Equivalent Gates Pb−Free Packages are Available 1 HC4066AG AWLYWW 1 14 14 1 TSSOP−14 DT SUFFIX CASE 948G 1 HC40 66A ALYW 14 14 1 SOEIAJ−14 F SUFFIX CASE 965 74HC4066A ALYWG 1 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 8 1 Publication Order Number: MC74HC4066A/D MC74HC4066A PIN ASSIGNMENT LOGIC DIAGRAM XA 1 14 VCC YA 2 13 A ON/OFF CONTROL YB 3 12 D ON/OFF CONTROL XB 4 11 XD B ON/OFF CONTROL 5 10 YD C ON/OFF CONTROL 6 9 YC B ON/OFF CONTROL GND 7 8 XC XC XA A ON/OFF CONTROL XB C ON/OFF CONTROL XD FUNCTION TABLE On/Off Control Input State of Analog Switch L H Off On D ON/OFF CONTROL 1 2 YA 13 4 3 YB 5 8 9 YC ANALOG OUTPUTS/INPUTS 6 11 10 YD 12 ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD PIN 14 = VCC PIN 7 = GND ORDERING INFORMATION Device Package MC74HC4066AN PDIP−14 MC74HC4066ANG PDIP−14 (Pb−Free) MC74HC4066AD SOIC−14 MC74HC4066ADG SOIC−14 (Pb−Free) MC74HC4066ADR2 SOIC−14 MC74HC4066ADR2G SOIC−14 (Pb−Free) MC74HC4066ADTR2 TSSOP−14* MC74HC4066ADTR2G TSSOP−14* MC74HC4066AFEL SOEIAJ−14 MC74HC4066AFELG SOEIAJ−14 (Pb−Free) Shipping† 25 Units / Rail 55 Units / Rail 2500 / Tape & Reel 2000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 2 MC74HC4066A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Unit VCC Positive DC Supply Voltage (Referenced to GND) – 0.5 to + 14.0 V VIS Analog Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Vin Digital Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Current Into or Out of Any Pin ± 25 mA PD Power Dissipation in Still Air, 750 500 450 mW Tstg Storage Temperature – 65 to + 150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) I Plastic DIP† EIAJ/SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. °C 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating − Plastic DIP: – 10 mW/°C from 65° to 125°C EIAJ/SOIC Package: – 7 mW/°C from 65° to 125°C TSSOP Package: − 6.1 mW/°C from 65° to 125°C For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 2.0 12.0 V VCC Positive DC Supply Voltage (Referenced to GND) VIS Analog Input Voltage (Referenced to GND) GND VCC V Vin Digital Input Voltage (Referenced to GND) GND VCC V VIO* Static or Dynamic Voltage Across Switch − 1.2 V –55 + 125 °C 0 0 0 0 0 1000 600 500 400 250 TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time, ON/OFF Control Inputs (Figure 10) ns VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 9.0 V VCC = 12.0 V *For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V – 55 to 25°C v 85°C v 125°C Unit VIH Minimum High−Level Voltage ON/OFF Control Inputs Ron = Per Spec 2.0 3.0 4.5 9.0 12.0 1.5 2.1 3.15 6.3 8.4 1.5 2.1 3.15 6.3 8.4 1.5 2.1 3.15 6.3 8.4 V VIL Maximum Low−Level Voltage ON/OFF Control Inputs Ron = Per Spec 2.0 3.0 4.5 9.0 12.0 0.5 0.9 1.35 2.7 3.6 0.5 0.9 1.35 2.7 3.6 0.5 0.9 1.35 2.7 3.6 V Iin Maximum Input Leakage Current ON/OFF Control Inputs Vin = VCC or GND 12.0 ± 0.1 ± 1.0 ± 1.0 A ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND VIO = 0 V 6.0 12.0 2 4 20 40 40 160 A NOTE: Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D). http://onsemi.com 3 MC74HC4066A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND) Guaranteed Limit Symbol Ron Parameter VCC V – 55 to 25°C v 85°C v 125°C Unit Vin = VIH VIS = VCC to GND IS v 2.0 mA (Figures 1, 2) 2.0† 3.0† 4.5 9.0 12.0 − − 120 70 70 − − 160 85 85 − − 200 100 100 Vin = VIH VIS = VCC or GND (Endpoints) IS v 2.0 mA (Figures 1, 2) 2.0 3.0 4.5 9.0 12.0 − − 70 50 50 − − 85 60 60 − − 120 80 80 Test Conditions Maximum “ON” Resistance Ron Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Vin = VIH VIS = 1/2 (VCC − GND) IS v 2.0 mA 2.0 4.5 9.0 12.0 − 20 15 15 − 25 20 20 − 30 25 25 Ioff Maximum Off−Channel Leakage Current, Any One Channel Vin = VIL VIO = VCC or GND Switch Off (Figure 3) 12.0 0.1 0.5 1.0 A Ion Maximum On−Channel Leakage Current, Any One Channel Vin = VIH VIS = VCC or GND (Figure 4) 12.0 0.1 0.5 1.0 A †At supply voltage (VCC) approaching 3 V the analog switch−on resistance becomes extremely non−linear. Therefore, for low−voltage operation, it is recommended that these devices only be used to control digital signals. NOTE: Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D). ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V – 55 to 25°C v 85°C v 125°C Unit tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9) 2.0 3.0 4.5 9.0 12.0 40 30 10 10 10 50 40 13 13 13 60 50 15 15 15 ns tPLZ, tPHZ Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 11) 2.0 3.0 4.5 9.0 12.0 80 60 30 25 25 90 70 38 28 28 110 80 45 30 30 ns tPZL, tPZH Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 1 1) 2.0 3.0 4.5 9.0 12.0 80 45 25 25 25 90 50 32 32 32 100 60 37 37 37 ns ON/OFF Control Input − 10 10 10 pF Control Input = GND Analog I/O Feedthrough − − 35 1.0 35 1.0 35 1.0 C Maximum Capacitance NOTES: 1. For propagation delays with loads other than 50 pF, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V 15 CPD Power Dissipation Capacitance (Per Switch) (Figure 13)* pF * Used to determine the no−load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). http://onsemi.com 4 MC74HC4066A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted) VCC V Limit* 25°C 54/74HC Symbol Parameter Test Conditions BW Maximum On−Channel Bandwidth or Minimum Frequency Response (Figure 5) fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads – 3 dB RL = 50 , CL = 10 pF 4.5 9.0 12.0 150 160 160 MHz Off−Channel Feedthrough Isolation (Figure 6) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF 4.5 9.0 12.0 − 50 − 50 − 50 dB fin = 1.0 MHz, RL = 50 , CL = 10 pF 4.5 9.0 12.0 − 40 − 40 − 40 Vin v 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 , CL = 50 pF 4.5 9.0 12.0 60 130 200 RL = 10 k, CL = 10 pF 4.5 9.0 12.0 30 65 100 fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF 4.5 9.0 12.0 – 70 – 70 – 70 fin = 1.0 MHz, RL = 50 , CL = 10 pF 4.5 9.0 12.0 – 80 – 80 – 80 − − − THD Feedthrough Noise, Control to Switch (Figure 7) Crosstalk Between Any Two Switches (Figure 12) Total Harmonic Distortion (Figure 14) fin = 1 kHz, RL = 10 k, CL = 50 pF THD = THDMeasured − THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave *Guaranteed limits not tested. Determined by design and verified by qualification. http://onsemi.com 5 Unit mVPP dB % 4.5 9.0 12.0 0.10 0.06 0.04 MC74HC4066A 400 350 RON @ 2 V 300 250 200 150 +25 °C +125°C −55°C 100 50 0 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND Figure 1a. Typical On Resistance, VCC = 2.0 V 200 180 RON @ 3 V 160 140 120 100 80 60 +25 °C +125°C −55°C 40 20 0 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00 Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND Figure 1b. Typical On Resistance, VCC = 3.0 V 200 180 RON @ 4.5 V 160 140 +25 °C +125°C −55°C 120 100 80 60 40 20 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND Figure 1c. Typical On Resistance, VCC = 4.5 V http://onsemi.com 6 4.00 4.50 MC74HC4066A 90 80 RON @ 6 V 70 60 50 40 30 +25 °C +125°C −55°C 20 10 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND Figure 1d. Typical On Resistance, VCC = 6.0 V 90 +25 °C +125°C −55°C 80 RON @ 9V 70 60 50 40 30 20 10 0 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND Figure 1e. Typical On Resistance, VCC = 9.0 V 60 RON @ 12 V 50 40 30 20 +25 °C +125°C −55°C 10 0 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND Figure 1f. Typical On Resistance, VCC = 12.0 V http://onsemi.com 7 11.00 12.00 MC74HC4066A PLOTTER PROGRAMMABLE POWER SUPPLY − MINI COMPUTER + DC ANALYZER VCC DEVICE UNDER TEST ANALOG IN COMMON OUT GND Figure 2. On Resistance Test Set−Up VCC VCC VCC VCC 14 GND 14 A VCC A OFF 7 SELECTED CONTROL INPUT N/C ON GND VIL 7 Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set−Up SELECTED CONTROL INPUT VIH Figure 4. Maximum On Channel Leakage Current, Test Set−Up http://onsemi.com 8 MC74HC4066A VOS VCC VCC VIS 14 fin 14 ON 0.1F CL* 7 VOS SELECTED CONTROL INPUT fin dB METER OFF 0.1F CL* RL dB METER SELECTED CONTROL INPUT VCC 7 *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 5. Maximum On−Channel Bandwidth Test Set−Up VCC VCC/2 Figure 6. Off−Channel Feedthrough Isolation, Test Set−Up VCC/2 14 RL RL OFF/ON VOS IS VCC CL* VCC GND Vin ≤ 1 MHz tr = tf = 6 ns 7 ANALOG IN SELECTED CONTROL INPUT 50% GND tPLH CONTROL ANALOG OUT tPHL 50% *Includes all probe and jig capacitance. Figure 7. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set−Up Figure 8. Propagation Delays, Analog In to Analog Out http://onsemi.com 9 MC74HC4066A VCC tr 14 ANALOG IN ANALOG OUT ON TEST POINT VCC 90% 50% 10% CONTROL GND CL* 7 SELECTED CONTROL INPUT tf tPZL tPLZ 50% VCC ANALOG OUT tPZH Figure 9. Propagation Delay Test Set−Up VCC VOS ON 0.1 F 1 k TEST POINT ON/OFF 2 14 RL fin 1 VOH VIS VCC 14 90% HIGH IMPEDANCE 2 POSITIONWHEN TESTING tPLZ AND tPZL VCC VOL Figure 10. Propagation Delay, ON/OFF Control to Analog Out 1 POSITIONWHEN TESTING tPHZ AND tPZH 2 10% tPHZ 50% *Includes all probe and jig capacitance. 1 HIGH IMPEDANCE OFF VCC OR GND CL* RL RL SELECTED CONTROL INPUT SELECTED CONTROL INPUT CL* VCC/2 RL CL* VCC/2 7 7 VCC/2 *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 11. Propagation Delay Test Set−Up Figure 12. Crosstalk Between Any Two Switches, Test Set−Up VCC A VIS VCC 14 N/C OFF/ON VOS 0.1 F N/C fin ON RL 7 CL* TO DISTORTION METER VCC/2 SELECTED CONTROL INPUT 7 SELECTED CONTROL INPUT VCC ON/OFF CONTROL *Includes all probe and jig capacitance. Figure 13. Power Dissipation Capacitance Test Set−Up Figure 14. Total Harmonic Distortion, Test Set−Up http://onsemi.com 10 MC74HC4066A 0 −10 FUNDAMENTAL FREQUENCY −20 dBm −30 −40 −50 DEVICE −60 SOURCE −70 −80 −90 1.0 3.0 2.0 FREQUENCY (kHz) Figure 15. Plot, Harmonic Distortion APPLICATION INFORMATION below, the difference between VCC and GND is twelve volts. Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peak−to−peak can be controlled. When voltage transients above VCC and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn−on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with Mosorbs (Mosorb™ is an acronym for high current surge protectors). Mosorbs are fast turn−on devices ideally suited for precise DC protection with no inherent wear out mechanism. The ON/OFF Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked−up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and GND. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In the example VCC VCC = 12 V + 12 V 14 ANALOG I/O ON ANALOG O/I Dx + 12 V SELECTED CONTROL INPUT 7 16 Dx ON 0V 0V VCC Dx VCC OTHER CONTROL INPUTS (VCC OR GND) Dx SELECTED CONTROL INPUT 7 Figure 16. 12 V Application OTHER CONTROL INPUTS (VCC OR GND) Figure 17. Transient Suppressor Application http://onsemi.com 11 MC74HC4066A +5 V +5 V 14 ANALOG SIGNALS R* LSTTL/ NMOS R* R* R* HC4066A 6 HCT BUFFER LSTTL/ NMOS 5 14 ANALOG SIGNALS HC4066A 5 6 CONTROL INPUTS 15 14 ANALOG SIGNALS ANALOG SIGNALS 14 CONTROL INPUTS 15 7 7 R* = 2 TO 10 k a. Using Pull-Up Resistors b. Using HCT Buffer Figure 18. LSTTL/NMOS to HCMOS Interface VDD = 5 V 13 1 VCC = 5 TO 12 V 16 14 ANALOG SIGNALS 3 HC4066A 5 7 ANALOG SIGNALS MC14504 2 5 9 4 6 11 6 14 CONTROL INPUTS 10 15 7 14 8 Figure 19. TTL/NMOS−to−CMOS Level Converter Analog Signal Peak−to−Peak Greater than 5 V (Also see HC4316A) CHANNEL 4 1 OF 4 SWITCHES CHANNEL 3 1 OF 4 SWITCHES CHANNEL 2 1 OF 4 SWITCHES CHANNEL 1 1 OF 4 SWITCHES COMMON I/O − INPUT 1 OF 4 SWITCHES + OUTPUT LF356 OR EQUIVALENT 0.01 F 1 2 3 4 CONTROL INPUTS Figure 20. 4−Input Multiplexer Figure 21. Sample/Hold Amplifier http://onsemi.com 12 MC74HC4066A PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE P 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F L N C −T− SEATING PLANE H G D 14 PL J K 0.13 (0.005) M M http://onsemi.com 13 DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10 0.38 1.01 MC74HC4066A PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 14 8 −B− P 7 PL 0.25 (0.010) M 7 1 G −T− 0.25 (0.010) M T B S A DIM A B C D F G J K M P R J M K D 14 PL F R X 45 C SEATING PLANE B M S SOLDERING FOOTPRINT* 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 14 MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 MC74HC4066A PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U 0.25 (0.010) 8 S DETAIL E ÇÇÇ ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ K A −V− K1 J J1 SECTION N−N C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 −W− K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 15 MC74HC4066A PACKAGE DIMENSIONS SOEIAJ−14 CASE 965−01 ISSUE A 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 8 Q1 E HE M L 7 1 DETAIL P Z D VIEW P A e A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 −−− 1.42 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 −−− 0.056 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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