HP HCNW2201 Low input current logic gate optocoupler Datasheet

H
Low Input Current Logic Gate
Optocouplers
Technical Data
HCPL-2200
HCPL-2219
Features
• 2.5 kV/µs Minimum Common
Mode Rejection (CMR) at
VCM = 400 V (HCPL-2219)
• Compatible with LSTTL,
TTL, and CMOS Logic
• Wide VCC Range (4.5 to 20 V)
• 2.5 Mbd Guaranteed over
Temperature
• Low Input Current (1.6 mA)
• Three State Output (No
Pullup Resistor Required)
• Guaranteed Performance
from 0°C to 85°C
• Hysteresis
• Safety Approval
UL Recognized -2500 V rms
for 1 minute
CSA Approved
VDE 0884 Approved with
VIORM = 630 V peak
(HCPL-2219 Option 060
Only)
• MIL-STD-1772 Version
Available (HCPL-5200/1)
Description
detector threshold with hysteresis.
The three state output eliminates
the need for a pullup resistor and
allows for direct drive of data
busses. The hysteresis provides
differential mode noise immunity
and eliminates the potential for
output signal chatter.
The HCPL-2200/2219 are
optically coupled logic gates that
combine a GaAsP LED and an
integrated high gain photo
detector. The detector has a three
state output stage and has a
A superior internal shield on the
HCPL-2219 guarantees common
mode transient immunity of
2.5 kV/µs at a common mode
voltage of 400 volts.
• Ground Loop Elimination
• Pulse Transformer
Replacement
• Isolated Buss Driver
• High Speed Line Receiver
Functional Diagram
8 VCC
NC 1
ANODE 2
7 VO
CATHODE 3
6 VE
NC 4
SHIELD
TRUTH TABLE
(POSITIVE LOGIC)
LED
ENABLE OUTPUT
ON
Z
H
OFF
Z
H
ON
H
L
OFF
L
L
5 GND
Applications
• Isolation of High Speed
Logic Systems
• Computer-Peripheral
Interfaces
• Microprocessor System
Interfaces
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.
1-120
5965-3596E
The Electrical and Switching
Characteristics of the HCPL2200/2219 are guaranteed over
the temperature range of 0°C to
85°C and a VCC range of 4.5 volts
to 20 volts. Low IF and wide VCC
range allow compatibility with
TTL, LSTTL, and CMOS logic and
result in lower power consumption compared to other high
speed optocouplers. Logic signals
are transmitted with a typical
propagation delay of 160 nsec.
The HCPL-2200/2219 are useful
for isolating high speed logic
interfaces, buffering of input and
output lines, and implementing
isolated line receivers in high
noise environments.
Selection Guide
Minimum CMR
dV/dt
(V/µs)
1,000
VCM
(V)
50
Input OnCurrent
(mA)
1.6
2,500
5,000[2]
400
300[2]
1.8
1.6
1.6
50
1.8
2.0
1,000
8-Pin DIP (300 Mil)
Single
Dual
Channel
Channel
Package
Package
HCPL-2200[1]
HCPL-2201
HCPL-2202
HCPL-2231
HCPL-2219[1]
HCPL-2211
HCPL-2212
HCPL-2232
Small-Outline Widebody
SO-8
(400 Mil)
Hermetic
Single
Single
Single and Dual
Channel
Channel
Channel
Package
Package
Packages
HCPL-0201 HCNW2201
HCPL-0211
HCNW2211
HCPL-52XX
HCPL-62XX
Notes:
1. HCPL-2200/2219 devices include output enable/disable functionality.
2. Minimum CMR of 10 kV/µs with VCM = 1000 V can be achieved with input current, IF, of 5 mA.
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-2219#XXX
060 = VDE 0884 VIORM = 630 Vpeak Option*
300 = Gull Wing Surface Mount Option
500 = Tape and Reel Packaging Option
Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for
information.
*For HCPL-2219 only.
Schematic
ICC
8
IF
+
VF
IO
2
7
IE
–
6
3
SHIELD
5
VCC
VO
VE
GND
1-121
Package Outline Drawings
8-Pin DIP Package
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
TYPE NUMBER
8
7
6
5
OPTION CODE*
6.35 ± 0.25
(0.250 ± 0.010)
DATE CODE
HP XXXXZ
YYWW RU
1
2
3
4
UL
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
5° TYP.
4.70 (0.185) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
0.51 (0.020) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
*MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
2.92 (0.115) MIN.
0.65 (0.025) MAX.
1.080 ± 0.320
(0.043 ± 0.013)
2.54 ± 0.25
(0.100 ± 0.010)
8-Pin DIP Package with Gull Wing Surface Mount Option 300
PAD LOCATION (FOR REFERENCE ONLY)
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
1.016 (0.040)
1.194 (0.047)
5
4.826 TYP.
(0.190)
6.350 ± 0.25
(0.250 ± 0.010)
1
2
3
9.398 (0.370)
9.906 (0.390)
4
1.194 (0.047)
1.778 (0.070)
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
4.19 MAX.
(0.165)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
1-122
0.381 (0.015)
0.635 (0.025)
0.635 ± 0.25
(0.025 ± 0.010)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
12° NOM.
TEMPERATURE – °C
Maximum Solder Reflow Thermal Profile
260
240
220
200
180
160
140
120
100
80
∆T = 145°C, 1°C/SEC
∆T = 115°C, 0.3°C/SEC
∆T = 100°C, 1.5°C/SEC
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10
11
12
TIME – MINUTES
Note: Use of nonchlorine activated fluxes is highly recommended.
Regulatory Information
The HCPL-2200/2219 have been
approved by the following
organizations:
UL
Recognized under UL 1577,
Component Recognition
Program, File E55361.
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
VDE
Approved according to VDE
0884/06.92. (HCPL-2219 Option
060 Only)
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Min. External Air Gap L(IO1)
7.1
mm
Measured from input terminals to output terminals,
(External Clearance)
shortest distance through air.
Min. External
L(IO2)
7.4
mm
Measured from input terminals to output terminals,
Tracking Path
shortest distance path along body.
(External Creepage)
Minimum Internal
0.08
mm
Through insulation distance, conductor to conductor,
Plastic Gap
usually the direct distance between the photoemitter
(Internal Clearance)
and photodetector inside the optocoupler cavity.
Tracking Resistance
CTI
200
V
DIN IEC 112/VDE 0303 Part 1
(Comparative
Tracking Index)
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
1-123
VDE 0884 Insulation Related Characteristics (HCPL-2219 OPTION 060 ONLY)
Description
Symbol
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms
Units
I-IV
for rated mains voltage ≤ 450 V rms
I-III
Climatic Classification
55/85/21
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Characteristic
2
VIORM
630
V peak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
VPR
1181
V peak
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test,
tm = 60 sec, Partial Discharge < 5 pC
VPR
945
V peak
VIOTM
6000
V peak
TS
IS,INPUT
PS,OUTPUT
175
230
600
°C
mA
mW
RS
≥ 109
Ω
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 12, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, VIO = 500 V
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, (VDE 0884), for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
1-124
Absolute Maximum Ratings
(No Derating Required up to 70°C)
Parameter
Storage Temperature
Operating Temperature
Average Forward Input Current
Peak Transient Input Current
(≤ 1 µs Pulse Width, 300 pps)
Reverse Input Voltage
Average Output Current
Supply Voltage
Three State Enable Voltage
Output Voltage
Total Package Power Dissipation
Lead Solder Temperature
Solder Reflow Temperature Profile
Symbol
TS
TA
IF(AVG)
IF(TRAN)
Min.
-55
-40
Max.
125
85
10
1.0
Units
°C
°C
mA
A
VR
5
V
IO
25
mA
VCC
0
20
V
VE
-0.5
20
V
VO
-0.5
20
V
PT
210
mW
260°C for 10 sec., 1.6 mm below seating plane
See Package Outline Drawings section
Note
1
1
Recommended Operating Conditions
Parameter
Power Supply Voltage
Enable Voltage High
Enable Voltage Low
Forward Input Current
Forward Input Current
Operating Temperature
Fan Out
Symbol
VCC
VEH
VEL
IF(ON)
IF(OFF)
TA
N
Min.
4.5
2.0
0
1.6*
–
0
Max.
20
20
0.8
5
0.1
85[1]
4
Units
V
V
V
mA
mA
°C
TTL Loads
*The initial switching threshold is 1.6 mA or less. It is recommended that 2.2 mA be
used to permit at least a 20% CTR degradation guardband.
1-125
Electrical Specifications
For 0°C ≤ TA[1] ≤ 85°C, 4.5 V ≤ VCC ≤ 20 V, 1.6 mA ≤ IF(ON) ≤ 5 mA, 2.0 V ≤ VEH ≤ 20 V,
0.0 V ≤ VEL ≤ 0.8 V, 0 mA ≤ IF(OFF) ≤ 0.1 mA. All Typicals at TA = 25°C, VCC = 5 V, IF(ON) = 3 mA unless
otherwise specified. See Note 7.
Parameter
Sym.
Logic Low
VOL
Output Voltage
Logic High
VOH
Output Voltage
Output Leakage
IOHH
Current (VOUT > VCC)
Logic High Enable
Voltage
Logic Low Enable
Voltage
Logic High Enable
Current
VEH
Logic Low Enable
Current
Logic Low Supply
Current
IEL
Logic High Supply
Current
High Impedance
State Output
Current
Logic Low Short
Circuit Output
Current
Logic High Short
Circuit Output
Current
Input Current
Hysteresis
Input Forward
Voltage
Input Reverse
Breakdown Voltage
Input Diode
Temperature
Coefficient
Input Capacitance
1-126
Min. Typ. Max. Units
Test Conditions
0.5
V
IOL = 6.4 mA (4 TTL Loads)
2.4
*
IEH
0.8
V
IOH = -2.6 mA
VO = 5.5 V
VO = 20 V
µA
µA
µA
mA
VEN = 2.7 V
VEN = 5.5 V
VEN = 20 V
VEN = 0.4 V
*VOH = VCC - 2.1 V
IF = 0 mA
IO = Open
VE = Don’t Care
IF = 5 mA
IO = Open
VE = Don’t Care
VEN = 2 V,
IF = 5 mA
VEN = 2 V,
IF = 5 mA
6.0
mA
VCC = 5.5 V
5.25
7.5
mA
VCC = 20 V
2.7
4.5
mA
VCC = 5.5 V
3.1
6.0
-20
mA
µA
VCC = 20 V
VO = 0.4 V
20
100
500
µA
µA
µA
VO = 2.4 V
VO = 5.5 V
VO = 20 V
25
mA
VO = VCC = 5.5 V IF = 0 mA
40
mA
VO = VCC = 20 V
-10
mA
VCC = 5.5 V
-25
mA
VCC = 20 V
mA
VCC = 5 V
V
TA = 25°C
V
IR = 10 µA
IOZL
IOZH
IHYS
0.12
VF
1.5
5
∆VF
∆TA
-1.7
CIN
60
1.7
1.75
2
IF = 5 mA,
VO = GND
2
3
IF = 5 mA
mV/°C IF = 5 mA
pF
2
IF = 5 mA
VCC = 4.5 V
4.5
ICCH
BVR
µA
µA
V
20
100
0.004 250
-0.32
ICCL
IOSH
100
500
2.0
VEL
IOSL
V
Fig. Note
1
f = 1 MHz, VF = 0 V, Pins 2 and 3
4
Switching Specifications (AC)
For 0°C ≤ TA[1] ≤ 85°C, 4.5 V ≤ VCC ≤ 20 V, 1.6 mA ≤ IF(ON) ≤ 5 mA, 0.0 mA ≤ IF(OFF) ≤ 0.1 mA.
All Typicals at TA = 25°C, VCC = 5 V, IF(ON) = 3 mA unless otherwise specified.
Parameter
Propagation Delay Time to
Logic Low Output Level
Sym.
tPHL
Propagation Delay Time to
Logic High Output Level
tPLH
Output Enable Time to
Logic High
Output Enable Time to
Logic Low
Output Disable Time from
Logic High
Output Disable Time from
Logic Low
Output Rise Time (10-90%)
Output Fall Time (90-10%)
tPZH
Parameter
Logic High
Common Mode
Transient
Immunity
Logic Low
Common Mode
Transient
Immunity
Device
Min.
Units
HCPL-2200
1,000
V/µs
HCPL-2219
2,500
V/µs
Test Conditions
IF = 1.6 mA
|VCM| = 50 V
VCC = 5 V
TA = 25°C
|VCM| = 400 V
HCPL-2200
1,000
V/µs
|VCM| = 50 V
HCPL-2219
2,500
V/µs
|VCM| = 400 V
Sym.
|CMH|
|CML|
Min. Typ. Max. Units
Test Conditions
210
ns
Without Peaking Capacitor
160 300
With Peaking Capacitor
170
ns
Without Peaking Capacitor
115 300
With Peaking Capacitor
25
ns
Fig. Note
5, 6 4, 5
5, 6
7, 9
tPZL
28
ns
7, 8
tPHZ
105
ns
7, 9
tPLZ
60
ns
7, 8
tr
tf
55
15
ns
ns
5, 10
5, 10
VF = 0 V
VCC = 5 V
TA = 25°C
4, 5
Fig.
11
Note
6
11
6
Package Characteristics
Parameter
Input-Output Momentary
Withstand Voltage*
Input-Output Resistance
Input-Output Capacitance
Sym.
VISO
RI-O
CI-O
Min.
2500
Typ.
1012
0.6
Max. Units
V rms
Ω
pF
Test Conditions
RH ≤ 50%, t = 1 min.,
TA = 25°C
VI-O = 500 VDC
f = 1 MHz, VI-O = 0 VDC
Fig. Note
3, 8
3
3
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level
safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,” publication number 5963-2203E.
1-127
Notes:
1. Derate total package power dissipation, PT, linearly above 70°C free air
temperature at a rate of 4.5 mW/°C.
2. Duration of output short circuit time
should not exceed 10 ms.
3. Device considered a two-terminal
device: pins 1, 2, 3, and 4 shorted
together and pins 5, 6, 7, and 8
shorted together.
4. The tPLH propagation delay is
measured from the 50% point on the
leading edge of the input pulse to the
1.3 V point on the leading edge of the
output pulse. The tPHL propagation
delay is measured from the 50% point
on the trailing edge of the input pulse
to the 1.3 V point on the trailing edge
of the output pulse.
5. When the peaking capacitor is omitted,
propagation delay times may increase
by 100 ns.
6. CML is the maximum rate of rise of the
common mode voltage that can be
sustained with the output voltage in the
logic low state (VO < 0.8 V). CMH is
the maximum rate of fall of the
common mode voltage that can be
VOL – LOW LEVEL OUTPUT VOLTAGE – V
IOH – HIGH LEVEL OUTPUT CURRENT – mA
VCC = 4.5 V
IF = 0 mA
VO = 6.4 mA
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-60 -40 -20
0
20
40
60
80 100
5
0
VCC = 4.5 V
IF = 5 mA
-1
-2
VO = 2.7 V
-3
-4
-5
VO = 2.4 V
-6
-7
-8
-60 -40 -20
TA – TEMPERATURE – °C
Figure 1. Typical Logic Low Output
Voltage vs. Temperature.
0
INPUT
MONITORING
NODE
IF – FORWARD CURRENT – mA
R1
TA = 25 °C
10
40
60
4
3
IOH = -2.6 mA
2
1
IOL = 6.4 mA
0
80 100
0
OUTPUT VO
MONITORING
NODE
HCPL-2200
1
VCC 8
2
7
3
6
GND 5
5 kΩ
ALL DIODES ARE 1N916 OR 1N3064.
1.4
1.5
Figure 4. Typical Input Diode Forward
Characteristic.
1-128
IF (ON)
50 % IF (ON)
0 mA
INPUT IF
1.3
tPLH
OUTPUT
VO
D3
D4
0.1
1.2
619 Ω
D2
C2 =
15 pF
2.15 kΩ 1.10 kΩ 681 Ω
RI
5 mA
IF (ON) 1.6 mA 3 mA
VF – FORWARD VOLTAGE – V
5V
D1
1.0
0.001
1.1
1.5
2.0
Figure 3. Output Voltage vs. Forward
Input Current.
THE PROBE AND JIG CAPACITANCES
ARE INCLUDED IN C1 AND C2.
0.01
1.0
VCC
4
C1 =
120 pF
IF
+
VF
–
0.5
IF – INPUT CURRENT – mA
Figure 2. Typical Logic High Output
Current vs. Temperature.
IF
100
20
VCC = 4.5 V
TA = 25 °C
TA – TEMPERATURE – °C
PULSE GEN.
tr = tf = 5 ns
f = 100 kHz
10 % DUTY
CYCLE
VO = 5 V
1000
VO – OUTPUT VOLTAGE – V
1.0
sustained with the output voltage in the
logic high state (VO > 2.0 V).
7. Use of a 0.1 µF bypass capacitor
connected between pins 5 and 8 is
recommended.
8. In accordance with UL1577, each
optocoupler is proof tested by applying
an insulation test voltage ≥ 3000 V rms
for one second (leakage detection
current limit, II-O ≤ 5 µA). This test is
performed before the 100% production
test for partial discharge (Method b)
shown in the VDE 0884 Insulation
Characteristics Table, if applicable.
tPHL
VOH
1.3 V
VOL
Figure 5. Test Circuit for tPLH, tPHL, tr, and tf.
tP – PROPAGATION DELAY – ns
250
200
VCC = 5 V
C1 (120 pF) PEAKING
CAPACITOR IS USED.
SEE FIGURE 5.
CL= 15 pF INCLUDING PROBE
PULSE
AND JIG CAPACITANCES.
GENERATOR
VCC
ZO = 50 Ω
tr = tf = 5 ns
VO
HCPL-2200
IF (mA)
5
3
1.6
150
1.6
3
5
tPHL
20
40
60
619 Ω
D1
IF
tPLH
0
S1
VCC 8
1
100
50
-60 -40 -20
+5 V
2
7
3
6
4
GND 5
D2
CL
5 kΩ
D3
INPUT VC
MONITORING
NODE
80 100
TA – TEMPERATURE – °C
D4
S2
D1-4 ARE 1N916 OR 1N3064.
Figure 6. Typical Propagation Delays
vs. Temperature.
INPUT
VE
tPZL
3.0 V
1.3 V
0V
S1 AND
S2 CLOSED
tPLZ
OUTPUT S1 CLOSED
VO
S2 OPEN
tPZH
OUTPUT
VO
S1 OPEN
S2 CLOSED
0.5 V
1.3 V
VOL
0.5 V
VOH
≈1.5 V
S1 AND
S2 CLOSED
1.3 V
0V
tPHZ
VCC
20 V
CL = 15 pF
80
4.5 V
tPLZ
60
20 V
40
4.5 V
tPZL
20
0
-60 -40 -20
0
20
40
60
80 100
TA – TEMPERATURE – °C
Figure 8. Typical Logic Low Enable
Propagation Delay vs. Temperature.
200
120
CL = 15 pF
VCC
150
20 V
tPHZ
4.5 V
100
20 V
50
4.5 V
tPZH
tr, tf – RISE, FALL TIME – ns
100
tP – ENABLE PROPAGATION DELAY – ns
Tp – ENABLE PROPAGATION DELAY – ns
Figure 7. Test Circuit for tPHZ, tPZH, tPLZ, and tPZL.
VCC = 5 V
C2 = 15 pF
100
80
60
tr
40
20
tf
0
-60 -40 -20
0
20
40
60
80 100
TA – TEMPERATURE – °C
Figure 9. Typical Logic High Enable
Propagation Delay vs. Temperature.
0
-60 -40 -20
0
20
40
60
80 100
TA – TEMPERATURE – °C
Figure 10. Typical Rise, Fall Time vs.
Temperature.
1-129
OUTPUT VO
MONITORING
NODE
VCC 8
A
1
B
2
7
3
6
RIN
VFF
4
GND
OUTPUT POWER – PS, INPUT CURRENT – IS
VCC
HCPL-2200
0.1 µF
BYPASS
5
VCM
–
PULSE GENERATOR +
50 V
VCM
0V
VOH
PS (mW)
700
IS (mA)
600
500
400
300
200
100
0
0
25
50
75 100 125 150 175 200
TS – CASE TEMPERATURE – °C
SWITCH AT A: IF = 1.6 mA
VO (MIN.)*
SWITCH AT B: IF = 0 mA
VO (MAX.)*
OUTPUT
VO
HCPL-2219 OPTION 060 ONLY
800
Figure 12. Thermal Derating Curve,
Dependence of Safety Limiting Value
with Case Temperature per
VDE 0884.
VOL
* SEE NOTE 6.
Figure 11. Test Circuit for Common Mode Transient Immunity and Typical
Waveforms.
VCC1
(+5 V)
VCC1
(+5 V)
120 pF
HCPL-2200
1.1
kΩ
DATA
INPUT
TTL OR
LSTTL
TOTEM
POLE
OUTPUT
GATE
VCC
1
2
7
3
6
GND
4
HCPL-2200
1.1
kΩ
DATA
OUTPUT
8
5
DATA
INPUT
TOTEM
POLE
OUTPUT
GATE
1
2
Figure 13. Recommended LSTTL to LSTTL Circuit.
DATA
INPUT
TTL OR
LSTTL
RL
1.1 K
2.37 K
3.83 K
5.11 K
VCC 8
2
7
2
120 pF (OPTIONAL*)
1.1
kΩ
HCPL-2200
1
5
Figure 14. LSTTL to CMOS Interface Circuit.
VCC (+5 V)
1.1 kΩ
CMOS
6
GND
4
VCC2
5V
10 V
15 V
20 V
RL
8
7
3
TTL OR
LSTTL
1
VCC1 (+5 V)
VCC
1
2
UP TO 16
LSTTL
LOADS
OR 4 TTL
LOADS
VCC2
(4.5 TO 20 V)
120 pF (OPTIONAL*)
VCC2
(+5 V)
HCPL-2200
1
VCC
2
8
7
4.7 kΩ
D1
3
4
6
GND
5
DATA
INPUT
OPEN
COLLECTOR
GATE
3
TTL OR
LSTTL
4
6
GND
5
D1 (1N4150) REQUIRED FOR
ACTIVE PULL-UP DRIVER.
Figure 15. Recommended LED Drive Circuit.
Figure 16. Series LED Drive with Open Collector Gate
(4.7 kΩ Resistor Shunts IOH from the LED).
*The 120 pF capacitor may be omitted in applications where 500 ns propagation delay is sufficient.
1-130
DATA
OUTPUT