Intel E28F200BX-T120 2-mbit (128k x 16, 256k x 8) boot block flash memory family Datasheet

2-MBIT (128K x 16, 256K x 8)
BOOT BLOCK
FLASH MEMORY FAMILY
28F200BX-T/B, 28F002BX-T/B
Y
x8/x16 Input/Output Architecture
Ð 28F200BX-T, 28F200BX-B
Ð For High Performance and High
Integration 16-bit and 32-bit CPUs
Y
x8-only Input/Output Architecture
Ð 28F002BX-T 28F002BX-B
Ð For Space Constrained 8-bit
Applications
Y
Upgradeable to Intel’s SmartVoltage
Products
Y
Optimized High-Density Blocked
Architecture
Ð One 16-KB Protected Boot Block
Ð Two 8-KB Parameter Blocks
Ð One 96-KB Main Block
Ð One 128 KB Main Block
Ð Top or Bottom Boot Locations
Y
Extended Cycling Capability
Ð 100,000 Block Erase Cycles
Y
Automated Word/Byte Write and
Block Erase
Ð Command User Interface
Ð Status Registers
Ð Erase Suspend Capability
Y
SRAM-Compatible Write Interface
Y
Automatic Power Savings Feature
Ð 1 mA Typical ICC Active Current in
Static Operation
Y
Hardware Data Protection Feature
Ð Erase/Write Lockout during Power
Transitions
Y
Very High-Performance Read
Ð 60/80/120 ns Maximum Access Time
Ð 30/40/40 ns Maximum Output Enable
Time
Y
Low Power Consumption
Ð 20 mA Typical Active Read Current
Y
Reset/Deep Power-Down Input
Ð 0.2 mA ICC Typical
Ð Acts as Reset for Boot Operations
Y
Extended Temperature Operation
Ð b 40§ C to a 85§ C
Y
Write Protection for Boot Block
Y
Industry Standard Surface Mount
Packaging
Ð 28F200BX: JEDEC ROM Compatible
44-Lead PSOP
56-Lead TSOP
Ð 28F002BX: 40-Lead TSOP
Y
12V Word/Byte Write and Block Erase
Ð VPP e 12V g 5% Standard
Ð VPP e 12V g 10% Option
Y
ETOX TM III Flash Technology
Ð 5V Read
Y
Independent Software Vendor Support
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 1995
November 1995
Order Number: 290448-005
28F200BX-T/B, 28F002BX-T/B
Intel’s 2-Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes block-selective erasure, automated write and erase operations and standard microprocessor interface. The 2-Mbit Flash
Memory Family enhances the Boot Block Architecture by adding more density and blocks, x8/x16 input/output control, very high speed, low power, an industry-standard ROM compatible pinout and surface mount
packaging. The 2-Mbit flash family allows for an easy upgrade to Intel’s 4-Mbit Boot Block Flash Memory
Family.
The Intel 28F200BX-T/B are 16-bit wide flash memory offerings. These high-density flash memories provide
user selectable bus operation for either 8-bit or 16-bit applications. The 28F200BX-T and 28F200BX-B are
2,097,152-bit nonvolatile memories organized as either 262,144 bytes or 131,072 words of information. They
are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the industrystandard ROM/EPROM pinout.
The Intel 28F002BX-T/B are 8-bit wide flash memories with 2,097,152 bits organized as 262,144 bytes of
information. They are offered in a 40-lead TSOP package, which is ideal for space-constrained portable
systems.
These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word/byte write and block erasure. The 28F200BX-T/28F002BX-T provide block locations compatible with
Intel’s MCSÉ-186 family, 80286, i386 TM , i486 TM , i860 TM and 80960CA microprocessors. The 28F200BX-B/
28F002BX-B provide compatibility with Intel’s 80960KX and 80960SX families as well as other embedded
microprocessors.
The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 60 ns, these 2-Mbit flash devices are very high-performance memories which interface at zero wait-state to a wide range of microprocessors and microcontrollers. A deep power-down mode
lowers the total VCC power consumption to 1 mW typical. This is critical in handheld battery-powered systems.
For very low-power applications using a 3.3V supply, refer to the Intel 28F200BX-TL/BL, 28F002BX-TL/BL
2-Mbit Boot Block Flash Memory Family datasheet.
Manufactured on Intel’s 0.8 micron ETOX III process, the 2-Mbit flash memory family provides world-class
quality, reliability and cost-effectiveness at the 2-Mbit density level.
2
28F200BX-T/B, 28F002BX-T/B
1.0
PRODUCT FAMILY OVERVIEW
Throughout this datasheet the 28F200BX refers to
both the 28F200BX-T and 28F200BX-B devices and
28F002BX refers to both the 28F002BX-T and
28F002BX-B devices. The 2-Mbit flash memory family refers to both the 28F200BX and 28F002BX products. This datasheet comprises the specifications for
four separate products in the 2-Mbit flash memory
family. Section 1 provides an overview of the 2-Mbit
flash memory family including applications, pinouts
and pin descriptions. Sections 2 and 3 describe in
detail the specific memory organizations for the
28F200BX and 28F002BX products respectively.
Section 4 combines a description of the family’s
principles of operations. Finally Section 5 describes
the family’s operating specifications.
1.2 Main Features
The 28F200BX/28F002BX boot block flash memory
family is a very high performance 2-Mbit (2,097,152
bit) memory family organized as either 128 KWords
(131,072 words) of 16 bits each or 256 Kbytes
(262,144 bytes) of 8 bits each.
Five Separately Erasable Blocks including a hardware-lockable boot block (16,384 Bytes), two parameter blocks (8,192 Bytes each) and two main
blocks (1 block of 98,304 Bytes and 1 block of
131,072 Bytes) are included on the 2-Mbit family. An
erase operation erases one of the main blocks in
typically 2.4 seconds, and the boot or parameter
blocks in typically 1.0 second. Each block can be
independently erased and programmed 100,000
times.
PRODUCT FAMILY
x8/x16 Products
x8-Only Products
28F200BX-T
28F002BX-T
28F200BX-B
28F002BX-B
1.1 Designing for Upgrade to
SmartVoltage Products
Today’s high volume boot block products are upgradable to Intel’s SmartVoltage boot block products that provide program and erase operation at 5V
or 12V VPP and read operation at 3V or 5V VCC.
Intel’s SmartVoltage boot block products provide the
following enhancements to the boot block products
described in this data sheet:
1. DU pin is replaced by WPÝ to provide a means
to lock and unlock the boot block with logic signals.
2. 5V Program/Erase operation uses proven program and erase techniques with 5V g 10% applied to VPP.
3. Enhanced circuits optimize performance at 3.3V
VCC.
Refer to the 2, 4 or 8 Mbit SmartVoltage Boot Block
Flash Memory Data Sheets for complete specifications.
When you design with 12V VPP boot block products
you should provide the capability in your board design to upgrade to SmartVoltage products.
Follow these guidelines to ensure compatibility:
1. Connect DU (WPÝ on SmartVoltage products) to
a control signal or to VCC or GND.
2. If adding a switch on VPP for write protection,
switch to GND for complete write protection.
3. Allow for connecting 5V to VPP and disconnect
12V from the VPP line, if desired.
The Boot Block is located at either the top
(28F200BX-T, 28F002BX-T) or the bottom
(28F200BX-B, 28F002BX-B) of the address map in
order to accommodate different microprocessor protocols for boot code location. The hardware lockable boot block provides the most secure code storage. The boot block is intended to store the kernel
code required for booting-up a system. When the
RPÝ pin is between 11.4V and 12.6V the boot block
is unlocked and program and erase operations can
be performed. When the RPÝ pin is at or below 6.5V
the boot block is locked and program and erase operations to the boot block are ignored.
The 28F200BX products are available in the ROM/
EPROM compatible pinout and housed in the 44Lead PSOP (Plastic Small Outline) package and the
56-Lead TSOP (Thin Small Outline, 1.2mm thick)
package as shown in Figures 3 and 4. The
28F002BX products are available in the 40-Lead
TSOP (1.2mm thick) package as shown in Figure 5.
The Command User Interface (CUI) serves as the
interface between the microprocessor or microcontroller and the internal operation of the 28F200BX
and 28F002BX flash memory products.
Program and Erase Automation allows program
and erase operations to be executed using a twowrite command sequence to the CUI. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller. Writing of memory data is performed in word or
byte increments for the 28F200BX family and in byte
increments for the 28F002BX family typically within
9 ms which is a 100% improvement over current
flash memory products.
3
28F200BX-T/B, 28F002BX-T/B
The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation.
Maximum Access Time of 60 ns (tACC) is achieved
over the commercial temperature range (0§ C to
70§ C), 5% VCC supply voltage range (4.75V to
5.25V) and 30 pF output load. Refer to Figure 19;
tACC vs Output Load Capacitance for larger output
loads. Maximum Access Time of 80 ns (tACC) is
achieved over the commercial temperature range,
10% VCC supply range (4.5V to 5.5V) and 100 pF
output load.
IPP maximum Program current is 40 mA for x16
operation and 30 mA for x8 operation. IPP Erase
current is 30 mA maximum. VPP erase and programming voltage is 11.4V to 12.6V (VPP e 12V
g 5%) under all operating conditions. As an option, VPP can also vary between 10.8V to 13.2V (VPP
e 12V g 10%) with a guaranteed number of 100
block erase cycles.
Typical ICC Active Current of 25 mA is achieved
for the x16 products (28F200BX), typical ICC Active
Current of 20 mA is achieved for the x8 products
(28F200BX, 28F002BX). Refer to the ICC active current derating curves in this datasheet.
The 2-Mbit boot block flash family is also designed
with an Automatic Power Savings (APS) feature to
minimize system battery current drain and allow for
very low power designs. Once the device is accessed to read array data, APS mode will immediately put the memory in static mode of operation
where ICC active current is typically 1 mA until the
next read is initiated.
When the CEÝ and RPÝ pins are at VCC and the
BYTEÝ pin (28F200BX-only) is at either VCC or
GND the CMOS Standby mode is enabled where
ICC is typically 50 mA.
A Deep Power-Down Mode is enabled when the
RPÝ pin is at ground minimizing power consumption
and providing write protection during power-up conditions. ICC current during deep power-down mode
is 0.20 mA typical. An initial maximum access time
or Reset Time of 300 ns is required from RPÝ
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 215 ns until
writes to the Command User Interface are recognized. When RPÝ is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature prevents data corruption and protects the code stored
in the device during system reset. The system Reset
pin can be tied to RPÝ to reset the memory to normal read mode upon activation of the Reset pin.
With on-chip program/erase automation in the
2-Mbit family and the RPÝ functionality for data pro4
tection, when the CPU is reset and even if a program
or erase command is issued, the device will not recognize any operation until RPÝ returns to its normal
state.
For the 28F200BX, Byte-wide or Word-wide Input/Output Control is possible by controlling the
BYTEÝ pin. When the BYTEÝ pin is at a logic low
the device is in the byte-wide mode (x8) and data is
read and written through DQ [0:7] . During the bytewide mode, DQ [8:14] are tri-stated and DQ15/A b 1
becomes the lowest order address pin. When the
BYTEÝ pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
through DQ [0:15] .
1.3 Applications
The 2-Mbit boot block flash family combines high
density, high performance, cost-effective flash memories with blocking and hardware protection capabilities. Its flexibility and versatility will reduce costs
throughout the product life cycle. Flash memory is
ideal for Just-In-Time production flow, reducing system inventory and costs, and eliminating component
handling during the production phase. During the
product life cycle, when code updates or feature enhancements become necessary, flash memory will
reduce the update costs by allowing either a userperformed code change via floppy disk or a remote
code change via a serial link. The 2-Mbit boot block
flash family provides full function, blocked flash
memories suitable for a wide range of applications.
These applications include Extended PC BIOS,
Digital Cellular Phone program and data storage,
Telecommunication boot/firmware, and various
other embedded applications where both program
and data storage are required.
Reprogrammable systems such as personal computers, are ideal applications for the 2-Mbit flash
products. Portable and handheld personal computer
applications are becoming more complex with the
addition of power management software to take advantage of the latest microprocessor technology,
the availability of ROM-based application software,
pen tablet code for electronic hand writing, and diagnostic code. Figure 1 shows an example of a
28F200BX-T application.
This increase in software sophistication augments
the probability that a code update will be required
after the PC is shipped. The 2-Mbit flash products
provide an inexpensive update solution for the notebook and handheld personal computers while extending their product lifetime. Furthermore, the
2-Mbit flash products’ power-down mode provides
added flexibility for these battery-operated portable
designs which require operation at very low power
levels.
28F200BX-T/B, 28F002BX-T/B
The 2-Mbit flash products also provide excellent design solutions for Digital Cellular Phone and Telecommunication switching applications requiring high
performance, high density storage capability coupled with modular software designs, and a small
form factor package (x8-only bus). The 2-Mbit’s
blocking scheme allows for an easy segmentation of
the embedded code with; 16 Kbytes of HardwareProtected Boot code, 2 Main Blocks of program
code and 2 Parameter Blocks of 8 Kbytes each for
frequently updatable data storage and diagnostic
messages (e.g. phone numbers, authorization
codes). Figure 2 is an example of such an application with the 28F002BX-T.
These are a few actual examples of the wide range
of applications for the 2-Mbit Boot Block flash memory family which enable system designers to achieve
the best possible product design. Only your imagination limits the applicability of such a versatile product
family.
290448 – 4
Figure 1. 28F200BX Interface to Intel386 TM EX Embedded Processor
290448 – 24
Figure 2. 28F002BX Interface to INTEL 80C188EB 8-Bit Embedded Microprocessor
5
28F200BX-T/B, 28F002BX-T/B
1.4 Pinouts
The 28F200BX 44-Lead PSOP pinout follows the industry standard ROM/EPROM pinout as shown in
Figure 3 with an upgrade to the 28F400BX (4-Mbit
flash family). Furthermore, the 28F200BX 56-Lead
TSOP pinout shown in Figure 4 provides density upgrades to the 28F400BX and to future higher density
boot block memories.
The 28F002BX 40-Lead TSOP pinout shown in Figure 5 is 100% compatible and provides a density
upgrade to the 28F004BX 4-Mbit Boot Block flash
memory.
28F400BX
28F400BX
290448 – 25
Figure 3. PSOP Lead Configuration for x8/x16 28F200BX
6
28F200BX-T/B, 28F002BX-T/B
28F400BX
28F400BX
290448 – 3
Figure 4. TSOP Lead Configuration for x8/x16 28F200BX
28F004BX
28F004BX
290448 – 20
Figure 5. TSOP Lead Configuration for x8 28F002BX
7
28F200BX-T/B, 28F002BX-T/B
1.5 Pin Descriptions for the x8/x16 28F200BX
Symbol
8
Type
Name and Function
A0 –A16
I
ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle.
A9
I
ADDRESS INPUT: When A9 is at 12V the signature mode is accessed. During this
mode A0 decodes between the manufacturer and device ID’s. When BYTEÝ is at
a logic low only the lower byte of the signatures are read. DQ15/Ab1 is a don’t
care in the signature mode when BYTEÝ is low.
DQ0 –DQ7
I/O
DATA INPUTS/OUTPUTS: Inputs array data on the second CEÝ and WEÝ cycle
during a program command. Inputs commands to the Command User Interface
when CEÝ and WEÝ are active. Data is internally latched during the write and
program cycles. Outputs array, Intelligent Identifier and Status Register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.
DQ8 –DQ15
I/O
DATA INPUTS/OUTPUTS: Inputs array data on the second CEÝ and WEÝ cycle
during a program command. Data is internally latched during the write and program
cycles. Outputs array data. The data pins float to tri-state when the chip is
deselected or the outputs are disabled as in the byte-wide mode (BYTEÝ e ‘‘0’’).
In the byte-wide mode DQ15/Ab1 becomes the lowest order address for data
output on DQ0 –DQ7.
CEÝ
I
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CEÝ is active low; CEÝ high deselects the memory device and
reduces power consumption to standby levels. If CEÝ and RPÝ are high, but not
at a CMOS high level, the standby current will increase due to current flow through
the CEÝ and RPÝ input stages.
RPÝ
I
RESET/DEEP POWER-DOWN: Provides three-state control. Puts the device in
deep power-down mode. Locks the boot block from program/erase.
When RPÝ is at logic high level and equals 6.5V maximum the boot block is
locked and cannot be programmed or erased.
When RPÝ e 11.4V minimum the boot block is unlocked and can be programmed
or erased.
When RPÝ is at a logic low level the boot block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions. When RPÝ transitions from logic low to logic high the flash memory
enters the read array mode.
OEÝ
I
OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a
read cycle. OEÝ is active low.
WEÝ
I
WRITE ENABLE: Controls writes to the Command Register and array blocks.
WEÝ is active low. Addresses and data are latched on the rising edge of the WEÝ
pulse.
BYTEÝ
I
BYTEÝ ENABLE: Controls whether the device operates in the byte-wide mode
(x8) or the word-wide mode (x16). BYTEÝ pin must be controlled at CMOS levels
to meet 100 mA CMOS current in the standby mode. BYTEÝ e ‘‘0’’ enables the
byte-wide mode, where data is read and programmed on DQ0 –DQ7 and
DQ15/Ab1 becomes the lowest order address that decodes between the upper
and lower byte. DQ8 – DQ14 are tri-stated during the byte-wide mode.
BYTEÝ e ‘‘1’’ enables the word-wide mode where data is read and programmed
on DQ0 –DQ15.
VPP
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
Note: VPP k VPPLMAX memory contents cannot be altered.
VCC
DEVICE POWER SUPPLY (5V g 10%, 5V g 5%)
GND
GROUND: For all internal circuitry.
NC
NO CONNECT: Pin may be driven or left floating.
DU
DON’T USE PIN: Pin should not be connected to anything.
28F200BX-T/B, 28F002BX-T/B
1.6 Pin Descriptions for x8 28F002BX
Type
Name and Function
A0 –A17
Symbol
I
ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.
A9
I
ADDRESS INPUT: When A9 is at 12V the signature mode is accessed. During this
mode A0 decodes between the manufacturer and device ID’s.
I/O
DATA INPUTS/OUTPUTS: Inputs array data on the second CEÝ and WEÝ cycle
during a program command. Inputs commands to the command user interface
when CEÝ and WEÝ are active. Data is internally latched during the write and
program cycles. Outputs array, Intelligent Identifier and status register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.
DQ0 –DQ7
CEÝ
I
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CEÝ is active low; CEÝ high deselects the memory device and
reduces power consumption to standby levels. If CEÝ and RPÝ are high, but not at
a CMOS high level, the standby current will increase due to current flow through the
CEÝ and RPÝ input stages.
ÝRPÝ
I
RESET/DEEP POWERDOWN: Provides Three-State control. Puts the device in
deep powerdown mode. Locks the Boot Block from program/erase.
When RPÝ is at logic high level and equals 6.5V maximum the Boot Block is locked
and cannot be programmed or erased.
When RPÝ e 11.4V minimum the Boot Block is unlocked and can be programmed
or erased.
When RPÝ is at a logic low level the Boot Block is locked, the deep powerdown
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions. When RPÝ transitions from logic low to logic high, the flash memory
enters the read-array mode.
OEÝ
I
OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a
read cycle. OEÝ is active low.
WEÝ
I
WRITE ENABLE: Controls writes to the Command Register and array blocks. WEÝ
is active low. Addresses and data are latched on the rising edge of the WEÝ pulse.
VPP
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
Note: VPP k VPPLMAX memory contents cannot be altered.
VCC
DEVICE POWER SUPPLY (5V g 10%, 5V g 5%)
GND
GROUND: For all internal circuitry.
NC
NO CONNECT: Pin may be driven or left floating.
DU
DON’T USE PIN: Pin should not be connected to anything.
9
28F200BX-T/B, 28F002BX-T/B
28F200BX WORD/BYTE-WIDE PRODUCTS DESCRIPTION
290448– 1
2.0
Figure 6. 28F200BX Word/Byte-Wide Block Diagram
10
28F200BX-T/B, 28F002BX-T/B
2.1 28F200BX Memory Organization
2.1.1 BLOCKING
The 28F200BX uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block address range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F200BX is
a random read/write memory, only erasure is performed by block.
2.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
erased when RPÝ is not at 12V. The boot block can
be erased and written when RPÝ is held at 12V for
the duration of the erase or program operation. This
allows customers to change the boot code when
necessary while providing security when needed.
See the Block Memory Map section for address
locations of the boot block for the 28F200BX-T
and 28F200BX-B.
2.1.1.2 Parameter Block Operation
The 28F200BX has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The parameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. The parameter blocks provide for more efficient memory utilization when dealing with parameter changes versus regularly blocked
devices. See the Block Memory Map section for address locations of the parameter blocks for the
28F200BX-T and 28F200BX-B.
2.1.1.3 Main Block Operation
Two main blocks of memory exist on the 28F200BX
(1 x 128 Kbyte block and 1 x 96-Kbyte block). See
the following section on Block Memory Map for the
address location of these blocks for the 28F200BX-T
and 28F200BX-B products.
2.1.2 BLOCK MEMORY MAP
Two versions of the 28F200BX product exist to support two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F200BX-T
memory map is inverted from the 28F200BX-B
memory map.
2.1.2.1 28F200BX-B Memory Map
The 28F200BX-B device has the 16-Kbyte boot
block located from 00000H to 01FFFH to accommodate those microprocessors that boot from the bottom of the address map at 00000H. In the
28F200BX-B the first 8-Kbyte parameter block resides in memory space from 02000H to 02FFFH.
The second 8-Kbyte parameter block resides in
memory space from 03000H to 03FFFH. The
96-Kbyte main block resides in memory space from
04000H to 0FFFFH. The 128-Kbyte main block resides in memory space from 10000H to 1FFFFH
(word locations). See Figure 7.
(Word Addresses)
1FFFFH
128-Kbyte MAIN BLOCK
10000H
0FFFFH
96-Kbyte MAIN BLOCK
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
00000H
Figure 7. 28F200BX-B Memory Map
11
28F200BX-T/B, 28F002BX-T/B
2.1.2.2 28F200BX-T Memory Map
The 28F200BX-T device has the 16-Kbyte boot
block located from 1E000H to 1FFFFH to accommodate those microprocessors that boot from the top
of the address map. In the 28F200BX-T the first
8-Kbyte parameter block resides in memory space
from 1D000H to 1DFFFH. The second 8-Kbyte parameter block resides in memory space from
1C000H to 1CFFFH. The 96-Kbyte main block resides in memory space from 10000H to 1BFFFH.
The 128-Kbyte main block resides in memory space
from 00000H to 0FFFFH as shown in Figure 8.
(Word Addresses)
1FFFFH
16-Kbyte BOOT BLOCK
1E000H
1DFFFH
1D000H
1CFFFH
1C000H
1BFFFH
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
10000H
0FFFFH
128-Kbyte MAIN BLOCK
00000H
Figure 8. 28F200BX-T Memory Map
12
28F200BX-T/B, 28F002BX-T/B
28F002BX BYTE-WIDE PRODUCTS DESCRIPTION
290448– 19
3.0
Figure 9. 28F002BX Byte-Wide Block Diagram
13
28F200BX-T/B, 28F002BX-T/B
3.1 28F002BX Memory Organization
3.1.1 BLOCKING
The 28F002BX uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block address range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F002BX is
a random read/write memory, only erasure is performed by block.
3.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being programmed
or erased when RPÝ is not at 12V. The boot block
can be erased and programmed when RPÝ is held
at 12V for the duration of the erase or program operation. This allows customers to change the boot
code when necessary while still providing security
when needed. See the Block Memory Map section
for address locations of the boot block for the
28F002BX-T and 28F002BX-B.
3.1.1.3 Main Block Operation
Two main blocks of memory exist on the 28F002BX
(1 x 128-Kbyte block and 1 x 96-Kbyte block). See
the following section on Block Memory Map for
address location of these blocks for the
28F002BX-T and 28F002BX-B.
3.1.2 BLOCK MEMORY MAP
Two versions of the 28F002BX product exist to support two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F002BX-T
memory map is inverted from the 28F002BX-B
memory map.
3.1.2.1 28F002BX-B Memory Map
The 28F002BX-B device has the 16-Kbyte boot
block located from 00000H to 03FFFH to accommodate those microprocessors that boot from the bottom of the address map at 00000H. In the
28F002BX-B the first 8-Kbyte parameter block resides in memory from 04000H to 05FFFH. The second 8-Kbyte parameter block resides in memory
space from 06000H to 07FFFH. The 96-Kbyte main
block resides in memory space from 08000H to
1FFFFH. The 128-Kbyte main block resides in memory space from 20000H to 3FFFFH. See Figure 10.
3FFFFH
3.1.1.2 Parameter Block Operation
The 28F002BX has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The parameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. Parameter blocks provide
for more efficient memory utilization when dealing
with small parameter changes versus regularly
blocked devices. See the Block Memory Map section for address locations of the parameter blocks
for the 28F002BX-T and 28F002BX-B.
128-Kbyte MAIN BLOCK
20000H
1FFFFH
96-Kbyte MAIN BLOCK
08000H
07FFFH
06000H
05FFFH
04000H
03FFFH
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
00000H
Figure 10. 28F002BX-B Memory Map
14
28F200BX-T/B, 28F002BX-T/B
3.1.2.2 28F002BX-T Memory Map
The 28F002BX-T device has the 16-Kbyte boot
block located from 3C000H to 3FFFFH to accommodate those microprocessors that boot from the
top of the address map. In the 28F002BX-T the first
8-Kbyte parmeter block resides in memory space
from 3A000H to 3BFFFH. The second 8-Kbyte parameter block resides in memory space from
38000H to 39FFFH. The 96-Kbyte main block resides in memory space from 20000H to 37FFFH.
The 128-Kbyte main block resides in memory space
from 00000H to 1FFFFH.
3FFFFH
16-Kbyte BOOT BLOCK
3C000H
3BFFFH
3A000H
39FFFH
38000H
37FFFH
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
20000H
1FFFFH
128-Kbyte MAIN BLOCK
00000H
Figure 11. 28F002BX-T Memory Map
4.0 PRODUCT FAMILY PRINCIPLES
OF OPERATION
Flash memory augments EPROM functionality with
in-circuit electrical write and erase. The 2-Mbit flash
family utilizes a Command User Interface (CUI) and
internally generated and timed algorithms to simplify
write and erase operations.
The CUI allows for 100% TTL-level control inputs,
fixed power supplies during erasure and programming, and maximum EPROM compatibility.
In the absence of high voltage on the VPP pin, the
2-Mbit boot block flash family will only successfully
execute the following commands: Read Array, Read
Status Register, Clear Status Register and Intelligent Identifier mode. The device provides standard
EPROM read, standby and output disable operations. Manufacturer Identification and Device Identification data can be accessed through the CUI or
through the standard EPROM A9 high voltage access (VID) for PROM programming equipment.
The same EPROM read, standby and output disable
functions are available when high voltage is applied
to the VPP pin. In addition, high voltage on VPP allows write and erase of the device. All functions associated with altering memory contents: write and
erase, Intelligent Identifier read and Read Status are
accessed via the CUI.
The purpose of the Write State Machine (WSM) is to
completely automate the write and erasure of the
device. The WSM will begin operation upon receipt
of a signal from the CUI and will report status back
through a Status Register. The CUI will handle the
WEÝ interface to the data and address latches, as
well as system software requests for status while the
WSM is in operation.
4.1 28F200BX Bus Operations
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
15
28F200BX-T/B, 28F002BX-T/B
Table 1. Bus Operations for WORD-WIDE Mode (BYTEÝ e VIH)
Mode
Notes
Read
1, 2
Output Disable
Standby
Deep Power-Down
Intelligent Identifier (Mfr)
RPÝ
CEÝ
OEÝ
WEÝ
A9
A0
VPP
DQ0–15
VIH
VIL
VIL
VIH
X
X
X
DOUT
VIH
VIL
VIH
VIH
X
X
X
High Z
VIH
VIH
X
X
X
X
X
High Z
9
VIL
X
X
X
X
X
X
High Z
3, 4
VIH
VIL
VIL
VIH
VID
VIL
X
0089H
Intelligent Identifier (Device)
3, 4, 5
VIH
VIL
VIL
VIH
VID
VIH
X
2274H
2275H
Write
6, 7, 8
VIH
VIL
VIH
VIL
X
X
X
DIN
Table 2. Bus Operations for BYTE-WIDE Mode (BYTEÝ e VIL)
Mode
Read
Notes
1, 2, 3
Output Disable
Standby
Deep Power-Down
Intelligent Identifier (Mfr)
Intelligent Identifier
(Device)
Write
9
RPÝ
CEÝ
OEÝ
WEÝ
A9
A0
Ab1
VPP
DQ8–14
VIH
VIL
VIL
VIH
X
X
X
X
DOUT
High Z
VIH
VIL
VIH
VIH
X
X
X
X
High Z
High Z
VIH
VIH
X
X
X
X
X
X
High Z
High Z
VIL
X
X
X
X
X
X
X
High Z
High Z
4
VIH
VIL
VIL
VIH
VID
VIL
X
X
89H
High Z
4, 5
VIH
VIL
VIL
VIH
VID
VIH
X
X
74H
75H
High Z
6, 7, 8
VIH
VIL
VIH
VIL
X
X
X
X
DIN
High Z
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL or VIH for control pins and addresses, VPPL or VPPH for VPP.
3. See DC characteristics for VPPL, VPPH, VHH, VID voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A1 –A17 e X.
5. Device ID e 2274H for 28F200BX-T and 2275H for 28F200BX-B.
6. Refer to Table 4 for valid DIN during a write operation.
7. Command writes for Block Erase or Word/Byte Write are only executed when VPP e VPPH.
8. To write or erase the boot block, hold RPÝ at VHH.
9. RPÝ must be at GND g 0.2V to meet the 1.2 mA maximum deep power-down current.
16
DQ0–7
28F200BX-T/B, 28F002BX-T/B
4.2 28F002BX Bus Operations
Table 3. Bus Operations
Mode
Read
Notes
1, 2
Output Disable
Standby
Deep Power-Down
Intelligent Identifier (Mfr)
RPÝ
CEÝ
OEÝ
WEÝ
A9
A0
VPP
DQ0–7
VIH
VIL
VIL
VIH
X
X
X
DOUT
VIH
VIL
VIH
VIH
X
X
X
High Z
VIH
VIH
X
X
X
X
X
High Z
9
VIL
X
X
X
X
X
X
High Z
3, 4
VIH
VIL
VIL
VIH
VID
VIL
X
89H
Intelligent Identifier (Device)
3, 4, 5
VIH
VIL
VIL
VIH
VID
VIH
X
7CH
7DH
Write
6, 7, 8
VIH
VIL
VIH
VIL
X
X
X
DIN
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL or VIH for control pins and addresses, VPPL or VPPH for VPP.
3. See DC characteristics for VPPL, VPPH, VHH, VID voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A1 –A16 e X.
5. Device ID e 7CH for 28F002BX-T and 7DH for 28F002BX-B.
6. Refer to Table 4 for valid DIN during a write operation.
7. Command writes for Block Erase or byte program are only executed when VPP e VPPH.
8. Program or erase the Boot block by holding RPÝ at VHH.
9. RPÝ must be at GND g 0.2V to meet the 1.2 mA maximum deep power-down current.
4.3 Read Operations
(DQ [0:15] or DQ [0:7] ) are tri-stated. Data input is
then controlled by WEÝ.
The 2-Mbit boot block flash family has three user
read modes; Array, Intelligent Identifier, and Status
Register. Status Register read mode will be discussed in detail in the ‘‘Write Operations’’ section.
4.3.1.2 Input Control
During power-up conditions (VCC supply ramping), it
takes a maximum of 600 ns from when VCC is at
4.5V minimum to valid data on the outputs.
With WEÝ at logic-high level (VIH), input to the device is disabled. Data Input/Output pins (DQ- [0:15]
or DQ [0:7]) are controlled by OEÝ.
4.3.2 INTELLIGENT IDENTlFlERS
4.3.1 READ ARRAY
If the memory is not in the Read Array mode, it is
necessary to write the appropriate read mode command to the CUI. The 2-Mbit boot block flash family
has three control functions, all of which must be
logically active, to obtain data at the outputs.
Chip-Enable CEÝ is the device selection control.
Power-Down RPÝ is the device power control. Output-Enable OEÝ is the DATA INPUT/OUTPUT
(DQ [0:15] or DQ [0:7] ) direction control and when
active is used to drive data from the selected memory on to the I/O bus.
28F200BX Products
The manufacturer and device codes are read via the
CUI or by taking the A9 pin to 12V. Writing 90H to
the CUI places the device into Intelligent Identifier
read mode. A read of location 00000H outputs the
manufacturer’s identification code, 0089H, and location 00001H outputs the device code; 2274H for
28F200BX-T, 2275H for 28F200BX-B. When
BYTEÝ is at a logic low only the lower byte of the
above signatures is read and DQ15/Ab1 is a ‘‘don’t
care’’ during Intelligent Identifier mode. A read array
command must be written to the CUI to return to the
read array mode.
4.3.1.1 Output Control
With OEÝ at logic-high level (VIH), the output from
the device is disabled and data input/output pins
17
28F200BX-T/B, 28F002BX-T/B
28F002BX Products
4.4.1 BOOT BLOCK WRITE OPERATIONS
The manufacturer and device codes are also read
via the CUI or by taking the A9 pin to 12V. Writing
90H to the CUI places the device into Intelligent
Identifier read mode. A read of location 00000H outputs the manufacturer’s identification code, 89H,
and location 00001H outputs the device code; 7CH
for 28F002BX-T, 7DH for 28F002BX-B.
In the case of Boot Block modifications (write and
erase), RPÝ is set to VHH e 12V typically, in addition to VPP at high voltage. However, if RPÝ is not at
VHH when a program or erase operation of the boot
block is attempted, the corresponding status register
bit (Bit 4 for Program and Bit 5 for Erase, refer to
Table 5 for Status Register Definitions) is set to indicate the failure to complete the operation.
4.4 Write Operations
Commands are written to the CUI using standard microprocessor write timings. The CUl serves as the
interface between the microprocessor and the internal chip operation. The CUI can decipher Read Array, Read Intelligent Identifier, Read Status Register,
Clear Status Register, Erase and Program commands. In the event of a read command, the CUI
simply points the read path at either the array, the
intelligent identifier, or the status register depending
on the specific read command given. For a program
or erase cycle, the CUI informs the write state machine that a write or erase has been requested. During a program cycle, the Write State Machine will
control the program sequences and the CUI will only
respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase suspend.
After the Write State Machine has completed its
task, it will allow the CUI to respond to its full command set. The CUI will stay in the current command
state until the microprocessor issues another command.
The CUI will successfully initiate an erase or write
operation only when VPP is within its voltage range.
Depending upon the application, the system designer may choose to make the VPP power supply
switchable, available only when memory updates
are desired. The system designer can also choose
to ‘‘hard-wire’’ VPP to 12V. The 2 Mbit boot block
flash family is designed to accommodate either design practice. It is recommended that RPÝ be tied to
logical Reset for data protection during unstable
CPU reset function as described in the ‘‘Product
Family Overview’’ section.
18
4.4.2 COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) serves as the
interface to the microprocessor. The CUI points the
read/write path to the appropriate circuit block as
described in the previous section. After the WSM
has completed its task, it will set the WSM Status bit
to a ‘‘1’’, which will also allow the CUI to respond to
its full command set. Note that after the WSM has
returned control to the CUI, the CUI will remain in its
current state.
4.4.2.1 Command Set
Command
Codes
Device Mode
00
10
20
40
50
70
90
B0
D0
FF
Invalid/Reserved
Alternate Program Setup
Erase Setup
Program Setup
Clear Status Register
Read Status Register
Intelligent Identifier
Erase Suspend
Erase Resume/Erase Confirm
Read Array
4.4.2.2 Command Function Descriptions
Device operations are selected by writing specific
commands into the CUI. Table 4 defines the 2-Mbit
boot block flash family commands.
28F200BX-T/B, 28F002BX-T/B
Table 4. Command Definitions
Command
Bus
Notes
First Bus Cycle
Second Bus Cycle
Cycles
Req’d
8
Operation Address Data Operation Address Data
Read Array/Reset
1
1
Write
X
FFH
Intelligent Identifier
3
2, 4
Write
X
90H
Read
IA
IID
Read Status Register
2
3
Write
X
70H
Read
X
SRD
Clear Status Register
1
Write
X
50H
Erase Setup/Erase Confirm
2
5
Write
BA
20H
Write
BA
D0H
Word/Byte Write Setup/Write
2
6, 7
Write
WA
40H
Write
WA
WD
Erase Suspend/Erase Resume
2
Write
X
B0H
Write
X
D0H
Alternate Word/Byte Write Setup/Write
2
6, 7
Write
WA
10H
Write
WA
WD
NOTES:
1. Bus operations are defined in Tables 1, 2, 3.
2. IA e Identifier Address: 00H for manufacturer code, 01H for device code.
3. SRD e Data read from Status Register.
4. IID e Intelligent Identifier Data.
Following the Intelligent Identifier Command, two read operations access manufacturer and device codes.
5. BA e Address within the block being erased.
6. WA e Address to be written.
WD e Data to be written at location PA.
7. Either 40H or 10H command is valid.
8. When writing commands to the device, the upper data bus [DQ8 – DQ15] e X (28F200BX-only) which is either VCC or
VSS to avoid burning additional current.
Invalid/Reserved
Read Status Register (70H)
These are unassigned commands. It is not recommended that the customer use any command other
than the valid commands specified above. Intel reserves the right to redefine these codes for future
functions.
This is one of the two commands that is executable
while the state machine is operating. After this command is written, a read of the device will output the
contents of the status register, regardless of the address presented to the device.
Read Array (FFH)
The device automatically enters this mode after program or erase has completed.
This single write command points the read path at
the array. If the host CPU performs a CEÝ/OEÝ
controlled read immediately following a two-write sequence that started the WSM, then the device will
output status register contents. If the Read Array
command is given after Erase Setup the device is
reset to read the array. A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup.
Inteligent Identifier (90H)
After this command is executed, the CUI points the
output path to the Intelligent Identifier circuits. Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address A0 is used in this mode, all
other address inputs are ignored).
Clear Status Register (50H)
The WSM can only set the Program Status and
Erase Status bits in the status register, it can not
clear them. Two reasons exist for operating the
status register in this fashion. The first is a synchronization. The WSM does not know when the host
CPU has read the status register, therefore it would
not know when to clear the status bits. Secondly, if
the CPU is programming a string of bytes, it may be
more efficient to query the status register after programming the string. Thus, if any errors exist while
programming the string, the status register will return
the accumulated error status.
19
28F200BX-T/B, 28F002BX-T/B
Program Setup (40H or 10H)
This command simply sets the CUI into a state such
that the next write will load the address and data
registers. Either 40H or 10H can be used for Program Setup. Both commands are included to accommodate efforts to achieve an industry standard
command code set.
Program
The second write after the program setup command,
will latch addresses and data. Also, the CUI initiates
the WSM to begin execution of the program algorithm. While the WSM finishes the algorithm, the device will output Status Register contents. Note that
the WSM cannot be suspended during programming.
Erase Setup (20H)
Prepares the CUI for the Erase Confirm command.
No other action is taken. lf the next command is not
an Erase Confirm command then the CUI will set
both the Program Status and Erase Status bits of the
Status Register to a ‘‘1’’, place the device into the
Read Status Register state, and wait for another
command.
Erase Confirm (D0H)
If the previous command was an Erase Setup command, then the CUI will enable the WSM to erase, at
the same time closing the address and data latches,
and respond only to the Read Status Register and
Erase Suspend commands. While the WSM is executing, the device will output Status Register data
when OEÝ is toggled low. Status Register data can
only be updated by toggling either OEÝ or CEÝ low.
Erase Suspend (B0H)
This command only has meaning while the WSM is
executing an Erase operation, and therefore will only
be responded to during an erase operation. After
this command has been executed, the CUl will set
an output that directs the WSM to suspend Erase
operations, and then return to responding to only
Read Status Register or to the Erase Resume commands. Once the WSM has reached the Suspend
state, it will set an output into the CUI which allows
the CUI to respond to the Read Array, Read Status
Register, and Erase Resume commands. In this
mode, the CUI will not respond to any other commands. The WSM will also set the WSM Status bit to
a ‘‘1’’. The WSM will continue to run, idling in the
SUSPEND state, regardless of the state of all input
20
control pins, with the exclusion of RPÝ. RPÝ will
immediately shut down the WSM and the remainder
of the chip. During a suspend operation, the data
and address latches will remain closed, but the address pads are able to drive the address into the
read path.
Erase Resume (D0H)
This command will cause the CUI to clear the Suspend state and set the WSM Status bit to a ‘‘0’’, but
only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.
4.4.3 STATUS REGISTER
The 2-Mbit boot block flash family contains a status
register which may be read to determine when a program or erase operation is complete, and whether
that operation completed successfully. The status
register may be read at any time by writing the Read
Status command to the CUI. After writing this command, all subsequent Read operations output data
from the status register until another command is
written to the CUI. A Read Array command must be
written to the CUI to return to the Read Array mode.
The status register bits are output on DQ [0:7]
whether the device is in the byte-wide (x8) or wordwide (x16) mode for the 28F200BX. In the word-wide
mode the upper byte, DQ [8:15] is set to 00H during
a Read Status command. In the byte-wide mode,
DQ [8:14] are tri-stated and DQ15/Ab1 retains the
low order address function.
It should be noted that the contents of the status
register are latched on the falling edge of OEÝ or
CEÝ whichever occurs last in the read cycle. This
prevents possible bus errors which might occur if the
contents of the status register change while reading
the status register. CEÝ or OEÝ must be toggled
with each subsequent status read, or the completion
of a program or erase operation will not be evident.
The Status Register is the interface between the microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate
the status of the WSM, and will also hold the bits
indicating whether or not the WSM was successful in
performing the desired operation. The WSM sets
status bits ‘‘Three’’ through ‘‘Seven’’ and clears bits
‘‘Six’’ and ‘‘Seven’’, but cannot clear status bits
‘‘Three’’ through ‘‘Five’’. These bits can only be
cleared by the controlling CPU through the use of
the Clear Status Register command.
28F200BX-T/B, 28F002BX-T/B
4.4.3.1 Status Register Bit Definition
Table 5. Status Register Definitions
WSMS
ESS
ES
PS
VPPS
R
R
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 e WRITE STATE MACHINE STATUS
1 e Ready
0 e Busy
Write State Machine Status bit must first be checked to
determine byte/word program or block erase completion,
before the Program or Erase Status bits are checked for
success.
SR.6 e ERASE SUSPEND STATUS
1 e Erase Suspended
0 e Erase in Progress/Completed
When Erase Suspend is issued, WSM halts execution
and sets both WSMS and ESS bits to ‘‘1’’. ESS bit remains set to ‘‘1’’ until an Erase Resume command is issued.
SR.5 e ERASE STATUS
1 e Error in Block Erasure
0 e Successful Block Erase
When this bit is set to ‘‘1’’. WSM has applied the maximum number of erase pulses to the block and is still unable to successfully perform an erase verify.
SR.4 e PROGRAM STATUS
1 e Error in Byte/Word Program
0 e Successful Byte/Word Program
When this bit is set to ‘‘1’’, WSM has attempted but failed
to Program a byte or word.
SR.3 e VPP STATUS
1 e VPP Low Detect; Operation Abort
0 e VPP OK
The VPP Status bit, unlike an A/D converter, does not
provide continuous indication of VPP level. The WSM interrogates the VPP level only after the byte write or block
erase command sequences have been entered and informs the system if VPP has not been switched on. The
VPP Status bit is not guaranteed to report accurate feedback between VPPL and VPPH.
SR.2 – SR.0 e RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use and should be
masked out when polling the Status Register.
4.4.3.2 Clearing the Status Register
4.4.4 PROGRAM MODE
Certain bits in the status register are set by the write
state machine, and can only be reset by the system
software. These bits can indicate various failure conditions. By allowing the system software to control
the resetting of these bits, several operations may
be performed (such as cumulatively programming
several bytes or erasing multiple blocks in sequence). The status register may then be read to
determine if an error occurred during that programming or erasure series. This adds flexibility to the
way the device may be programmed or erased. To
clear the status register, the Clear Status Register
command is written to the CUI. Then, any other
command may be issued to the CUI. Note again that
before a read cycle can be initiated, a Read Array
command must be written to the CUI to specify
whether the read data is to come from the array,
status register, or Intelligent Identifier.
Program is executed by a two-write sequence. The
Program Setup command is written to the CUI followed by a second write which specifies the address
and data to be programmed. The write state machine will execute a sequence of internally timed
events to:
1. Program the desired bits of the addressed memory word (byte), and
2. Verify that the desired bits are sufficiently programmed
Programming of the memory results in specific bits
within a byte or word being changed to a ‘‘0’’.
If the user attempts to program ‘‘1’’s, there will be no
change of the memory cell content and no error occurs.
Similar to erasure, the status register indicates
whether programming is complete. While the program sequence is executing, bit 7 of the status register is a ‘‘0’’. The status register can be polled by
21
28F200BX-T/B, 28F002BX-T/B
toggling either CEÝ or OEÝ to determine when the
program sequence is complete. Only the Read
Status Register command is valid while programming is active.
When programming is complete, the status bits,
which indicate whether the program operation was
successful, should be checked. If the programming
operation was unsuccessful, Bit 4 of the status register is set to a ‘‘1’’ to indicate a Program Failure. lf Bit
3 is set then VPP was not within acceptable limits,
and the WSM will not execute the programming sequence.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, it
must be recognized that reads from the memory,
status register, or Intelligent Identifier cannot be accomplished until the CUI is given the appropriate
command. A Read Array command must first be given before memory contents can be read.
Figure 12 shows a system software flowchart for device byte programming operation. Figure 13 shows a
similar flowchart for device word programming operation (28F200BX-only).
4.4.5 ERASE MODE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
CUI, along with the addresses, A [12:16] for the
28F200BX or A [12:17] for the 28F002BX, identifying
the block to be erased. These addresses are latched
internally when the Erase Confirm command is issued. Block erasure results in all bits within the block
being set to ‘‘1’’.
The WSM will execute a sequence of internally
timed events to:
1. Program all bits within the block
2. Verify that all bits within the block are sufficiently
programmed
3. Erase all bits within the block and
4. Verify that all bits within the block are sufficiently
erased
While the erase sequence is executing, Bit 7 of the
status register is a ‘‘0’’.
When the status register indicates that erasure is
complete, the status bits, which indicate whether the
erase operation was successful, should be checked.
If the erasure operation was unsuccessful, Bit 5 of
the status register is set to a ‘‘1’’ to indicate an
Erase Failure. If VPP was not within acceptable limits
after the Erase Confirm command is issued, the
WSM will not execute an erase sequence; instead,
Bit 5 of the status register is set to a ‘‘1’’ to indicate
22
an Erase Failure, and Bit 3 is set to a ‘‘1’’ to identify
that VPP supply voltage was not within acceptable
limits.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after erasure is completed; however, it must
be recognized that reads from the memory array,
status register, or Intelligent Identifier can not be accomplished until the CUI is given the appropriate
command. A Read Array command must first be given before memory contents can be read.
Figure 14 shows a system software flowchart for
Block Erase operation.
4.4.5.1 Suspending and Resuming Erase
Since an erase operation typically requires 1 to 3
seconds to complete, an Erase Suspend command
is provided. This allows erase-sequence interruption
in order to read data from another block of the memory. Once the erase sequence is started, writing the
Erase Suspend command to the CUI requests that
the Write State Machine (WSM) pause the erase sequence at a predetermined point in the erase algorithm. The status register must be read to determine
when the erase operation has been suspended.
At this point, a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register operation.
Figure 15 shows a system software flowchart detailing the operation.
During Erase Suspend mode, the chip can go into a
pseudo-standby mode by taking CEÝ to VIH and the
active current is now a maximum of 10 mA. If the
chip is enabled while in this mode by taking CEÝ to
VIL, the Erase Resume command can be issued to
resume the erase operation.
Upon completion of reads from any block other than
the block being erased, the Erase Resume command must be issued. When the Erase Resume
command is given, the WSM will continue with the
erase sequence and complete erasing the block. As
with the end of erase, the status register must be
read, cleared, and the next instruction issued in order to continue.
4.4.6 EXTENDED CYCLING
Intel has designed extended cycling capability into
its ETOX III flash memory technology. The 2-Mbit
boot block flash family is designed for 100,000 program/erase cycles on each of the five blocks. The
combination of low electric fields, clean oxide processing and minimized oxide area per memory cell
subjected to the tunneling electric field, results in
very high cycling capability.
28F200BX-T/B, 28F002BX-T/B
Bus
Operation
Command
Comments
Write
Setup
Program
Data e 40H
Address e Byte to be
programmed
Write
Program
Data to be programmed
Address e Byte to be
programmed
Read
Status Register Data.
Toggle OEÝ or CEÝ to update
Status Register
Standby
Check SR.7
1 e Ready, 0 e Busy
Repeat for subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.
Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
290448 – 6
Full Status Check Procedure
Bus
Operation
Command
Comments
Standby
Check SR.3
1 e VPP Low Detect
Standby
Check SR.4
1 e Byte Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290448 – 7
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 12. Automated Byte Programming Flowchart
23
28F200BX-T/B, 28F002BX-T/B
Bus
Operation
Command
Comments
Write
Setup
Program
Data e 40H
Address e Word to be
programmed
Write
Program
Data to be programmed
Address e Word to be
programmed
Read
Status Register Data.
Toggle OEÝ or CEÝ to update
Status Register
Standby
Check SR.7
1 e Ready, 0 e Busy
Repeat for subsequent words.
Full status check can be done after each word or after a
sequence of words.
290448 – 8
Write FFH after the last word programming operation to
reset the device to Read Array Mode.
Full Status Check Procedure
Bus
Operation
Command
Comments
Standby
Check SR.3
1 e VPP Low Detect
Standby
Check SR.4
1 e Word Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290448 – 9
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple words are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 13. Automated Word Programming Flowchart
24
28F200BX-T/B, 28F002BX-T/B
Bus
Operation
Command
Comments
Write
Setup
Erase
Data e 20H
Address e Within block to be
erased
Write
Erase
Data e D0H
Address e Within block to be
erased
Read
Status Register Data.
Toggle OEÝ or CEÝ to update
Status Register
Standby
Check SR.7
1 e Ready, 0 e Busy
Repeat for subsequent blocks.
Full status check can be done after each block or after a
sequence of blocks.
290448 – 10
Write FFH after the last block erase operation to reset the
device to Read Array Mode.
Full Status Check Procedure
Bus
Operation
Command
Comments
Standby
Check SR.3
1 e VPP Low Detect
Standby
Check SR.4,5
Both 1 e Command Sequence
Error
Standby
Check SR.5
1 e Block Erase Error
SR.3 MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
290448 – 11
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 14. Automated Block Erase Flowchart
25
28F200BX-T/B, 28F002BX-T/B
Bus
Operation
Write
Command
Erase
Suspend
Comments
Data e B0H
Read
Status Register Data.
Toggle OEÝ or CEÝ to
update Status Register
Standby
Check SR.7
1 e Ready
Standby
Check SR.6
1 e Suspended
Write
Read Array
Read
Write
Data e FFH
Read array data from block
other than that being
erased.
Erase Resume
Data e D0H
290448 – 12
Figure 15. Erase Suspend/Resume Flowchart
4.5 Power Consumption
4.5.1 ACTIVE POWER
With CEÝ at a logic-low level and RPÝ at a logichigh level, the device is placed in the active mode.
The device ICC current is a maximum of 60 mA at
10 MHz with TTL input signals.
4.5.2 AUTOMATIC POWER SAVINGS
Automatic Power Savings (APS) is a low power feature during active mode of operation. The 2-Mbit
family of products incorporate Power Reduction
Control (PRC) circuitry which basically allows the device to put itself into a low current state when it is
not being accessed. After data is read from the
memory array, PRC logic controls the device’s power consumption by entering the APS mode where
26
maximum ICC current is 3 mA and typical ICC current
is 1 mA. The device stays in this static state with
outputs valid until a new location is read.
4.5.3 STANDBY POWER
With CEÝ at a logic-high level (VIH), and the CUI in
read mode, the memory is placed in standby mode
where the maximum ICC standby current is 100 mA
with CMOS input signals. The standby operation disables much of the device’s circuitry and substantially
reduces device power consumption. The outputs
(DQ [0:15] or DQ [0:7] ) are placed in a high-impedance state independent of the status of the OEÝ
signal. When the 2-Mbit boot block flash family is
deselected during erase or program functions, the
devices will continue to perform the erase or program function and consume program or erase active
power until program or erase is completed.
28F200BX-T/B, 28F002BX-T/B
4.5.4 RESET/DEEP POWER-DOWN
The 2-Mbit boot block flash family supports a typical
ICC of 0.2 mA in deep power-down mode. One of the
target markets for these devices is in portable equipment where the power consumption of the machine
is of prime importance. The 2-Mbit boot block flash
family has a RPÝ pin which places the device in the
deep power-down mode. When RPÝ is at a logiclow (GND g 0.2V), all circuits are turned off and the
device typically draws 0.2 mA of VCC current.
During read modes, the RPÝ pin going low deselects the memory and places the output drivers in a
high impedance state. Recovery from the deep power-down state, requires a maximum of 300 ns to access valid data (tPHQV).
During erase or program modes, RPÝ low will abort
either erase or program operation. The contents of
the memory are no longer valid as the data has been
corrupted by the RPÝ function. As in the read mode
above, all internal circuitry is turned off to achieve
the 0.2 mA current level.
RPÝ transitions to VIL or turning power off to the
device will clear the status register.
This use of RPÝ during system reset is important
with automated write/erase devices. When the system comes out of reset it expects to read from the
flash memory. Automated flash memories provide
status information when accessed during write/
erase modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data. Intel’s
Flash Memories allow proper CPU initialization following a system reset through the use of the RPÝ
input. In this application RPÝ is controlled by the
same RESETÝ signal that resets the system CPU.
4.6 Power-Up Operation
The 2-Mbit boot block flash family is designed to
offer protection against accidental block erasure or
programming during power transitions. Upon powerup the 2-Mbit boot block flash family is indifferent as
to which power supply, VPP or VCC, powers-up first.
Power suppy sequencing is not required.
The 2-Mbit boot block flash family ensures the CUI is
reset to the read mode on power-up.
In addition, on power-up the user must either drop
CEÝ low or present a new address to ensure valid
data at the outputs.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active. Since both WEÝ and CEÝ must be low for a
command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides
an added level of protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. Finally, the device is disabled until RPÝ is brought to VIH,
regardless of the state of its control inputs. This feature provides yet another level of memory protection.
4.7 Power Supply Decoupling
Flash memory’s power switching characteristics require careful device decoupling methods. System
designers are interested in 3 supply current issues:
# Standby current levels (ICCS)
# Active current levels (ICCR)
# Transient peaks produced by falling and rising
edges of CEÝ.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 mF ceramic capacitor
connected between each VCC and GND, and between its VPP and GND. These high frequency, lowinherent inductance capacitors should be placed as
close as possible to the package leads.
4.7.1 VPP TRACE ON PRINTED CIRCUIT
BOARDS
Writing to flash memories while they reside in the
target system, requires special consideration of the
VPP power supply trace by the printed circuit board
designer. The VPP pin supplies the flash memory
cell’s current for programming and erasing. One
should use similar trace widths and layout considerations given to the VCC power supply trace. Adequate VPP supply traces and decoupling will decrease spikes and overshoots.
4.7.2 VCC, VPP AND RPÝ TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by VPP or CEÝ transitions or WSM actions. Its state upon power-up, after exit from deep power-down mode or after VCC
transitions below VLKO (Lockout voltage), is Read
Array mode.
After any word/byte write or block erase operation is
complete and even after VPP transitions down to
VPPL, the CUI must be reset to Read Array mode via
the Read Array command when accesses to the
flash memory are desired.
27
28F200BX-T/B, 28F002BX-T/B
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Commercial Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0§ C to 70§ C(1)
During Block Erase
and Word/Byte WriteÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0§ C to 70§ C
Temperature Under BiasÀÀÀÀÀÀÀ b 10§ C to a 80§ C
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
Extended Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 40§ C to a 85§ C
During Block Erase
and Word/Byte Write ÀÀÀÀÀÀÀÀÀ b 40§ C to a 85§ C
Temperature Under BiasÀÀÀÀÀÀÀ b 40§ C to a 85§ C
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 125§ C
Voltage on Any Pin
(except VCC, VPP, A9 and RPÝ)
with Respect to GND ÀÀÀÀÀÀÀÀ b 2.0V to a 7.0V(2)
Voltage on Pin RPÝ or Pin A9
with Respect to GND ÀÀÀÀÀ b 2.0V to a 13.5V(2, 3)
VPP Program Voltage with Respect
to GND during Block Erase
and Word/Byte Write ÀÀÀÀÀ b 2.0V to a 14.0V(2, 3)
VCC Supply Voltage
with Respect to GND ÀÀÀÀÀÀÀÀ b 2.0V to a 7.0V(2)
Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA(4)
OPERATING CONDITIONS
Symbol
Parameter
Notes
Min
Max
Units
TA
Operating Temperature
0
70
§C
VCC
VCC Supply Voltage (10%)
5
4.50
5.50
V
VCC
VCC Supply Voltage (5%)
6
4.75
5.25
V
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is b0.5V on input/output pins. During transitions, this level may undershoot to b2.0V for periods
k 20 ns. Maximum DC voltage on input/output pins is VCC a 0.5V which, during transitions, may overshoot to VCC
a 2.0V for periods k 20 ns.
3. Maximum DC voltage on VPP may overshoot to a 14.0V for periods k20 ns. Maximum DC voltage on RPÝ or A9 may
overshoot to 13.5V for periods k 20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. 10% VCC specifications reference the 28F200BX-60/28F002BX-60 in their standard test configuration, and the
28F200BX-80/28F002BX-80.
6. 5% VCC specifications reference the 28F200BX-60/28F002BX-60 in their high speed test configuration.
DC CHARACTERISTICS
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Test Condition
ILI
Input Load Current
1
g 1.0
mA
VCC e VCC Max
VIN e VCC or GND
ILO
Output Leakage Current
1
g 10
mA
VCC e VCC Max
VOUT e VCC or GND
28
28F200BX-T/B, 28F002BX-T/B
DC CHARACTERISTICS
Symbol
ICCS
(Continued)
Parameter
VCC Standby Current
ICCD
VCC Deep Power-Down Current
ICCR
Notes Min Typ
1, 3
Max
Unit
1.5
mA VCC e VCC Max
CEÝ e RPÝ e VIH
Test Condition
100
mA VCC e VCC Max
CEÝ e RPÝ e VCC g 0.2V
28F200BX:
BYTEÝ e VCC g 0.2V or GND
1
0.20
1.2
mA RPÝ e GND g 0.2V
VCC Read Current for
28F200BX Word-Wide and
Byte-Wide Mode and
28F002BX Byte-Wide Mode
1, 5,
6, 10
20
55
mA VCC e VCC Max, CEÝ e GND
f(max) e 10 MHz, f(typ) e 5 MHz
IOUT e 0 mA, CMOS Inputs
20
60
mA VCC e VCC Max, CEÝ e GND
f(max) e 10 MHz, f(typ) e 5 MHz
IOUT e 0 mA, TTL Inputs
ICCW
VCC Word Byte Write Current
1, 4
65
mA Word Write in Progress
ICCE
VCC Block Erase Current
1, 4
30
mA Block Erase in Progress
ICCES
VCC Erase Suspend Current
1, 2
10
mA CEÝ e VIH
Block Erase Suspended
IPPS
VPP Standby Current
1
g 15
IPPD
VPP Deep Power-Down Current
1
5.0
mA RPÝ e GND g 0.2V RPÝ
IPPR
VPP Read Current
1
200
mA VPP l VCC
IPPW
VPP Word Write Current
1, 4
40
mA VPP e VPPH
Word Write in Progress
IPPW
VPP Byte Write Current
1, 4
30
mA VPP e VPPH
Byte Write in Progress
IPPE
VPP Block Erase Current
1, 4
30
mA VPP e VPPH
Block Erase in Progress
IPPES
VPP Erase Suspend Current
1
200
mA VPP e VPPH
Block Erase Suspended
IRPÝ
RPÝ Boot Block Unlock Current 1, 4
500
mA RPÝ e VHH
IID
A9 Intelligent Identifier Current
500
mA A9 e VID
VID
A9 Intelligent Identifier Voltage
11.5
VIL
Input Low Voltage
b 0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
5
1, 4
mA VPP s VCC
13.0
V
0.8
V
VCC a 0.5 V
0.45
V VCC e VCC Min
IOL e 5.8 mA
29
28F200BX-T/B, 28F002BX-T/B
DC CHARACTERISTICS
Symbol
(Continued)
Parameter
VOH1
Output High Voltage (TTL)
VOH2
Output High Voltage (CMOS)
Notes
Min
Typ Max Unit
Test Condition
2.4
V
VCC e VCC Min
IOH e b 2.5 mA
0.85 VCC
V
VCC e VCC Min
IOH e b 2.5 mA
VCC b 0.4
VCC e VCC Min
IOH e b 100 mA
VPPL
VPP during Normal Operations
3
0.0
6.5
V
VPPH
VPP during Erase/Write Operations
7
11.4
12.0 12.6
V
VPPH
VPP during Erase/Write Operations
8
10.8
12.0 13.2
V
VLKO
VCC Erase/Write Lock Voltage
2.0
VHH
RPÝ Unlock Voltage
11.5
V
13.0
V
Boot Block Write/Erase
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC e 5.0V, VPP e 12.0V, T e 25§ C. These currents
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
of ICCES and ICCR.
3. Block Erases and Word/Byte Writes are inhibited when VPP e VPPL and not guaranteed in the range between VPPH and
VPPL.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA typical in static operation.
6. CMOS Inputs are either VCC g 0.2V or GND g 0.2V. TTL Inputs are either VIL or VIH.
7. VPP e 12.0V g 5% for applications requiring 100,000 block erase cycles.
8. VPP e 12.0V g 10% for applications requiring wider VPP tolerances at 100 block erase cycles.
9. For the 28F002BX, address pin A10 follows the COUT capacitance numbers.
10. ICCR typical is 25 mA for X16 active read current.
EXTENDED TEMPERATURE OPERATING CONDITIONS
Symbol
Parameter
TA
Operating Temperature
VCC
VCC Supply Voltage (10%)
30
Notes
5
Min
Max
Units
b 40
a 85
§C
4.50
5.50
V
28F200BX-T/B, 28F002BX-T/B
DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION
Symbol
Parameter
Notes Min Typ Max Unit
Test Condition
ILI
Input Load Current
1
g 1.0
mA VCC e VCC Max
VIN e VCC or GND
ILO
Output Leakage Current
1
g 10
mA VCC e VCC Max
VOUT e VCC or GND
ICCS
VCC Standby Current
1, 3
1.5
mA VCC e VCC Max
CEÝ e RPÝ e VIH
100
mA VCC e VCC Max
CEÝ e RPÝ e VCC g 0.2V
28F200BX:
BYTEÝ e VCC g 0.2V or GND
20
mA RPÝ e GND g 0.2V
60
mA VCC e VCC Max, CEÝ e GND
f e 10 MHz, IOUT e 0 mA
CMOS Inputs
65
mA VCC e VCC Max, CEÝ e VIL
f e 10 MHz, IOUT e 0 mA
TTL Inputs
70
mA Word Write in Progress
40
mA Block Erase in Progress
10
mA Block Erase Suspended
CEÝ e VIH
ICCD
VCC Deep Power-Down Current
1
0.20
ICCR
VCC Read Current for
28F200BX Word-Wide and
Byte-Wide Mode and
28F002BX Byte-Wide Mode
1, 5,
6
ICCW
VCC Word Byte Write Current
1
ICCE
VCC Block Erase Current
ICCES
VCC Erase Suspend Current
IPPS
VPP Standby Current
1
g 15
IPPD
VPP Deep Power-Down Current
1
5.0
mA RPÝ e GND g 0.2V
IPPR
VPP Read Current
1
200
mA VPP l VCC
IPPW
VPP Word Write Current
1, 4
40
mA VPP e VPPH
Word Write in Progress
IPPW
VPP Byte Write Current
1, 4
30
mA VPP e VPPH
Byte Write in Progress
IPPE
VPP Block Erase Current
1, 4
30
mA VPP e VPPH
Block Erase in Progress
IPPES
VPP Erase Suspend Current
1
200
mA VPP e VPPH
Block Erase Suspended
IRPÝ
RPÝ Boot Block Unlock Current
1, 4
500
mA RPÝ e VHH
IID
A9 Intelligent Identifier Current
500
mA A9 e VID
VID
A9 Intelligent Identifier Voltage
1
1, 2
5
1
11.5
13.0
mA VPP s VCC
V
31
28F200BX-T/B, 28F002BX-T/B
DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION
Symbol
Parameter
Notes
Min
Typ
Max
Unit
(Continued)
Test Condition
VIL
Input Low Voltage
b 0.5
0.8
V
VIH
Input High Voltage
2.0
VCC a 0.5
V
VOL
Output Low Voltage
0.45
V
VCC e VCC Min
IOL e 5.8 mA
VOH1
Output High Voltage (TTL)
2.4
V
VCC e VCC Min
IOH e b 2.5 mA
VOH2
Output High Voltage (CMOS)
0.85 VCC
V
VCC e VCC Min
IOH e b 2.5 mA
VCC b 0.4
VCC e VCC Min
IOH e b 100 mA
VPPL
VPP during Normal Operations
3
0.0
6.5
V
VPPH
VPP during Erase/Write Operations
7
11.4
12.0
12.6
V
VPPH
VPP during Erase/Write Operations
8
10.8
12.0
13.2
VLKO
VCC Erase/Write Lock Voltage
2.0
VHH
RPÝ Unlock Voltage
11.5
V
V
13.0
V
Boot Block Write/Erase
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC e 5.0V, VPP e 12.0V, T e 25§ C. These currents
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
of ICCES and ICCR.
3. Block Erases and Word/Byte Writes are inhibited when VPP e VPPL and not guaranteed in the range between VPPH and
VPPL.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA typical in static operation.
6. CMOS Inputs are either VCC g 0.2V or GND g 0.2V. TTL Inputs are either VIL or VIH.
7. VPP e 12.0V g 5% for applications requiring 100,000 block erase cycles.
8. VPP e 12.0V g 10% for applications requiring wider VPP tolerances at 100 block erase cycles.
9. For the 28F002BX, address pin A10 follows the COUT capacitance numbers.
10. ICCR typical is 25 mA for X16 active read current.
32
28F200BX-T/B, 28F002BX-T/B
CAPACITANCE(1, 2)
Symbol
TA e 25§ C, f e 1 MHz
Typ
Max
Unit
CIN
Input Capacitance
Parameter
6
8
pF
VIN e 0V
Condition
COUT
Output Capacitance
10
12
pF
VOUT e 0V
NOTES:
1. Sampled, not 100% tested.
2. For the 28F002BX, address pin A10 follows the COUT capacitance numbers.
STANDARD TEST CONFIGURATION(1)
STANDARD AC INPUT/OUTPUT REFERENCE WAVEFORM
STANDARD AC TESTING
LOAD CIRCUIT
290448 – 14
AC test inputs are driven at VOH (2.4 VTTL) for a Logic ‘‘1’’ and VOL
(0.45 VTTL) for a logic ‘‘0’’. Input timing begins at VIH (2.0 VTTL) and VIL
(0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10%
to 90%) k 10 ns.
290448 – 13
CL e 100 pF
CL Includes Jig Capacitance
RL e 3.3 KX
HIGH SPEED TEST CONFIGURATION(2)
HIGH SPEED AC INPUT/OUTPUT REFERENCE WAVEFORM
HIGH SPEED AC TESTING
LOAD CIRCUIT
290448 – 22
AC test inputs are driven at 3.0V for a Logic ‘‘1’’ and 0.0V for a logic ‘‘0’’.
Input timing begins, and output timing ends, at 1.5V. Input rise and fall times
(10% to 90%) k 10 ns.
NOTES:
1. Testing characteristics for 28F200BX-60/28F002BX-60 in standard test configuration and 28F200BX-80/28F002BX-80.
2. Testing characteristics for 28F200BX-60/28F002BX-60 in high speed test configuration.
290448 – 21
CL e 30 pF
CL Includes Jig Capacitance
RL e 3.3 KX
33
28F200BX-T/B, 28F002BX-T/B
AC CHARACTERISTICSÐRead Only Operations(1)
VCC g 5%
Versions
Symbol
Parameter
Notes
tAVAV tRC Read Cycle Time
tAVQV tACC Address to
Output Delay
tELQV tCE
CEÝ to Output Delay
Min
2
2
3
3
tGLQX tOLZ OEÝ to Output Low Z
3
tGHQZ tDF
3
tOH Output Hold from
Addresses,
CEÝ or OEÝ Change,
Whichever is First
tIR
Input Rise Time
tIF
Input Fall Time
Min
3
Max
70
60
tEHQZ tHZ CEÝ High to Output
High Z
OEÝ High to Output
High Z
Max
60
tPHQV tPWH RPÝ High to
Output Delay
tGLQV tOE OEÝ to Output Delay
tELQX tLZ CEÝ to Output Low Z
VCC g 10%
28F200BX-60(4) 28F200BX-60(5) 28F200BX-80(5) 28F200BX-120(5)
Unit
28F002BX-60(4) 28F002BX-60(5) 28F002BX-80(5) 28F002BX-120(5)
Min
Max
80
70
Min
Max
120
ns
80
120
ns
60
70
80
120
ns
300
300
300
300
ns
30
0
35
0
20
0
25
0
20
0
40
0
30
0
25
0
40
0
30
ns
30
ns
0
30
0
ns
ns
ns
0
ns
10
10
10
10
ns
10
10
10
10
ns
3
5
5
5
5
ns
BYTEÝ Switching
High to
Valid Output Delay
3, 6
60
70
80
120
ns
BYTEÝ Switching
Low to
Output High Z
3
20
25
30
30
ns
tELFL
tELFH
CEÝ to BYTEÝ
Switching
Low or High
tFHQV
tFLQZ
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OEÝ may be delayed up to tCE – tOE after the falling edge of CEÝ without impact on tCE.
3. Sampled, not 100% tested.
4. See High Speed Test Configuration.
5. See Standard Test Configuration.
6. tFLQV, BYTEÝ switching low to valid output delay, will be equal to tAVQV, measured from the time DQ15/A-1 becomes
valid.
34
28F200BX-T/B, 28F002BX-T/B
EXTENDED TEMPERATURE OPERATIONS
AC CHARACTERISTICSÐRead Only Operations(1):
T28F200BX-80(4)
T28F002BX-80(4)
Versions
Symbol
Parameter
Notes
Min
Unit
Max
tAVAV
tRC
Read Cycle Time
80
tAVQV
tACC
Address to
Output Delay
tELQV
tCE
CEÝ to Output Delay
tPHQV
tPWH
RPÝ High to
Output Delay
tGLQV
tOE
OEÝ to Output Delay
2
tELQX
tLZ
CEÝ to Output Low Z
3
tEHQZ
tHZ
CEÝ High to Output
High Z
3
tGLQX
tOLZ
OEÝ to Output Low Z
3
tGHQZ
tDF
OEÝ High to Output
High Z
3
tOH
Output Hold from
Addresses,
CEÝ or OEÝ Change,
Whichever is First
3
tIR
Input Rise Time
10
ns
tIF
Input Fall Time
10
ns
3
5
ns
2
ns
80
ns
80
ns
300
ns
40
ns
0
ns
30
0
ns
ns
30
0
ns
ns
tELFL
tELFH
CEÝ to BYTEÝ
tFHQV
BYTEÝ Switching
High to
Valid Output Delay
3, 5
80
ns
tFLQZ
BYTEÝ Switching
Low to
Output High Z
3
30
ns
Switching
Low or High
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OEÝ may be delayed up to tCE – tOE after the falling edge of CEÝ without impact on tCE.
3. Sampled, not 100% tested.
4. See Standard Test Configuration.
5. tFLQV, BYTEÝ switching low to valid output delay, will be equal to tAVQV, measured from the time DQ5/A-1 becomes
valid.
35
290448– 15
28F200BX-T/B, 28F002BX-T/B
Figure 16. AC Waveforms for Read Operations
36
28F200BX-T/B, 28F002BX-T/B
290448 – 26
Figure 17. ICC (RMS) vs Frequency
(VCC e 5.5V) for x16 Operation
290448 – 27
Figure 18. ICC (RMS) vs Frequency
(VCC e 5.5V) for x8 Operation
290448 – 28
Figure 19. TACC vs Output Load
Capacitance (VCC e 4.5V, T e 70§ C)
37
290448– 29
28F200BX-T/B, 28F002BX-T/B
Figure 20. BYTEÝ Timing for Both Read and Write Operations for 28F200BX
38
28F200BX-T/B, 28F002BX-T/B
AC CHARACTERISTICS FOR WEÝ-CONTROLLED WRITE OPERATIONS(1)
VCC g 5%
Versions
Symbol
Parameter
VCC g 10%
28F200BX-60(9) 28F200BX-60(10) 28F200BX-80(10) 28F200BX-120(10)
Unit
28F002BX-60(9) 28F002BX-60(10) 28F002BX-80(10) 28F002BX-120(10)
Notes
Min
Max
Min
Max
Min
Max
Min
Max
tAVAV
tWC Write Cycle Time
60
70
80
120
ns
tPHWL
RPÝ High
215
215
215
215
ns
0
0
0
0
ns
tPS
Recovery to
WEÝ Going Low
tELWL
tCS
CEÝ Setup to
WEÝ Going Low
tPHHWH tPHS RPÝ VHH
Setup to
WEÝ Going High
6, 8
100
100
100
100
ns
tVPWH tVPS VPP Setup to
WEÝ Going High
5, 8
100
100
100
100
ns
tAVWH tAS
Address Setup to
WEÝ Going High
3
50
50
50
50
ns
tDVWH tDS
Data Setup to
WEÝ Going High
4
50
50
50
50
ns
tWLWH tWP WEÝ Pulse Width
50
50
60
60
ns
tWHDX tDH Data Hold from
WEÝ High
4
0
0
0
0
ns
tWHAX tAH
3
10
10
10
10
ns
tWHEH tCH CEÝ Hold from
WEÝ High
10
10
10
10
ns
tWHWL tWPH WEÝ Pulse
Width High
10
20
20
20
ns
6
6
6
6
ms
Address Hold
from WEÝ High
tWHQV1
Duration of
Word/Byte Write
Operation
tWHQV2
Duration of Erase 2, 5, 6
Operation (Boot)
0.3
0.3
0.3
0.3
s
tWHQV3
Duration of Erase
Operation
(Parameter)
0.3
0.3
0.3
0.3
s
tWHQV4
Duration of Erase 2, 5, 6
Operation (Main)
0.6
0.6
0.6
0.6
s
0
0
0
0
ns
tQVVL
tVPH VPP Hold from
Valid SRD
2, 5
2, 5
5, 8
39
28F200BX-T/B, 28F002BX-T/B
AC CHARACTERISTICS FOR WEÝ-CONTROLLED WRITE OPERATIONS(1)
(Continued)
VCC g 5%
Versions
Symbol
VCC g 10%
28F200BX-60(9)
28F002BX-60(9)
Notes
Min
tQVPH tPHH RPÝ VHH Hold
from Valid SRD
Parameter
6, 8
0
tPHBR
7, 8
Boot-Block
Relock Delay
28F200BX-60(10)
28F002BX-60(10)
Max
Min
Max
0
100
28F200BX-80(10)
28F002BX-80(10)
Min
Max
0
28F200BX-120(10)
Unit
28F002BX-120(10)
Min
Max
0
100
100
ns
100
ns
tIR
Input Rise Time
10
10
10
10
ns
tIF
Input Fall Time
10
10
10
10
ns
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during Read Mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations.
3. Refer to command definition table for valid AIN.
4. Refer to command definition table for valid DIN.
5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7 e 1).
6. For Boot Block Program/Erase, RPÝ should be held at VHH until operation completes successfully.
7. Time tPHBR is required for successful relocking of the Boot Block.
8. Sampled but not 100% tested.
9. See High Speed Test Configuration.
10. See Standard Test Configuration.
BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE: VPP e 12.0V g 5%
28F200BX-60
28F200BX-80
28F200BX-120
28F002BX-60
28F002BX-80
28F002BX-120
Parameter
Notes
(1)
(1)
Min Typ
Max Min Typ
Max Min Typ(1) Max
Unit
Boot/Parameter
Block Erase Time
2
1.0
7
1.0
7
1.0
7
s
Main Block
Erase Time
2
2.4
14
2.4
14
2.4
14
s
Main Block Byte
Program Time
2
1.2
4.2
1.2
4.2
1.2
4.2
s
Main Block Word
Program Time
2
0.6
2.1
0.6
2.1
0.6
2.1
s
NOTES:
1. 25§ C
2. Excludes System-Level Overhead.
BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE: VPP e 12.0V g 10%
28F200BX-60
28F200BX-80
28F200BX-120
28F002BX-60
28F002BX-80
28F002BX-120
Parameter
Notes
Min Typ(1) Max Min Typ(1) Max Min Typ(1) Max
Unit
Boot/Parameter
Block Erase Time
2
5.8
40
5.8
40
5.8
40
s
Main Block
Erase Time
2
14
60
14
60
14
60
s
Main Block Byte
Program Time
2
6.0
20
6.0
20
6.0
20
s
Main Block Word
Program Time
2
3.0
10
3.0
10
3.0
10
s
NOTES:
1. 25§ C
2. Excludes System-Level Overhead.
40
28F200BX-T/B, 28F002BX-T/B
EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICS FOR WEÝ-CONTROLLED WRITE OPERATIONS(1)
T28F200BX-80(9)
T28F002BX-80(9)
Versions(4)
Symbol
Parameter
Notes
Min
Unit
Max
tAVAV
tWC
Write Cycle Time
80
ns
tPHWL
tPS
RPÝ High Recovery to
WEÝ Going Low
220
ns
tELWL
tCS
CEÝ Setup to WEÝ Going Low
0
ns
tPHHWH
tPHS
RPÝ VHH Setup to WEÝ Going High
6, 8
100
ns
tVPWH
tVPS
VPP Setup to WEÝ Going High
5, 8
100
ns
tAVWH
tAS
Address Setup to WEÝ Going High
3
60
ns
tDVWH
tDS
Data Setup to WEÝ Going High
4
60
ns
tWLWH
tWP
WEÝ Pulse Width
60
ns
tWHDX
tDH
Data Hold from WEÝ High
4
0
ns
tWHAX
tAH
Address Hold from WEÝ High
3
10
ns
tWHEH
tCH
CEÝ Hold from WEÝ High
10
ns
tWHWL
tWPH
WEÝ Pulse Width High
20
ns
2, 5
7
ms
2, 5, 6
0.4
s
2, 5
0.4
s
2, 5, 6
0.7
s
tWHQV1
Duration of Word/Byte
Write Operation
tWHQV2
Duration of Erase Operation (Boot)
tWHQV3
Duration of Erase
Operation (Parameter)
tWHQV4
Duration of Erase Operation (Main)
tQVVL
tVPH
VPP Hold from Valid SRD
5, 8
0
ns
tQVPH
tPHH
RPÝ VHH Hold from Valid SRD
6, 8
0
ns
Boot-Block Relock Delay
7, 8
tPHBR
100
ns
tIR
Input Rise Time
10
ns
tIF
Input Fall Time
10
ns
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during Read Mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations.
3. Refer to command definition table for valid AIN.
4. Refer to command definition table for valid DIN.
5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7 e 1).
6. For Boot Block Program/Erase, RPÝ should be held at VHH until operation completes successfully.
7. Time tPHBR is required for successful relocking of the Boot Block.
8. Sampled but not 100% tested.
9. See Standard Test Configuration.
41
28F200BX-T/B, 28F002BX-T/B
EXTENDED TEMPERATURE OPERATION
BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE: VPP e 12.0V g 5%
Parameter
T28F200BX-80
T28F002BX-80
Notes
Min
Max
Boot/Parameter
Block Erase Time
2
1.5
10.5
s
Main Block
Erase Time
2
3.0
18
s
Main Block Byte
Program Time
2
1.4
5.0
s
Main Block Word
Program Time
2
0.7
2.5
s
NOTES:
1. 25§ C, 12.0V VPP.
2. Excludes System-Level Overhead.
42
Unit
Typ(1)
290448– 16
28F200BX-T/B, 28F002BX-T/B
Figure 21. AC Waveforms for Write and Erase Operations (WEÝ-Controlled Writes)
43
28F200BX-T/B, 28F002BX-T/B
AC CHARACTERISTICS FOR CEÝ-CONTROLLED WRITE OPERATIONS(1, 9)
VCC g 5%
Versions
Symbol
Parameter
VCC g 10%
28F200BX-60(10) 28F200BX-60(11) 28F200BX-80(11) 28F200BX-120(11)
Unit
28F002BX-60(10) 28F002BX-60(11) 28F002BX-80(11) 28F002BX-120(11)
Notes
tAVAV tWC Write Cycle Time
tPHEL tPS RPÝ High Recovery
to CEÝ Going Low
tWLEL tWS WEÝ Setup to CEÝ
Going Low
Min
Max
Min
Max
Min
Max
Min
Max
60
70
80
120
ns
215
215
215
215
ns
0
0
0
0
ns
tPHHEH tPHS RPÝ VHH Setup to
CEÝ Going High
6, 8
100
100
100
100
ns
tVPEH tVPS VPP Setup to CEÝ
Going High
5, 8
100
100
100
100
ns
tAVEH tAS Address Setup to
CEÝ Going High
3
50
50
50
50
ns
tDVEH tDS Data Setup to CEÝ
Going High
4
60
60
60
60
ns
tELEH tCP CEÝ Pulse Width
50
50
60
60
ns
tEHDX tDH Data Hold from
CEÝ High
4
0
0
0
0
ns
tEHAX tAH Address Hold
from CEÝ High
3
10
10
10
10
ns
tEHWH tWH WEÝ Hold from
CEÝ High
10
10
10
10
ns
tEHEL tCPH CEÝ Pulse
Width High
10
20
20
20
ns
2, 5
6
6
6
6
ms
tEHQV1
Duration of
Word/Byte
Programming
Operation
tEHQV2
Duration of Erase
Operation (Boot)
2, 5, 6
0.3
0.3
0.3
0.3
s
tEHQV3
Duration of Erase
Operation
(Parameter)
2, 5
0.3
0.3
0.3
0.3
s
tEHQV4
Duration of Erase
Operation (Main)
2, 5
0.6
0.6
0.6
0.6
s
tQVVL tVPH VPP Hold from
Valid SRD
5, 8
0
0
0
0
ns
tQVPH tPHH RPÝ VHH Hold
from Valid SRD
6, 8
0
0
0
0
ns
tPHBR
Boot-Block Relock
Delay
7
100
100
100
100
ns
tIR
Input Rise Time
10
10
10
10
ns
tIF
Input Fall Time
10
10
10
10
ns
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CEÝ and WEÝ in systems where
CEÝ defines the write pulse-width (within a longer WEÝ timing waveform), all set-up, hold and inactive WEÝ time should
be measured relative to the CEÝ waveform.
2, 3, 4, 5, 6, 7, 8: Refer to AC Characteristics notes for WEÝ-Controlled Write Operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
10. See High Speed Test Configuration.
11. See Standard Test Configuration.
44
28F200BX-T/B, 28F002BX-T/B
EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICS FOR CEÝ-CONTROLLED WRITE OPERATIONS(1, 9)
T28F200BX-80(10)
T28F002BX-80(10)
Versions
Symbol
Parameter
Notes
Min
Unit
Max
tAVAV
tWC
Write Cycle Time
80
ns
tPHEL
tPS
RPÝ High Recovery
to CEÝ Going Low
220
ns
tWLEL
tWS
WEÝ Setup to CEÝ
Going Low
0
ns
tPHHEH
tPHS
RPÝ VHH Setup to
CEÝ Going High
6, 8
100
ns
tVPEH
tVPS
VPP Setup to CEÝ
Going High
5, 8
100
ns
tAVEH
tAS
Address Setup to
CEÝ Going High
3
60
ns
tDVEH
tDS
Data Setup to CEÝ
Going High
4
60
ns
tELEH
tCP
CEÝ Pulse Width
60
ns
tEHDX
tDH
Data Hold from
CEÝ High
4
0
ns
tEHAX
tAH
Address Hold
from CEÝ High
3
10
ns
tEHWH
tWH
WEÝ Hold from CEÝ High
10
ns
tEHEL
tCPH
CEÝ Pulse
Width High
20
ns
2, 5
7
ms
2, 5, 6
0.4
s
tEHQV1
Duration of Word/Byte
Programming
Operation
tEHQV2
Duration of Erase
Operation (Boot)
tEHQV3
Duration of Erase
Operation (Parameter)
2, 5
0.4
s
tEHQV4
Duration of Erase
Operation (Main)
2, 5
0.7
s
tQVVL
tVPH
VPP Hold from
Valid SRD
5, 8
0
ns
tQVPH
tPHH
RPÝ VHH Hold
from Valid SRD
6, 8
0
ns
tPHBR
100
ns
tIR
Boot-Block Relock Delay
Input Rise Time
7
10
ns
tIF
Input Fall Time
10
ns
NOTES:
1. Ship-Enable Controlled Writes: Write operations are driven by the valid combination of CEÝ and WEÝ in systems where
CEÝ defines the write pulse-width (within a longer WEÝ timing waveform), all set-up, hold and inactive WEÝ time should
be measured relative to the CEÝ waveform.
2, 3, 4, 5, 6, 7, 8: Refer to AC Characteristics for WEÝ-Controlled Write Operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
10. See Standard Test Configuration.
45
290448– 17
28F200BX-T/B, 28F002BX-T/B
Figure 22. Alternate AC Waveforms for Write and Erase Operations (CEÝ-Controlled Writes)
46
28F200BX-T/B, 28F002BX-T/B
ORDERING INFORMATION
290448 – 18
Valid Combinations:
E28F200BX-T60
E28F200BX-B60
E28F200BX-T80
E28F200BX-B80
E28F200BX-T120
E28F200BX-B120
PA28F200BX-T60
PA28F200BX-B60
PA28F200BX-T80
PA28F200BX-B80
PA28F200BX-T120
PA28F200BX-B120
TE28F200BX-T80
TE28F200BX-B80
TB28F200BX-T80
TB28F200BX-B80
290448 – 23
Valid Combinations:
E28F002BX-T60
E28F002BX-B60
E28F002BX-T80
TE28F002BX-T80
E28F002BX-B80
TE28F002BX-B80
E28F002BX-T120
E28F002BX-B120
ADDITIONAL INFORMATION
References
Order
Number
Document
290449
28F002/200BL-T/B 2-Mbit Low Power Boot Block Flash Memory Datasheet
290450
28F004/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory Datasheet
290451
28F004/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet
290531
2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290530
4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290539
8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
292098
AP-363 ‘‘Extended Flash BIOS Concepts for Portable Computers’’
292148
AP-604 ‘‘Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM’’
292161
AP-608 ‘‘Implementing a Plug & Play BIOS Using Intel’s Boot Block Flash Memory’’
292178
AP-623 ‘‘Multi-Site Layout Planning Using Intel’s Boot Block Flash Memory’’
292130
AB-57 ‘‘Boot Block Architecture for Safe Firmware Updates’’
292154
AB-60 ‘‘2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family’’
47
28F200BX-T/B, 28F002BX-T/B
Revision History
Number
48
Description
-002
Removed b 70 speed bin
Integrated b 70 characteristics into b 60 speed bin
Added Extended Temperature characteristics
Modified BYTEÝ Timing Diagram
Improved tPHQV, RPÝ High to Output Delay and tPHEL, RPÝ High Recovery to CEÝ going low
specifications
-003
PWD changed to RPÝ for JEDEC standardization compatibility.
Combined VCC Read current for 28F200BX Word-wide mode and Byte-wide mode, and
28F002BX Byte-wide mode in DC Characteristics tables.
Change IPPS current spec from g 10 mA to g 15 mA in DC Characteristics tables.
Improved ICCR and ICCW in DC Characteristics: Extended Temperature Operation table.
Improved tAVAV, tAVQV, tELQV, tGLQV, tEHQZ, tGHQZ, tFHQV and tFLQZ specifications for
Extended Temperature Operations AC CharacteristicsÐRead and Write Operations.
-004
Added specifications for 120 ns access time product version; 28F200BX-120 and
28F002BX-120.
Included permanent change on write timing parameters for -80 ns product versions. Write
pulse width (tWP and tCP) increases from 50 ns to 60 ns. Write pulse width high (tWPH and
tCPH) decreases from 30 ns to 20 ns. Total write cycle time (tWC) remains unchanged.
Added ICCR test condition note for typical frequency value in DC characteristics table.
Added IOH CMOS specification.
Added 28F400BX interface to Intel386 TM EX Embedded Processor block diagram.
Added description of how to upgrade to SmartVoltage Boot Block products.
-005
Added references to input rise/fall times.