HI-8050/51, HI-8150/51 CMOS High Voltage Display Driver November 2007 GENERAL DESCRIPTION APPLICATIONS The data is serially clocked into the device on the negative edge of the clock and latched in parallel to the segment outputs on the high to low transition of the load input. Serial output data changes on the positive edge of the clock allowing the cascading of multiple drivers for larger displays. Dichroic Liquid Crystal Displays Standard Liquid Crystal Displays 5 Volt Serial Data to Parallel High Voltage MEMS Drivers N/C DIN LD CL CS 8020OPT VSS S36 S35 S34 S33 S32 S31 S30 S29 S28 PAD CONFIGURATION (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 The HI-8050 and HI-8150 are designed to replace the HI-8010 and HI-8020 devices in all 5 volt applications. They offer significantly enhanced ESD protection along with a considerably faster serial input data rate. ! ! ! ! BPIN BPOSC VDD N/C CONVOSC CONVOUT VEE S37 S38 S1 S2 S3 S4 S5 S6 S7 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S27 S26 S25 S24 S23 S22 S21 S20 DOUT38 DOUT32 DOUT30 T2 T1 N/C BPOUT N/C N/C S8 S9 S10 S11 S12 S13 S14 N/C S15 S16 S17 S18 S19 N/C N/C The device layout supports all previous pinouts of the HI-8010/HI-8020 products. In addition, new technology and features afford new packaging options. Consult your Holt Sales Representative to explore the possibilities. HI-8050PQI HI-8150PQI HI-8050PQT & HI-8150PQT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 The HI-8050, HI-8051, HI-8150 and HI-8151 are CMOS integrated circuits designed for high voltage LCD display drive applications. The HI-8050 & HI-8051 have TTL logic inputs whereas the HI-8150 & HI-8151 have CMOS logic inputs. They drive up to 38 segments at voltages between +5 and -30 volts. The optional voltage converter on the HI-8050 & HI-8150 can be used to generate the negative display drive voltage. All products have test inputs to facilitate opens and shorts testing as well as automatic blanking of the display if the +5V power is lost. 64 Pin plastic PQFP (See page 6 for HI-8051 & HI-8151pin configurations) FEATURES FUNCTIONAL BLOCK DIAGRAM ! 4 MHz serial input data rate Þ Þ CS Þ DIN CL ! 38 segment outputs ! Cascadable ! 5 Volt inputs translated to 35 Volts 8020OPT ! Test pins allow hardware all "ON", all "OFF" or alternating ! Monitors 5 volt supply and forces all segments to "OFF" condition if lost Þ Þ BPIN Þ BPOSC Þ DATA IN 38 Stage Shift Register DOUT30 CLK CONTROL LOGIC LE 38 Bit Latch LD ! Negative voltage converter available on-chip Oscillator Divider Vo l t a g e Tr a n s l a t o r ! CMOS low power Vo l t a g e Tr a n s l a t o r s H i g h Vo l t a g e Drivers H i g h Vo l t a g e B u ff e r ! Military processing available Þ BPOUT (DS8050, Rev. F) DOUT38 Þ DOUT32 HOLT INTEGRATED CIRCUITS www.holtic.com 38 SEGMENTS 11/07 HI-8050/51, HI-8150/51 PIN DESCRIPTION TABLE SIGNAL FUNCTION VSS POWER 8020OPT DESCRIPTION 0 Volts LOGIC INPUT Open or high logic level selects the HI-8010/HI-8110 CL / CS logic. A low selects the HI-8020/HI-8120 Logic (HI-8050 & HI-8150 only) CS LOGIC INPUT Chip select - Active low CL LOGIC INPUT Serial data input clock - Active low LD LOGIC INPUT Latches data in shift register to the segment outputs - Active high DIN LOGIC INPUT Serial input data to the shift register BPIN INPUT Backplane frequency input. Either driven from an external source or connected to BPOSC and an external resistor and capacitor. BPOSC OUTPUT Internal oscillator pin. Connected to BPIN and an external resistor and capacitor VDD POWER +5V ±5%, Positive voltage of the backplane and segments CONVOSC INPUT Used in conjunction with CONVOUT to generate the negative VEE voltage on-chip (HI-8050 & HI-8150 only). CONVOUT OUTPUT Used in conjunction with CONVOSC to generate the negative VEE voltage on-chip (HI-8050 & HI-8150 only). VEE POWER Negative voltage of the backplane and segments - between VSS and VDD - 35V S1 to S38 OUTPUT Segment outputs to LCD display BPOUT OUTPUT Backplane output to LCD display (See Figure 3 for cascading drivers) T1 LOGIC INPUT Used in conjunction with T2 to control display mode. Normal mode is logic low. T2 LOGIC INPUT Used in conjunction with T1 to control display mode. Normal mode is logic low. DOUT30 OUTPUT Logic output from the 30th bit of the shift register. Use for pattern verification or as the DIN of the next cascaded driver (HI-8050 & HI-8150 only). DOUT32 OUTPUT Logic output from the 32nd bit of the shift register. Use for pattern verification or as the DIN of the next cascaded driver (HI-8050 & HI-8150 only). DOUT38 OUTPUT Logic output from the 38th bit of the shift register. Use for pattern verification or as the DIN of the next cascaded driver. HOLT INTEGRATED CIRCUITS 2 HI-8050/51, HI-8150/51 FUNCTIONAL DESCRIPTION INPUT LOGIC DOUT The data is clocked into a serial shift register from the DIN input on the negative edge of CL while CS is held low. LD is normally held low and pulsed high only when data from the shift register is parallel latched to the segment outputs. CS must be low when LD is pulsed. The latches are transparent while LD is high. A logic "1" in the shift register causes the corresponding segment output to be out of phase with the BP output. All four logic inputs are TTL compatible on the HI-8050/51and CMOS compatible on the HI-8150/51. The DOUT30, DOUT32, and DOUT38 pins are available for cascading devices to drive more segments (See Figure 3) and for verifying the integrity of the shift register data. The outputs can drive 2 TTL loads. They change on the positive edge of CL. BPOSC and BPIN The user has the option of creating the backplane frequency internally or providing a signal from an external source. For an internal oscillator, BPIN and BPOSC are connected together and the appropriate R & C combination is applied as shown in Figure 1. The resulting backplane frequency is approximately: fBP = 1 . (R = 220KW, C = 220pF, fBP » 100HZ) 256 RC The value of the resistor must be greater than 30KW. Alternatively, BPOSC is left open and an external backplane signal of the desired frequency is applied to the BPIN input. AUTOMATIC SEGMENTS OFF A threshold device detects when the 5V supply is below approximately 1V and forces all the segments and the backplane to the same level. This feature is used to discharge the VEE capacitor when the 5V power is switched off, to prolong the life of the LCD display. 8020OPT The CL and CS inputs function the same as the HI-8010 and HI-8110 product (See Figure 5) if this pin is left open or held high. If held low, the two pins function the same as the HI-8020 and HI-8120 product (See Figure 6). This input is available only on the HI-8050 (TTL) and HI-8150 (CMOS) products. TEST INPUTS The test functions available are: VEE & NEGATIVE VOLTAGE CONVERTER VEE can be connected to a negative power supply. Alternatively, the HI-8050 & HI-8150 have the option of generating the VEE voltage with a built-in -25 volt negative voltage converter (See Figure 2). When not used, the open CONVOSC pin is detected and all power consuming circuitry is disabled. The converter will survive a short between two segments and still maintain a VEE voltage of -20V. T2 0 0 1 1 T1 0 1 0 1 Display Mode Normal All Off All On Alternating On/Off Segments The test inputs must be tied to the appropriate logic level for correct circuit operation. Both test inputs are TTL compatible on the HI-8050/51 and CMOS compatible on the HI-8150/51. VDD 68KW C R CONVOSC RSENSE ÷ 256 Control VDD Q R VDD 330µH VSS BPOSC VSS IN5818, IN5819 CONVOUT BPIN C OSC TO BACKPLANE TRANSLATOR AND DRIVER VEE 10µF VSS Figure 1. INTERNAL OSCILLATOR CIRCUIT Figure 2. OPTIONAL VOLTAGE CONVERTER HOLT INTEGRATED CIRCUITS 3 HI-8050/51, HI-8150/51 LD CL CS DIN CS CL LD CS CL LD CS CL LD DIN DIN DIN DO DO 1MW 1MW BPOUT 1500pF 1µF 1µF DO R V os C BPIN BPOUT BPIN BPOUT BPIN BPOUT BPOSC BPOSC BPOSC 1MW 1MW SEG n SEGMENTS SEGMENTS BACK PLANE DATA IN 38 Stage Shift Register CL Þ CS Þ 1µF 1µF SEGMENTS Figure 4. OFFSET MEASUREMENT Figure 3. RC OSCILLATOR AND CASCADED DEVICES DIN Þ 360pF Þ DOUT CLK DIN Þ DATA IN 38 Stage Shift Register CL Þ CS Þ Figure 5. HI-8010/HI-8110 CL & CS LOGIC (8020OPT = OPEN or HIGH) CLK Figure 6. HI-8020/HI-8120 CL & CS LOGIC (8020OPT = LOW) CL INPUT tCL DIN INPUT VALID VALID tDS tDH CS INPUT tCSS tLCS tLS tCSH LD INPUT tLS tCDO DOUT OUTPUT VALID Þ DOUT VALID Figure 7. TIMING DIAGRAM HOLT INTEGRATED CIRCUITS 4 tCSL tLW VALID HI-8050/51, HI-8150/51 ABSOLUTE MAXIMUM RATINGS Voltages referenced to VSS = 0V Supply Voltage VDD ..........................0V to 7V VEE................VDD-35V to 0V Voltage at any input, except BPIN..-0.3V to VDD+0.3V Voltage at BPIN input ..............VDD-35V to VDD+0.3V DC current per input pin .....................................10 mA Power Dissipation............................................500 mW Operating Temperature Range(Industrial) ....... -40°C to +85°C (Hi-Temp/Mil) ..... -55°C to +125°C Storage Temperature ..................................... -65°C to +125°C Solder Temperature (Leads) ..................... +280°C for 10 sec. (Package) ........................................ +220°C Junction Temperature, Tj ... ....................................... £+175°C NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS VDD = 5V ±5%, VEE = -25V, VSS = 0V, TA = operating temperature range (unless otherwise specified). PARAMETER SYMBOL Operating Voltage Supply Current: (Static, No Load, Converter Off, fBP = 0Hz) Input Low Voltage, HI-8050/51 only (except BPIN) Input High Voltage, HI-8050/51 only (except BPIN) Input Low Voltage, HI-8150/51 only (except BPIN) Input High Voltage, HI-8150/51 only (except BPIN) Input Low Voltage, BPIN Input High Voltage, BPIN Input Current (except T1 & T2) Input Current (T1 & T2) Input Capacitance (Guaranteed, not tested) Segment Output Impedance Backplane Output Impedance Data Out Current: Source Current Sink Current Voltage Converter: @ No Load (VDD - VSS = 5V, TA = 25°C) @ 0.1mA Load @ 10KW Load Offset Voltage (Guaranteed, not tested) CONDITION VDD IDD IEE VILTTL VIHTTL VILCMOS VIHCMOS VILX VIHX IIN1 IIN2 CI RSEG RBP IDOH IDOL VEEC IDD VEEC VOS MIN TYP 3.0 @ +85°C @ +125°C @ +125°C Logic Inputs Logic Inputs Logic Inputs Logic Inputs VIN = 0V to 5V VIN = 0V to 5V IL = 10µA IL = 10µA @ 25°C VOH = 4.5 VOL = 0.4 See Fig. 2 See Fig. 2 See Fig. 2 See Fig. 4 HOLT INTEGRATED CIRCUITS 5 0 2 0 0.7 VDD VEE 0.8 VDD MAX UNITS 7.0 200 300 120 0.8 VDD 0.3 VDD VDD 0.6 VDD VDD 100 V µA µA µA V V V V V V nA µA pF KW W mA mA V mA V mV 10 10 450 3.2 -22 -21.5 10 15 600 -3.0 -21 1.8 -20 25 HI-8050/51, HI-8150/51 AC ELECTRICAL CHARACTERISTICS (See Figure 7) VDD = 5V ±5% , VEE = -25V, VSS = 0V, TA = operating temperature range (unless otherwise specified). PARAMETER Clock Period non-cascaded cascaded non-cascaded cascaded Clock Pulse Width Data In - Setup Data In - Hold Chip Select - Setup to Clock Chip Select - Hold to Clock Load - Setup to Clock Chip Select - Setup to Load Load Pulse Width Chip Select - Hold to Load Data Out Valid, from Clock SYMBOL VDD MIN tCL tCL tCW tCW tDS tDH tCSS tCSH tLS tCSL tLW tLCS tCDO 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 250 500 125 250 50 80 100 120 120 0 130 120 HI-8051 & HI-8151 PIN CONFIGURATIONS HI-8051PQI HI-8151PQI HI-8051PQT & HI-8151PQT 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 12 13 S7 S8 S9 S10 S11 S12 S13 S14 VEE S15 S16 S17 S18 LD DIN BPIN BPOSC VDD S37 S38 S1 S2 S3 S4 S5 S6 52 51 50 49 48 47 46 45 44 43 42 41 40 CL CS VSS S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 (See page 1 for HI-8050 & HI-8150 pin configurations) 52 Pin Plastic PQFP HOLT INTEGRATED CIRCUITS 6 S26 S25 S24 S23 S22 S21 S20 DOUT 38 N/C T2 T1 BPOUT S19 TYP MAX UNITS 170 ns ns ns ns ns ns ns ns ns ns ns ns ns HI-8050/51, HI-8150/51 ORDERING INFORMATION HI - 8x5xPQ x x PART NUMBER Blank F PART NUMBER LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free RoHS compliant) TEMPERATURE RANGE FLOW BURN IN I -40°C TO + 85°C I No T -55°C TO +125°C T No PART NUMBER INPUT LEVELS PACKAGE DESCRIPTION HI-8050PQ TTL 64 PIN PLASTIC THIN FLAT QUAD PACK PTQFP (64PTQS) HI-8051PQ TTL 52 PIN PLASTIC QUAD FLAT PACK PQFP (52PQS) HI-8150PQ CMOS 64 PIN PLASTIC THIN FLAT QUAD PACK PTQFP (64PTQS) HI-8151PQ CMOS 52 PIN PLASTIC QUAD FLAT PACK PQFP (52PQS) HOLT INTEGRATED CIRCUITS 7 HI-8050/51, HI-8150/51 PACKAGE DIMENSIONS 52-PIN PLASTIC QUAD FLAT PACK (PQFP) inches (millimeters) Package Type: 52PQS .0256 BSC (.65) .520 BSC SQ (13.2) .394 BSC SQ (10.0) .012 ± .003 (.30 ± .08) .035 ± .006 (.88 ± .15) .063 typ (1.6) .008 min (.20) See Detail A .084 ± .013 (2.13 ± .32) .008 ± .003 (.215 ± .085) R min .079 ± .008 (2.00 ± .20) 0° £ Q £ 7° .005 R min (.13) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) DETAIL A inches (millimeters) 64 PIN PLASTIC THIN QUAD FLAT PACK (TQFP) Package Type: 64PTQS .276 BSC SQ (7.00) .354 (9.00) BSC SQ .0157 BSC (0.40) .007 ± .004 (0.18 ± .05) .024 ± .006 (0.60 ± .15 .055 ± .002 (1.4 ± .05) .008 R max (0.20) See Detail A .063 max (1.60) 0° £ Q £ 7° BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .004 ± .002 (0.10 ± .05) HOLT INTEGRATED CIRCUITS 8 .003 R min (0.08) Detail A