ACT8810 Rev 9, 15-Nov-12 Eight Channel ActivePathTM Power Management IC FEATURES GENERAL DESCRIPTION • ActivePathTM Li+ Charger with System Power The patent-pending ACT8810 is a complete, cost effective, highly-efficient ActivePMUTM power management solution that is ideal for a wide range of high performance portable handheld applications such as personal navigation devices (PNDs). This device integrates the ActivePathTM complete battery charging and management system with six power supply channels. Selection • Six Integrated Regulators − 1.3A High Efficiency Step-Down DC/DC − 1.0A High Efficiency Step-Down DC/DC − 0.55A High Efficiency Step-Down DC/DC − 2×360mA Low Noise, High PSRR LDOs − 30mA RTC LDO / Backup Battery Charger • I2CTM Serial Interface • Minimal External Components The ActivePath architecture automatically selects the best available input supply for the system. If the external input source is not present or the system load current is more than the input source can provide, the ActivePath supplies additional current from the battery to the system. The charger is a complete, thermallyregulated, stand-alone single-cell linear Li+ charger that incorporates an internal power MOSFET. • Compatible with USB or AC-Adapter Charging • 5mm × 5mm, Thin-QFN (TQFN55-40) Package − Only 0.75mm Height − RoHS Compliant REG1, REG2, and REG3 are three independent, fixed-frequency, current-mode step-down DC/DC converters that output 1.3A, 1.0A, and 0.55A, respectively. REG4 and REG5 are high performance, low-noise, low-dropout linear regulators that output up to 360mA each. REG6 is a RTC LDO that outputs up to 30mA for a real time clock. Finally, an I2C serial interface provides programmability for the DC/DC converters and LDOs. APPLICATIONS • Personal Navigation Devices • Portable Media Players • Smart Phones The ACT8810 is available in a tiny 5mm x 5mm 40pin Thin-QFN package that is just 0.75mm thin. SYSTEM BLOCK DIAGRAM CHG_IN CHGLEV DCCC ISET ACIN nSTAT0 nSTAT1 TH BTR nPBIN nIRQ nRSTO SCL SDA ON1 ON2 ON3 VSEL Battery Programmable Up to 1A VSYS ActivePathTM & Single-Cell Li+ Battery Charger REG1 Step-Down DC/DC REG2 Step-Down DC/DC REG3 Step-Down DC/DC System Control REG4 LDO REG5 LDO ACT8810 ActivePMU REG6 RTC_LDO TM Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -1- OUT1 Adjustable, or 0.8V to 4.4V Up to 1.3A OUT2 Adjustable, or 0.8V to 4.4V Up to 1.0A OUT3 Adjustable, or 0.8V to 4.4V Up to 0.55A OUT4 0.9V to 3.3V Up to 360mA OUT5 0.9V to 3.3V Up to 360mA OUT6 0.9V to 3.3V Up to 30mA www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 TABLE OF CONTENTS GENERAL INFORMATION ..........................................................................................P. 01 Functional Block Diagram ...................................................................................................... p. 03 Ordering Information .............................................................................................................. p. 04 Pin Configuration .................................................................................................................... p. 04 Pin Descriptions ..................................................................................................................... p. 05 Absolute Maximum Ratings.................................................................................................... p. 07 SYSTEM MANAGEMENT ...........................................................................................P. 08 Register Descriptions ............................................................................................................. p. 08 I2C Interface Electrical Characteristics ................................................................................... p. 09 Electrical Characteristics ........................................................................................................ p. 10 Register Descriptions ............................................................................................................. p. 11 Typical Performance Characteristics...................................................................................... p. 12 Functional Description ............................................................................................................ p. 13 STEP-DOWN DC/DC CONVERTERS ..........................................................................P. 17 Electrical Characteristics ........................................................................................................ p. 17 Typical Performance Characteristics...................................................................................... p. 20 Register Descriptions ............................................................................................................. p. 22 Functional Description ............................................................................................................ p. 28 LOW-DROPOUT LINEAR REGULATORS ..................................................................P. 31 Electrical Characteristics ........................................................................................................ p. 31 Typical Performance Characteristics...................................................................................... p. 33 Register Descriptions ............................................................................................................. p. 34 Functional Description ............................................................................................................ p. 36 RTC LOW-DROPOUT LINEAR REGULATOR ............................................................P. 37 Electrical Characteristics ........................................................................................................ p. 37 Register Descriptions ............................................................................................................. p. 38 Functional Description ............................................................................................................ p. 39 ActivePathTM CHARGER .............................................................................................P. 40 Electrical Characteristics ........................................................................................................ p. 40 Typical Performance Characteristics...................................................................................... p. 42 Functional Description ............................................................................................................ p. 44 PACKAGE INFORMATION ..........................................................................................P. 53 Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -2- www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 REG3 REG2 REG1 FUNCTIONAL BLOCK DIAGRAM Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -3- www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 ORDERING INFORMATION PART NUMBER VOUT1/VSTBY1 ACT8810QJ1C1-T 3.3V/3.3V 1.1V/1.2V 1.2V/1.2V 1.2V 2.8V 3.3V Sequence A ACT8810QJ213-T 1.2V/1.2V 1.8V/1.8V 1.0V/1.0V 3.3V 1.2V 3.0V Sequence B ACT8810QJ3EB-T 3.3V/3.3V 1.2V/1.2V 1.8V/1.8V 1.5V 2.8V 3.3V Sequence C ACT8810QJ420-T 3.3V/3.3V 1.8V/1.8V 1.1V/1.2V 1.2V 3.3V 2.5V Sequence D ACT8810QJ50F-T 1.2V/1.2V 3.3V/3.3V 1.8V/1.8V 3.3V 1.8V 3.0V Sequence E VOUT2/VSTBY2 VOUT3/VSTBY3 VOUT4 VOUT5 VOUT6 CONTROL SEQUENCE PACKAGING DETAILS PACKAGE PINS TEMPERATURE RANGE PACKING ACT8810QJ###-T TQFN55-40 40 -40°C to +85°C TAPE & REEL : All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards. : To select VSTBYx as a output regulation voltage of REGx, tie VSEL to VSYS or a logic high. : Refer to the Control Sequence section for more information. PIN CONFIGURATION TOP VIEW INL OUT4 nSTAT0 GA ON2 REFBP nSTAT1 nRSTO nIRQ CHGLEV TH OUT5 DCCC OUT6 BTR VP3 ACIN SW3 BAT GP3 BAT OUT3 ACT8810 VSYS nPBIN SDA VSYS CHG_IN SCL EP ON3 ISET OUT1 VP1 SW1 GP1 GP2 SW2 VP2 OUT2 ON1 VSEL Thin - QFN (TQFN55-40) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -4- www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 PIN DESCRIPTIONS PIN NAME DESCRIPTION 1 TH Temperature Sensing Input. Connect to battery thermistor. TH is pulled up with a 100µA current internally. See the Battery Temperature Monitoring section for more information. 2 DCCC Dynamic Charging Current Control. Connect a resistor to set the dynamic charging current control point. A internal 100µA current source sets up a voltage that is used to compare with VSYS and dynamically scale the charging current to maintain VSYS regulation. See the Dynamic Charge Current Control section for more information. 3 BTR Safety Timer Program Pin. The resistance between this pin and GA determines the timers timeout values. See the Charging Safety Timers section for more information. 4 ACIN AC Adaptor Detect. Detects presence of a wall adaptor and automatically adjusts the charge current to the maximum charge current level. Do not leave ACIN floating. 5, 6 BAT Battery Charger Output. Connect this pin directly to the battery anode (+ terminal) 7, 8 VSYS 9 System Output Pin. Bypass to GA with a 10µF or larger ceramic capacitor. Power Input for the Battery Charger. Bypass CHG_IN to GA with a capacitor placed as close to the CHG_IN IC as possible. The battery charger are automatically enabled when a valid voltage is present on CHG_IN. See the CHG_IN Bypass Capacitor Selection section for more information. 10 ISET Charge Current Set. Program the maximum charge current by connecting a resistor (RISET) between ISET and GA. See the Charger Current Programming section for more information. 11 VSEL Step-Down DC/DCs Output Voltage Selection. Drive to logic low to select default output voltage. Drive to logic high to select secondary output voltage. See the Output Voltage Selection Pin section for more information. 12 ON1 Independent Enable Control Input for REG1. Drive ON1 to VSYS or to a logic high for normal operation, drive to GA or a logic low to disable REG1. Do not leave ON1 floating. 13 OUT2 Output Feedback Sense for REG2. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. 14 VP2 Power Input for REG2. Bypass to GP2 with a high quality ceramic capacitor placed as close as possible to the IC. 15 SW2 Switching Node Output for REG2. Connect this pin to the switching end of the inductor. 16 GP2 Power Ground for REG2. Connect GA, GP1, GP2 and GP3 together at a single point as close to the IC as possible. 17 GP1 Power Ground for REG1. Connect GA, GP1, GP2 and GP3 together at a single point as close to the IC as possible. 18 SW1 Switching Node Output for REG1. Connect this pin to the switching end of the inductor. 19 VP1 Power Input for REG1. Bypass to GP1 with a high quality ceramic capacitor placed as close as possible to the IC. 20 OUT1 Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. 21 ON3 Enable Control Input for REG3. Drive ON3 to a logic high for normal operation, drive to GA or a logic low to disable REG3. Do not leave ON3 floating. 22 SCL Clock Input for I2C Serial Interface. 23 SDA Data Input for I2C Serial Interface. Data is read on the rising edge of SCL. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -5- www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 PIN DESCRIPTIONS CONT’D PIN NAME DESCRIPTION 24 nPBIN Master Enable Input. Drive nPBIN to GA through a 100kΩ resistor to enable the IC, drive nPBIN directly to GA to assert a Hard-Reset condition. Refer to the System Startup & Shutdown and Control Sequence sections for more information. nPBIN is internally pulled up to VSYS through a 50kΩ resistor. 25 OUT3 Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. 26 GP3 Power Ground for REG3. Connect GA, GP1, GP2, and GP3 together at a single point as close to the IC as possible. 27 SW3 Switching Node Output for REG3. Connect this pin to the switching end of the inductor. 28 VP3 Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close as possible to the IC. 29 OUT6 RTC LDO Output Voltage. Capable of delivering up to 30mA of output current. 30 OUT5 Output Voltage for REG5. Capable of delivering up to 360mA of output current. The output is discharged to GA with 1kΩ when disabled. 31 INL Power Input for REG4, REG5, and REG6. Bypass to GA with a high quality ceramic capacitor placed as close as possible to the IC. 32 OUT4 Output Voltage for REG4. Capable of delivering up to 360mA of output current. The output is discharged to GA with 1kΩ when disabled. 33 Active-Low Open-Drain Charger Status Output. nSTAT0 has a 5mA (typ) current limit, allowing it to directly drive an indicator LED without additional external components. To generate a logic-level nSTAT0 output, connect nSTAT0 to an appropriate supply voltage (typically VSYS) through a 10kΩ or greater pull-up resistor. See the Charge Status Indication section for more information. Independent Enable Control Input for REG2. Drive ON2 to a logic high for normal operation, drive to GA or a logic low to disable REG2. Do not leave ON2 floating. 34 ON2 35 GA 36 REFBP 37 Active-Low Open-Drain Charger Status Output. nSTAT1 has a 5mA (typ) current limit, allowing it to directly drive an indicator LED without additional external components. To generate a logic-level nSTAT1 output, connect nSTAT1 to an appropriate supply voltage (typically VSYS) through a 10kΩ or greater pull-up resistor. See the Charge Status Indication section for more information. 38 nRSTO 39 nIRQ Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1, GP2, and GP3 together at a single point as close to the IC as possible. Reference Noise Bypass. Connect a 0.01μF ceramic capacitor from REFBP to GA. This pin is discharged to GA in shutdown. Open-Drain Reset Output. nRSTO asserts low whenever REG1 is out of regulation, and remains low for 260ms (typ) after REG1 reaches regulation. Open-Drain Interrupt Output. nIRQ asserts any time nPBIN is asserted or an unmasked fault condition exists. See the nIRQ Output section for more information. Charging State Select Input. 40 CHGLEV EP EP When ACIN = 0 charge current is internally set; Drive CHGLEV to a logic-high for high-current USB charging mode (maximum charge current is 500mA), drive CHGLEV to a logic-low for low-current USB charging mode (maximum charge current is 100mA). When ACIN = 1 charge current is externally set by RISET; Drive CHGLEV to a logic-high to for highcurrent charging mode (ISET (mA) = KISET × 1V/(RISET (kΩ) +0.031) where KISET = 628), drive CHGLEV to a logic-low for low-current charging mode (ISET (mA) = KISET × 1V/(RISET (kΩ) + 0.031) where KISET = 314). Do not leave CHGLEV floating. Exposed Pad. Must be soldered to ground on the PCB. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -6- www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE UNIT CHG_IN to GA t < 1ms and duty cycle <1% Steady State -0.3 to +18 -0.3 to +14 V V VP1 to GP1, VP2 to GP2, VP3 to GP3 -0.3 to +6 V BAT, VSYS, INL to GA -0.3 to +6 V SW1, OUT1 to GP1 -0.3 to (VVP1 +0.3) V SW2, OUT2 to GP2 -0.3 to (VVP2 +0.3) V SW3, OUT3 to GP3 -0.3 to (VVP3 +0.3) V -0.3 to +6 V -0.3 to (VINL +0.3) V Operating Ambient Temperature -40 to 85 °C Maximum Junction Temperature 125 °C Maximum Power Dissipation TQFN55-40 (Thermal Resistance θJA = 30oC/W) 2.7 W -65 to 150 °C 300 °C ON1, ON2, ON3, ISET, ACIN, VSEL, DCCC, CHGLEV, TH, SCL, SDA, REFBP, nIRQ, nRSTO, nSTAT0, nSTAT1, BTR, nPBIN to GA OUT4, OUT5, OUT6 to GA Storage Temperature Lead Temperature (Soldering, 10 sec) : Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect device reliability. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -7- www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 SYSTEM MANAGEMENT REGISTER DESCRIPTIONS Table 1: Global Register Map OUTPUT ADDRESS DATA (DEFAULT VALUE) HEX A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SYS 06h 0 0 0 0 0 1 1 0 R R R 0 R R 1 R REG1 10h 0 0 0 1 0 0 0 0 R R V V V V V V REG1 11h 0 0 0 1 0 0 0 1 R R R R R R R R REG1 12h 0 0 0 1 0 0 1 0 R R R R R 0 R 1 REG1 13h 0 0 0 1 0 0 1 1 R V V V V V V V REG2 20h 0 0 1 0 0 0 0 0 R R V V V V V V REG2 21h 0 0 1 0 0 0 0 1 R R R R R R R R REG2 22h 0 0 1 0 0 0 1 0 R R R R R 0 R 1 REG2 23h 0 0 1 0 0 0 1 1 R V V V V V V V REG3 30h 0 0 1 1 0 0 0 0 R R V V V V V V REG3 31h 0 0 1 1 0 0 0 1 R R R R R R R R REG3 32h 0 0 1 1 0 0 1 0 R R R R R 0 R 1 REG3 33h 0 0 1 1 0 0 1 1 R V V V V V V V REG4 40h 0 1 0 0 0 0 0 0 1 R 1 V V V V V REG4 43h 0 1 0 0 0 0 1 1 R R R R R R 0 R REG5 41h 0 1 0 0 0 0 0 1 1 R 1 V V V V V REG6 42h 0 1 0 0 0 0 1 0 R R R V V V V V KEY: R: Read-Only bits. No Default Assigned. V: Default Values Depend on Voltage Option. Default Values May Vary. Note: Addresses other than those specified in Table 1 may be used for factory settings. Do not access any registers other than those specified in Table 1. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -8- www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 SYSTEM MANAGEMENT I2C INTERFACE ELECTRICAL CHARACTERISTICS (VVSYS = 3.6V, TA = 25°C, unless otherwise specified.) PARAMETER TEST CONDITIONS MIN SCL, SDA Low Input Voltage VVSYS = 2.6V to 5.5V, TA = -40ºC to 85ºC SCL, SDA High Input Voltage VVSYS = 2.6V to 5.5V, TA = -40ºC to 85ºC 0.35 1.55 SCL, SDA Leakage Current SDA Low Output Voltage TYP MAX UNIT IOL = 5mA V V 1 µA 0.3 V SCL Clock Period, tSCL 2.5 µs SDA Data In Setup Time to SCL High, tSU 100 ns SDA Data Out Hold Time after SCL Low, tHD 300 ns Start Condition 100 ns SDA Data High Hold Time after Clock High, tSP Stop Condition 100 ns SDA Data Low Setup Time to SCL Low, tST Figure 1: I2C Serial Bus Timing tSCL SCL tST tSU SDA IN tSP tHD SDA OUT Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -9- www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 SYSTEM MANAGEMENT ELECTRICAL CHARACTERISTICS (VVSYS = 3.6V, TA = 25°C, unless otherwise specified.) PARAMETER TEST CONDITIONS Input Voltage Range MIN TYP 2.6 2.35 2.5 MAX UNIT 5.5 V 2.6 V UVLO Threshold Voltage VSYS Rising UVLO Hysteresis VSYS Falling 100 mV VSYS Supply Current ONx = VSYS 70 µA VSYS Shutdown Current ONx = GA, Not Charging 30 µA Voltage Reference 1.24 1.25 1.26 V Oscillator Frequency 1.35 1.6 1.85 MHz Logic High Input Voltage ON1, ON2, ON3, VSEL Logic Low Input Voltage ON1, ON2, ON3, VSEL Leakage Current VON1 = VON2 = VON3 = VVSEL = VnIRQ = VnRSTO = 4V nPBIN Internal Pull-up Resistance Low Level Output Voltage nIRQ, nRSTO. Sinking 10mA nRSTO Delay 1.4 V 0.4 V 1 µA 50 kΩ 0.3 V 260 ms Thermal Shutdown Temperature Temperature Rising 160 °C Thermal Shutdown Hysteresis Temperature Decreasing 20 °C Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 10 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 SYSTEM MANAGEMENT REGISTER DESCRIPTIONS Note: See Table 1 for default register settings. Table 2: Control Register Map DATA ADDRESS 06h D7 D6 D5 D4 D3 D2 D1 D0 R R R W/E R R nPBMASK PBSTAT R: Read-Only bits. Default Values May Vary. W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1. Table 3: Control Register Bit Descriptions ADDRESS NAME BIT ACCESS FUNCTION 06h PBSTAT [0] R/W Push Button Status 06h nPBMASK [1] R/W Push Button Interrupt Mask Option 06h [3:2] R READ ONLY 06h [4] W/E WRITE-EXACT 06h [7:5] R READ ONLY Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 11 - DESCRIPTION 0 De-assert 1 Asserted 0 Masked 1 Not Mask www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 SYSTEM MANAGEMENT TYPICAL PERFORMANCE CHARACTERISTICS (VVSYS = 3.6V, TA = 25°C, unless otherwise specified.) Oscillator Frequency vs. Temperature Oscillator Frequency (MHz) ACT8810-001 1.71 1.68 1.65 1.62 1.59 1.56 1.53 1.50 -40 -20 0 20 40 60 85 Temperature (°C) Shutdown Current vs. Temperature Shutdown Current (µA) ACT8810-002 26 ON1 = ON2 = ON3 = GA VVSYS = 4.2V 24 VVSYS = 3.6V VVSYS = 3.2V 22 20 -40 -20 0 20 40 60 85 Temperature (°C) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 12 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 SYSTEM MANAGEMENT FUNCTIONAL DESCRIPTION General Description The ACT8810 offers a wide array of system management functions that allow it to be configured for optimal performance in a wide range of applications. I2C Serial Interface At the core of the ACT8810’s flexible architecture is an I2C interface that permits optional programming capability to enhance overall system performance. To ensure compatibility with a wide range of system processors, the ACT8810 uses standard I2C commands; I2C write-byte commands are used to program the ACT8810, and I2C read-byte commands are used to read the ACT8810’s internal registers. The ACT8810 always operates as a slave device, and is addressed using a 7-bit slave address followed by an eighth bit, which indicates whether the transaction is a read-operation or a write-operation, [1011010x]. SDA is a bi-directional data line and SCL is a clock input. The master initiates a transaction by issuing a START condition, defined by SDA transitioning from high to low while SCL is high. Data is transferred in 8-bit packets, beginning with the MSB, and is clocked-in on the rising edge of SCL. Each packet of data is followed by an “Acknowledge” (ACK) bit, used to confirm that the data was transmitted successfully. For more information regarding the I2C 2-wire serial interface, go to the NXP website: http://www.nxp.com System Startup and Shutdown Startup Sequence The ACT8810 features a flexible enable architecture that allows it to support a variety of push-button enable/disable schemes. Although other startup routines are possible, ACT8810 provides three typical startup and shutdown processes proceed as shown in Control Sequence section. process is completely software-controlled, a typical shutdown sequence proceeds as follows: The second assertion of nPBIN asserts nPBIN and interrupts the microprocessor, which then initiates an interrupt service routine to reveal that nPBIN has been asserted. If there is no input to the charger, then the microprocessor disables each regulator according to the sequencing requirements of the system, then the system will finally be disabled when each of ON1, ON2, and ON3 have been deasserted. nPBIN Input ACT8810's nPBIN pin is a dual-function pin, combining system enable/disable control with a hardware reset function. Refering to Figure 2, the two pin functions are obtained by asserting this pin low, either through a direct connection or through a 100kΩ resistor, as described below. In most applications, nPBIN will be driven through a 100kΩ resistor. When driven in this way, nPBIN initiates system startup or shutdown, as described in the System Startup and Shutdown section. When a hardware-reset function is desired, nPBIN may also be driven directly to GA. In this case, nRSTO is immediately asserted low and remains low until nPBIN is de-asserted and the reset timeout period expires. This provides a hardware-reset function, allowing the system to be manually reset if the system processor locks up. Although a typical application will use momentary switches to drive nPBIN, as shown in Figure 2, nPBIN may also be driven by other sources, such as a GPIO or other logic output. Figure 2: nPBIN Input Shutdown Sequence Once a successful power-up routine is completed, a shutdown process may be initiated by asserting nPBIN a second time, typically as the result of pressing the push-button. Although the shutdown Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. Enable/Disable Inputs (ON1, ON2 and ON3) The ACT8810 provides three manual enable/disable inputs, ON1, ON2 and ON3, which - 13 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 SYSTEM MANAGEMENT FUNCTIONAL DESCRIPTION CONT’D enable and disable REG1, REG2, and REG3, respectively. Once the system is enabled, the system will remain enabled until all of ON1, ON2, and ON3 have been de-asserted. See the Control Sequence section for more information. Power-On Reset Output nRSTO is an open-drain output which asserts low upon startup or when nPBIN is driven directly to GA, and remains asserted low until the 260ms (default) power-on reset timer has expired. Connect a 10kΩ or greater pull-up resistor from nRSTO to an appropriate voltage supply. nIRQ Output nIRQ is an open-drain output that asserts low any time startup or an unmasked fault condition exists. When asserted, nIRQ remains low until the microprocessor polls the ACT8810's I2C interface. The ACT8810 supports a variety of other fault conditions, which may each be optionally unmasked via the I2C interface. For more information about the available fault conditions, refer to the appropriate sections of this datasheet. Connect a pull-up resistor from nIRQ to an appropriate voltage supply. nIRQ is typically used to drive the interrupt input of the system processor, and is useful in a variety of software-controlled enable/disable control routines. ACT8810QJ1## begins its system startup procedure by enabling REG1. When REG1 reaches 94% of its final regulation voltage, ACT8810QJ1## automatically turns on REG4 and REG5 and nRSTO is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. If VOUT1 is within 6% of its regulation voltage when the reset timer expires, the nRSTO is de-asserted, and the microprocessor can begin its power-up sequence. Once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microprocessor asserts any one of ON1, ON2 or ON3, and REG4, REG5 may be enabled or disabled via the I2C interface. This start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of ON1, ON2, and ON3), providing protection against inadvertent momentary assertions of the pushbutton. If desired, longer “push-and-hold” times can be easily implemented by simply adding an additional time delay before asserting ON1, ON2, or ON3. If the microprocessor is unable to complete its power-up routine successfully before the user lets go of the push-button, the ACT8810QJ1## automatically shuts itself down. Figure 3: Sequence A Thermal Shutdown First Push Button The ACT8810 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. This circuitry disables all regulators if the ACT8810 die temperature exceeds 160°C, and prevents the regulators from being enabled until the IC temperature drops by 20°C (typ). Assert Power-Hold Release Button Second Push System Button Shutdown nPBIN System Enable OUT1 94% of VOUT1 ON1, ON2, ON3 OUT2, OUT3 OUT4, OUT5 Control Sequence Sequence A The ACT8810QJ1## which is set with “sequence A“, has a system startup is initiated whenever the following conditions occurs: Reset time Enable 260ms nRSTO nIRQ 1) nPBIN is pushed low via 100kΩ resistance, When ever this condition exists, the Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 14 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 SYSTEM MANAGEMENT Sequence C Sequence B The ACT8810QJ2## which is set with “sequence B“, has a system startup is initiated whenever the following conditions occurs: The ACT8810QJ3## which is set with “sequence C“, has a system startup is initiated whenever the following conditions occurs: 1) nPBIN is pushed low via 100kΩ resistance, 1) nPBIN is pushed low via 100kΩ resistance, When ever this condition exists, the ACT8810QJ2## begins its system startup procedure by enabling REG1. When REG1 reaches 94% of its final regulation voltage, ACT8810QJ2## automatically turns on REG2 and REG3 and nRSTO is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. If VOUT1 is within 6% of its regulation voltage when the reset timer expires, the nRSTO is de-asserted, and the microprocessor can begin its power-up sequence. Once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microprocessor asserts any one of ON1, ON2 or ON3. REG4 and REG5 may be enabled if the microprocessor sets REG4.ON[ ] and REG5.ON[ ] to 1 via the I2C interface. In other case, REG4 and REG5 are disable. This start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of ON1, ON2, and ON3), providing protection against inadvertent momentary assertions of the pushbutton. If desired, longer “push-and-hold” times can be easily implemented by simply adding an additional time delay before asserting ON1, ON2, or ON3. If the microprocessor is unable to complete its power-up routine successfully before the user lets go of the push-button, the ACT8810QJ2## automatically shuts itself down. When ever this condition exists, the ACT8810QJ3## begins its system startup procedure by enabling REG1. When REG1 reaches 94% of its final regulation voltage, ACT8810QJ3## automatically turns on REG2, REG3, REG4, REG5 and nRSTO is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. If VOUT1 is within 6% of its regulation voltage when the reset timer expires, the nRSTO is de-asserted, and the microprocessor can begin its power-up sequence. Once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microprocessor asserts any one of ON1, ON2 or ON3, and REG4, REG5 may be enabled or disabled via the I2C interface. Figure 4: This start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of ON1, ON2, and ON3), providing protection against inadvertent momentary assertions of the pushbutton. If desired, longer “push-and-hold” times can be easily implemented by simply adding an additional time delay before asserting ON1, ON2, or ON3. If the microprocessor is unable to complete its power-up routine successfully before the user lets go of the push-button, the ACT8810QJ3## automatically shuts itself down. Figure 5: Sequence C Sequence B First Push Button Assert Power-Hold Release Button Second Push System Button Shutdown First Push Button nPBIN Release Button Second Push System Button Shutdown nPBIN System Enable OUT1 Assert Power-Hold System Enable 94% of V OUT1 ~100ms OUT1 Enable Qualification 94% of VOUT1 ~100ms Enable Qualification ON1, ON2, ON3 ON1, ON2, ON3 OUT2, OUT3 REG4.ON[ ], REG5.ON[ ] OUT2, OUT3 OUT4, OUT5 OUT4, OUT5 Reset time Enable Reset time Enable 260ms nRSTO nIRQ nIRQ Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. 260ms nRSTO - 15 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 SYSTEM MANAGEMENT Sequence D Sequence E The ACT8810QJ4## which is set with “sequence D“, has a system startup is initiated whenever the following condition occurs: The ACT8810QJ5## which is set with “sequence E“, has a system startup is initiated whenever the following conditions occurs: 1) nPBIN is pushed low via 100kΩ resistance, 1) A valid input voltage is present at VIN, or When ever this condition exists, the ACT8810QJ4## begins its system startup procedure by enabling REG1, When REG1 reaches 94% of its final regulation voltage, ACT8810QJ4## automatically turns on REG2, REG4, REG5 and nRSTO is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. when the reset timer expires, the nRSTO is deasserted and the microprocessor can begin its power-up sequence. Once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microprocessor asserts any one of ON1, ON2 or ON3, holding REG1, REG2, REG4, REG5, and enabling REG3. And any regulators could be enabled or disabled via the I2C interface. 2) nPBIN is pushed low via 100kΩ resistance, When ever this condition exists, the ACT8810QJ5## begins its system startup procedure by enabling REG1. When REG1 reaches 94% of its final regulation voltage, ACT8810QJ5## automatically turns on REG2, REG3, REG4, REG5 and nRSTO is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. If VOUT1 is within 6% of its regulation voltage when the reset timer expires, the nRSTO is de-asserted, and the microprocessor can begin its power-up sequence. Once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microprocessor asserts any one of ON1, ON2 or ON3, and REG4, REG5 may be enabled or disabled via the I2C interface. This start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of ON1, ON2, and ON3), providing protection against inadvertent momentary assertions of the pushbutton. If desired, longer “push-and-hold” times can be easily implemented by simply adding an additional time delay before asserting ON1, ON2, or ON3. If the microprocessor is unable to complete its power-up routine successfully before the user lets go of the push-button, the ACT8810QJ4## automatically shuts itself down. Figure 6: This start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of ON1, ON2, and ON3), providing protection against inadvertent momentary assertions of the pushbutton. If desired, longer “push-and-hold” times can be easily implemented by simply adding an additional time delay before asserting ON1, ON2, or ON3. If the microprocessor is unable to complete its power-up routine successfully before the user lets go of the push-button or un-plug charger input, the ACT8810QJ5## automatically shuts itself down. Sequence D Figure 7: First Push Button Assert Power-Hold Release Button Second Push Button System Shutdown Sequence E First Push Button nPBIN Release Button Second Push System Button Shutdown CHG_IN OR nPBIN System Enable OUT1 Assert Power-Hold 94% of VOUT1 System Enable OUT2, OUT4, OUT5 OUT1 ON1, ON2, ON3 94% of VOUT1 ~100ms Enable Qualification OUT3 ON1, ON2, ON3 Reset time Enable OUT2, OUT3 260ms nRSTO OUT4, OUT5 nIRQ Reset time Enable 260ms nRSTO nIRQ Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 16 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 STEP-DOWN DC/DC CONVERTERS ELECTRICAL CHARACTERISTICS (REG1) (VVSYS = 3.6V, TA = 25°C, unless otherwise specified.) PARAMETER TEST CONDITIONS VP1 Operating Voltage Range MIN 2.9 VP1 UVLO Threshold Input Voltage Rising VP1 UVLO Hysteresis Input Voltage Falling 2.7 Output Voltage Accuracy REG1 is disabled, VVP1 = 4.2V UNIT 5.5 V 2.9 V mV 130 200 µA 0.1 1 µA VNOM1 < 1.5V, IOUT1 = 10mA -2.1% VNOM1 +2.1% VNOM1 ≥ 1.5V, IOUT1 = 10mA -1.5% VNOM1 +1.5% Line Regulation VVP1 = Max(VNOM1 + 1V, 3.2V) to 5.5V Load Regulation IOUT1 = 10mA to 1.3A Current Limit Oscillator Frequency 2.8 MAX 85 Quiescent Supply Current Shutdown Supply Current TYP VOUT1 ≥ 20% of VNOM1 V 0.15 %/V 0.0017 %/mA 1.4 1.8 A 1.35 1.6 1.85 MHz VOUT1 = 0V 540 PMOS On-Resistance ISW1 = -100mA 0.16 0.24 Ω NMOS On-Resistance ISW1 = 100mA 0.16 0.24 Ω SW1 Leakage Current VVP1 = 5.5V, VSW1 = 5.5V or 0V 1 µA kHz Power Good Threshold 94 %VNOM1 Minimum On-Time 60 ns : VNOM1 refers to the nominal output voltage level for VOUT1 as defined by the Ordering Information section. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 17 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 STEP-DOWN DC/DC CONVERTERS ELECTRICAL CHARACTERISTICS (REG2) (VVSYS = 3.6V, TA = 25°C, unless otherwise specified.) PARAMETER TEST CONDITIONS VP2 Operating Voltage Range MIN 2.9 VP2 UVLO Threshold Input Voltage Rising VP2 UVLO Hysteresis Input Voltage Falling 2.7 Output Voltage Regulation Accuracy REG2 Disabled, VVP2 = 4.2V UNIT 5.5 V 2.9 V mV 130 200 µA 0.1 1 µA VNOM2 < 1.5V, IOUT2 = 10mA -2.1% VNOM2 +2.1% VNOM2 ≥ 1.5V, IOUT2 = 10mA -1.5% VNOM2 +1.5% Line Regulation VVP2 = Max(VNOM2 + 1V, 3.2V) to 5.5V Load Regulation IOUT2 = 10mA to 1.0A Current Limit Oscillator Frequency 2.8 MAX 85 Quiescent Supply Current Shutdown Supply Current TYP VOUT2 ≥ 20% of VNOM2 V 0.15 %/V 0.0017 %/mA 1.15 1.45 A 1.35 1.6 1.85 MHz VOUT2 = 0V 540 PMOS On-Resistance ISW2 = -100mA 0.25 0.38 Ω NMOS On-Resistance ISW2 = 100mA 0.17 0.26 Ω SW2 Leakage Current VVP2 = 5.5V, VSW2 = 5.5V or 0V 1 µA kHz Power Good Threshold 94 %VNOM2 Minimum On-Time 60 ns : VNOM2 refers to the nominal output voltage level for VOUT2 as defined by the Ordering Information section. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 18 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 STEP-DOWN DC/DC CONVERTERS ELECTRICAL CHARACTERISTICS (REG3) (VVSYS = 3.6V, TA = 25°C, unless otherwise specified.) PARAMETER TEST CONDITIONS VP3 Operating Voltage Range MIN 2.9 VP3 UVLO Threshold Input Voltage Rising VP3 UVLO Hysteresis Input Voltage Falling 2.7 Output Voltage Regulation Accuracy REG3 Disabled, VVP3 = 4.2V UNIT 5.5 V 2.9 V mV 130 200 µA 0.1 1 µA VNOM3 < 1.5V, IOUT3 = 10mA -2.1% VNOM3 +2.1% VNOM3 ≥ 1.5V, IOUT3 = 10mA -1.5% VNOM3 +1.5% Line Regulation VVP3 = Max(VNOM3 + 1V, 3.2V) to 5.5V Load Regulation IOUT3 = 10mA to 550mA Current Limit Oscillator Frequency 2.8 MAX 85 Quiescent Supply Current Shutdown Supply Current TYP VOUT3 ≥ 20% of VNOM3 V 0.15 %/V 0.0017 %/mA 0.55 0.7 A 1.35 1.6 1.85 MHz VOUT3 = 0V 540 PMOS On-Resistance ISW3 = -100mA 0.46 0.69 Ω NMOS On-Resistance ISW3 = 100mA 0.3 0.55 Ω SW3 Leakage Current VVP3 = 5.5V, VSW3 = 5.5V or 0V 1 µA kHz Power Good Threshold 94 %VNOM3 Minimum On-Time 60 ns : VNOM3 refers to the nominal output voltage level for VOUT3 as defined by the Ordering Information section. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 19 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 STEP-DOWN DC/DC CONVERTERS TYPICAL PERFORMANCE CHARACTERISTICS (ACT8810QJ3EB, VVP1 = VVP2 = 3.6V, L = 3.3µH, CVP1 = CVP2 = 4.7μF, COUT1 = 22µF, COUT2 = 10μF, TA = 25°C, unless otherwise specified.) REG1 Efficiency vs. Load Current VVSYS = 5.2V 80 VVSYS = 4.6V VVSYS = 4.2V 60 100 REG2 Efficiency (%) VVSYS = 3.6V 40 20 VVSYS = 3.6V 80 VVSYS = 5.2V 60 VVSYS = 4.6V VVSYS = 4.2V 40 20 VOUT1 = 3.3V VOUT2 = 1.2V 0 0 1 2000 10 1000 100 Load Current (mA) Load Current (mA) OUT1 Regulation Voltage vs. Temperature OUT2 Regulation Voltage vs. Temperature 1.212 3.312 3.309 3.306 OUT3 Regulation Voltage (V) IOUT1 = 35mA 3.303 3.300 3.297 3.294 3.291 3.288 3.285 3.282 -40 ACT8810-006 3.315 ACT8810-005 3.318 OUT2 Regulation Voltage (V) 200 20 2 IOUT2 = 35mA 1.208 1.204 1.200 1.196 1.192 1.188 -20 0 20 40 60 85 -40 -20 REG1 RDSON vs. VP1 Input Voltage 40 60 85 REG2 RDSON vs. VP2 Input Voltage NMOS REG2 RDSON (mΩ) 0.14 0.10 0.08 0.06 0.04 ACT8810-008 PMOS 0.12 20 0.5 ACT8810-007 0.18 0.16 0 Temperature (°C) Temperature (°C) REG1 RDSON (mΩ) ACT8810-004 REG1 Efficiency (%) REG2 Efficiency vs. Load Current ACT8810-003 100 0.4 0.3 PMOS 0.2 NMOS 0.1 0.02 0 3.5 0 4.0 4.5 5.0 5.5 6.0 3.0 6.5 ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. 4.0 4.5 5.0 5.5 6.0 VP2 Input Voltage (V) VP1 Input Voltage (V) Innovative PowerTM 3.5 - 20 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 STEP-DOWN DC/DC CONVERTERS TYPICAL PERFORMANCE CHARACTERISTICS CONT’D (ACT8810QJ3EB, VVP3 = 3.6V, L = 3.3µH, CVP3 = 4.7μF, COUT3 = 10μF, TA = 25°C, unless otherwise specified.) REG3 Efficiency vs. Load Current REG3 Efficiency (%) ACT8810-009 100 VOUT3 = 1.2V VVSYS = 3.6V 80 VVSYS = 4.6V 60 VVSYS = 4.2V 40 20 0 10 1 100 1000 Load Current (mA) OUT3 Regulation Voltage vs. TemperaOUT1 Regulation Voltage (V) ACT8810-010 1.812 IOUT3 = 35mA 1.808 1.804 1.800 1.796 1.792 1.788 -40 -20 0 20 40 60 85 Temperature (°C) REG3 RDSON vs. VP3 Input Voltage REG3 RDSON (mΩ) 0.45 0.40 PMOS ACT8810-011 0.50 0.35 0.30 0.25 NMOS 0.20 0.15 0.1 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VP3 Input Voltage (V) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 21 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 STEP-DOWN DC/DC CONVERTERS REGISTER DESCRIPTIONS Note: See Table 1 for default register settings. Table 4: REG1 Control Register Map DATA ADDRESS D7 D6 D5 D4 10h R R 11h R R R R 12h R R R R 13h R VRANGE D3 D2 D1 D0 R R R R R nFLTMSK OK ON VSET1 VSET0 R: Read-Only bits. Default Values May Vary. Table 5: REG1 Control Register Bit Descriptions ADDRESS NAME BIT ACCESS FUNCTION DESCRIPTION 10h VSET1 [5:0] R/W REG1 Standby Output Voltage Selection See Table 4 10h [7:6] R READ ONLY 11h [7:0] R READ ONLY 12h ON [0] R/W REG1 Enable 12h OK [1] R REG1 Power-OK 12h nFLTMSK [2] R/W REG1 Output Voltage Fault Mask Option [7:3] R 12h REG1 Disable 1 REG1 Enable 0 Output is not OK 1 Output is OK 0 Masked 1 Not Mask READ ONLY 13h VSET0 [5:0] R/W REG1 Output Voltage Selection 13h VRANGE [6] R/W REG1 Voltage Range [7] R 13h 0 Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. See Table 4 0 Min VOUT = 0.8V 1 Min VOUT = 1.25V READ ONLY - 22 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 STEP-DOWN DC/DC CONVERTERS REGISTER DESCRIPTIONS CONT’D Table 6: REG1/VSETx[ ] Output Voltage Setting REG1/VSETx[5:4] REG1/VSETx[3:0] REG1/VRANGE[ ] = [1] REG1/VRANGE[ ] = [0] 00 01 10 11 00 01 10 11 0000 Adjustable 1.025 1.425 1.825 Adjustable 2.050 2.850 3.650 0001 0.800 1.050 1.450 1.850 1.300 2.100 2.900 3.700 0010 0.800 1.075 1.480 1.875 1.350 2.150 2.950 3.750 0011 0.800 1.100 1.500 1.900 1.400 2.200 3.000 3.800 0100 0.800 1.125 1.525 1.925 1.450 2.250 3.050 3.850 0101 0.800 1.150 1.550 1.950 1.500 2.300 3.100 3.900 0110 0.800 1.175 1.575 1.975 1.550 2.350 3.150 3.950 0111 0.800 1.200 1.600 2.000 1.600 2.400 3.200 4.000 1000 0.825 1.225 1.625 2.025 1.650 2.450 3.250 4.050 1001 0.850 1.250 1.650 2.050 1.700 2.500 3.300 4.100 1010 0.875 1.275 1.675 2.075 1.750 2.550 3.350 4.150 1011 0.900 1.300 1.700 2.100 1.800 2.600 3.400 4.200 1100 0.925 1.325 1.725 2.125 1.850 2.650 3.450 4.250 1101 0.950 1.350 1.750 2.150 1.900 2.700 3.500 4.300 1110 0.975 1.375 1.775 2.175 1.950 2.750 3.550 4.350 1111 1.000 1.400 1.800 2.200 2.000 2.800 3.600 4.400 : Care must be taken when adjusting the VRANGE[ ] selection at address 13h bit-6 to avoid undesired output voltage selections. The VRANGE bit allows selection of the two output voltage ranges available for REG1, REG2 and REG3 (VRANGE = 0 – VOUT range 0.8V to 2.2V, VRANGE = 1 – VOUT range 1.3V to 4.4V). It is recommended that the user first establishes if the new VOUT voltage is within the current selected voltage range (selected by VRANGE) prior to changing the value of the VRANGE bit. : Refer to the Output Voltage Programming section for more information. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 23 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 STEP-DOWN DC/DC CONVERTERS REGISTER DESCRIPTIONS Note: See Table 1 for default register settings. Table 7: REG2 Control Register Map DATA ADDRESS D7 D6 D5 D4 20h R R 21h R R R R 22h R R R R 23h R VRANGE D3 D2 D1 D0 R R R R R nFLTMSK OK ON VSET1 VSET0 R: Read-Only bits. Default Values May Vary. Table 8: REG2 Control Register Bit Descriptions ADDRESS NAME BIT ACCESS FUNCTION DESCRIPTION 20h VSET1 [5:0] R/W REG2 Standby Output Voltage Selection See Table 7 20h [7:6] R READ ONLY 21h [7:0] R READ ONLY 22h ON [0] R/W REG2 Enable 22h OK [1] R REG2 Power-OK 22h nFLTMSK [2] R/W REG2 Output Voltage Fault Mask Option [7:3] R 22h REG2 Disable 1 REG2 Enable 0 Output is not OK 1 Output is OK 0 Masked 1 Not Mask READ ONLY 23h VSET0 [5:0] R/W REG2 Output Voltage Selection 23h VRANGE [6] R/W REG2 Voltage Range [7] R 23h 0 Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. See Table 7 0 Min VOUT = 0.8V 1 Min VOUT = 1.25V READ ONLY - 24 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 STEP-DOWN DC/DC CONVERTERS REGISTER DESCRIPTIONS CONT’D Table 9: REG2/VSETx[ ] Output Voltage Setting REG2/VSETx[5:4] REG2/VSETx[3:0] REG2/VRANGE[ ] = [1] REG2/VRANGE[ ] = [0] 00 01 10 11 00 01 10 11 0000 Adjustable 1.025 1.425 1.825 Adjustable 2.050 2.850 3.650 0001 0.800 1.050 1.450 1.850 1.300 2.100 2.900 3.700 0010 0.800 1.075 1.480 1.875 1.350 2.150 2.950 3.750 0011 0.800 1.100 1.500 1.900 1.400 2.200 3.000 3.800 0100 0.800 1.125 1.525 1.925 1.450 2.250 3.050 3.850 0101 0.800 1.150 1.550 1.950 1.500 2.300 3.100 3.900 0110 0.800 1.175 1.575 1.975 1.550 2.350 3.150 3.950 0111 0.800 1.200 1.600 2.000 1.600 2.400 3.200 4.000 1000 0.825 1.225 1.625 2.025 1.650 2.450 3.250 4.050 1001 0.850 1.250 1.650 2.050 1.700 2.500 3.300 4.100 1010 0.875 1.275 1.675 2.075 1.750 2.550 3.350 4.150 1011 0.900 1.300 1.700 2.100 1.800 2.600 3.400 4.200 1100 0.925 1.325 1.725 2.125 1.850 2.650 3.450 4.250 1101 0.950 1.350 1.750 2.150 1.900 2.700 3.500 4.300 1110 0.975 1.375 1.775 2.175 1.950 2.750 3.550 4.350 1111 1.000 1.400 1.800 2.200 2.000 2.800 3.600 4.400 : Care must be taken when adjusting the VRANGE[ ] selection at address 23h bit-6 to avoid undesired output voltage selections. The VRANGE bit allows selection of the two output voltage ranges available for REG1, REG2 and REG3 (VRANGE = 0 – VOUT range 0.8V to 2.2V, VRANGE = 1 – VOUT range 1.3V to 4.4V). It is recommended that the user first establishes if the new VOUT voltage is within the current selected voltage range (selected by VRANGE) prior to changing the value of the VRANGE bit. : Refer to the Output Voltage Programming section for more information. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 25 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 STEP-DOWN DC/DC CONVERTERS REGISTER DESCRIPTIONS Note: See Table 1 for default register settings. Table 10: REG3 Control Register Map DATA ADDRESS D7 D6 D5 D4 30h R R 31h R R R R 32h R R R R 33h R VRANGE D3 D2 D1 D0 R R R R R nFLTMSK OK ON VSET1 VSET0 R: Read-Only bits. Default Values May Vary. W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1 Table 11: REG3 Control Register Bit Descriptions ADDRESS NAME BIT ACCESS FUNCTION DESCRIPTION 30h VSET1 [5:0] R/W REG3 Standby Output Voltage Selection See Table 10 30h [7:6] R READ ONLY 31h [7:0] R READ ONLY 32h ON [0] R/W REG3 Enable 32h OK [1] R REG3 Power-OK 32h nFLTMSK [2] R/W REG3 Output Voltage Fault Mask Option [7:3] R 32h REG3 Disable 1 REG3 Enable 0 Output is not OK 1 Output is OK 0 Masked 1 Not Mask READ ONLY 33h VSET0 [5:0] R/W REG3 Output Voltage Selection 33h VRANGE [6] R/W REG3 Voltage Range [7] R 33h 0 Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. See Table 10 0 Min VOUT = 0.8V 1 Min VOUT = 1.25V READ ONLY - 26 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 STEP-DOWN DC/DC CONVERTERS REGISTER DESCRIPTIONS CONT’D Table 12: REG3/VSETx[ ] Output Voltage Setting REG3/VSETx[5:4] REG3/VSETx[3:0] REG3/VRANGE[ ] = [1] REG3/VRANGE[ ] = [0] 00 01 10 11 00 01 10 11 0000 Adjustable 1.025 1.425 1.825 Adjustable 2.050 2.850 3.650 0001 0.800 1.050 1.450 1.850 1.300 2.100 2.900 3.700 0010 0.800 1.075 1.480 1.875 1.350 2.150 2.950 3.750 0011 0.800 1.100 1.500 1.900 1.400 2.200 3.000 3.800 0100 0.800 1.125 1.525 1.925 1.450 2.250 3.050 3.850 0101 0.800 1.150 1.550 1.950 1.500 2.300 3.100 3.900 0110 0.800 1.175 1.575 1.975 1.550 2.350 3.150 3.950 0111 0.800 1.200 1.600 2.000 1.600 2.400 3.200 4.000 1000 0.825 1.225 1.625 2.025 1.650 2.450 3.250 4.050 1001 0.850 1.250 1.650 2.050 1.700 2.500 3.300 4.100 1010 0.875 1.275 1.675 2.075 1.750 2.550 3.350 4.150 1011 0.900 1.300 1.700 2.100 1.800 2.600 3.400 4.200 1100 0.925 1.325 1.725 2.125 1.850 2.650 3.450 4.250 1101 0.950 1.350 1.750 2.150 1.900 2.700 3.500 4.300 1110 0.975 1.375 1.775 2.175 1.950 2.750 3.550 4.350 1111 1.000 1.400 1.800 2.200 2.000 2.800 3.600 4.400 : Care must be taken when adjusting the VRANGE[ ] selection at address 33h bit-6 to avoid undesired output voltage selections. The VRANGE bit allows selection of the two output voltage ranges available for REG1, REG2 and REG3 (VRANGE = 0 – VOUT range 0.8V to 2.2V, VRANGE = 1 – VOUT range 1.3V to 4.4V). It is recommended that the user first establishes if the new VOUT voltage is within the current selected voltage range (selected by VRANGE) prior to changing the value of the VRANGE bit. : Refer to the Output Voltage Programming section for more information. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 27 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 STEP-DOWN DC/DC CONVERTERS FUNCTIONAL DESCRIPTION General Description REG1, REG2, and REG3 are fixed-frequency, current-mode, synchronous PWM step-down converters that are capable of supplying up to 1.3A, 1.0A, and 0.55A of output current, respectively. These regulators operate with a fixed frequency of 1.6MHz, minimizing noise in sensitive applications and allowing the use of small external components, and achieve peak efficiencies of up to 97%. Each step-down DC/DC is available with a variety of standard and custom output voltages, which may be software-controlled by systems requiring advanced power management functions, via the I2C interface. Buck Regulator PFM/PWM Operating Modes The buck converters offer PFM/PWM operating modes to maximize efficiency under both light and full load conditions. The device will automatically transition from fixed frequency PWM mode to PFM mode when the output current is approximately 100mA. In PFM mode, the device maintains output voltage regulation by adjusting the switching frequency. The device transitions into fixed frequency PWM mode when the output current reaches approximately 100mA. 100% Duty Cycle Operation REG1, REG2 and REG3 are each capable of operating at up to 100% duty cycle. During 100% duty-cycle operation, the high-side power MOSFET is held on continuously, providing a direct connection from the input to the output (through the inductor), ensuring the lowest possible dropout voltage in battery powered applications. Synchronous Rectification REG1, REG2 and REG3 each feature integrated channel synchronous rectifiers, maximizing efficiency and minimizing the total solution size and cost by eliminating the need for external rectifiers. Enabling and Disabling REG1, REG2 and REG3 REG1, REG2, and REG3 are typically enabled and disabled using the ACT8810's closed-loop enable/disable control scheme, including the nPBIN input. Refer to the System Startup and Shutdown section for more information about this function. Each regulator is enabled when the following conditions are met: Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. 1) ONx is asserted high to enable REGx, 2) REGx/ONx[ ] is set to 1 when ONx is high In addition REG1, REG2, or REG3 may be enabled when nPBIN is pushed low via 100kΩ resistance. It depends on sequence is set. See the Control Sequence section for more information. When none of these conditions are true, REG1, REG2 and REG3 are disabled, and each regulator’s quiescent supply current drops to less than 1μA. Power-OK REG1, REG2 and REG3 each feature a variety of status bits that can be read by the system microprocessor. If any output falls below its powerOK threshold, typically 6% below the programmed regulation voltage, REGx/OK[ ] is cleared to 0. Soft-Start REG1, REG2 and REG3 each include matched soft-start circuitry. When enabled, the output voltages track the internal 80μs soft-start ramp and both power up in a monotonic manner that is independent of loading on either output. This circuitry ensures that each output powers up in a controlled manner, greatly simplifying power sequencing design considerations. Compensation REG1, REG2 and REG3 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. No compensation design is required; simply follow a few simple guide lines described below when choosing external components. Input Capacitor Selection The input capacitor reduces peak currents and noise induced upon the voltage source. A 4.7μF ceramic capacitor for each of REG1, REG2 and REG3 is recommended for most applications. Output Capacitor Selection For most applications, 22μF ceramic output capacitors are recommended for REG1 and 10μF ceramic output capacitors are recommended for REG2, REG3. Although the these regulators were designed to take advantage of the benefits of ceramic capacitors, namely small size and very-low ESR, low-ESR tantalum capacitors can provide acceptable results as well. - 28 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 STEP-DOWN DC/DC CONVERTERS FUNCTIONAL DESCRIPTION CONT’D Inductor Selection REG1, REG2 and REG3 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. REG1, REG2 and REG3 of the device were optimized for operation with and 3.3μH inductor, although inductors in the 2.2μH to 4.7μH range can be used. Choose an inductor with a low DC-resistance, and avoid inductor saturation by choosing inductors with DC ratings that exceed the maximum output current of the application by at least 30%. Figure 8: Output Voltage Programming OUTx ACT8810 CFF RFB1 FBx RFB2 Finally choose CFF using the following equation: C FF = 2.2 × 10 −6 R FB1 (2) Output Voltage Programming Where RFB1 = 47kΩ, use 47pF. By default, REG1, REG2 and REG3 each power up and regulate to their default output voltage, as defined in the Ordering Information section. Once the system is enabled, each regulator’s output voltage may be modified through either the I2C interface or the Voltage Selection (VSEL) pin. When using Adjustable Option, OUTx pins works as FBx function. Programming via the I2C Interface Following startup, REG1, REG2, and REG3 may be independently programmed to different values by writing to the REGx/VSETx[_] and REGx/VRANGE[_] registers via the I2C interface. To program each regulator, first select the desired output voltage range via the REGx/VRANGE[ ] bit. Each regulator supports two overlapping ranges; set REGx/VRANGE[_] to 0 for voltages below 2.245V, set REGx/VRANGE[_] to 1 for voltages above 1.25V. Once the desired range has been selected, program the output to a voltage within that range by setting the REGx/VSETx bits. For more information about the output voltage setting options, refer to Tables 4, 7, and 10, for REG1, REG2, and REG3, respectively. Programming with Adjustable Option Figure 8 shows the feedback network necessary to set the output voltage when using the adjustable output voltage option. Select components as follows: Set RFB2 = 51kΩ, then calculate RFB1 using the following equation: ⎛V ⎞ R FB 1 = R FB 2 ⎜⎜ OUTx − 1 ⎟⎟ ⎝ V FBx ⎠ (1) Where VFBx is 0.625V when REGx × VRANGE[ ] = 0 and 1.25V when REGx × VRANGE[ ] = 1 Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. Output Voltage Selection Pin (VSEL) ACT8810's VSEL pin provides a simple means of alternating between two preset output voltage settings, such as may be needed for dynamic voltage selection (DVS). The operation of this pin is as follows: when VSEL is driven to GA or a logic low, the output voltages of REG1, REG2, and REG3 are each defined by their VSET0[ ] register. when VSEL is driven to VSYS or a logic high, the output voltages of REG1, REG2, and REG3 are each defined by their VSET1[ ] register. By default, each regulator's VSET0[ ] and VSET1[ ] registers are both programmed to the same voltage, as defined in the Ordering Information section. As a result, toggling VSET under default conditions has no affect. However, by re-programming one or more regulator's VSET0[ ] and/or VSET1[ ] registers, one can easily toggle these regulators' output voltages between two sets of voltages, such as to implement 'normal' and 'standby' modes in a system utilizing the ACT8810 to implement an advanced power management architecture. PCB Layout Considerations High switching frequencies and large peak currents make PC board layout an important part of stepdown DC/DC converter design. A good design minimizes excessive EMI on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. Step-down DC/DCs exhibit discontinuous input current, so the input capacitors should be placed as - 29 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 STEP-DOWN DC/DC CONVERTERS FUNCTIONAL DESCRIPTION CONT’D close as possible to the IC, and avoiding the use of vias if possible. The inductor, input filter capacitor, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. The ground nodes for each regulator’s power loop should be connected at a single point in a starground configuration, and this point should be connected to the backside ground plane with multiple vias. The output node for each regulator should be connected to its corresponding OUTx pin through the shortest possible route, while keeping sufficient distance from switching nodes to prevent noise injection. Finally, the exposed pad should be directly connected to the backside ground plane using multiple vias to achieve low electrical and thermal resistance. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 30 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 LOW-DROPOUT LINEAR REGULATORS ELECTRICAL CHARACTERISTICS (REG4) (VINL = 3.6V, COUT4 = 1µF, TA = 25°C, unless otherwise specified.) PARAMETER TEST CONDITIONS INL Operating Voltage Range VINL Input Rising UVLO Hysteresis VINL Input Falling 2.4 V 2.6 V V VNOM4 +2% TA = -40°C to 85°C -3% VNOM4 +3% IOUT5 = 1mA to 360mA %/V -0.07 mV/mA f = 1kHz, IOUT4 = 360mA, COUT4 = 1µF 70 f = 10kHz, IOUT4 = 360mA, COUT4 = 1µF 60 Regulator Enabled 35 Regulator Disabled 0 IOUT4 = 160mA, VOUT4 > 3.1V dB µA 100 200 360 VOUT4 = 95% of regulation voltage V 0 Output Current Current Limit 5.5 -2% Load Regulation Error Dropout Voltage3 UNIT TA = 25°C VINL = Max(VOUT5 + 0.5V, 3.6V) to 5.5V Supply Current per Output 2.5 MAX 0.1 Line Regulation Error Power Supply Rejection Ratio TYP 2.6 INL UVLO Threshold Output Voltage Accuracy MIN 400 mV mA Internal Soft-Start 100 µs Power Good Flag High Threshold VOUT4, hysteresis = -2% 88 % Output Noise 40 µVRMS COUT4 = 10µF, f = 10Hz to 100kHz Stable COUT4 Range Discharge Resistor in Shutdown 1 LDO Disabled, DIS4[ ] = [1] 20 1000 µF Ω : VNOM4 refers to the nominal output voltage level for VOUT4 as defined by the Ordering Information section. : PSRR is lower with VSET < 1.25V 3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage (for 2.8V output voltage or higher) : LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Under heavy overload conditions the output current limit folds back by 40% (typ) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 31 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 LOW-DROPOUT LINEAR REGULATORS ELECTRICAL CHARACTERISTICS (REG5) (VINL = 3.6V, COUT5 = 1µF, TA = 25°C, unless otherwise specified.) PARAMETER TEST CONDITIONS INL Operating Voltage Range VINL Input Rising UVLO Hysteresis VINL Input Falling 2.4 V +2% TA = -40°C to 85°C -3% VNOM5 +3% %/V -0.07 mV/mA f = 1kHz, IOUT5 = 360mA, COUT5 = 1µF 70 f = 10kHz, IOUT5 = 360mA, COUT5 = 1µF 60 Regulator Enabled 35 Regulator Disabled 0 IOUT5 = 160mA, VOUT5 > 3.1V VOUT5 = 95% of regulation voltage dB µA 100 mV 360 mA mA 100 µs 40 µVRMS 1 LDO Disabled, DIS5[ ] = [1] 200 400 COUT5 = 10µF, f = 10Hz to 100kHz Stable COUT5 Range V 0 Internal Soft-Start Discharge Resistor in Shutdown 2.6 V Output Current Output Noise V VNOM5 IOUT5 = 1mA to 360mA Current Limit 5.5 -2% Load Regulation Error Dropout Voltage3 UNIT TA = 25°C VINL = Max(VOUT5 + 0.5V, 3.6V) to 5.5V Supply Current per Output 2.5 MAX 0.1 Line Regulation Error Power Supply Rejection Ratio TYP 2.6 INL UVLO Threshold Output Voltage Accuracy MIN 20 1000 µF Ω : VNOM5 refers to the nominal output voltage level for VOUT5 as defined by the Ordering Information section. : PSRR is lower with VSET < 1.25V 3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage (for 2.8V output voltage or higher) : LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Under heavy overload conditions the output current limit folds back by 40% (typ) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 32 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 LOW-DROPOUT LINEAR REGULATORS TYPICAL PERFORMANCE CHARACTERISTICS (ACT8810QJ3EB, VVSYS = 5V, TA = 25°C, unless otherwise specified.) 200 Dropout Voltage (mV) 0.5 ACT8810-013 1.0 0.0 -0.5 -1.0 175 150 REG4, REG5 125 100 75 50 3.1V 3.3V 3.6V 25 0 -1.5 0 80 120 160 200 240 280 320 0 360 50 100 150 200 250 300 Load Current (mA) Output Current (mA) Output Voltage Deviation vs. Temperature LDO Output Voltage Noise 360 ACT8810-015 2.00 40 ACT8810-014 Output Voltage Deviation (%) Dropout Voltage vs. Output Current 225 ACT8810-012 Output Regulation Voltage (%) Output Regulation Voltage vs. Load Current 1.5 ILOAD = 0mA 1.50 CH1 1.00 0.50 0.00 CREF = 10nF -0.5 -40 -15 10 35 60 85 CH1: VOUTx, 200µV/div (AC COUPLED) TIME: 200ms/div Temperature (°C) Region of Stable COUT ESR vs. Output Current ACT8810-016 ESR (Ω) 1 0.1 Stable ESR 0.01 0 50 100 150 200 250 300 360 Output Current (mA) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 33 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 LOW-DROPOUT LINEAR REGULATORS REGISTER DESCRIPTIONS Note: See Table 1 for default register settings. Table 13: REG45 Control Register Map DATA ADDRESS D7 D6 D5 D4 40h DIS4 R ON4 VSET4 41h DIS5 R ON5 VSET5 43h R R R R D3 R D2 R D1 D0 nFLTMSK OK R: Read-Only bits. Default Values May Vary. Table 14: REG45 Control Register Bit Descriptions ADDRESS NAME BIT ACCESS FUNCTION DESCRIPTION 40h VSET4 [4:0] R/W REG4 Output Voltage Selection See Table 15 40h ON4 [5] R/W REG4 Enable [6] R 40h DIS4 [7] R/W REG4 Discharge Enable 41h VSET5 [4:0] R/W REG5 Output Voltage Selection 41h ON5 [5] R/W REG5 Enable [6] R 1 REG4 Enable 0 Discharge Disable 1 Discharge Enable See Table 15 0 REG5 Disable 1 REG5 Enable READ ONLY 41h DIS5 [7] R/W REG5 Discharge Enable 43h OK [0] R REG4 Power-OK 43h nFLTMSK [1] R/W REG4 Output Voltage Fault Mask Option [7:2] R 43h REG4 Disable READ ONLY 40h 41h 0 Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. 0 Discharge Disable 1 Discharge Enable 0 Output is not OK 1 Output is OK 0 Masked 1 Not Mask READ ONLY - 34 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 LOW-DROPOUT LINEAR REGULATORS REGISTER DESCRIPTIONS CONT’D Table 15: REG45/VSETx[ ] Output Voltage Setting REG45CFG/VSETx[2:0] REG45CFG/VSETx[4:3] 00 01 10 11 000 0.90 1.45 1.90 2.75 001 1.00 1.50 2.00 2.80 010 1.10 1.55 2.10 2.85 011 1.20 1.60 2.20 2.90 100 1.25 1.70 2.40 3.00 101 1.30 1.75 2.50 3.10 110 1.35 1.80 2.60 3.20 111 1.40 1.85 2.70 3.30 Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 35 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 LOW-DROPOUT LINEAR REGULATORS FUNCTIONAL DESCRIPTION General Description REG4 and REG5 are low-noise, low-dropout linear regulators (LDOs) that are optimized for low noise and high-PSRR operation, achieving more than 60dB PSRR at frequencies up to 10kHz. LDO Output Voltage Programming All LDOs feature independently-programmable output voltages that are set via the I2C serial interface, increasing the ACT8810’s flexibility while reducing total solution size and cost. Set the output voltage by writing to the REG45CFG/VSETx[ ] registers. Output Current Capability REG4 and REG5 each supply an output current of 360mA. Excellent performance is achieved over this load current range. Output Current Limit In order to ensure safe operation under over-load conditions, each LDO features current-limit circuitry with current fold-back. The current-limit circuitry limits the current that can be drawn from the output, providing protection in over-load conditions. For additional protection under extreme over current conditions, current-fold-back protection reduces the current-limit by approximately 40% under extreme overload conditions. Enabling and Disabling the LDOs All LDOs feature independent enable/disable control via the I2C serial interface. Independently enable or disable each output by writing to the appropriate REG45CFG/ONx[ ] bit. In addition REG4 or REG5 may be enable when nPBIN is pushed low via 100kΩ resistance. It depends on sequence is set. See the Control Sequence section for more information. Power-OK REG4 features power-OK status bit that can be read by the system microprocessor via the I2C interface. If an output voltage is lower than the power-OK threshold, typically 12% below the programmed regulation voltage, the corresponding REG45CFG/OK[ ] will clear to 0. Reference Bypass Pin The ACT8810 contains a reference bypass pin Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. which filters noise from the reference, providing a low noise voltage reference to the LDOs. Bypass REFBP to GA with a 0.01μF ceramic capacitor. Optional LDO Output Discharge Each of the ACT8810’s LDOs features an optional, independent output voltage discharge feature. When this feature is enabled, the LDO output is discharged to ground through a 1kΩ resistance when the LDO is shutdown. This feature may be enabled or disabled via the I2C interface by writing to the REG45CFG/DISx[ ] bits. Output Capacitor Selection REG4 and REG5 each require only a small ceramic capacitor for stability. For best performance, each output capacitor should be connected directly between the OUTx and GA pins as possible, with a short and direct connection. To ensure best performance for the device, the output capacitor should have a minimum capacitance of 1μF, and ESR value between 10mΩ and 200mΩ. High quality ceramic capacitors such as X7R and X5R dielectric types are strongly recommended. PCB Layout Considerations The ACT8810’s LDOs provide good DC, AC, and noise performance over a wide range of operating conditions, and are relatively insensitive to layout considerations. When designing a PCB, however, careful layout is necessary to prevent other circuitry from degrading LDO performance. A good design places input and output capacitors as close to the LDO inputs and output as possible, and utilizes a star-ground configuration for all regulators to prevent noise-coupling through ground. Output traces should be routed to avoid close proximity to noisy nodes, particularly the SW nodes of the DC/DCs. REFBP is a filtered reference noise, and internally has a direct connection to the linear regulator controller. Any noise injected onto REFBP will directly affect the outputs of the linear regulators, and therefore special care should be taken to ensure that no noise is injected to the outputs via REFBP. As with the LDO output capacitors, the REFBP bypass capacitor should be placed as close to the IC as possible, with short, direct connections to the star-ground. Avoid the use of vias whenever possible. Noisy nodes, such as from the DC/DCs, should be routed as far away from REFBP as possible. - 36 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 RTC LOW-DROPOUT LINEAR REGULATOR ELECTRICAL CHARACTERISTICS (REG6) (TA = 25°C, unless otherwise specified.) PARAMETER TEST CONDITIONS Input Supply Range Output Voltage Accuracy MIN TYP 2.6 MAX UNIT 5.5 V TA = 25°C -2% VNOM6 +2% TA = -40°C to 85°C -3% VNOM6 +3% V Line Regulation Error VINL = VOUT6 + 0.5V to VINL = 5.5V Load Regulation Error IOUT6 = 0mA to 30mA Input Supply Current ON1 = ON2 = ON3 = GA 6 12 µA Dropout Voltage IOUT6 = 10mA 35 70 mV 30 mA Output Current Current Limit3 VOUT6 = 95% of regulation voltage Stable COUT6 Range 0.1 %/V -0.01 %/mA 45 1 mA 20 µF : VNOM6 refers to the nominal output voltage level for VOUT6 as defined by the Ordering Information section. : Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage (for 2.8V output voltage or higher) 3: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 37 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 RTC LOW-DROPOUT LINEAR REGULATOR REGISTER DESCRIPTIONS Note: See Table 1 for default register settings. Table 16: REG6 Control Register Map ADDRESS 42h DATA D7 D6 D5 R R R D4 D3 D2 D1 D0 VSET6 R: Read-Only bits. Default Values May Vary. Table 17: REG6 Control Register Bit Descriptions ADDRESS NAME BIT ACCESS FUNCTION DESCRIPTION 42h VSET6 [4:0] R/W REG6 Output Voltage Selection See Table 18 [7:5] R 42h READ ONLY Table 18: REG6/VSETx[ ] Output Voltage Setting REG6CFG/VSETx[2:0] REG6CFG/VSETx[4:3] 00 01 10 11 000 0.90 1.45 1.90 2.75 001 1.00 1.50 2.00 2.80 010 1.10 1.55 2.10 2.85 011 1.20 1.60 2.20 2.90 100 1.25 1.70 2.40 3.00 101 1.30 1.75 2.50 3.10 110 1.35 1.80 2.60 3.20 111 1.40 1.85 2.70 3.30 Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 38 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 RTC LOW-DROPOUT LINEAR REGULATOR FUNCTIONAL DESCRIPTION Backup Battery Charging General Description REG6 is an always-on, low-dropout linear regulator (LDO) that is optimized for RTC and backup-battery applications. REG6 features low-quiescent supply current, current-limit protection, and reverse-current protection, and is ideally suited for always-on power supply applications, such as for a real-time clock, or as a backup-battery or super-cap charger. REG6 features a constant current-limit, which protects the IC under output short-circuit conditions as well as provides a constant charge current, when operating as a backup battery charger. As shown in Figure 10, REG6 features a CC/CV output characteristic, regulating its output voltage for load currents up to 30mA, and regulating output current when the load exceeds (typically) 60mA. Output Voltage By default, REG6's output voltage is as defined in the Ordering Information section. However, this voltage may be programmed by writing to the REG6CFG/VSETx[ ] register via the I2C interface. Figure 10: REG6 Output Voltage REG6 Output Voltage vs. Load Current Reverse-Current Protection Output Voltage (V) REG6 features internal circuitry that limits the reverse supply current to less than 1µA when the input voltage falls below the output voltage, as can be encountered in backup-battery charging applications. REG6's internal circuitry monitors the input and the output, and disconnects internal circuitry and parasitic diodes when the input voltage falls below the output voltage, greatly minimizing backup battery discharge. ACT8810-017 4 3 2 Constant Voltage Region Constant Current Region 1 0 0 Typical Application 20 40 80 60 100 Load Current (mA) Voltage Regulators REG6 is ideally suited for always-on voltageregulation applications, such as for real-time clock and memory keep-alive applications. This regulator requires only a small ceramic capacitor with a minimum capacitance of 1μF for stability. For best performance, the output capacitor should be connected directly between the output and GA, with a short and direct connection. Figure 9: Typical Application of RTC LDO ACT8810 OUT6 RTC Supper cap or Back-up battery Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 39 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 TM ActivePath CHARGER ELECTRICAL CHARACTERISTICS (VCHG_IN = 5V, TA = 25°C, unless otherwise specified.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 6.0 V 4.0 V ActivePath CHG_IN Operating Voltage Range 4.35 CHG_IN UVLO Threshold CHG_IN Voltage Rising CHG_IN UVLO Hysteresis CHG_IN Voltage Falling CHG_IN OVP Threshold CHG_IN Voltage Falling CHG_IN OVP Hysteresis CHG_IN Voltage Rising 350 mV VCHG_IN < VUVLO 20 µA CHG_IN Supply Current CHG_IN to VSYS On-Resistance CHG_IN to VSYS Current Limit VCHG_IN < VBAT + 120mV, VCHG_IN > VUVLO 3.6 3.8 0.8 6.0 50 6.5 120 V 7.0 200 V µA VCHG_IN > VBAT + 120mV, VCHG_IN > VUVLO Charger disabled, ISYS = 0mA 1.8 IVSYS = 100mA 0.4 0.6 Ω A mA ACIN = VSYS 1.5 2 3 ACIN = GA, CHGLEV = GA 85 95 105 ACIN = GA, CHGLEV = VSYS 400 450 500 mA VSYS AND DCCC REGULATION VSYS Regulated Voltage IVSYS = 10mA 4.4 4.6 4.8 V DCCC Pull-Up Current VCHG_IN > VBAT + 120mV, Hysteresis = 50mV 92 100 108 µA nSTATx Sink Current VnSTATx = 2V 3 5 7 mA nSTATx Output Low Voltage InSTATx = 1mA 0.4 V nSTATx Leakage Current VnSTATx = 4.2V 1 µA nSTATx OUTPUT ACIN AND CHGLEV INPUTS CHGLEV Logic High Input Voltage 1.4 V CHGLEV Logic Low Input Voltage CHGLEV Leakage Current VCHGLEV = 4.2V ACIN Logic High Input Voltage V 1 µA 1.4 V ACIN Logic Low Input Voltage ACIN Leakage Current 0.4 VACIN = 4.2V 0.4 V 1 µA TEMPERATURE SENSE COMPARATOR TH Pull-Up Current VCHG_IN > VBAT + 120mV, Hysteresis = 50mV 92 100 108 µA VTH Upper Temperature Voltage Threshold (VTHH) Hot Detect NTC Thermistor 0.485 0.500 0.525 V VTH Lower Temperature Voltage Threshold (VTHL) Cold Detect NTC Thermistor 2.47 2.52 2.57 V VTH Hysteresis Upper and Lower Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. 30 - 40 - mV www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 TM ActivePath CHARGER ELECTRICAL CHARACTERISTICS CONT’D (VCHG_IN = 5V, TA = 25°C, unless otherwise specified.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CHARGER BAT Reverse Leakage Current VCHG_IN = 0V, VBAT = 4.2V, IVSYS = 0mA BAT to VSYS On-Resistance ISET Pin Voltage Charge Termination Voltage Charge Current 0.12 TA = -20°C to 70°C 4.179 TA = -40°C to 85°C 4.170 Precondition Safety Timer 4.221 4.230 ISET1 ACIN = VSYS, CHGLEV = GA -16% 50%ISET +16% VBAT = 3.5V, ACIN = GA, CHGLEV = VSYS RISET = 1.2kΩ -10% Smallest (450mA or ISET) -10% Smallest (90mA or +10% ISET) ACIN = VSYS, CHGLEV = VSYS 12%ISET ACIN = VSYS, CHGLEV = GA 12%ISET VBAT = 2.5V, ACIN = GA, CHGLEV = VSYS RISET = 1.2kΩ 12%ISET VBAT Voltage Rising +10% mA mA Smallest (90mA or 12%ISET) 2.75 2.85 2.95 100 V mV 10%ISET VBAT = 4.2V, ACIN = VSYS, CHGLEV = GA RISET = 1.2kΩ ACIN = GA, CHGLEV = VSYS VSET - VBAT, VBAT Falling V +10% -10% 10%ISET mA 5%ISET ACIN = GA, CHGLEV = GA Fast Charge Safety Timer 4.2 V ACIN = VSYS, CHGLEV = VSYS ACIN = VSYS, CHGLEV = VSYS Charge Restart Threshold mΩ Precondition Precondition Threshold Hysteresis VBAT Voltage Falling End-of-Charge Current Threshold 80 1.02 ACIN = GA, CHGLEV = GA Precondition Threshold Voltage µA Fast Charge ACIN = GA, CHGLEV = GA Precondition Charge Current 5 5%ISET 150 170 190 mV RBTR = 62 kΩ 3 hr TPRECONDITION RBTR = 62 kΩ 1 hr TNORMAL 2 THERMAL REGULATION Thermal Regulation Threshold 100 145 °C : ISET (mA) = KISET × 1V/(RISET (kΩ) +0.031) where KISET = 628 2: TPRECONDITION = TNORMAL / 3 (typ) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 41 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 TM ActivePath CHARGER TYPICAL PERFORMANCE CHARACTERISTICS (VCHG_IN = 5V, RDCCC = 20k, RISET = 680Ω, TA = 25°C, unless otherwise specified.) SYS Output Voltage vs. CHG_IN Voltage 4.15 SYS Voltage (V) 4.6 ACT8810-019 4.7 SYS Voltage (V) SYS Voltage vs. SYS Current 4.25 ACT8810-018 4.8 4.5 4.4 4.3 4.2 4.05 3.95 3.85 4.1 ISYS = 10mA 4.0 0 2 4 6 8 10 12 VBAT = 4.2V 3.75 0 14 1000 Charger Current vs. Battery Voltage (USB Mode) Charger Current vs. Battery Voltage (USB Mode) 450 Charger Current (mA) Charger Current (mA) 80 VBAT Falling VBAT Rising 20 CHG_IN = 5V ISYS = 0mA 100mA USB 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Battery Voltage Falling 400 350 Battery Voltage Rising 300 250 200 150 100 CHG_IN = 5V ISYS = 0mA 500mA USB 50 0 0.0 4.5 0.5 1.0 Battery Voltage (V) 3.0 3.5 4.0 4.5 Fast Charge Current vs. Ambient Temperature Fast Charger Current (mA) Charger Current (mA) 700 Battery Voltage Rising 500 2.5 400 300 200 100 0 ACT8810-023 Battery Voltage Falling 600 2.0 1200 ACT8810-022 ISYS = 0mA 800 1.5 Battery Voltage (V) Charger Current vs. Battery Voltage (AC Mode) 900 ACT8810-021 500 ACT8810-020 100 40 3000 SYS Current (mA) CHG_IN Voltage (V) 60 2000 ACIN, CHGLEV = 11 1000 800 ACIN, CHGLEV = 10 600 400 ACIN, CHGLEV = 01 200 ACIN, CHGLEV = 00 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -40 4.5 ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. 0 20 40 60 80 100 120 140 Ambient Temperature (°C) Battery Voltage (V) Innovative PowerTM -20 - 42 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 TM ActivePath CHARGER TYPICAL PERFORMANCE CHARACTERISTICS CONT’D (VCHG_IN = 5V, RDCCC = 20k, RISET = 680Ω, TA = 25°C, unless otherwise specified.) VAC Applied, CHGLEV = LOW VAC Applied, CHGLEV = HIGH CH2 ACT8810-025 ACT8810-024 CH1 CH1 CH2 CH3 CH3 100mA 450mA CH4 CH4 CH1: VUSB, 2.00V/div CH2: VCHG_IN, 2.00V/div CH3: IBAT, 500mA/div CH4: VVAC, 2.00V/div TIME: 400µs/div CH1: VUSB, 2.00V/div CH2: VCHG_IN, 2.00V/div CH3: IBAT, 500mA/div CH4: VVAC, 2.00V/div TIME: 400µs/div VAC Removed, CHGLEV = HIGH VAC Removed, CHGLEV = LOW CH2 ACT8810-027 ACT8810-026 CH1 CH1 CH2 CH3 CH3 100mA 450mA CH4 CH4 CH1: VUSB, 2.00V/div CH2: VCHG_IN, 2.00V/div CH3: IBAT, 500mA/div CH4: VVAC, 2.00V/div TIME: 400µs/div CH1: VUSB, 2.00V/div CH2: VCHG_IN, 2.00V/div CH3: IBAT, 500mA/div CH4: VVAC, 2.00V/div TIME: 400µs/div Battery Leakage Current vs. Battery Voltage Battery Leakage Current (µA) ACT8810-028 10 8 6 4 2 No CHG_IN CHGLEV = 0 0 0 1 2 3 4 5 Battery Voltage (V) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 43 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 TM ActivePath CHARGER FUNCTIONAL DESCRIPTION System Configuration Optimization General Description The ACT8810 incorporates Active-Semi's patentpending ActivePath architecture. ActivePath is a complete battery-charging and system powermanagement solution for portable hand-held equipment. This circuitry performs a variety of advanced battery-management functions, including automatic selection of the best available input supply, current-management to ensure system power availability, and a complete, high-accuracy (±0.5%), thermally regulated, full-featured singlecell linear Li+ charger with an integrated 12V power MOSFET. ActivePath Architecture Active-semi's patent-pending ActivePath architecture performs three important functions: 1) Input Protection, 2) System Configuration Optimization, and ActivePath circuitry automatically detects the state of the input supply, the battery, and the system, and automatically reconfigures itself to optimize the power system. If the input supply is present, ActivePath powers the system in parallel with charging the battery, so that system power and charge current can be independently managed to satisfy all system power requirements. This allows the battery to charge as quickly as possible, while ensuring that the total system current does not exceed the capability of the input supply. If the input supply is not present, however, then ActivePath automatically configures the system to draw power from the battery. Finally, if the input is present and the system current requirement exceeds the capability of the input supply, such as under momentary peak-power consumption conditions, ActivePath automatically configures itself for maximum power capability by drawing system power from both the battery and the input supply. 3) Battery-Management Battery Management Input Protection At the input of the ACT8810's ActivePath circuit is an internal, low-dropout linear regulator (LDO) that regulates the system voltage (VSYS). This LDO features a 12V power MOSFET, allowing the ActivePath system to withstand input voltages of up to 12V, and additionally includes a variety of other protection features, including current limit protection and input over-voltage protection. The ActivePath circuitry provides a very simple means of implementing a solution that safely operates within the current-capability limitations of a USB port while taking advantage of the high outputcurrent capability of an AC adapter, when available. ActivePath limits the total current drawn from the input supply to a value set by the ACIN input; when ACIN is driven to a logic-low ActivePath operates in “USB Mode” and limits the current to either 500mA (when CHGLEV is driven to a logic-high) or to 100mA (when CHGLEV is driven to a logic-low), and when ACIN is driven to a logic-high ActivePath operates in “AC-Mode” and limits the input current to 2A. In either case, ActivePath's DCCC circuitry, described below, allows the input overload protection to be adjusted to accommodate a wide range of input supplies. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. ActivePath includes a full-featured battery charger for single-cell Li-based batteries. This charger is a full-featured, intelligent, linear-mode, single-cell charger for Lithium-based cells, and was designed specifically to provide a complete charging solution with minimum system design effort. The core of the ActivePath's charger is a CC/CV (Constant-Current/Constant-Voltage), linear-mode charge controller. This controller incorporates current and voltage sense circuitry, an internal 80mΩ power MOSFET, a full-featured statemachine that implements charge control and safety features, and circuitry that eliminates the reverseblocking diode required by conventional charger designs. This charger also features thermal-regulation circuitry that protects it against excessive junction temperature, allowing the fastest possible charging times, as well as proprietary input protection circuitry that makes the charger robust against input voltage transients that can damage other chargers. The charge termination voltage is highly accurate (±0.5%), and features a selection of charge safety timeout periods that protect the system from operation with damaged cells. Other features include pin-programmable fast-charge current and - 44 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 TM ActivePath CHARGER FUNCTIONAL DESCRIPTION CONT’D two current-limited nSTAT0 and nSTAT1 outputs that can directly drive LED indicators or provide a logic-level status signal to the host microprocessor. Dynamic Charge Current Control (DCCC) The ACT8810's ActivePath Charger features Dynamic Charge Current Control (DCCC) circuitry, which continuously monitors the input supply to prevent input overload conditions. DCCC reduces the charge current when the VSYS voltage decreases to VDCCC and stops charging when VSYS drops below VDCCC by 1.5% (typical). The DCCC voltage threshold is programmed by connecting a resistor from DCCC to GA according to the following equation: VDCCC = 2 × (IDCCC × RDCCC) (2) Where RDCCC is the value of the external resistor, and IDCCC (100µA typical) is the value of the current sourced from DCCC. the current programmed by RISET, ISET (mA) = KISET × 1V/(RISET (kΩ) +0.031) where KISET = 628 when CHGLEV is driven to a logic high, and KISET = 314 when CHGLEV is driven to a logic low. When ACIN is driven to a logic-low, the circuitry operates in “USB-Mode”, which maximum charge current setting of CHGLEV is driven to a logic-high, or CHGLEV is driven to a logic-low. The ACT8810's charge current summarized in the table below: The ACT8810's ActivePath charger features a flexible charge current-programming scheme that combines the convenience of internal charge current programming with the flexibility of resistor based charge current programming. Current limits and charge current programming are managed as a function of the ACIN and CHGLEV pins, in combination with RISET, the resistance connected to the ISET pin. ACIN and CHGLEV Inputs ACIN is a logic input that configures the current-limit of ActivePath's linear regulator as well as that of the battery charger. ACIN features a precise 1.25V logic threshold, so that the input voltage detection threshold may be adjusted with a simple resistive voltage divider. This input also allows a simple, lowcost dual-input charger switch to be implemented with just a few, low-cost components. When ACIN is driven to a logic high, the ActivePath operates in “AC-Mode” and the charger charges at Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. ActivePath enforces a 500mA, if 100mA, if settings are Table 19: ACIN and CHGLEV Inputs Table ACIN CHGLEV Given the tolerances of the RDCCC and IDCCC ,the DCCC voltage threshold should be programmed to be no less than 3.3V to prevent triggering the UVLO, and to be no larger than 4.4V to prevent engaging DCCC prematurely. A 19.1k (1%), or 18.7k (1%) resistor for RDCCC is recommended. Charger Current Programming (3) CHARGE CURRENT ICHG (mA) PRECONDITION CHARGE CURRENT ICHG (mA) 0 0 90mA or ISET (Smallest one) 90mA or 12%ISET (Smallest one) 0 1 450mA or ISET (Smallest one) 12% × ISET 1 0 50% × ISET 12% × ISET 1 1 ISET 12% × ISET Note that the actual charging current may be limited to a current that is lower than the programmed fast charge current due to the ACT8810’s internal thermal regulation loop. See the Thermal Regulation and Protection section for more information. Battery Temperature Monitoring The ACT8810 continuously monitors the temperature of the battery pack by sensing the resistance of its thermistor, and suspends charging if the temperature of the battery pack exceeds the safety limits. In a typical application, shown in Figure 11, the TH pin is connected to the battery pack's thermistor input. The ACT8810 injects a 100µA current out of the TH pin into the thermistor, so that the thermistor resistance is monitored by comparing the voltage at TH to the internal VTHH and VTHL thresholds of 0.5V and 2.5V, respectively. When VTH > VTHL or VTH < VTHH charging and the charge timers are suspended. When VTH returns to the normal range, charging and the - 45 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 TM ActivePath CHARGER FUNCTIONAL DESCRIPTION CONT’D charge timers resume. The net resistance from TH to GA required to cross the threshold is given by: 100µA × RNOM × kHOT = 0.5V → RNOM × kHOT = 5kΩ 100µA × RNOM × kCOLD = 2.5V → RNOM × kCOLD = 25kΩ where RNOM is the nominal thermistor resistance at room temperature, and kHOT and kCOLD are the ratios of the thermistor's resistance at the desired hot and cold thresholds, respectively. Figure 11: Simple Configuration In each design example, we refer to the Vishay NTHS series of NTCs, and more specifically those which follow a "curve 2" characteristic. For more information on these NTCs, as well as access to the resistance/temperature characteristic tables referred to in the example, please refer to the Vishay website at http://www.vishay.com/thermistors. Simple Solution The ACT8810 was designed to accommodate most requirements with very little design effort, but also provides flexibility when additional control over a design is required. Initial thermistor selection is accomplished by choosing one that best meets the following requirements: RNOM = 5kΩ/kHOT, and RNOM = 25kΩ/kCOLD where kHOT and kCOLD for a given thermistor can be found on its characteristic tables. Taking a 0°C to 40°C application using a "curve 2" NTC for this example, from the characteristic tables one finds that kHOT and kCOLD are 0.5758 and 2.816, respectively, and the RNOM that most closely satisfies these requirements is therefore around 8.8kΩ. Selecting 10kΩ as the nearest standard value, calculate kCOLD and kHOT as: Design Procedure When designing with thermistors it is important to keep in mind that their nonlinear behavior typically allows one to directly control no more than one threshold at a time. As a result, the design procedure can change depending on which threshold is most critical for a given application. Most application requirements can be solved using one of three cases, kCOLD = VTHL/(ITH × RNOM) = 2.5V/(100µA × 10kΩ) = 2.5 kHOT = VTHH/(ITH × RNOM) = 0.5V/(100µA × 10kΩ) = 0.5 Identifying these values on the curve 2 characteristic tables indicates that the resulting operating temperature range is 2°C to 44°C, vs. the design goal of 0°C to 40°C. This example demonstrates that one can satisfy common operating temperature ranges with very little design effort. 1) Simple solution 2) Fix VTHH, accept the resulting VTHL 3) Fix VTHL, accept the resulting VTHH The ACT8810 was designed to achieve an operating temperature range that is suitable for most applications with very little design effort. The simple solution is often found to provide reasonable results and should always be used first, then the design procedure may proceed to one of the other solutions if necessary. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. Fix VTHH For demonstration purposes, supposing that we had selected the next closest standard thermistor value of 6.8kΩ in the example above, we would have obtained the following results: kCOLD = VTHL/(ITH × RNOM) = 2.5V/(100µA × 6.8kΩ) = 3.67 kHOT = VTHH/(ITH × RNOM) = 0.5V/(100µA × 6.8kΩ) = 0.74 which, according to the characteristic tables would have resulted in an operating temperature range of -6°C to 33°C vs. the design goal of 0°C to 40°C. - 46 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 TM ActivePath CHARGER FUNCTIONAL DESCRIPTION CONT’D In this case, one can add resistance in series with the thermistor to shift the range upwards, using the following equation: (VTHH/ITH) = kHOT(@40°C) × RNOM + R R = (VTHH/ITH) - kHOT(@40°C) × RNOM R = (2.5V/100µA) - 0.5758 × 6.8kΩ Finally, Fix VTHL Following the same example as above, the "unadjusted" results yield an operating temperature range of -6°C to 33°C vs. the design goal of 0°C to 40°C. In applications that favor VTHL over VTHH, however, one can control the voltage present at TH at low temperatures by connecting a resistor in parallel with ITH. The desired resistance can be found using the following equation: R = 5kΩ - 3.9kΩ = 1.1kΩ (ITH + (VCHG_IN - VTHL)/R) × kCOLD(@0°C) × RNOM = VTHL This result shows that adding 1.1kΩ in series with the thermistor sets the net resistance from TH to G to be 0.5V at 40°C, satisfying VTHH at the correct temperature. Adding this resistance, however, also impacts the lower temperature limit as follows: Rearranging yields VTHL/ITH = kCOLD(@TC) × RNOM + R kCOLD(@TC) = (VTHL/ITH) - R)/RNOM Finally, kCOLD(@TC) = (25kΩ - 1.1kΩ)/6.8kΩ = 3.51 Reviewing the characteristic curves, the lower threshold is found to move to -5°C, a change of only 1°C. As a result, the system satisfies the upper threshold of 40°C with an operating temperature range of -5°C to 40°C, vs. our design target of 0°C to 40°C. It is informative to highlight that due to the NTC behavior of the thermistor, the relative impact on the lower threshold is significantly smaller than the impact on the upper threshold. R = (VCHG_IN - VTHL)/(VTHL/(kCOLD(@0°C) × RNOM) - ITH) R = (5V - 2.5V)/(2.5V/(2.816 × 6.8kΩ) - 100µA) R = 82kΩ Adding 82kΩ in parallel with the current source increases the net current flowing into the thermistor, thus increasing the voltage at TH. Adding this resistance, however, also impacts the upper temperature limit: VTHH = (ITH + (VCHG_IN - VTHH)/R) × kHOT(@40°C) × RNOM Rearranging yields, kHOT(@TC) = VTHH/(RNOM × (ITH + (VCHG_IN - VTHH)/R)) kHOT(@TC) = 0.5V/(6.8kΩ × (100µA + (5V - 0.5V)/82kΩ)) = 0.4748 Reviewing the characteristic curves, the upper threshold is found to move to 45°C, a change of Figure 12: Figure 13: Fix VTHH Configuration Fix VTHL Configuration Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 47 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 TM ActivePath CHARGER FUNCTIONAL DESCRIPTION CONT’D about 14°C. Adding the parallel resistance has allowed us to achieve our desired lower threshold of 0°C with an operating temperature range of 0°C to 45°C, vs. our design target of 0°C to 40°C. Table 20: Charging Status Indication Table STATE Thermal Regulation The ACT8810's ActivePath charger features an internal thermal regulation loop that reduces the charging current as necessary to ensure that the die temperature does not rise beyond the thermal regulation threshold of 110°C. This feature protects the against excessive junction temperature and makes the device more accommodating to aggressive thermal designs. Note, however, that attention to good thermal designs is required to achieve the fastest possible charge time by maximizing charge current. In order to account for the reduced charge current resulting from operation in thermal regulation mode, the charge timeout periods are extended proportionally to the reduction in charge current. Charging Safety Timers The ACT8810 features a safety timer that is programmable via an external resistor (RBTR) connected from BTR to GA. The timeout period is calculated as show in Figure 14. If the ACT8810 detects that the charger remains in precondition for longer than the precondition time out period (which determined as tCHG/3), the ACT8810 turns off the charger and generate a FAULT to ensure prevent charging a bad cell. Charging Status Indication The ACT8810 provides two charge-status outputs, nSTAT0 and nSTAT1, which indicate charge status as defined in Table 20. nSTAT0 and nSTAT1 are open-drain outputs with internal 5mA current limits, which sink current when asserted and are high-Z otherwise, and are capable of directly driving LEDs without the need of current-limiting resistors or other external circuitry. To drive an LED, simply connect the LED between each pin and an appropriate supply (typically VSYS). For a logic level indication, simply connect a resistor from each output to a appropriate voltage supply. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. nSTAT0 nSTAT1 PRECONDITION ON ON FAST-CHARGE, TOP-OFF ON OFF END-OF-CHARGE OFF ON FAULT, SUSPEND OFF OFF Input Supply Detection The ACT8810's ActivePath charger is capable of withstanding voltages of up to 12V, protecting the system from fault conditions such as input voltage transients or application of an incorrect input supply. Although the ACT8810 can withstand a wide range of input voltages, valid input voltages for charging must be greater than the under-voltage lockout voltage (UVLO) and the over-voltage protection (OVP) thresholds, as described below. Under Voltage Lock Output (UVLO) Whenever the input voltage applied to CHG_IN falls below 3.0V (typ), an input under-voltage condition is detected and the charger is disabled. Once an input under-voltage condition is detected, the input must exceed the under-voltage threshold by at least 800mV for charging to resume. Over Voltage Protection (OVP) If the charger detects that the voltage applied to CHG_IN exceeds 6.5V (typ), an over-voltage condition is detected and the charger is disabled. Once an input over-voltage condition is detected, the input must fall below the OVP threshold by at least 350mV for charging to resume. Reverse Leakage Current The ACT8810's ActivePath charger includes internal circuitry that eliminates the need for blocking diodes, reducing solution size and cost as well as dropout voltage relative to conventional battery chargers. When the voltage at CHG_IN falls below VBAT, the charger automatically reconfigures its power switch to minimize current drain from the battery. - 48 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 TM ActivePath CHARGER Figure 14: TNORMAL vs. RBTR 275 TNORMAL (Min) 225 175 125 75 20 30 40 50 60 70 80 90 100 110 RBTR (kΩ) Figure 15: Typical Li+ Charge Profile and ACT8810 Charge States A: PRECONDITION State B: FAST-CHARGE State C: TOP-OFF State D: END-OF-CHARGE State Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 49 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 TM ActivePath CHARGER Figure 16: Charger State Diagram TEMP NOT OK ANY STATE BATTERY REMOVED OR (VCHGIN < VBAT) OR (VCHGIN < VCHGIN UVLO) OR (VCHGIN > VOVP) SUSPEND TEMP-FAULT BATTERY REPLACED AND (VCHGIN > VBAT) AND (VCHGIN > VCHGIN UVLO) AND (VCHGIN < VOVP) TEMP OK T > TPRECONDITION TIMEOUT-FAULT PRECONDITION VBAT > 2.85V T > TNORMAL FAST-CHARGE VBAT = VTERM TOP-OFF IBAT < IEOC OR T > TNORMAL END-OF-CHARGE Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 50 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 TM ActivePath CHARGER FUNCTIONAL DESCRIPTION CONT’D END-OF-CHARGE State Charger State-Machine PRECONDITION State A new charging cycle begins with the PRECONDITION state, and operation continues in this state until VBAT exceeds the Precondition Threshold Voltage of 2.85V (typ). When operating in PRECONDITION state, the cell is charged at a reduced current, 12% of the programmed maximum fast-charge constant current, ISET. Once VBAT reaches the Precondition Threshold Voltage the state machine jumps to the FAST-CHARGE state. If VBAT does not reach the Precondition Threshold Voltage before the Precondition Timeout period tPRECONDITION expires, then a damaged cell is detected and the state machine jumps to the TIMEOUT-FAULT State. For the Precondition Timeout period, see the Charging Safety Timers section for more information. FAST-CHARGE State In FAST-CHARGE state, the ACT8810 charges at the current programmed by RISET (see the Current Limits and Charge Current Programming section for more information). During a normal charge cycle fast-charge continues in CC mode until VBAT reaches the charge termination voltage (VTERM), at which point the ACT8810 jumps to the TOP-OFF state. If VBAT does not reach VTERM before the total time out period expires then state-machine will jump to the END-OF-CHARGE (EOC) state and will reinitiate a new charge cycle after 2-4ms “relax”. TOP-OFF State In the TOP-OFF state, the cell charges in constant voltage (CV) mode. In CV mode operation, the charger regulates its output voltage to the 4.20V (typ) charge termination voltage, and the charge current is naturally reduced as the cell approaches full charge. Charging continues until the charge current drops to END-OF-CHARGE current threshold, at which point the state machine jumps to the END-OF-CHARGE (EOC) state. If the statemachine does not jump out of the TOP-OFF state before the Total-Charge Timeout period expires, the state machine jumps to the EOC state and will reinitiate a new charge cycle if VBAT falls below termination voltage 170mv (typ). For more information about the charge safety timers, see the Charging Safety Times section. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. In the End-of-Charge (EOC) state, the ACT8810 presents a high-impedance to the battery, allowing the cell to “relax” and minimizes battery leakage current. The ACT8810 continues to monitor the cell voltage, so that it can re-initiate charging cycles when VBAT drops to 170mV (typ) below the Charge Termination Voltage. SUSPEND State In the SUSPEND state, ACT8810 disables the charger but keeps other circuiting functional. Upon exiting the SUSPEND State, the charge timer is reset and the state machine jumps to PRECONDITION state. CHG_IN Bypass Capacitor Selection CHG_IN is the power input for the ACT8810 battery charger. The battery charger is automatically enabled whenever a valid voltage is present on CHG_IN. In most applications, CHG_IN is connected to either a wall adapter or USB port. Under normal operation, the input of the charger will often be “hot-plugged” directly to a powered USB or wall adapter cable, and supply voltage ringing and overshoot may appear at the CHG_IN pin. In most applications a high quality capacitor connected from CHG_IN to GA, placed as close as possible to the IC, is sufficient to absorb the energy. Wall-adapter powered applications provide flexibility in input capacitor selection, but the USB specification presents limitations to input capacitance selection. In order to meet both the USB 2.0 and USB OTG (On The Go) specifications while avoiding USB supply under-voltage conditions resulting from the current limit slew rate (100mA/µS) limitations of the USB bus, the CHG_IN bypass capacitance value must to be between 4.7µF and 10µF for the ACT8810. Ceramic capacitors are often preferred for bypassing applications due to their small size and good surge current ratings, but care must be taken in applications that can encounter hot plug conditions as their very low ESR, in combination with the inductance of the cable, can create a highQ filter that induces excessive ringing at the CHG_IN pin. This ringing can couple to the output and be mistaken as loop instability, or the ringing may be large enough to damage the input itself. - 51 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 TM ActivePath CHARGER FUNCTIONAL DESCRIPTION CONT’D Although the CHG_IN pin is designed for maximum robustness and an absolute maximum voltage rating of 14V for transients, attention must be given to bypass techniques to ensure safe operation. As a result, design of the CHG_IN bypass must take care to “de-Q” the filter. This can be accomplished by connecting a 1Ω resistor in series with a ceramic capacitor (as shown in Figure 17), or by using a tantalum or electrolytic capacitor to utilize it’s higher ESR to dampen the ringing. For additional protection in extreme situations, Zener diodes with 12V clamp voltages may also be used. In any case, it is always critical to evaluate voltage transients at the ACT8810 CHG_IN pin with an oscilloscope to ensure safe operation. Figure 17: CHG_IN Bypass Options for USB or Wall Adaptor Supplies Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 52 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ACT8810 Rev 9, 15-Nov-12 PACKAGE OUTLINE AND DIMENSIONS PACKAGE OUTLINE TQFN55-40 PACKAGE OUTLINE AND DIMENSIONS SYMBOL A A1 DIMENSION IN MILLIMETERS DIMENSION IN INCHES MIN MAX MIN MAX 0.700 0.800 0.028 0.031 0.200 REF 0.008 REF A2 0.000 0.050 0.000 0.002 b 0.150 0.250 0.006 0.010 D 4.900 5.100 0.193 0.201 E 4.900 5.100 0.193 0.201 D2 3.450 3.750 0.136 0.148 E2 3.450 3.750 0.136 0.148 e L R 0.400 BSC 0.300 0.500 0.300 0.016 BSC 0.012 0.020 0.012 Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of the use of any product or circuit described in this datasheet, nor does it convey any patent license. Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact [email protected] or visit http://www.active-semi.com. is a registered trademark of Active-Semi. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. - 53 - www.active-semi.com Copyright © 2012 Active-Semi, Inc.