HM62V16256B Series 4 M SRAM (256-kword × 16-bit) ADE-203-933C (Z) Rev. 2.0 Oct. 14, 1999 Description The Hitachi HM62V16256B Series is 4-Mbit static RAM organized 262,144-word × 16-bit. HM62V16256B Series has realized higher density, higher performance and low power consumption by employing Hi-CMOS process technology. It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in standard 44-pin plastic TSOPII. Features • • • • • • • Single 3.0 V supply: 2.7 V to 3.6 V Fast access time: 70 ns/85 ns (max) Power dissipation: Active: 9 mW (typ) Standby: 3 µW (typ) Completely static memory. No clock or timing strobe required Equal access and cycle times Common data input and output. Three state output Battery backup operation. 2 chip selection for battery backup HM62V16256B Series Ordering Information Type No. Access time Package HM62V16256BLTT-7 HM62V16256BLTT-8 70 ns 85 ns 400-mil 44-pin plastic TSOPII (normal-bend type) (TTP-44DB) HM62V16256BLTT-7SL HM62V16256BLTT-8SL 70 ns 85 ns 2 HM62V16256B Series Pin Arrangement 44-pin TSOP A4 A3 A2 A1 A0 CS1 I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 CS2 A8 A9 A10 A11 A12 (Top view) Pin Description Pin name Function A0 to A17 Address input I/O0 to I/O15 Data input/output CS1 Chip select 1 CS2 Chip select 2 WE Write enable OE Output enable LB Lower byte select UB Upper byte select VCC Power supply VSS Ground 3 HM62V16256B Series Block Diagram LSB A4 V CC A3 V SS A15 A14 A16 A1 Row decoder • • • • • Memory matrix 2,048 x 2,048 A2 A17 MSB A0 A13 I/O0 Column I/O • • Input data control Column decoder I/O15 LSB A7 A6 A5 A8 A9A10A11A12MSB • • CS2 CS1 LB UB WE OE 4 Control logic • • HM62V16256B Series Operation Table CS1 CS2 WE OE UB LB I/O0 to I/O7 I/O8 to I/O15 Operation H × × × × × High-Z High-Z Standby × L × × × × High-Z High-Z Standby × × × × H H High-Z High-Z Standby L H H L L L Dout Dout Read L H H L H L Dout High-Z Lower byte read L H H L L H High-Z Dout Upper byte read L H L × L L Din Din Write L H L × H L Din High-Z Lower byte write L H L × L H High-Z Din Upper byte write L H H H × × High-Z High-Z Output disable Note: H: V IH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Symbol Value Power supply voltage relative to V SS VCC –0.5 to + 4.6 Unit V 1 2 Terminal voltage on any pin relative to V SS VT –0.5* to V CC + 0.3* V Power dissipation PT 1.0 W Storage temperature range Tstg –55 to +125 °C Storage temperature range under bias Tbias –10 to +85 °C Notes: 1. VT min: –3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +4.6 V. DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 2.7 3.0 3.6 V VSS 0 0 0 V Input high voltage VIH 2.0 — VCC + 0.3 V Input low voltage VIL –0.3 — 0.6 V Ambient temperature range Ta 0 — 70 °C Note: Note 1 1. VIL min: –3.0 V for pulse half-width ≤ 30 ns. 5 HM62V16256B Series DC Characteristics Parameter Symbol Min Typ* 1 Max Unit Test conditions Input leakage current |ILI| — — 1 µA Vin = VSS to V CC Output leakage current |ILO | — — 1 µA CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL, or LB = UB =VIH VI/O = VSS to V CC Operating current I CC — — 20 mA CS1 = VIL, CS2 = VIH, Others = VIH/VIL, I I/O = 0 mA Average HM62V16256B-7 I CC1 operating current — — 70 mA Min. cycle, duty = 100%, I I/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/VIL HM62V16256B-8 I CC1 — — 65 mA I CC2 — 3 15 mA Cycle time = 1 µs, duty = 100%, I I/O = 0 mA, CS1 ≤ 0.2 V, CS2 ≥ V CC – 0.2 V VIH ≥ V CC – 0.2 V, VIL ≤ 0.2 V Standby current Standby current Output high voltage Output low voltage I SB — — 0.3 mA CS2 = VIL 2 — 1 40 µA 0 V ≤ Vin (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS1 ≥ V CC – 0.2 V, CS2 ≥ V CC – 0.2 V I SB1*3 — 1 20 µA VOH 2.4 — — V I OH = –1 mA VCC – 0.2 — — V I OH = –100 µA — — 0.4 V I OL = 2 mA — — 0.2 V I OL = 100 µA I SB1* VOL Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed. 2. This characteristic is guaranteed only for L-version. 3. This characteristic is guaranteed only for L-SL version. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Symbol Min Typ Max Unit Test conditions Note Input capacitance Cin — — 8 pF Vin = 0 V 1 Input/output capacitance CI/O — — 10 pF VI/O = 0 V 1 Note: 6 1. This parameter is sampled and not 100% tested. HM62V16256B Series AC Characteristics (Ta = 0 to +70°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.) Test Conditions • • • • • Input pulse levels: VIL = 0.4 V, VIH = 2.2 V Input rise and fall time: 5 ns Input timing reference levels: 1.4 V Output timing reference levels: 1.4 V Output load: 1 TTL + 30 pF (HM62V16256B-7) (Including scope and jig) 1 TTL + 100 pF (HM62V16256B-8) (Including scope and jig) Read Cycle HM62V16256B -7 -8 Parameter Symbol Min Max Min Max Unit Notes Read cycle time t RC 70 — 85 — ns Address access time t AA — 70 — 85 ns Chip select access time t ACS1 — 70 — 85 ns t ACS2 — 70 — 85 ns Output enable to output valid t OE — 40 — 45 ns Output hold from address change t OH 10 — 10 — ns LB, UB access time t BA — 70 — 85 ns Chip select to output in low-Z t CLZ1 10 — 10 — ns 2, 3 t CLZ2 10 — 10 — ns 2, 3 LB, UB enable to low-z t BLZ 5 — 5 — ns 2, 3 Output enable to output in low-Z t OLZ 5 — 5 — ns 2, 3 Chip deselect to output in high-Z t CHZ1 0 25 0 25 ns 1, 2, 3 t CHZ2 0 25 0 25 ns 1, 2, 3 LB, UB disable to high-Z t BHZ 0 25 0 25 ns 1, 2, 3 Output disable to output in high-Z t OHZ 0 25 0 25 ns 1, 2, 3 7 HM62V16256B Series Write Cycle HM62V16256B -7 -8 Parameter Symbol Min Max Min Max Unit Write cycle time t WC 70 — 85 — ns Address valid to end of write t AW 60 — 70 — ns Chip selection to end of write t CW 60 — 70 — ns 5 Write pulse width t WP 50 — 55 — ns 4 LB, UB valid to end of write t BW 55 — 70 — ns Address setup time t AS 0 — 0 — ns 6 Write recovery time t WR 0 — 0 — ns 7 Data to write time overlap t DW 30 — 35 — ns Data hold from write time t DH 0 — 0 — ns Output active from end of write t OW 5 — 5 — ns 2 Output disable to output in High-Z t OHZ 0 25 0 25 ns 1, 2 Write to output in high-Z 0 25 0 25 ns 1, 2 t WHZ Notes Notes: 1. t CHZ, tOHZ , t WHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given device and from device to device. 4. A write occures during the overlap of a low CS1, a high CS2, a low WE and a low LB or a low UB. A write begins at the latest transition among CS1 going low, CS2 going high, WE going low and LB going low or UB going low. A write ends at the earliest transition among CS1 going high, CS2 going low, WE going high and LB going high or UB going high. tWP is measured from the beginning of write to the end of write. 5. t CW is measured from the later of CS1 going low or CS2 going high to the end of write. 6. t AS is measured from the address valid to the beginning of write. 7. t WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle. 8 HM62V16256B Series Timing Waveform Read Cycle t RC Address Valid address tAA tACS1 CS1 tCLZ1*2, 3 CS2 tCHZ1*1, 2, 3 tACS2 tCLZ2*2, 3 tCHZ2*1, 2, 3 tBHZ*1, 2, 3 tBA LB, UB tBLZ*2, 3 tOHZ*1, 2, 3 tOE OE tOLZ*2, 3 Dout High impedance tOH Valid data 9 HM62V16256B Series Write Cycle (1) (WE Clock) tWC Valid address Address tWR*7 tCW*5 CS1 tCW*5 CS2 tBW LB, UB tAW tWP*4 WE tAS*6 tDW tDH Valid data Din tWHZ*1, 2 tOW*2 High impedance Dout 10 HM62V16256B Series Write Cycle (2) (CS Clock, OE = VIH) tWC Valid address Address tAW tAS*6 tWR*7 tCW*5 CS1 tCW*5 CS2 tBW LB, UB tWP*4 WE tDW tDH Valid data Din High impedance Dout 11 HM62V16256B Series Write Cycle (3) (LB, UB Clock, OE = VIH) tWC Valid address Address tAW tCW*5 tWR*7 CS1 tCW*5 CS2 tAS*6 tBW LB, UB tWP*4 WE tDW Valid data Din High impedance Dout 12 tDH HM62V16256B Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) Parameter Symbol Min Typ* 4 Max Unit Test conditions*3 VCC for data retention VDR 2.0 — — V Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ V CC – 0.2 V CS1 ≥ V CC – 0.2 V or (3) LB = UB ≥ V CC – 0.2 V CS2 ≥ V CC – 0.2 V CS1 ≤ 0.2 V Data retention current I CCDR*1 — 0.8 20 µA VCC = 3.0 V, Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ V CC – 0.2 V, CS1 ≥ V CC – 0.2 V or (3) LB = UB ≥ V CC – 0.2 V CS2 ≥ V CC – 0.2 V CS1 ≤ 0.2 V I CCDR*2 — 0.8 10 µA Chip deselect to data retention time t CDR 0 — — ns Operation recovery time tR t RC* 5 — — ns See retention waveform Notes: 1. This characteristic is guaranteed only for L-version, 10 µA max. at Ta = 0 to +40°C. 2. This characteristic is guaranteed only for L-SL version, 5 µA max. at Ta = 0 to +40°C. 3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, LB, UB buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, LB, UB, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 ≥ V CC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, LB, UB, I/O) can be in the high impedance state. 4. Typical values are at VCC = 3.0 V, Ta = +25˚C and not guaranteed. 5. t RC = read cycle time. 13 HM62V16256B Series Low V CC Data Retention Timing Waveform (1) (CS1 Controlled) t CDR Data retention mode tR V CC 2.7 V V DR 2.0 V CS1 0V CS1 ≥ VCC – 0.2 V Low V CC Data Retention Timing Waveform (2) (CS2 Controlled) t CDR Data retention mode tR V CC 2.7 V CS2 V DR 0.4 V 0 V < CS2 < 0.2 V 0V Low V CC Data Retention Timing Waveform (3) (LB, UB Controlled) t CDR Data retention mode V CC 2.7 V V DR 2.0 V LB, UB 0V 14 LB, UB ≥ VCC – 0.2 V tR HM62V16256B Series Package Dimensions HM62V16256BLTT Series (TTP-44DB) Unit: mm 18.41 18.81 Max 23 10.16 44 1 0.80 22 0.80 *0.30 ± 0.10 0.25 ± 0.05 0.13 M 11.76 ± 0.20 1.005 Max *Dimension including the plating thickness Base material dimension 0.13 ± 0.05 0.10 *0.17 ± 0.05 0.125 ± 0.04 1.20 Max 0° – 5° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-44DB — — 0.43 g 15 HM62V16256B Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 16