Dual Bootstrapped, 12 V MOSFET Driver with Output Disable ADP3120A FEATURES GENERAL DESCRIPTION All-in-one synchronous buck driver Bootstrapped high-side drive One PWM signal generates both drives Anticross conduction protection circuitry OD for disabling the driver outputs Meets CPU VR requirement when used with Analog Devices Flex -Mode™ 1 controller The ADP3120A is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, the two switches in a nonisolated synchronous buck power converter. Each driver is capable of driving a 3000 pF load with a 45 ns propagation delay and a 25 ns transition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. The ADP3120A includes overlapping drive protection to prevent shoot-through current in the external MOSFETs. APPLICATIONS Multiphase desktop CPU supplies Single-supply synchronous buck converters The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown. The ADP3120A is specified over the commercial temperature range of 0°C to 85°C and is available in 8-lead SOIC_N and 8-lead LFCSP_VD packages. 1 Flex-Mode is protected by U.S. Patent 6683441; other patents pending. FUNCTIONAL BLOCK DIAGRAM 12V D1 VCC 4 BST ADP3120A 1 LATCH R1 R2 Q S IN 2 CBST2 CBST1 DRVH RG 8 Q1 DELAY RBST TO INDUCTOR SW 7 CMP VCC 6 CMP CONTROL LOGIC DRVL Q2 5 PGND DELAY 6 OD 3 05812-001 1V Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADP3120A TABLE OF CONTENTS Features .............................................................................................. 1 Low-Side Driver ............................................................................9 Applications....................................................................................... 1 High-Side Driver ...........................................................................9 General Description ......................................................................... 1 Overlap Protection Circuit...........................................................9 Functional Block Diagram .............................................................. 1 Application Information................................................................ 10 Revision History ............................................................................... 2 Supply Capacitor Selection ....................................................... 10 Specifications..................................................................................... 3 Bootstrap Circuit........................................................................ 10 Absolute Maximum Ratings............................................................ 4 MOSFET Selection..................................................................... 10 ESD Caution.................................................................................. 4 High-Side (Control) MOSFETs................................................ 10 Pin Configurations and Function Descriptions ........................... 5 Low-Side (Synchronous) MOSFETs ........................................ 11 Timing Characteristics..................................................................... 6 PC Board Layout Considerations............................................. 11 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 13 Theory of Operation ........................................................................ 9 Ordering Guide .......................................................................... 13 REVISION HISTORY 3/06—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADP3120A SPECIFICATIONS VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted. 1 Table 1. Parameter DIGITAL INPUTS (PWM, OD) Input Voltage High Input Voltage Low Input Current Hysteresis HIGH-SIDE DRIVER Output Resistance, Sourcing Current Symbol Propagation Delay Times −1 90 trDRVH tfDRVH tpdhDRVH tpdlDRVH t pdl OD tpdh OD SW Pull-Down Resistance LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times trDRVL tfDRVL tpdhDRVL tpdlDRVL t pdl OD tpdh Timeout Delay SUPPLY Supply Voltage Range Supply Current UVLO Voltage Hysteresis 1 Min Typ Max Unit 0.8 +1 V V μA mV 2.0 Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Conditions VCC ISYS OD BST − SW = 12 V ; TA = 25°C BST − SW = 12 V ; TA = 0°C to 85°C BST – SW = 12 V; TA = 25°C BST − SW = 12 V; TA = 0°C to 85°C BST – SW = 0 V BST – SW = 12 V, CLOAD = 3 nF, see Figure 5 BST – SW = 12 V, CLOAD = 3 nF, see Figure 5 BST – SW = 12 V, CLOAD = 3 nF, 25°C ≤ TA ≤ 85°C, see Figure 5 BST – SW = 12 V, CLOAD = 3 nF, see Figure 5 See Figure 4 250 1.4 10 25 20 45 40 30 70 Ω Ω Ω Ω kΩ ns ns ns 25 20 35 35 ns ns See Figure 4 40 55 ns SW to PGND 10 2.5 32 TA = 25°C TA = 0°C to 85°C TA = 25°C TA = 0°C to 85°C VCC = PGND CLOAD = 3 nF, see Figure 5 CLOAD = 3 nF, see Figure 5 CLOAD = 3 nF, see Figure 5 CLOAD = 3 nF, see Figure 5 See Figure 4 2.4 1.4 10 20 16 12 30 20 3.3 3.9 1.8 2.6 kΩ 3.3 3.9 1.8 2.6 35 30 35 45 35 Ω Ω Ω Ω kΩ ns ns ns ns ns See Figure 4 110 190 ns SW = 5 V SW = PGND 110 95 190 150 ns ns 4.15 BST = 12 V, IN = 0 V VCC rising 2 1.5 350 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. Rev. 0 | Page 3 of 16 13.2 5 3.0 V mA V mV ADP3120A ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC BST DC <200 ns BST to SW SW DC <200 ns DRVH DC <200 ns DRVL DC <200 ns IN, OD θJA, SOIC_N 2-Layer Board 4-Layer Board θJA, LFCSP_VD1 4-Layer Board Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating −0.3 V to +15 V −0.3 V to VCC + 15 V −0.3 V to +35 V −0.3 V to +15 V Unless otherwise specified, all voltages are referenced to PGND. −5 V to +15 V −10 V to +25 V SW − 0.3 V to BST + 0.3 V SW − 2 V to BST + 0.3 V −0.3 V to VCC + 0.3 V −2 V to VCC + 0.3 V −0.3 V to +6.5 V 123°C/W 90°C/W 50°C/W 0°C to 85°C 0°C to 150°C −65°C to +150°C 300°C 215°C 260°C For LFCSP_VD, θJA is measured per JEDEC STD with exposed pad soldered to PCB. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 4 of 16 ADP3120A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADP3120A OD 3 TOP VIEW (Not to Scale) VCC 4 8 DRVH 7 SW 6 5 PGND DRVL BST 1 IN 2 OD 3 VCC 4 Figure 2. 8-Lead SOIC_N Pin Configuration PIN 1 INDICATOR ADP3120A TOP VIEW (Not to Scale) 8 DRVH 7 SW 6 PGND 5 DRVL 05812-003 IN 2 05812-002 BST 1 Figure 3. 8-Lead LFCSP_VD Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic BST 2 IN 3 4 5 6 7 OD VCC DRVL PGND SW 8 DRVH Description Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high-side MOSFET while it is switching. Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling this pin low turns on the low-side driver; pulling it high turns on the high-side driver. Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low. Input Supply. This pin should be bypassed to PGND with an ~1 μF ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. Power Ground. This pin should be closely connected to the source of the lower MOSFET. Switch Node Connection. This pin is connected to the buck switching node, close to the upper MOSFET source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent the lower MOSFET from turning on until the voltage is below ~1 V. Buck Drive. Output drive for the upper (buck) MOSFET. Rev. 0 | Page 5 of 16 ADP3120A TIMING CHARACTERISTICS Timing is referenced to the 90% and 10% points, unless otherwise noted. OD tpdlOD tpdhOD 05812-004 90% DRVH OR DRVL 10% Figure 4. Output Disable Timing Diagram IN tpdlDRVL tfDRVL tpdlDRVH trDRVL DRVL tfDRVH tpdhDRVH DRVH-SW trDRVH VTH VTH 1V Figure 5. Timing Diagram Rev. 0 | Page 6 of 16 05812-005 tpdhDRVL SW ADP3120A TYPICAL PERFORMANCE CHARACTERISTICS 24 VCC = 12V CLOAD = 3nF IN DRVH FALL TIME (ns) 22 DRVL 20 18 DRVL 16 14 05812-006 0 25 50 75 100 125 JUNCTION TEMPERATURE (°C) Figure 6. DRVH Rise and DRVL Fall Times CLOAD = 6 nF for DRVL, CLOAD = 2 nF for DRVH 05812-009 DRVH Figure 9. DRVH and DRVL Fall Times vs. Temperature 40 35 TA = 25°C VCC = 12V DRVH IN RISE TIME (ns) 30 DRVL 25 DRVL 20 15 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LOAD CAPACITANCE (nF) 05812-010 05812-007 10 DRVH Figure 10. DRVH and DRVL Rise Times vs. Load Capacitance Figure 7. DRVH Fall and DRVL Rise Times CLOAD = 6 nF for DRVL, CLOAD = 2 nF for DRVH 35 35 VCC = 12V TA = 25°C VCC = 12V CLOAD = 3nF 30 DRVH 30 FALL TIME (ns) 25 DRVL 25 DRVL 20 15 20 15 0 25 50 75 100 JUNCTION TEMPERATURE (°C) 125 5 2.0 2.5 3.0 3.5 4.0 4.5 LOAD CAPACITANCE (nF) Figure 11. DRVH and DRVL Fall Times vs. Load Capacitance Figure 8. DRVH and DRVL Rise Times vs. Temperature Rev. 0 | Page 7 of 16 5.0 05812-011 10 05812-008 RISE TIME (ns) DRVH ADP3120A 60 12 TA = 25°C CLOAD = 3nF 11 10 DRVL OUTPUT VOLTAGE (V) SUPPLY CURRENT (mA) TA= 25°C VCC = 12V CLOAD = 3nF 45 30 15 9 8 7 6 5 4 3 2 200 400 600 800 1000 1200 1400 FREQUENCY (kHz) Figure 12. Supply Current vs. Frequency 12 11 10 9 50 75 100 JUNCTION TEMPERATURE (°C) 125 05812-013 SUPPLY CURRENT (mA) VCC = 12V CLOAD = 3nF fIN = 250kHz 25 0 1 2 3 4 5 6 7 8 9 10 11 VCC (V) Figure 14. DRVL Output Voltage vs. Supply Voltage 13 0 0 Figure 13. Supply Current vs. Temperature Rev. 0 | Page 8 of 16 12 05812-014 0 05812-012 1 0 ADP3120A THEORY OF OPERATION The ADP3120A is optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each driver is capable of driving a 3 nF load at speeds up to 500 kHz. A functional block diagram of ADP3120A is shown in Figure 1. LOW-SIDE DRIVER The low-side driver is designed to drive a ground referenced N-channel MOSFET. The bias to the low-side driver is internally connected to the VCC supply and PGND. When the driver is enabled, the driver output is 180° out of phase with the PWM input. When the ADP3120A is disabled, the low-side gate is held low. HIGH-SIDE DRIVER The high-side driver is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by an external bootstrap supply circuit that is connected between the BST and SW pins. The bootstrap circuit comprises Diode D1 and Bootstrap Capacitor CBST1. CBST2 and RBST are included to reduce the highside gate drive voltage and to limit the switch node slew rate (called a Boot-Snap™ circuit—see the Application Information section for more details). When the ADP3120A starts up, the SW pin is at ground, so the bootstrap capacitor charges up to VCC through D1. When the PWM input goes high, the high-side driver begins to turn on the high-side MOSFET, Q1, by pulling charge out of CBST1 and CBST2. As Q1 turns on, the SW pin rises up to VIN and forces the BST pin to VIN + VC (BST). This holds Q1 on because enough gate-to-source voltage is provided. To complete the cycle, Q1 is switched off by pulling the gate down to the voltage at the SW pin. When the low-side MOSFET, Q2, turns on, the SW pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again. OVERLAP PROTECTION CIRCUIT The overlap protection circuit prevents both of the main power switches, Q1 and Q2, from being on at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on/off transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from the Q1 turn-off to the Q2 turn-on, and by internally setting the delay from the Q2 turn-off to the Q1 turn-on. To prevent the overlap of the gate drives during the Q1 turn-off and the Q2 turn-on, the overlap circuit monitors the voltage at the SW pin. When the PWM input signal goes low, Q1 begins to turn off (after propagation delay). Before Q2 can turn on, the overlap protection circuit makes sure that SW has first gone high and then waits for the voltage at the SW pin to fall from VIN to 1 V. Once the voltage on the SW pin falls to 1 V, Q2 begins turn-on. If the SW pin has not gone high first, the Q2 turn-on is delayed by a fixed 150 ns. By waiting for the voltage on the SW pin to reach 1 V or for the fixed delay time, the overlap protection circuit ensures that Q1 is off before Q2 turns on, regardless of variations in temperature, supply voltage, input pulse width, gate charge, and drive current. If SW does not go below 1 V after 190 ns, DRVL turns on. This can occur if the current flowing in the output inductor is negative and flows through the high-side MOSFET body diode. The output of the high-side driver is in phase with the PWM input. When the driver is disabled, the high-side gate is held low. Rev. 0 | Page 9 of 16 ADP3120A APPLICATION INFORMATION SUPPLY CAPACITOR SELECTION For the supply input (VCC) of the ADP3120A, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents that are drawn. Use a 4.7 μF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. Keep the ceramic capacitor as close as possible to the ADP3120A. BOOTSTRAP CIRCUIT The bootstrap circuit uses a charge storage capacitor (CBST) and a diode, as shown in Figure 1. These components can be selected after the high-side MOSFET is chosen. The bootstrap capacitor must have a voltage rating that can handle twice the maximum supply voltage. A minimum 50 V rating is recommended. The capacitor values are determined by Q (1) C BST1 + C BST2 = 10 × GATE VGATE C BST1 VGATE = C BST1 + C BST2 VCC − VD (2) where: QGATE is the total gate charge of the high-side MOSFET at VGATE. VGATE is the desired gate drive voltage (usually in the range of 5 V to 10 V, 7 V being typical). VD is the voltage drop across D1. Rearranging Equation 1 and Equation 2 to solve for CBST1 yields Q C BST1 = 10 × GATE VCC − VD CBST2 can then be found by rearranging Equation 1 C BST2 = 10 × QGATE − C BST 1 VGATE For example, an NTD60N02 has a total gate charge of about 12 nC at VGATE = 7 V. Using VCC = 12 V and VD = 1 V, then CBST1 = 12 nF and CBST2 = 6.8 nF. Good quality ceramic capacitors should be used. RBST is used to limit slew rate and minimize ringing at the switch node. It also provides peak current limiting through D1. An RBST value of 1.5 Ω to 2.2 Ω is a good choice. The resistor needs to handle at least 250 mW due to the peak currents that flow through it. A small signal diode can be used for the bootstrap diode due to the ample gate drive voltage supplied by VCC. The bootstrap diode must have a minimum 15 V rating to withstand the maximum supply voltage. The average forward current can be estimated by I F ( AVG ) = QGATE × f MAX (3) where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be calculated by I F ( PEAK ) = VCC − VD RBST (4) MOSFET SELECTION When interfacing the ADP3120A to external MOSFETs, the designer should consider ways to make a robust design that minimizes stresses on both the driver and the MOSFETs. These stresses include exceeding the short time duration voltage ratings on the driver pins as well as the external MOSFET. It is also highly recommended to use the Boot-Snap circuit to improve the interaction of the driver with the characteristics of the MOSFETs. If a simple bootstrap arrangement is used, make sure to include a proper snubber network on the SW node. HIGH-SIDE (CONTROL) MOSFETS A high-side, high speed MOSFET is usually selected to minimize switching losses (see the ADP3186 or ADP3188 data sheet for Flex-Mode controller details). This typically implies a low gate resistance and low input capacitance/charge device. Yet, a significant source lead inductance can also exist that depends mainly on the MOSFET package; it is best to contact the MOSFET vendor for this information. The ADP3120A DRVH output impedance and the input resistance of the MOSFETs determine the rate of charge delivery to the internal capacitance of the gate. This determines the speed at which the MOSFETs turn on and off. However, because of potentially large currents flowing in the MOSFETs at the on and off times (this current is usually larger at turn-off due to ramping up of the output current in the output inductor), the source lead inductance generates a significant voltage when the high-side MOSFETs switch off. This creates a significant drainsource voltage spike across the internal die of the MOSFETs and can lead to a catastrophic avalanche. The mechanisms involved in this avalanche condition are referenced in literature from the MOSFET suppliers. Rev. 0 | Page 10 of 16 ADP3120A I MAX = I DC ( per phase ) + (VCC − VOUT ) × D MAX f MAX × LOUT (5) where: DMAX is determined for the VR controller being used with the driver. This current is divided roughly equally between MOSFETs if more than one is used (assume a worst-case mismatch of 30% for design margin). LOUT is the output inductor value. When producing the design, there is no exact method for calculating the dV/dt due to the parasitic effects in the external MOSFETs as well as the PCB. However, it can be measured to determine if it is safe. If it appears that the dV/dt is too fast, an optional gate resistor can be added between DRVH and the high-side MOSFETs. This resistor slows down the dV/dt, but it increases the switching losses in the high-side MOSFETs. The ADP3120A is optimally designed with an internal drive impedance that works with most MOSFETs to switch them efficiently, yet minimizes dV/dt. However, some high speed MOSFETs can require this external gate resistor depending on the currents being switched in the MOSFET. LOW-SIDE (SYNCHRONOUS) MOSFETS The low-side MOSFETs are usually selected to have a low on resistance to minimize conduction losses. This usually implies a large input gate capacitance and gate charge. The first concern is to make sure the power delivery from the ADP3120A DRVL does not exceed the thermal rating of the driver (see the ADP3186, ADP3188, or ADP3189 data sheets for Flex-Mode controller details). monitored to go below one sixth of VCC; then, a delay is added. Due to the Miller capacitance and internal delays of the lowside MOSFET gate, ensure that the Miller-to-input capacitance ratio is low enough, and that the low-side MOSFET internal delays are not so large as to allow accidental turn-on of the lowside when the high-side turns on. Contact ADI for an updated list of recommended low-side MOSFETs. PC BOARD LAYOUT CONSIDERATIONS Use these general guidelines when designing printed circuit boards: • Trace out the high current paths and use short, wide (>20 mil) traces to make these connections. • Minimize trace inductance between DRVH and DRVL outputs and MOSFET gates. • Connect the PGND pin of the ADP3120A as closely as possible to the source of the lower MOSFET. • Locate the VCC bypass capacitor as close as possible to the VCC and PGND pins. • Use vias to other layers, when possible, to maximize thermal conduction away from the IC. The circuit in Figure 16 shows how four drivers can be combined with an ADP3188 to form a total power conversion solution for generating VCC (CORE) for an Intel CPU that is VRD 10.x-compliant. Figure 15 shows an example of the typical land patterns based on the guidelines given previously. For more detailed layout guidelines for a complete CPU voltage regulator subsystem, refer to the PC Board Layout Considerations section of the ADP3188 data sheet. The next concern for the low-side MOSFETs is to prevent them from being inadvertently switched on when the high-side MOSFET turns on. This occurs due to the drain-gate (Miller capacitance, also specified as Crss capacitance) of the MOSFET. When the drain of the low-side MOSFET is switched to VCC by the high-side turning on (at a dV/dt rate), the internal gate of the low-side MOSFET is pulled up by an amount roughly equal to VCC × (Crss/Ciss). It is important to make sure this does not put the MOSFET into conduction. Another consideration is the nonoverlap circuitry of the ADP3120A that attempts to minimize the nonoverlap period. During the state of the high-side turning off to low-side turning on, the SW pin is monitored (as well as the conditions of SW prior to switching) to adequately prevent overlap. However, during the low-side turn-off to high-side turn-on, the SW pin does not contain information for determining the proper switching time, so the state of the DRVL pin is Rev. 0 | Page 11 of 16 CBST1 CBST2 RBST D1 CVCC 05812-015 The MOSFET vendor should provide a rating for the maximum voltage slew rate at drain current around which this can be designed. Once this specification is obtained, determine the maximum current expected in the MOSFET by Figure 15. External Component Placement Example Rev. 0 | Page 12 of 16 Figure 16. VRD 10.x-Compliant Power Supply Circuit 05812-016 POWER GOOD ENABLE C211 1nF FROM CPU VIN RTN VIN 12V C4 1μF D1 1N4148 + C2 RLDY 470kΩ RT 137kΩ, 1% CFB 22pF R1 10Ω PWM4 24 SW1 23 VID1 VID0 VID5 4 5 6 SW4 20 CSREF 16 C23 1nF 14 RAMPADJ ILIMIT 15 CSSUM 17 13 RT CSCOMP 18 12 DELAY 11 EN GND 19 COMP 9 10 PWRGD SW3 21 FB 8 SW2 22 PWM3 25 VID2 3 FBRTN PWM2 26 VID3 7 VCC 28 PWM1 27 VID4 2 U1 ADP3188 1 R2 357kΩ, 1% 1.5nF RLIM 150kΩ, 1% C22 1nF CCS2 CCS1 560pF RSW41 RSW21 RCS2 35.7kΩ 84.5kΩ RCS1 RPH4 158kΩ, 1% RSW31 RSW11 RPH2 RPH3 158kΩ, RPH1 1% 158kΩ, 158kΩ, 1% 1% 1FOR A DESCRIPTION OF OPTIONAL COMPONENTS, SEE THE ADP3188 THEORY OF OPERATION SECTION. CLDY 39nF CA RB RA 1.21kΩ 470pF 12.1kΩ CB 470pF + + C1 2700μF/16V/3.3A × 2 SANYO MV-WX SERIES C3 100μF L1 370nH 18A C17 4.7μF D5 1N4148 C13 4.7μF D4 1N4148 C9 4.7μF D3 1N4148 C5 4.7μF D2 1N4148 C8 12nF DRVL 5 VCC 4 DRVL 5 VCC SW 7 PGND 6 DRVL 5 BST IN OD VCC 2 3 4 DRVH 8 U5 C186.8nF ADP3120A C20 12nF PGND 6 OD R6 2.2Ω SW 7 DRVH 8 IN BST 1 4 3 2 1 U4 C14 ADP3120A 6.8nF C16 12nF DRVL 5 VCC R5 2.2Ω PGND 6 OD SW 7 DRVH 8 4 IN 2 3 BST 1 U3 C10 ADP3120A 6.8nF C12 12nF PGND 6 OD 3 R4 2.2Ω SW 7 IN 2 DRVH 8 BST 1 U2 C6 ADP3120A 6.8nF R3 2.2Ω Q15 NTD110N02 Q11 NTD110N02 Q7 NTD110N02 Q3 NTD110N02 Q16 NTD110N02 Q13 NTD60N02 C19 4.7μF Q12 NTD110N02 Q9 NTD60N02 C15 4.7μF Q8 NTD110N02 Q5 NTD60N02 C11 4.7μF Q4 NTD110N02 Q1 NTD60N02 C7 4.7μF L5 320nH/1.4mΩ L4 320nH/1.4mΩ L3 320nH/1.4mΩ RTH1 100kΩ, 5% NTC C24 + + 10μF × 18 MLCC IN SOCKET C31 560μF/4V × 8 L2 320nH/1.4mΩ SANYO SEPC SERIES 5mΩ EACH VCC (CORE) RTN VCC (CORE) 0.8375V – 1.6V 95A TDC, 119A PK ADP3120A ADP3120A OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 4.00 (0.1574) 3.80 (0.1497) 1 5 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 6.20 (0.2440) 4 5.80 (0.2284) 0.50 (0.0196) × 45° 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 17. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.00 BSC SQ 0.60 MAX 0.50 0.40 0.30 1 8 PIN 1 INDICATOR 0.90 MAX 0.85 NOM TOP VIEW 2.75 BSC SQ 0.50 BSC 1.50 REF 5 1.89 1.74 1.59 4 1.60 1.45 1.30 0.70 MAX 0.65 TYP 12° MAX PIN 1 INDICATOR 0.05 MAX 0.01 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF Figure 18. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm x 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters ORDERING GUIDE Model ADP3120AJRZ 1 ADP3120AJRZ-RL1 ADP3120AJCPZ-RL1 1 Temperature Range 0°C to 85°C 0°C to 85°C 0°C to 85°C Package Description 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) Z = Pb-free part. Rev. 0 | Page 13 of 16 Package Option R-8 R-8 CP-8-2 Ordering Quantity N/A 2,500 5,000 Branding L3C ADP3120A NOTES Rev. 0 | Page 14 of 16 ADP3120A NOTES Rev. 0 | Page 15 of 16 ADP3120A NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05812-0-3/06(0) Rev. 0 | Page 16 of 16