Sharp LH28F800BGHRBL85 8 m-bit (512 kb x 16) smartvoltage flash memory Datasheet

LH28F800BG-L/BGH-L (FOR TSOP, CSP)
LH28F800BG-L/BGH-L
(FOR TSOP, CSP)
8 M-bit (512 kB x 16) SmartVoltage
Flash Memories
DESCRIPTION
The LH28F800BG-L/BGH-L flash memories with
SmartVoltage technology are high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications. The LH28F800BG-L/BGH-L
can operate at VCC = 2.7 V and VPP = 2.7 V. Their
low voltage operation capability realizes longer
battery life and suits for cellular phone application.
Their boot, parameter and main-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for portable terminals and personal
computers. Their enhanced suspend capabilities
provide for an ideal solution for code + data storage
applications. For secure code storage applications,
such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the
LH28F800BG-L/BGH-L offer two levels of protection
: absolute protection with VPP at GND, selective
hardware boot block locking. These alternatives
give designers ultimate control of their code security
needs.
FEATURES
• SmartVoltage technology
– 2.7 V, 3.3 V or 5 V VCC
– 2.7 V, 3.3 V, 5 V or 12 V VPP
• High performance read access time
LH28F800BG-L85/BGH-L85
– 85 ns (5.0±0.25 V)/90 ns (5.0±0.5 V)/
100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V)
LH28F800BG-L12/BGH-L12
– 120 ns (5.0±0.5 V)/130 ns (3.3±0.3 V)/
150 ns (2.7 to 3.6 V)
• Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• Enhanced data protection features
– Absolute protection with VPP = GND
– Block erase/word write lockout during power
transitions
– Boot blocks protection with WP# = VIL
• SRAM-compatible write interface
• Optimized array blocking architecture
– Two 4 k-word boot blocks
– Six 4 k-word parameter blocks
– Fifteen 32 k-word main blocks
– Top or bottom boot location
• Enhanced cycling capability
– 100 000 block erase cycles
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases ICC
in static mode
• Automated word write and block erase
– Command user interface
– Status register
• ETOXTM∗ V nonvolatile flash technology
• Packages
– 48-pin TSOP Type I (TSOP048-P-1220)
Normal bend/Reverse bend
– 48-ball CSP (FBGA048-P-0808)
∗ ETOX is a trademark of Intel Corporation.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
-1-
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
COMPARISON TABLE
VERSIONS
OPERATING
TEMPERATURE
LH28F800BG-L
0 to +70°C
(FOR TSOP, CSP)
LH28F800BGH-L
–40 to +85°C
(FOR TSOP, CSP)
LH28F800BG-L∗1
0 to +70°C
(FOR SOP)
PACKAGE
DC CHARACTERISTICS
WRITE PROTECT FUNCTION
VCC deep power-down current (MAX.)
FOR BOOT BLOCKS
48-pin TSOP (I)
Controlled by
WP# and RP# pins
Controlled by
10 µA
48-ball CSP
48-pin TSOP (I)
20 µA
48-ball CSP
44-pin SOP
WP# and RP# pins
10 µA
Controlled by RP# pin
∗1 Refer to the datasheet of LH28F800BG-L (FOR SOP).
PIN CONNECTIONS
48-PIN TSOP (Type I)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
VPP
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
48-BALL CSP
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
A16
NC
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
TOP VIEW
1
2
3
4
5
6
7
8
A
A2
A5
A17
WP#
WE#
A8
A11
A14
B
A3
A6
A18
VPP
RP#
NC
A10
A13
C
A1
A4
A7
RY/BY#
NC
A9
A12
A15
D
A0
OE#
DQ1
DQ10
DQ12
DQ6
DQ15
A16
E GND
DQ8
DQ2
DQ11
VCC
DQ5
DQ14
GND
F CE#
DQ0
DQ9
DQ3
DQ4
DQ13
DQ7
NC
(FBGA048-P-0808)
(TSOP048-P-1220)
NOTE :
Reverse bend available on request.
-2-
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
BLOCK ORGANIZATION
Parameter Blocks : The boot block architecture
includes parameter blocks to facilitate storage of
frequently update small parameters that would
normally require an EEPROM. By using software
techniques, the byte-rewrite functionality of
EEPROMs can be emulated. Each boot block
component contains six parameter blocks of 4 k
words (4 096 words) each. The parameter blocks
are not write-protectable.
This product features an asymmetrically-blocked
architecture providing system memory integration.
Each erase block can be erased independently of
the others up to 100 000 times. For the address
locations of the blocks, see the memory map in
Fig. 1.
Boot Blocks : The two boot blocks are intended to
replace a dedicated boot PROM in a microprocessor or microcontroller-based system. The
boot blocks of 4 k words (4 096 words) feature
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
modification. The protection of the boot blocks is
controlled using a combination of the VPP, RP# and
WP# pins.
Main Blocks : The reminder is divided into main
blocks for data or code storage. Each 8 M-bit
device contains fifteen 32 k words (32 768 words)
blocks.
BLOCK DIAGRAM
DQ0-DQ15
OUTPUT
BUFFER
INPUT
BUFFER
I/O
LOGIC
STATUS
REGISTER
DATA
REGISTER
OUTPUT
MULTIPLEXER
IDENTIFIER
REGISTER
VCC
CE#
WE#
OE#
RP#
WP#
COMMAND
USER
INTERFACE
DATA
COMPARATOR
ADDRESS
COUNTER
-3-
MAIN BLOCK 14
15
32 k-WORD
MAIN BLOCKS
MAIN BLOCK 13
X
DECODER
WRITE
STATE
MACHINE
Y GATING
MAIN BLOCK 1
ADDRESS
LATCH
Y
DECODER
MAIN BLOCK 0
INPUT
BUFFER
BOOT BLOCK 0
BOOT BLOCK 1
PARAMETER BLOCK 0
PARAMETER BLOCK 1
PARAMETER BLOCK 2
PARAMETER BLOCK 3
PARAMETER BLOCK 4
PARAMETER BLOCK 5
A0-A18
RY/BY#
PROGRAM/ERASE
VOLTAGE SWITCH
VPP
VCC
GND
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
PIN DESCRIPTION
SYMBOL
TYPE
A0-A18
INPUT
DQ0-DQ15
CE#
NAME AND FUNCTION
ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
INPUT/
data during memory array, status register and identifier code read cycles. Data pins float
OUTPUT
to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
INPUT
CHIP ENABLE : Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
RP#
INPUT/
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode. With RP# = V HH, block erase or word
write can operate to all blocks without WP# state. Block erase or word write with VIH <
RP# < VHH produce spurious results and should not be attempted.
OUTPUT ENABLE : Gates the device’s outputs during a read cycle.
OE#
INPUT
WE#
INPUT
WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
WP#
INPUT
WRITE PROTECT : Master control for boot blocks locking. When VIL, locked boot
blocks cannot be erased and programmed.
READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
RY/BY#
OUTPUT
performing an internal operation (block erase or word write). RY/BY#-high indicates that
the WSM is ready for new commands, block erase is suspended, and word write is
inactive, word write is suspended, or the device is in deep power-down mode. RY/BY#
is always active and does not float when the chip is deselected or data outputs are
disabled.
VPP
SUPPLY
BLOCK ERASE AND WORD WRITE POWER SUPPLY : For erasing array blocks or
writing words. With VPP ≤ VPPLK, memory contents cannot be altered. Block erase and
word write with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce
spurious results and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V, 3.3 V or
VCC
SUPPLY
GND
NC
SUPPLY
5 V operation. To switch from one voltage to another, ramp VCC down to GND and then
ramp VCC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write
attempts to the flash memory are inhibited. Device operations at invalid VCC voltage
(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
not be attempted.
GROUND : Do not float any ground pins.
NO CONNECT : Lead is not internal connected; recommend to be floated.
-4-
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
1 INTRODUCTION
This datasheet contains LH28F800BG-L/BGH-L
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F800BG-L/
BGH-L flash memories documentation also includes
ordering information which is referenced in
Section 7.
1.1
Table 1 VCC and VPP Voltage Combinations
Offered by SmartVoltage Technology
New Features
Key enhancements of LH28F800BG-L/BGH-L
SmartVoltage flash memories are :
• SmartVoltage Technology
• Enhanced Suspend Capabilities
• Boot Block Architecture
VCC VOLTAGE
VPP VOLTAGE
2.7 V
2.7 V, 3.3 V, 5 V, 12 V
3.3 V
5V
3.3 V, 5 V, 12 V
5 V, 12 V
Internal VCC and VPP detection circuitry automatically configures the device for optimized read
and write operations.
Note following important differences :
• VPPLK has been lowered to 1.5 V to support
2.7 V, 3.3 V and 5 V block erase and word
write operations. Designs that switch VPP off
during read operations should make sure that
the VPP voltage transitions to GND.
• To take advantage of SmartVoltage technology,
allow VPP connection to 2.7 V, 3.3 V or 5 V.
1.2
But, 5 V VCC provides the highest read
performance. VPP at 2.7 V, 3.3 V and 5 V
eliminates the need for a separate 12 V converter,
while VPP = 12 V maximizes block erase and word
write performance. In addition to flexible erase and
program voltages, the dedicated VPP pin gives
complete data protection when VPP ≤ VPPLK.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase and word write
operations.
Product Overview
The LH28F800BG-L/BGH-L are high-performance
8 M-bit SmartVoltage flash memories organized as
512 k-word of 16 bits. The 512 k-word of data is
arranged in two 4 k-word boot blocks, six 4 k-word
parameter blocks and fifteen 32 k-word main blocks
which are individually erasable in-system. The
memory map is shown in Fig. 1.
SmartVoltage technology provides a choice of VCC
and VPP combinations, as shown in Table 1, to
meet system performance and power expectations.
2.7 V VCC consumes approximately one-fifth the
power of 5 V VCC and 3.3 V VCC consumes
approximately one-fourth the power of 5 V VCC.
-5-
A block erase operation erases one of the device’s
32 k-word blocks typically within 0.39 second (5 V
VCC, 12 V VPP), 4 k-word blocks typically within
0.25 second (5 V VCC, 12 V VPP) independent of
other blocks. Each block can be independently
erased 100 000 times. Block erase suspend mode
allows system software to suspend block erase to
read data from, or write data to any other block.
Writing memory data is performed in word
increments of the device’s 32 k-word blocks
typically within 8.4 µs (5 V VCC, 12 V VPP), 4 kword blocks typically within 17 µs (5 V VCC, 12 V
VPP). Word write suspend mode enables the
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
system to read data from, or write to any other
flash memory array location.
The boot block is located at either the top or the
bottom of the address map in order to
accommodate different micro-processor protect for
boot code location. The hardware-lockable boot
block provides complete code security for the
kernel code required for system initialization.
Locking and unlocking of the boot block is
controlled by WP# and/or RP# (see Section 4.9 for
details). Block erase or word write for boot block
must not be carried out by WP# to low and RP# to
VIH.
The status register indicates when the WSM’s block
erase or word write operation is finished.
The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase or word write.
RY/BY#-high indicates that the WSM is ready for a
new command, block erase is suspended (and
word write is inactive), word write is suspended, or
the device is in deep power-down mode.
-6-
The access time is 85 ns (tAVQV) at the VCC supply
voltage range of 4.75 to 5.25 V over the
temperature range, 0 to +70°C (LH28F800BG-L)/
– 40 to +85°C (LH28F800BGH-L). At 4.5 to 5.5 V
VCC, the access time is 90 ns or 120 ns. At lower
VCC voltage, the access time is 100 ns or 130 ns
(3.0 to 3.6 V) and 120 ns or 150 ns (2.7 to 3.6 V).
The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 1 mA at
5 V VCC and 3 mA at 2.7 V and 3.3 V VCC.
When CE# and RP# pins are at VCC, the ICC
CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (tPHQV) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
Top Boot
7FFFF
4 k-Word Boot Block
0
4 k-Word Boot Block
1
4 k-Word Parameter Block
0
4 k-Word Parameter Block
1
4 k-Word Parameter Block
2
4 k-Word Parameter Block
3
4 k-Word Parameter Block
4
4 k-Word Parameter Block
5
32 k-Word Main Block
0
32 k-Word Main Block
1
32 k-Word Main Block
2
32 k-Word Main Block
3
32 k-Word Main Block
4
32 k-Word Main Block
5
32 k-Word Main Block
6
7F000
7EFFF
7E000
7DFFF
7D000
7CFFF
7C000
7BFFF
7B000
7AFFF
7A000
79FFF
79000
78FFF
78000
77FFF
Bottom Boot
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
32 k-Word Main Block
7
32 k-Word Main Block
8
32 k-Word Main Block
9
32 k-Word Main Block
10
32 k-Word Main Block
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
07000
06FFF
06000
05FFF
05000
04FFF
04000
03FFF
11
32 k-Word Main Block
03000
02FFF
12
32 k-Word Main Block
02000
01FFF
13
32 k-Word Main Block
01000
00FFF
14
00000
00000
NOTES :
BLOCK CONFIGURATION
Top Boot
Bottom Boot
VERSIONS
LH28F800BG-TL
LH28F800BGH-TL
LH28F800BG-BL
LH28F800BGH-BL
Fig. 1 Memory Map
-7-
32 k-Word Main Block
14
32 k-Word Main Block
13
32 k-Word Main Block
12
32 k-Word Main Block
11
32 k-Word Main Block
10
32 k-Word Main Block
9
32 k-Word Main Block
8
32 k-Word Main Block
7
32 k-Word Main Block
6
32 k-Word Main Block
5
32 k-Word Main Block
4
32 k-Word Main Block
3
32 k-Word Main Block
2
32 k-Word Main Block
1
32 k-Word Main Block
0
4 k-Word Parameter Block
5
4 k-Word Parameter Block
4
4 k-Word Parameter Block
3
4 k-Word Parameter Block
2
4 k-Word Parameter Block
1
4 k-Word Parameter Block
0
4 k-Word Boot Block
1
4 k-Word Boot Block
0
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
2 PRINCIPLES OF OPERATION
The LH28F800BG-L/BGH-L SmartVoltage flash
memories include an on-chip WSM to manage
block erase and word write functions. It allows for :
100% TTL-level control inputs, fixed power supplies
during block erasure and word write, and minimal
processor overhead with RAM-like interface timings.
After initial device power-up or return from deep
power-down mode (see Table 2 "Bus Operations"),
the device defaults to read array mode.
Manipulation of external memory control pins allow
array read, standby and output disable operations.
Status register and identifier codes can be
accessed through the CUI independent of the VPP
voltage. High voltage on VPP enables successful
block erasure and word writing. All functions
associated with altering memory contents—block
erase, word write, status and identifier codes—are
accessed via the CUI and verified through the
status register.
Commands are written using standard microprocessor write timings. The CUI contents serve as
input to the WSM, which controls the block erase
and word write. The internal algorithms are
regulated by the WSM, including pulse repetition,
internal verification and margining of data.
Addresses and data are internally latched during
write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes or
outputs status register data.
Interface software that initiates and polls progress
of block erase and word write can be stored in any
block. This code is copied to and executed from
system RAM during flash memory updates. After
successful completion, reads are again possible via
the Read Array command. Block erase suspend
allows system software to suspend a block erase to
read/write data from/to blocks other than that which
is suspended. Word write suspend allows system
-8-
software to suspend a word write to read data from
any other flash memory array location.
2.1
Data Protection
Depending on the application, the system designer
may choose to make the VPP power supply
switchable (available only when memory block
erases or word writes are required) or hardwired to
VPPH1/2/3. The device accommodates either design
practice and encourages optimization of the
processor-memory interface.
When VPP ≤ VPPLK, memory contents cannot be
altered. The CUI, with two-step block erase or word
write command sequences, provides protection
from unwanted operations even when high voltage
is applied to VPP. All write functions are disabled
when VCC is below the write lockout voltage VLKO
or when RP# is at VIL. The device’s boot blocks
locking capability for WP# provides additional
protection from inadvertent code or data alteration
by block erase and word write operations.
3 BUS OPERATION
The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1
Read
Information can be read from any block, identifier
codes or status register independent of the VPP
voltage. RP# can be at either VIH or VHH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep powerdown mode, the device automatically resets to read
array mode. Five control pins dictate the data flow
in and out of the component : CE#, OE#, WE#,
RP# and WP#. CE# and OE# must be driven
active to obtain data at the outputs. CE# is the
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
device selection control, and when active enables
the selected memory device. OE# is the data
output (DQ0-DQ15) control and when active drives
the selected memory data onto the I/O bus. WE#
must be at VIH and RP# must be at VIH or VHH.
Fig. 11 illustrates read cycle.
3.2
Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins (DQ0-DQ15) are
placed in a high-impedance state.
3.3
Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ0-DQ15 outputs are placed
in a high-impedance state independent of OE#. If
deselected during block erase or word write, the
device continues functioning, and consuming active
power until the operation completes.
3.4
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase or
word write modes. If a CPU reset occurs with no
flash memory reset, proper CPU initialization may
not occur because the flash memory may be
providing status information instead of array data.
SHARP’s flash memories allow proper CPU
initialization following a system reset through the
use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets
the system CPU.
3.5
Read Identifier Codes Operation
The read identifier codes operation outputs the
manufacture code and device code (see Fig. 2).
Using the manufacture and device codes, the
system CPU can automatically match the device
with its proper algorithms.
Deep Power-Down
RP# at VIL initiates the deep power-down mode.
7FFFF
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time tPHQV is required
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.
During block erase or word write modes, RP#-low
will abort the operation. RY/BY# remains low until
the reset operation is complete. Memory contents
being altered are no longer valid; the data may be
partially erased or written. Time tPHWL is required
after RP# goes to logic-high (VIH) before another
command can be written.
As with any automated device, it is important to
-9-
Reserved for
Future Implementation
00002
00001
Device Code
00000
Manufacture Code
Fig. 2 Device Identifier Code Memory Map
3.6
Write
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
VCC = VCC1/2/3/4 and VPP = VPPH1/2/3, the CUI
additionally controls block erasure and word write.
The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word Write command requires the
command and address of the location to be written.
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 12 and
Fig. 13 illustrate WE# and CE# controlled write
operations.
4 COMMAND DEFINITIONS
When the VPP voltage ≤ VPPLK, read operations
from the status register, identifier codes, or blocks
are enabled. Placing VPPH1/2/3 on VPP enables
successful block erase and word write operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
Table 2 Bus Operations
MODE
Read
Output Disable
NOTE
RP#
1, 2, 3, 8 VIH or VHH
3
VIH or VHH
CE#
VIL
VIL
OE#
VIL
VIH
WE#
VIH
VIH
ADDRESS
X
X
VPP
X
X
DQ0-15
DOUT
High Z
RY/BY#
X
X
Standby
3
VIH or VHH
VIH
X
X
X
X
High Z
X
Deep Power-Down
Read Identifier Codes
4
8
VIL
VIH or VHH
X
VIL
X
VIL
X
VIH
X
See Fig. 2
X
X
High Z
(NOTE 5)
VOH
VOH
3, 6, 7, 8 VIH or VHH
VIL
VIH
VIL
X
X
DIN
X
Write
NOTES :
1.
2.
3.
Refer to Section 6.2.3 "DC CHARACTERISTICS".
When VPP ≤ VPPLK, memory contents can be read, but
not altered.
X can be VIL or VIH for control pins and addresses, and
VPPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC
CHARACTERISTICS" for VPPLK and VPPH1/2/3 voltages.
RY/BY# is VOL when the WSM is executing internal
block erase or word write algorithms. It is VOH during
when the WSM is not busy, in block erase suspend
mode (with word write inactive), word write suspend
mode or deep power-down mode.
4.
5.
6.
7.
8.
- 10 -
RP# at GND±0.2 V ensures the lowest deep powerdown current.
See Section 4.2 for read identifier code data.
Command writes involving block erase or word write are
reliably executed when VPP = VPPH1/2/3 and VCC =
VCC1/2/3/4. Block erase or word write with VIH < RP# <
VHH produce spurious results and should not be
attempted.
Refer to Table 3 for valid DIN during a write operation.
Don’t use the timing both OE# and WE# are VIL.
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
COMMAND
Table 3 Command Definitions (NOTE 7)
BUS CYCLES
FIRST BUS CYCLE
SECOND BUS CYCLE
NOTE
REQ’D.
Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3)
Read Array/Reset
Read Identifier Codes
1
≥2
Read Status Register
Clear Status Register
2
1
Block Erase
2
5
Write
BA
20H
Word Write
Block Erase and
2
5, 6
Write
WA
40H or 10H
1
5
Write
X
B0H
1
5
Write
X
D0H
Word Write Suspend
Block Erase and
Word Write Resume
4
Write
Write
X
X
FFH
90H
Write
Write
X
X
70H
50H
Read
IA
ID
Read
X
SRD
Write
BA
D0H
Write
WA
WD
NOTES :
1.
2.
3.
4.
Bus operations are defined in Table 2.
X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased.
WA = Address of memory location to be written.
SRD = Data read from status register. See Table 6 for a
description of the status register bits.
WD = Data to be written at location WA. Data is latched
on the rising edge of WE# or CE# (whichever
goes high first).
ID = Data read from identifier codes.
Following the Read Identifier Codes command, read
operations access manufacture and device codes. See
Section 4.2 for read identifier code data.
5.
6.
7.
- 11 -
If the block is boot block, WP# must be at VIH or RP#
must be at VHH to enable block erase or word write
operations. Attempts to issue a block erase or word write
to a boot block while WP# is VIH or RP# is VIH.
Either 40H or 10H is recognized by the WSM as the
word write setup.
Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
4.1
Read Array Command
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase or word write, the device will not
recognize the Read Array command until the WSM
completes its operation unless the WSM is
suspended via an Erase Suspend or Word Write
Suspend command. The Read Array command
functions independently of the VPP voltage and
RP# can be VIH or VHH.
4.2
Read Identifier Codes Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture and device codes
(see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the VPP voltage and RP# can be
VIH or VHH. Following the Read Identifier Codes
command, the following information can be read :
Table 4 Identifier Codes
CODE
ADDRESS
Manufacture Code
00000H
DATA
00B0H
Device Code (Top Boot)
Device Code (Bottom Boot)
0060H
0062H
4.3
00001H
00001H
Read Status Register Command
The status register may be read to determine when
a block erase or word write is complete and
whether the operation completed successfully. It
may be read at any time by writing the Read Status
Register command. After writing this command, all
subsequent read operations output data from the
status register until another valid command is
written. The status register contents are latched on
the falling edge of OE# or CE#, whichever occurs.
OE# or CE# must toggle to VIH before further reads
to update the status register latch. The Read Status
Register command functions independently of the
VPP voltage. RP# can be VIH or VHH.
4.4
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing
multiple blocks or writing several words in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied VPP voltage. RP# can
be VIH or VHH. This command is not functional
during block erase or word write suspend modes.
4.5
Block Erase Command
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFFFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
the device automatically outputs status register data
when read (see Fig. 3). The CPU can detect block
erase completion by analyzing the output data of
the RY/BY# pin or status register bit SR.7.
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.
- 12 -
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
The CUI remains in read status register mode until
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when VCC =
VCC1/2/3/4 and VPP = VPPH1/2/3. In the absence of
this high voltage, block contents are protected
against erasure. If block erase is attempted while
VPP ≤ VPPLK, SR.3 and SR.5 will be set to "1".
Successful block erase for boot blocks requires that
the corresponding if set, that WP# = VIH or RP# =
VHH. If block erase is attempted to boot block when
the corresponding WP# = VIL or RP# = VIH, SR.1
and SR.5 will be set to "1". Block erase operations
with VIH < RP# < VHH produce spurious results and
should not be attempted.
4.6
Word Write Command
Word write is executed by a two-cycle command
sequence. Word write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word write and write verify algorithms
internally. After the word write sequence is written,
the device automatically outputs status register data
when read (see Fig. 4). The CPU can detect the
completion of the word write event by analyzing the
RY/BY# pin or status register bit SR.7.
When word write is complete, status register bit
SR.4 should be checked. If word write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for "1"s that
do not successfully write to "0"s. The CUI remains
in read status register mode until it receives another
command.
Reliable word writes can only occur when VCC =
VCC1/2/3/4 and VPP = VPPH1/2/3. In the absence of
this high voltage, memory contents are protected
against word writes. If word write is attempted while
VPP ≤ VPPLK, status register bits SR.3 and SR.4 will
be set to "1". Successful word write for boot blocks
requires that the corresponding if set, that WP# =
VIH or RP# = VHH. If word write is attempted to
boot block when the corresponding WP# = VIL or
RP# = VIH, SR.1 and SR.4 will be set to "1". Word
write operations with VIH < RP# < VHH produce
spurious results and should not be attempted.
4.7
Block Erase Suspend Command
The Block Erase Suspend command allows block
erase interruption to read or word write data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be
set to "1"). RY/BY# will also transition to VOH.
Specification tWHRH2 defines the block erase
suspend latency.
At this point, a Read Array command can be
written to read data from blocks other than that
which is suspended. A Word Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the Word
Write Suspend command (see Section 4.8), a
word write operation can also be suspended.
During a word write operation with block erase
suspended, status register bit SR.7 will return to "0"
and the RY/BY# output will transition to VOL.
However, SR.6 will remain "1" to indicate block
erase suspend status.
- 13 -
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to VOL. After the Erase
Resume command is written, the device
automatically outputs status register data when
read (see Fig. 5). VPP must remain at VPPH1/2/3
(the same VPP level used for block erase) while
block erase is suspended. RP# must also remain at
VIH or VHH (the same RP# level used for block
erase). WP# must also remain at VIL or VIH (the
same WP# level used for block erase). Block erase
cannot resume until word write operations initiated
during block erase suspend have completed.
4.8
Word Write Suspend Command
The Word Write Suspend command allows word
write interruption to read data in other flash memory
locations. Once the word write process starts,
writing the Word Write Suspend command requests
that the WSM suspend the word write sequence at
a predetermined point in the algorithm. The device
continues to output status register data when read
after the Word Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the word write operation has been
suspended (both will be set to "1"). RY/BY# will
also transition to VOH. Specification tWHRH1 defines
the word write suspend latency.
At this point, a Read Array command can be
written to read data from locations other than that
which is suspended. The only other valid
commands while word write is suspended are Read
Status Register and Word Write Resume. After
Word Write Resume command is written to the
flash memory, the WSM will continue the word
write process. Status register bits SR.2 and SR.7
will automatically clear and RY/BY# will return to
VOL. After the Word Write Resume command is
written, the device automatically outputs status
register data when read (see Fig. 6). VPP must
remain at VPPH1/2/3 (the same VPP level used for
word write) while in word write suspend mode. RP#
must also remain at VIH or VHH (the same RP#
level used for word write). WP# must also remain
at VIL or VIH (the same WP# level used for word
write).
4.9
Block Locking
This Boot Block flash memory architecture features
two hardware-lockable boot blocks so that the
kernel code for the system can be kept secure
while other blocks are programmed or erased as
necessary.
4.9.1 VPP = VIL FOR COMPLETE PROTECTION
The VPP programming voltage can be held low for
complete write protection of all blocks in the flash
device.
4.9.2 WP# = VIL FOR BLOCK LOCKING
The lockable blocks are locked when WP# = VIL;
any program or erase operation to a locked block
will result in an error, which will be reflected in the
status register. For top configuration, the top two
boot blocks are lockable. For the bottom
configuration, the bottom two boot blocks are
lockable. Unlocked blocks can be programmed or
erased normally (Unless VPP is below VPPLK).
4.9.3 BLOCK UNLOCKING
WP# = VIH or RP# = VHH unlocks all lockable
blocks.
These blocks can now be programmed or erased.
WP# or RP# controls all block locking and VPP
provides protection against spurious writes. Table 5
defines the write protection methods.
- 14 -
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
Table 5 Write Protection Alternatives
OPERATION
VPP
VIL
Block Erase
RP# WP#
EFFECT
X
X All Blocks Locked.
VIL X All Blocks Locked.
or
VHH X All Blocks Unlocked.
> VPPLK
Word Write
VIL 2 Boot Blocks Locked.
VIH
VIH All Blocks Unlocked.
Table 6 Status Register Definition
WSMS
7
ESS
6
ES
5
WWS
4
VPPS
3
WWSS
2
DPS
1
R
0
NOTES :
Check RY/BY# or SR.7 to determine block erase or word
write completion. SR.6-0 are invalid while SR.7 = "0".
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
If both SR.5 and SR.4 are "1"s after a block erase attempt, an
improper command sequence was entered.
SR.5 = ERASE STATUS (ES)
1 = Error in Block Erase
0 = Successful Block Erase
SR.4 = WORD WRITE STATUS (WWS)
1 = Error in Word Write
0 = Successful Word Write
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = WORD WRITE SUSPEND STATUS (WWSS)
1 = Word Write Suspended
0 = Word Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = WP# or RP# Lock Detected, Operation Abort
0 = Unlock
SR.3 does not provide a continuous indication of VPP level.
The WSM interrogates and indicates the VPP level only after
Block Erase or Word Write command sequences.
SR.3 is not guaranteed to reports accurate feedback only
when VPP ≠ VPPH1/2/3.
The WSM interrogates the WP# and RP# only after Block
Erase or Word Write command sequences. It informs the
system, depending on the attempted operation, if the WP# is
not VIH, RP# is not VHH.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.0 is reserved for future use and should be masked out
when polling the status register.
- 15 -
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
BUS
OPERATION COMMAND
Start
Write 20H,
Block Address
Write D0H,
Block Address
Read
Status Register
No
0
Suspend Block
Erase Loop
Suspend
Block Erase
SR.7 =
Yes
1
COMMENTS
Write
Erase Setup
Data = 20H
Addr = Within Block to be Erased
Write
Erase
Confirm
Data = D0H
Addr = Within Block to be Erased
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures.
Full status check can be done after each block erase or after
a sequence of block erasures.
Write FFH after the last block erase operation to place device
in read array mode.
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
BUS
OPERATION COMMAND
VPP Range Error
COMMENTS
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.5
1 = Block Erase Error
0
SR.1 =
1
Device Protect Error
0
SR.4, 5 =
1
Command Sequence
Error
0
SR.5 =
1
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple blocks
are erased before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
Block Erase
Error
0
Block Erase
Successful
Fig. 3 Automated Block Erase Flowchart
- 16 -
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
BUS
OPERATION COMMAND
Start
Write 40H or 10H,
Address
Write Word
Data and Address
Read
Status Register
No
0
Suspend Word
Write Loop
Suspend
Word Write
SR.7 =
Yes
COMMENTS
Write
Setup
Word Write
Data = 40H or 10H
Addr = Location to be Written
Write
Word Write
Data = Data to be Written
Addr = Location to be Written
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent word writes.
SR full status check can be done after each word write or after
a sequence of word writes.
Write FFH after the last word write operation to place device
in read array mode.
1
Full Status
Check if Desired
Word Write
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
BUS
OPERATION COMMAND
VPP Range Error
COMMENTS
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
Standby
Check SR.4
1 = Data Write Error
0
SR.1 =
1
Device Protect Error
0
SR.4 =
1
Word Write Error
SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple locations are
written before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
0
Word Write
Successful
Fig. 4 Automated Word Write Flowchart
- 17 -
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
BUS
OPERATION
Start
Write
Write B0H
Read
Status Register
SR.7 =
0
1
SR.6 =
Erase
Suspend
Data = B0H
Addr = X
Read
Status Register Data
Addr = X
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.6
1 = Block Erase Suspended
0 = Block Erase Completed
Write
0
COMMENTS
COMMAND
Erase
Resume
Data = D0H
Addr = X
Block Erase
Completed
1
Read
Read
or Word
Write?
Read Array Data
Word Write
Word Write Loop
No
Done?
Yes
Write D0H
Write FFH
Block Erase
Resumed
Read
Array Data
Fig. 5 Block Erase Suspend/Resume Flowchart
- 18 -
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
BUS
OPERATION
Start
Write
Write B0H
Read
Status Register
0
SR.7 =
1
SR.2 =
Word Write
Completed
1
Word Write
Suspend
Data = B0H
Addr = X
Read
Status Register Data
Addr = X
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.2
1 = Word Write Suspended
0 = Word Write Completed
Write
0
COMMENTS
COMMAND
Read Array
Read array locations other
than that being written.
Read
Write
Data = FFH
Addr = X
Word Write
Resume
Data = D0H
Addr = X
Write FFH
Read
Array Data
Done
Reading
No
Yes
Write D0H
Write FFH
Word Write Resumed
Read
Array Data
Fig. 6 Word Write Suspend/Resume Flowchart
- 19 -
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
5 DESIGN CONSIDERATIONS
5.1
Three-Line Output Control
The device will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections. Threeline control provides for :
a. Lowest possible memory power consumption.
b. Complete assurance that data bus contention
will not occur.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2
RY/BY#, Block Erase and Word
Write Polling
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase and
word write completion. It transitions low after block
erase or word write commands and returns to VOH
when the WSM has finished executing the internal
algorithm.
RY/BY# can be connected to an interrupt input of
the system CPU or controller. It is active at all
times. RY/BY# is also VOH when the device is in
block erase suspend (with word write inactive),
word write suspend or deep power-down modes.
5.3
Power Supply Decoupling
Flash memory power switching characteristics
require careful device decoupling. System
designers are interested in three supply current
issues; standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device
should have a 0.1 µF ceramic capacitor connected
between its VCC and GND and between its VPP
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7 µF electrolytic capacitor should be placed at
the array’s power supply connection between VCC
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
5.4
VPP Trace on Printed Circuit Boards
Updating flash memories that reside in the target
system requires that the printed circuit board
designers pay attention to the VPP power supply
trace. The VPP pin supplies the memory cell current
for word writing and block erasing. Use similar trace
widths and layout considerations given to the VCC
power bus. Adequate VPP supply traces and
decoupling will decrease VPP voltage spikes and
overshoots.
5.5
VCC, VPP, RP# Transitions
Block erase and word write are not guaranteed if
VPP falls outside of a valid VPPH1/2/3 range, VCC falls
outside of a valid VCC1/2/3/4 range, or RP# ≠ VIH or
VHH. If VPP error is detected, status register bit SR.3
is set to "1" along with SR.4 or SR.5, depending on
the attempted operation. If RP# transitions to VIL
during block erase or word write, RY/BY# will
remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation
is restored. Device power-off or RP# transitions to
VIL clear the status register.
- 20 -
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
The CUI latches commands issued by system
software and is not altered by VPP or CE#
transitions or WSM actions. Its state is read array
mode upon power-up, after exit from deep powerdown or after VCC transitions below VLKO.
After block erase or word write, even after VPP
transitions down to VPPLK, the CUI must be placed
in read array mode via the Read Array command if
subsequent access to the memory array is desired.
5.6
Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure or word writing during
power transitions. Upon power-up, the device is
indifferent as to which power supply (VPP or VCC)
powers-up first. Internal circuitry resets the CUI to
read array mode at power-up.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active. Since both WE# and CE# must be low for a
command write, driving either to VIH will inhibit
writes. The CUI’s two-step command sequence
architecture provides added level of protection
against data alteration.
5.7
Power Consumption
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is
retained when system power is removed.
In addition, deep power-down mode ensures
extremely low power consumption even when
system power is applied. For example, portable
computing products and other power sensitive
applications that use an array of devices for solidstate storage can consume negligible power by
lowering RP# to VIL standby or sleep modes. If
access is again needed, the devices can be read
following the tPHQV and tPHWL wake-up cycles
required after RP# is first raised to VIH. See Section
6.2.4 through 6.2.6 "AC CHARACTERISTICS READ-ONLY and WRITE OPERATIONS" and
Fig. 11, Fig. 12 and Fig.13 for more information.
WP# provides additional protection from inadvertent
code or data alteration. The device is disabled
while RP# = VIL regardless of its control inputs
state.
- 21 -
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6 ELECTRICAL SPECIFICATIONS
6.1
NOTICE : The specifications are subject to
change without notice. Verify with your local
SHARP sales office that you have the latest
datasheet before finalizing a design.
Absolute Maximum Ratings∗
Operating Temperature
• LH28F800BG-L
During Read, Block Erase and
Word Write ............................. 0 to +70°C (NOTE 1)
Temperature under Bias ............. –10 to +80°C
• LH28F800BGH-L
During Read, Block Erase and
Word Write ........................ –40 to +85°C (NOTE 2)
Temperature under Bias............. –40 to +85°C
∗WARNING : Stressing the device beyond the
"Absolute
Maximum Ratings" may cause
permanent damage. These are stress ratings only.
Operation beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device reliability.
NOTES :
1.
Storage Temperature ........................ –65 to +125°C
Voltage On Any Pin
(except VCC, VPP, and RP#) .... –2.0 to +7.0 V (NOTE 3)
2.
3.
VCC Supply Voltage ................. –2.0 to +7.0 V (NOTE 3)
VPP Update Voltage during
Block Erase and
Word Write .................. –2.0 to +14.0 V (NOTE 3, 4)
RP# Voltage ........................ –2.0 to +14.0 V (NOTE 3, 4)
4.
5.
Operating temperature is for commercial product defined
by this specification.
Operating temperature is for extended temperature
product defined by this specification.
All specified voltages are with respect to GND. Minimum
DC voltage is –0.5 V on input/output pins and – 0.2 V on
VCC and VPP pins. During transitions, this level may
undershoot to –2.0 V for periods < 20 ns. Maximum DC
voltage on input/output pins and VCC is VCC+0.5 V
which, during transitions, may overshoot to VCC+2.0 V
for periods < 20 ns.
Maximum DC voltage on VPP and RP# may overshoot
to +14.0 V for periods < 20 ns.
Output shorted for no more than one second. No more
than one output shorted at a time.
Output Short Circuit Current............... 100 mA (NOTE 5)
6.2
Operating Conditions
SYMBOL
PARAMETER
NOTE
1
MIN.
0
MAX.
+70
–40
UNIT
˚C
˚C
TA
Operating Temperature
VCC1
VCC Supply Voltage (2.7 to 3.6 V)
2.7
+85
3.6
VCC2
VCC Supply Voltage (3.3±0.3 V)
3.0
3.6
V
VCC3
VCC4
VCC Supply Voltage (5.0±0.25 V)
VCC Supply Voltage (5.0±0.5 V)
4.75
4.50
5.25
5.50
V
V
NOTE :
1.
Test condition : Ambient temperature
- 22 -
VERSIONS
LH28F800BG-L
LH28F800BGH-L
V
LH28F800BG-L85/BGH-L85
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.1 CAPACITANCE (NOTE 1)
TA = +25˚C, f = 1 MHz
SYMBOL
CIN
COUT
PARAMETER
TYP.
MAX.
UNIT
7
9
10
12
pF
pF
Input Capacitance
Output Capacitance
CONDITION
VIN = 0.0 V
VOUT = 0.0 V
NOTE :
1.
Sampled, not 100% tested.
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
2.7
INPUT
1.35
TEST POINTS
1.35 OUTPUT
0.0
AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output
timing ends, at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns.
Fig. 7 Transient Input/Output Reference Waveform for VCC = 2.7 to 3.6 V
3.0
INPUT
1.5
TEST POINTS
1.5
OUTPUT
0.0
AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output
timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns.
Fig. 8 Transient Input/Output Reference Waveform for VCC = 3.3±0.3 V and
VCC = 5.0±0.25 V (High Speed Testing Configuration)
2.4
2.0
INPUT
0.45
2.0
TEST POINTS
0.8
OUTPUT
0.8
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing
begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to
90%) < 10 ns.
Fig. 9 Transient Input/Output Reference Waveform for
VCC = 5.0±0.5 V (Standard Testing Configuration)
- 23 -
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
Test Configuration Capacitance Loading Value
1.3 V
TEST CONFIGURATION
VCC = 3.3±0.3 V, 2.7 to 3.6 V
1N914
VCC = 5.0±0.25 V (NOTE 1)
VCC = 5.0±0.5 V
CL (pF)
50
30
100
NOTE :
RL = 3.3 kΩ
DEVICE
UNDER
TEST
1.
OUT
CL
CL Includes Jig
Capacitance
Fig. 10 Transient Equivalent Testing
Load Circuit
- 24 -
Applied to high-speed products, LH28F800BG-L85 and
LH28F800BGH-L85.
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.3 DC CHARACTERISTICS
SYMBOL
PARAMETER
NOTE
VCC = 2.7 to 3.6 V VCC = 5.0±0.5 V
UNIT
TYP.
MAX.
TYP.
MAX.
25
50
30
100
µA
0.2
2
0.4
2
mA
4
4
10
20
10
20
µA
15
25
50
mA
30
65
mA
—
35
30
—
30
25
mA
mA
mA
mA
mA
mA
VCC = VCC Max.
VIN = VCC or GND
VCC = VCC Max.
VOUT = VCC or GND
CMOS Inputs
VCC = VCC Max.
CE# = RP# = VCC±0.2 V
TTL Inputs
VCC = VCC Max.
CE# = RP# = VIH
RP# = GND±0.2 V
IOUT (RY/BY#) = 0 mA
CMOS Inputs
VCC = VCC Max.
CE# = GND
f = 5 MHz (3.3 V, 2.7 V),
8 MHz (5 V)
IOUT = 0 mA
TTL Inputs
VCC = VCC Max.
CE# = GND
f = 5 MHz (3.3 V, 2.7 V),
8 MHz (5 V)
IOUT = 0 mA
VPP = 2.7 to 3.6 V
VPP = 5.0±0.5 V
VPP = 12.0±0.6 V
VPP = 2.7 to 3.6 V
VPP = 5.0±0.5 V
VPP = 12.0±0.6 V
ILI
Input Load Current
1
±0.5
±1
µA
ILO
Output Leakage Current
1
±0.5
±10
µA
ICCS
ICCD
ICCR
VCC Standby Current
VCC Deep Power- LH28F800BG-L
Down Current
LH28F800BGH-L
VCC Read Current
1, 3, 6
1
1, 5, 6
5
5
5
4
4
4
17
17
12
17
17
12
—
1, 2
1
6
1
10
mA
CE# = VIH
1
±2
10
±15
200
±2
10
±15
200
µA
µA
VPP ≤ VCC
VPP > VCC
1
0.1
5
0.1
5
µA
RP# = GND±0.2 V
12
40
40
30
25
25
20
—
—
40
30
—
25
20
mA
mA
mA
mA
mA
mA
VPP
VPP
VPP
VPP
VPP
VPP
200
10
200
µA
VPP = VPPH1/2/3
ICCW
VCC Word Write Current
1, 7
ICCE
VCC Block Erase Current
1, 7
ICCWS VCC Word Write or Block
ICCES Erase Suspend Current
IPPS
VPP Standby or Read Current
IPPR
VPP Deep Power-Down
IPPD
Current
IPPW
VPP Word Write Current
1, 7
IPPE
VPP Block Erase Current
1, 7
8
IPPWS VPP Word Write or Block
IPPES Erase Suspend Current
TEST
CONDITIONS
1
10
- 25 -
—
—
=
=
=
=
=
=
2.7 to 3.6 V
5.0±0.5 V
12.0±0.6 V
2.7 to 3.6 V
5.0±0.5 V
12.0±0.6 V
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.3 DC CHARACTERISTICS (contd.)
SYMBOL
PARAMETER
NOTE
VIL
Input Low Voltage
7
VIH
Input High Voltage
7
VOL
Output Low Voltage
3, 7
VCC = 2.7 to 3.6 V VCC = 5.0±0.5 V
UNIT
MIN.
MAX.
MIN.
MAX.
–0.5
–0.5
0.8
0.8
V
VCC
+0.5
2.0
2.0
VCC
+0.5
V
0.45
V
TEST
CONDITIONS
VCC = VCC Min.
0.4
IOL = 5.8 mA (5 V)
IOL = 2.0 mA (3.3 V, 2.7 V)
VOH1
VOH2
VPPLK
VPPH1
VPPH2
VPPH3
VLKO
VHH
Output High Voltage
(TTL)
Output High Voltage
(CMOS)
VPP Lockout Voltage during
Normal Operations
VPP Voltage during Word Write
3, 7
3, 7
2.4
V
VCC = VCC Min.
IOH = –2.5 mA (5 V)
IOH = –2.0 mA (3.3 V, 2.7 V)
0.85
VCC
0.85
VCC
V
VCC = VCC Min.
IOH = –2.5 mA
VCC
–0.4
VCC
–0.4
V
VCC = VCC Min.
IOH = –100 µA
4, 7
or Block Erase Operations
VPP Voltage during Word Write
or Block Erase Operations
VPP Voltage during Word Write
or Block Erase Operations
VCC Lockout Voltage
RP# Unlock Voltage
2.4
8, 9
1.5
1.5
V
2.7
3.6
—
—
V
4.5
5.5
4.5
5.5
V
11.4
12.6
11.4
12.6
V
2.0
11.4
12.6
2.0
11.4
12.6
V
V
Unavailable WP#
NOTES :
1.
2.
3.
4.
All currents are in RMS unless otherwise noted. Typical
values at nominal VCC voltage and TA = +25˚C. These
currents are valid for all product versions (packages and
speeds).
ICCWS and ICCES are specified with the device deselected. If reading or word writing in erase suspend
mode, the device’s current draw is the sum of ICCWS or
ICCES and ICCR or ICCW, respectively.
Includes RY/BY#.
Block erases and word writes are inhibited when VPP ≤
VPPLK, and not guaranteed in the range between VPPLK
(max.) and VPPH1 (min.), between VPPH1 (max.) and
VPPH2 (min.), between VPPH2 (max.) and VPPH3 (min.),
and above VPPH3 (max.).
5.
6.
7.
8.
9.
- 26 -
Automatic Power Saving (APS) reduces typical ICCR to
1 mA at 5 V VCC and 3 mA at 2.7 V and 3.3 V VCC in
static operation.
CMOS inputs are either VCC±0.2 V or GND±0.2 V. TTL
inputs are either VIL or VIH.
Sampled, not 100% tested.
Boot block erases and word writes are inhibited when
the corresponding RP# = VIH or WP# = VIL. Block erase
and word write operations are not guaranteed with VIH <
RP# < VHH and should not be attempted.
RP# connection to a VHH supply is allowed for a
maximum cumulative period of 80 hours.
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C or –40 to +85˚C
LH28F800BG-L85
LH28F800BGH-L85
VERSIONS
SYMBOL
PARAMETER
NOTE
tAVAV
tAVQV
Read Cycle Time
Address to Output Delay
tELQV
tPHQV
CE# to Output Delay
RP# High to Output Delay
tGLQV
OE# to Output Delay
2
tELQX
CE# to Output in Low Z
3
tEHQZ
CE# High to Output in High Z
3
tGLQX
OE# to Output in Low Z
3
tGHQZ
OE# High to Output in High Z
3
tOH
Output Hold from Address, CE# or
OE# Change, Whichever Occurs First
3
MIN.
MAX.
120
2
LH28F800BG-L12
LH28F800BGH-L12 UNIT
MIN.
MAX.
150
120
150
ns
ns
120
600
150
600
ns
ns
55
ns
50
0
0
55
0
ns
55
0
20
0
ns
ns
25
0
ns
ns
• VCC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C
LH28F800BG-L85
VERSIONS
SYMBOL
PARAMETER
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
LH28F800BGH-L85
NOTE
MIN.
100
MAX.
LH28F800BG-L12
LH28F800BGH-L12 UNIT
MIN.
130
100
MAX.
130
ns
ns
tELQV
CE# to Output Delay
2
100
130
ns
tPHQV
tGLQV
RP# High to Output Delay
OE# to Output Delay
2
600
50
600
55
ns
ns
tELQX
CE# to Output in Low Z
3
tEHQZ
tGLQX
CE# High to Output in High Z
OE# to Output in Low Z
3
3
tGHQZ
OE# High to Output in High Z
Output Hold from Address, CE# or
3
tOH
OE# Change, Whichever Occurs First
3
0
0
55
0
0
NOTES :
1.
2.
3.
See AC Input/Output Reference Waveform (Fig. 7 through Fig. 9) for maximum allowable input slew rate.
OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV.
Sampled, not 100% tested.
- 27 -
ns
ns
25
ns
0
20
0
ns
55
ns
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (contd.) (NOTE 1)
• VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –40 to +85˚C
(NOTE 4)
VERSIONS
VCC±0.25 V LH28F800BG-L85
LH28F800BGH-L85
(NOTE 5)
SYMBOL
PARAMETER
tAVAV
Read Cycle Time
NOTE
tAVQV
tELQV
Address to Output Delay
CE# to Output Delay
tPHQV
RP# High to Output Delay
tGLQV
tELQX
OE# to Output Delay
CE# to Output in Low Z
2
3
tEHQZ
CE# High to Output in High Z
3
tGLQX
OE# to Output in Low Z
3
tGHQZ
OE# High to Output in High Z
3
tOH
Output Hold from Address,
CE# or OE# Change,
3
UNIT
(NOTE 5)
LH28F800BG-L85 LH28F800BG-L12
LH28F800BGH-L85 LH28F800BGH-L12
VCC±0.5 V
MIN.
85
MAX.
2
MIN.
90
MAX.
MAX.
ns
85
85
90
90
120
120
400
400
400
ns
40
45
50
ns
ns
55
ns
0
0
55
0
0
55
0
10
0
MIN.
120
0
10
0
ns
15
0
ns
ns
ns
ns
Whichever Occurs First
NOTES :
1.
2.
3.
4.
See AC Input/Output Reference Waveform (Fig. 7
through Fig. 9) for maximum allowable input slew rate.
OE# may be delayed up to tELQV-tGLQV after the falling
edge of CE# without impact on tELQV.
Sampled, not 100% tested.
See Fig. 8 "Transient Input/Output Reference
Waveform" and Fig. 10 "Transient Equivalent Testing
Load Circuit" (High Speed Configuration) for testing
characteristics.
5.
- 28 -
See Fig. 9 "Transient Input/Output Reference
Waveform" and Fig. 10 "Transient Equivalent Testing
Load Circuit" (Standard Configuration) for testing
characteristics.
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
VIH
Standby
Device
Address Selection
ADDRESSES (A)
Data Valid
Address Stable
VIL
tAVAV
VIH
CE# (E)
tEHQZ
VIL
VIH
OE# (G)
tGHQZ
VIL
VIH
WE# (W)
tGLQV
tELQV
VIL
VOH
DATA (D/Q)
(DQ0-DQ15)
tGLQX
tELQX
High Z
tOH
Valid Output
VOL
tAVQV
VCC
tPHQV
VIH
RP# (P)
VIL
Fig. 11 AC Waveform for Read Operations
- 29 -
High Z
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C or –40 to +85˚C
LH28F800BG-L85
LH28F800BGH-L85
VERSIONS
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
NOTE
MIN.
120
2
1
10
tPHHWH RP# VHH Setup to WE# Going High
tSHWH WP# VIH Setup to WE# Going High
2
2
tVPWH
tAVWH
VPP Setup to WE# Going High
Address Setup to WE# Going High
2
3
tDVWH
tWHDX
Data Setup to WE# Going High
Data Hold from WE# High
3
tWHAX
Address Hold from WE# High
5
5
ns
tWHEH
tWHWL
CE# Hold from WE# High
WE# Pulse Width High
10
30
10
30
ns
ns
tWHRL
tWHGL
WE# High to RY/BY# Going Low
Write Recovery before Read
0
0
ns
ns
tQVVL
VPP Hold from Valid SRD, RY/BY# High
2, 4
0
0
ns
tQVPH
tQVSL
RP# VHH Hold from Valid SRD, RY/BY# High
2, 4
0
0
ns
WP# VIH Hold from Valid SRD, RY/BY# High
2, 4
0
0
ns
Read timing characteristics during block erase and word
write operations are the same as during read-only
operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations.
Sampled, not 100% tested.
Refer to Table 3 for valid AIN and DIN for block erase or
word write.
4.
tPHWL
tELWL
RP# High Recovery to WE# Going Low
CE# Setup to WE# Going Low
tWLWH
WE# Pulse Width
MAX.
LH28F800BG-L12
LH28F800BGH-L12 UNIT
MIN.
150
MAX.
ns
1
10
µs
ns
50
50
ns
100
100
100
100
ns
ns
100
50
100
50
ns
ns
50
5
50
5
ns
ns
100
100
NOTES :
1.
2.
3.
- 30 -
VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase
or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,
SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS (contd.) (NOTE 1)
• VCC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C
LH28F800BG-L85
LH28F800BGH-L85
VERSIONS
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
MAX.
LH28F800BG-L12
LH28F800BGH-L12 UNIT
NOTE
MIN.
100
MIN.
130
2
1
1
MAX.
ns
tPHWL
RP# High Recovery to WE# Going Low
tELWL
CE# Setup to WE# Going Low
10
10
ns
tWLWH
WE# Pulse Width
50
50
ns
100
100
ns
tPHHWH RP# VHH Setup to WE# Going High
2
µs
tSHWH
WP# VIH Setup to WE# Going High
2
100
100
ns
tVPWH
VPP Setup to WE# Going High
2
100
100
ns
tAVWH
Address Setup to WE# Going High
3
50
50
ns
tDVWH
Data Setup to WE# Going High
3
50
50
ns
tWHDX
tWHAX
Data Hold from WE# High
Address Hold from WE# High
5
5
5
5
ns
ns
tWHEH
tWHWL
CE# Hold from WE# High
WE# Pulse Width High
10
30
10
30
ns
ns
tWHRL
WE# High to RY/BY# Going Low
tWHGL
Write Recovery before Read
tQVVL
tQVPH
tQVSL
VPP Hold from Valid SRD, RY/BY# High
RP# VHH Hold from Valid SRD, RY/BY# High
WP# VIH Hold from Valid SRD, RY/BY# High
2, 4
2, 4
2, 4
Read timing characteristics during block erase and word
write operations are the same as during read-only
operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations.
Sampled, not 100% tested.
Refer to Table 3 for valid AIN and DIN for block erase or
word write.
4.
100
100
ns
0
0
ns
0
0
0
0
0
0
ns
ns
ns
NOTES :
1.
2.
3.
- 31 -
VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase
or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,
SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS (contd.) (NOTE 1)
• VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –40 to +85˚C
(NOTE 5)
VERSIONS
VCC±0.25 V LH28F800BG-L85
LH28F800BGH-L85
(NOTE 6)
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
tPHWL
RP# High Recovery to WE#
Going Low
tELWL
CE# Setup to WE# Going Low
NOTE
UNIT
(NOTE 6)
LH28F800BG-L85 LH28F800BG-L12
LH28F800BGH-L85 LH28F800BGH-L12
VCC±0.5 V
MIN.
85
MAX.
MIN.
90
MAX.
MAX.
ns
2
1
10
10
10
ns
tWLWH WE# Pulse Width
tPHHWH RP# VHH Setup to WE# Going High
2
40
100
40
100
40
100
ns
ns
tSHWH
WP# VIH Setup to WE# Going High
2
100
100
100
ns
tVPWH
VPP Setup to WE# Going High
2
100
100
100
ns
tAVWH
Address Setup to WE# Going High
3
40
40
40
ns
tDVWH
tWHDX
Data Setup to WE# Going High
Data Hold from WE# High
3
40
5
40
5
40
5
ns
ns
tWHAX
tWHEH
Address Hold from WE# High
CE# Hold from WE# High
5
10
5
10
5
10
ns
ns
tWHWL
WE# Pulse Width High
30
tWHRL
WE# High to RY/BY# Going Low
tWHGL
Write Recovery before Read
tQVVL
tQVPH
tQVSL
VPP Hold from Valid SRD,
RY/BY# High
RP# VHH Hold from Valid SRD,
RY/BY# High
WP# VIH Hold from Valid SRD,
RY/BY# High
1
MIN.
120
1
30
90
µs
30
90
ns
90
ns
0
0
0
ns
2, 4
0
0
0
ns
2, 4
0
0
0
ns
2, 4
0
0
0
ns
NOTES :
1.
2.
3.
4.
Read timing characteristics during block erase and word
write operations are the same as during read-only
operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations.
Sampled, not 100% tested.
Refer to Table 3 for valid AIN and DIN for block erase or
word write.
VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase
or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,
SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).
5.
6.
- 32 -
See Fig. 8 "Transient Input/Output Reference
Waveform" and Fig. 10 "Transient Equivalent Testing
Load Circuit" (High Seed Configuration) for testing
characteristics.
See Fig. 9 "Transient Input/Output Reference
Waveform" and Fig. 10 "Transient Equivalent Testing
Load Circuit" (Standard Configuration) for testing
characteristics.
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
(NOTE 1) (NOTE 2)
(NOTE 3)
(NOTE 4)
(NOTE 5)
(NOTE 6)
VIH
AIN
AIN
ADDRESSES (A)
VIL
tAVAV
tAVWH tWHAX
VIH
CE# (E)
VIL
tWHEH
tELWL
tWHGL
VIH
OE# (G)
VIL
tWHWL
tWHQV1/2/3/4
VIH
WE# (W)
tWLWH
tDVWH
tWHDX
VIL
VIH
DATA (D/Q)
High Z
VIL
DIN
DIN
tPHWL
Valid
SRD
tWHRL
VOH
RY/BY# (R)
VOL
tSHWH
tQVSL
tPHHWH
tQVPH
tVPWH
tQVVL
VIH
WP# (S)
VIL
VHH
RP# (P)
VIH
VIL
VPPH1/2/3
VPP (V)
VPPLK
VIL
NOTES :
1.
2.
3.
4.
5.
6.
VCC power-up and standby.
Write block erase or word write setup.
Write block erase confirm or valid address and data.
Automated erase or program delay.
Read status register data.
Write Read Array command.
Fig. 12 AC Waveform for WE#-Controlled Write Operations
- 33 -
DIN
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C or –40 to +85˚C
LH28F800BG-L85
LH28F800BGH-L85
VERSIONS
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
MAX.
LH28F800BG-L12
LH28F800BGH-L12 UNIT
NOTE
MIN.
120
MIN.
150
MAX.
2
1
1
µs
0
0
ns
ns
tPHEL
RP# High Recovery to CE# Going Low
tWLEL
WE# Setup to CE# Going Low
tELEH
tPHHEH
tSHEH
CE# Pulse Width
RP# VHH Setup to CE# Going High
WP# VIH Setup to CE# Going High
2
2
70
100
100
70
100
100
ns
ns
ns
tVPEH
tAVEH
VPP Setup to CE# Going High
Address Setup to CE# Going High
2
3
100
50
100
50
ns
ns
tDVEH
Data Setup to CE# Going High
3
50
50
ns
tEHDX
Data Hold from CE# High
5
5
ns
tEHAX
Address Hold from CE# High
5
5
ns
tEHWH
tEHEL
WE# Hold from CE# High
CE# Pulse Width High
0
25
0
25
ns
ns
tEHRL
CE# High to RY/BY# Going Low
tEHGL
tQVVL
Write Recovery before Read
VPP Hold from Valid SRD, RY/BY# High
tQVPH
tQVSL
100
100
ns
2, 4
0
0
0
0
ns
ns
RP# VHH Hold from Valid SRD, RY/BY# High
WP# VIH Hold from Valid SRD, RY/BY# High
2, 4
2, 4
0
0
0
0
ns
ns
In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold,
and inactive WE# times should be measured relative to
the CE# waveform.
Sampled, not 100% tested.
Refer to Table 3 for valid AIN and DIN for block erase or
word write.
4.
NOTES :
1.
2.
3.
- 34 -
VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase
or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,
SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (contd.) (NOTE 1)
• VCC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C
LH28F800BG-L85
LH28F800BGH-L85
VERSIONS
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
NOTE
MIN.
100
2
MAX.
LH28F800BG-L12
LH28F800BGH-L12 UNIT
MIN.
MAX.
130
ns
tPHEL
RP# High Recovery to CE# Going Low
1
1
tWLEL
WE# Setup to CE# Going Low
0
0
ns
tELEH
CE# Pulse Width
70
70
ns
tPHHEH
tSHEH
RP# VHH Setup to CE# Going High
WP# VIH Setup to CE# Going High
2
2
100
100
100
100
ns
ns
tVPEH
tAVEH
VPP Setup to CE# Going High
Address Setup to CE# Going High
2
3
100
50
100
50
ns
ns
tDVEH
Data Setup to CE# Going High
3
50
50
ns
tEHDX
Data Hold from CE# High
5
5
ns
tEHAX
Address Hold from CE# High
5
5
ns
tEHWH
tEHEL
WE# Hold from CE# High
CE# Pulse Width High
0
25
0
25
ns
ns
tEHRL
CE# High to RY/BY# Going Low
tEHGL
tQVVL
Write Recovery before Read
VPP Hold from Valid SRD, RY/BY# High
tQVPH
tQVSL
100
µs
100
ns
2, 4
0
0
0
0
ns
ns
RP# VHH Hold from Valid SRD, RY/BY# High
WP# VIH Hold from Valid SRD, RY/BY# High
2, 4
2, 4
0
0
0
0
ns
ns
In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold,
and inactive WE# times should be measured relative to
the CE# waveform.
Sampled, not 100% tested.
Refer to Table 3 for valid AIN and DIN for block erase or
word write.
4.
NOTES :
1.
2.
3.
- 35 -
VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase
or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,
SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (contd.) (NOTE 1)
• VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –40 to +85˚C
(NOTE 5)
VERSIONS
VCC±0.25 V LH28F800BG-L85
LH28F800BGH-L85
(NOTE 6)
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
tPHEL
RP# High Recovery to CE#
Going Low
tWLEL
tELEH
tPHHEH
tSHEH
NOTE
UNIT
(NOTE 6)
LH28F800BG-L85 LH28F800BG-L12
LH28F800BGH-L85 LH28F800BGH-L12
VCC±0.5 V
MIN.
85
MAX.
MIN.
90
MAX.
MAX.
ns
2
1
WE# Setup to CE# Going Low
0
0
0
ns
CE# Pulse Width
RP# VHH Setup to CE# Going High
WP# VIH Setup to CE# Going High
2
2
50
100
100
50
100
100
50
100
100
ns
ns
ns
tVPEH
tAVEH
VPP Setup to CE# Going High
Address Setup to CE# Going High
2
3
100
40
100
40
100
40
ns
ns
tDVEH
tEHDX
Data Setup to CE# Going High
Data Hold from CE# High
3
40
5
40
5
40
5
ns
ns
tEHAX
Address Hold from CE# High
5
5
5
ns
tEHWH
WE# Hold from CE# High
0
0
0
ns
tEHEL
CE# Pulse Width High
25
tEHRL
tEHGL
CE# High to RY/BY# Going Low
Write Recovery before Read
tQVVL
VPP Hold from Valid SRD,
RY/BY# High
tQVPH
tQVSL
RP# VHH Hold from Valid SRD,
RY/BY# High
WP# VIH Hold from Valid SRD,
RY/BY# High
1
MIN.
120
1
25
90
µs
25
90
ns
90
0
0
0
ns
ns
2, 4
0
0
0
ns
2, 4
0
0
0
ns
2, 4
0
0
0
ns
NOTES :
1.
2.
3.
4.
In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold,
and inactive WE# times should be measured relative to
the CE# waveform.
Sampled, not 100% tested.
Refer to Table 3 for valid AIN and DIN for block erase or
word write.
VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase
or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,
SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).
5.
6.
- 36 -
See Fig. 8 "Transient Input/Output Reference
Waveform" and Fig. 10 "Transient Equivalent Testing
Load Circuit" (High Seed Configuration) for testing
characteristics.
See Fig. 9 "Transient Input/Output Reference
Waveform" and Fig. 10 "Transient Equivalent Testing
Load Circuit" (Standard Configuration) for testing
characteristics.
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
(NOTE 1) (NOTE 2)
(NOTE 3)
(NOTE 4)
(NOTE 5)
(NOTE 6)
VIH
AIN
ADDRESSES (A)
VIL
AIN
tAVAV
tAVEH
tEHAX
VIH
WE# (W)
VIL
tEHWH
tWLEL
tEHGL
VIH
OE# (G)
VIL
tEHEL
tEHQV1/2/3/4
VIH
CE# (E)
tELEH
tDVEH
tEHDX
VIL
VIH
DATA (D/Q)
High Z
VIL
DIN
DIN
tPHEL
Valid
SRD
tEHRL
VOH
RY/BY# (R)
VOL
tSHEH
tQVSL
tPHHEH
tQVPH
tVPEH
tQVVL
VIH
WP# (S)
VIL
VHH
RP# (P)
VIH
VIL
VPPH1/2/3
VPP (V)
VPPLK
VIL
NOTES :
1.
2.
3.
4.
5.
6.
VCC power-up and standby.
Write block erase or word write setup.
Write block erase confirm or valid address and data.
Automated erase or program delay.
Read status register data.
Write Read Array command.
Fig. 13 AC Waveform for CE#-Controlled Write Operations
- 37 -
DIN
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.7 RESET OPERATIONS
VOH
RY/BY# (R)
VOL
VIH
RP# (P)
VIL
tPLPH
(A) Reset During Read Array Mode
VOH
RY/BY# (R)
VOL
tPLRH
VIH
RP# (P)
VIL
tPLPH
(B) Reset During Block Erase or Word Write
2.7 V/3.3 V/5 V
VCC
VIL
t235VPH
VIH
RP# (P)
VIL
(C) RP# Rising Timing
Fig. 14 AC Waveform for Reset Operation
Reset AC Specifications (NOTE 1)
SYMBOL
tPLPH
tPLRH
t235VPH
PARAMETER
RP# Pulse Low Time
(If RP# is tied to VCC, this
specification is not applicable)
RP# Low to Reset during
Block Erase or Word Write
VCC 2.7 V to RP# High
VCC 3.0 V to RP# High
VCC 4.5 V to RP# High
NOTE
VCC = 2.7 to 3.6 V
MIN.
MAX.
100
100
2, 3
4
VCC = 3.3±0.3 V
MIN.
MAX.
22
100
VCC = 5.0±0.5 V
MIN.
MAX.
100
20
100
ns
12
100
UNIT
µs
ns
NOTES :
1.
2.
These specifications are valid for all product versions
(packages and speeds).
If RP# is asserted while a block erase or word write
operation is not executing, the reset will complete within
100 ns.
3.
4.
- 38 -
A reset time, tPHQV, is required from the latter of RY/BY#
or RP# going high until outputs are valid.
When the device power-up, holding RP#-low minimum
100 ns is required after VCC has been in predefined
range and also has been in stable there.
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.8 BLOCK ERASE AND WORD WRITE PERFORMANCE (NOTE 3, 4)
• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C or –40 to +85˚C
VPP = 2.7 to 3.6 V
SYMBOL
PARAMETER
NOTE
MIN. TYP.(NOTE 1) MAX.
32 k-Word
2
44.6
tWHQV1 Word Write Block
tEHQV1 Time
4 k-Word
2
45.9
Block
32 k-Word
2
1.46
Block Write Block
Time
4 k-Word
2
0.19
Block
32 k-Word
2
1.14
tWHQV2 Block Erase Block
tEHQV2 Time
4 k-Word
2
0.38
Block
tWHRH1 Word Write Suspend
7
8
tEHRH1 Latency Time to Read
tWHRH2 Erase Suspend Latency
18
22
tEHRH2 Time to Read
• VCC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C
VPP = 3.3±0.3 V
SYMBOL
PARAMETER
NOTE
MIN. TYP.(NOTE 1) MAX.
32 k-Word
2
44
tWHQV1 Word Write Block
tEHQV1 Time
4 k-Word
2
45
Block
32 k-Word
2
1.44
Block Write Block
Time
4 k-Word
2
0.19
Block
32 k-Word
2
1.11
tWHQV2 Block Erase Block
tEHQV2 Time
4 k-Word
2
0.37
Block
tWHRH1 Word Write Suspend
6
7
tEHRH1 Latency Time to Read
tWHRH2 Erase Suspend Latency
16.2
20
tEHRH2 Time to Read
VPP = 5.0±0.5 V
MIN. TYP.(NOTE 1) MAX.
VPP = 12.0±0.6 V
UNIT
MIN. TYP.(NOTE 1) MAX.
17.7
12.6
µs
26.1
24.5
µs
0.58
0.42
s
0.11
0.11
s
0.61
0.51
s
0.32
0.31
s
6
8
6
7
µs
11
14
11
14
µs
VPP = 5.0±0.5 V
MIN. TYP.(NOTE 1) MAX.
VPP = 12.0±0.6 V
UNIT
MIN. TYP.(NOTE 1) MAX.
17.3
12.3
µs
25.6
24
µs
0.57
0.41
s
0.11
0.1
s
0.59
0.5
s
0.31
0.3
s
5
7
5
6
µs
9.6
12
9.6
12
µs
NOTES :
1.
2.
Typical values measured at TA = +25˚C and nominal
voltages. Subject to change based on device
characterization.
Excludes system-level overhead.
3.
4.
- 39 -
These performance numbers are valid for all speed
versions.
Sampled, not 100% tested.
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.8 BLOCK ERASE AND WORD WRITE PERFORMANCE (contd.) (NOTE 3, 4)
• VCC = 5.0 V±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –40 to +85˚C
VPP = 5.0±0.5 V
SYMBOL
PARAMETER
NOTE
MIN. TYP.(NOTE 1) MAX.
tWHQV1
Word Write Time
tEHQV1
Block Write Time
tWHQV2
tEHQV2
tWHRH1
tEHRH1
tWHRH2
tEHRH2
Block Erase Time
32 k-Word Block
4 k-Word Block
2
2
12.2
18.3
VPP = 12.0±0.6 V
MIN. TYP.(NOTE 1) MAX.
UNIT
8.4
17
µs
µs
32 k-Word Block
2
0.4
0.28
s
4 k-Word Block
2
0.08
0.07
s
32 k-Word Block
2
0.46
0.39
s
4 k-Word Block
2
0.26
0.25
s
Word Write Suspend Latency Time to Read
Erase Suspend Latency Time to Read
5
6
4
5
µs
9.6
12
9.6
12
µs
NOTES :
1.
2.
Typical values measured at TA = +25˚C and nominal
voltages. Subject to change based on device
characterization.
Excludes system-level overhead.
3.
4.
- 40 -
These performance numbers are valid for all speed
versions.
Sampled, not 100% tested.
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
7 ORDERING INFORMATION
Product line designator for all SHARP Flash products
L H 2 8 F 8 0 0 B G (H) E - T L 8 5
Device Density
800 = 8 M-bit
Access Speed (ns)
85 : 85 ns (5.0±0.25 V), 90 ns (5.0±0.5 V)
100 ns (3.3±0.3 V), 120 ns (2.7 to 3.6 V)
12 : 120 ns (5.0±0.5 V), 130 ns (3.3±0.3 V),
150 ns (2.7 to 3.6 V)
Architecture
B = Boot Block
Block Locate Option
T = Top Boot
B = Bottom Boot
Power Supply Type
G = SmartVoltage Technology
Operating Temperature
Blank = 0 to +70°C
H = – 40 to +85°C
OPTION
ORDER CODE
Package
E = 48-pin TSOP (I) (TSOP048-P-1220) Normal bend
R = 48-pin TSOP (I) (TSOP048-P-1220) Reverse bend
B = 48-ball CSP (FBGA048-P-0808)
VCC
VALID OPERATIONAL COMBINATIONS
= 2.7 to 3.6 V
VCC = 3.3±0.3 V
VCC = 5.0±0.5 V
VCC = 5.0±0.25 V
50 pF load,
50 pF load,
100 pF load,
30 pF load,
1.35 V I/O Levels
1.5 V I/O Levels
TTL I/O Levels
1.5 V I/O Levels
85 ns
1
LH28F800BGXX-XL85
120 ns
100 ns
90 ns
2
LH28F800BGXX-XL12
150 ns
130 ns
120 ns
- 41 -
PACKAGING
48
24
0.1
12.0 ±0.2
0.10
0.5 TYP.
M
1
48 _ 0.2±0.08
48 TSOP (TSOP048-P-1220)
25
1.2MAX.
1.0 ±0.1
0.125
18.4 ±0.2
Package base plane
19.0 ±0.1
0.1±0.1
0.125 ±0.05
20.0±0.3
PACKAGING
48 CSP (FBGA048-P-0808)
A
8.00
+ 0.2
B
1.2MAX.
/ / 0.1 S
∗0.4TYP.
S
∗Land hole diameter
0.35±0.05
for ball mounting
+0.2
8.00
0.1 S
2.0TYP.
0.4TYP.
0.4TYP.
0.8TYP.
C
0.8TYP.
F
D
A
8
1
1.2TYP.
0.45±0.03
0.30
M
S
AB
0.15
M
S
CD