TI CY74FCT163543APVC 16-bit latched transceiver Datasheet

1CY74FCT163543
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT163543
16-Bit Latched Transceiver
SCCS063A - June 1997 - Revised April 2000
Features
Functional Description
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 5.1 ns
• Latch-up performance exceeds JEDEC standard no. 17
• ESD > 2000V per MIL-STD-883D, Method 3015
• Typical output skew < 250 ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical Volp (ground bounce) performance exceeds Mil
Std 883D
• VCC = 2.7V to 3.6V
The CY74FCT163543 is a 16-bit, high-speed, low power latched
transceiver that is organized as two independent 8-bit D-type latched
transceivers, containing two sets of eight D-type latches with separate
Latch Enable (LEAB, LEAB) and Output Enable (OEAB, OEAB) controls for each set to permit independent control of inputting and outputting in either direction of data flow. For data flow from A to B, for
example, the A-to-B input Enable (CEAB) must be LOW in order to
enter data from A or to take data from B, as indicated in the truth table.
With CAEB LOW, a LOW signal on the A-to-B Latch Enable (LEAB)
makes the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the LEAB signal puts the A latches in the storage mode
and their outputs no longer follow the A inputs. With CEAB and OEAB
both LOW, the three-state B output buffers are active and reflect the
data present at the output of the A latches. Control of data from B to
A is similar, but uses CEAB, LEAB, and OEAB inputs.
The CY74FCT163543 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The inputs
and outputs are capable of being driven by 5.0V buses, allowing them to be used in mixed voltage systems as translators.
The outputs are also designed with a power off disable feature
enabling them to be used in applications requiring live insertion. Flow-through pinout and small shrink packaging simplify board
design.
Logic Block Diagrams
Pin Configuration
1OEBA
Top View
SSOP/TSSOP
1CEBA
1LEBA
1OEAB
1OEAB
1LEAB
1CEAB
1CEAB
1LEAB
C
D
1A 1
GND
1A 1
1B 1
C
D
1A 2
V CC
1A 3
1A 4
1A 5
GND
1A 6
TO 7 OTHER CHANNELS
1A 7
1A 8
2OEBA
2A 1
2CEBA
2A 2
2LEBA
2CEAB
2A 3
GND
2A 4
2A 5
2LEAB
2A 6
2OEAB
C
D
2A 1
C
D
2B 1
V CC
2A 7
2A 8
GND
2CEAB
2LEAB
2OEAB
1
2
56
55
3
4
5
6
7
8
9
54
53
52
51
50
49
48
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEBA
1LEBA
1CEBA
GND
1B 1
1B 2
VCC
1B 3
1B 4
1B 5
GND
1B 6
1B 7
1B 8
2B 1
2B 2
2B 3
GND
2B 4
2B 5
2B 6
VCC
2B 7
2B 8
GND
2CEBA
2LEBA
2OEBA
TO 7 OTHER CHANNELS
Copyright
© 2000, Texas Instruments Incorporated
CY74FCT163543
Function Table[1]
Pin Description
Name
Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
CEAB
A-to-B Enable Input (Active LOW)
CEBA
B-to-A Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input (Active LOW)
LEBA
B-to-A Latch Enable Input (Active LOW)
A
A-to-B Data Inputs or B-to-A Three-State Outputs
B
B-to-A Data Inputs or A-to-B Three-State Outputs
Latch
Status
Inputs
Output
Buffers
CEAB
LEAB
OEAB
A to B
B
H
X
X
Storing
High Z
X
H
X
Storing
X
X
X
H
X
High Z
L
L
L
Transparent
Current A
Inputs
L
H
L
Storing
Previous A
Inputs[2]
Maximum Ratings[3, 4]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Power Dissipation .......................................................... 1.0W
Storage Temperature .............................. −55°C to +125°C
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied .......................................... −55°C to +125°C
Operating Range
Supply Voltage Range ..................................... 0.5V to +4.6V
Range
DC Input Voltage .................................................−0.5V to +7.0V
Industrial
DC Output Voltage ..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin) ...........................−60 to +120 mA
2
Ambient
Temperature
VCC
−40°C to +85°C
2.7V to 3.6V
CY74FCT163543
Electrical Characteristics Over the Operating Range VCC=2.7V to 3.6V
Parameter
Description
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Input Hysteresis[6]
Test Conditions
Min.
Typ.[5]
2.0
Max.
Unit
5.5
V
0.8
100
VIK
Input Clamp Diode Voltage
VCC=Min.,
IIN=−18 mA
−1.2
V
IIH
Input HIGH Current
VCC=Max.,
VCC=5.5V
+1
µA
IIL
Input LOW Current
VCC=Max.,
VCC=GND
+1
µA
IOZH
High Impedance Output Current VCC=Max.,
(Three-State pins)
VOUT=5.5V
+1
µA
IOZL
High Impedance Output Current VCC=Max.,
(Three-State pins)
VOUT=GND
+1
µA
IODL
Output LOW Current[7]
VCC=3.3V,
VOUT=1.5V
VIN=VIH or VIL,
50
90
200
mA
IODH
Output HIGH Current[7]
VCC=3.3V,
VOUT=1.5V
VIN=VIH or VIL,
−36
−60
−110
mA
VOH
Output HIGH Voltage
VCC=Min.,
IOH=−0.1 mA
VOL
Output LOW Voltage
−0.7
V
mV
VCC−0.2
V
VCC=3.0V,
IOH=−8 mA
2.4
3.0
VCC=3.0V,
IOH=−24 mA
2.0
3.0
VCC=Min.,
IOL=0.1mA
VCC=Min.,
IOL=24mA
IOS
Short Circuit Current[7]
VCC=Max.,
VOUT=GND
IOFF
Power-Off Disable
VCC=0V,
VOUT<4.5V
0.2
3.0
−60
−135
V
0.5
−240
mA
+100
µA
Notes:
1. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA, and OEBA.
2. Data prior to LEAB LOW-to-HIGH Transition H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = High Impedance.
3. Operation beyond the limits set forth may impair the useful life of the device. Unless noted, these limits are over the operating free-air temperature range.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
5. Typical values are at VCC= 3.3V, TA= +25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
Capacitance[6] (TA = +25˚C, f = 1.0 MHz)
Parameter
Description
Test Conditions
Typ.[5]
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6.0
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8.0
pF
3
CY74FCT163543
Power Supply Characteristics
Parameter
Description
Test Conditions
Typ.[5]
Max.
Unit
ICC
Quiescent Power Supply Current VCC=Max.
VIN≤0.2V,
VIN≥VCC−0.2V
0.1
10
µA
∆ICC
Quiescent Power Supply Current
(TTL inputs HIGH)
VCC=Max.
VIN=VCC-0.6V[8]
2.0
30
µA
ICCD
Dynamic Power Supply
Current[9]
VCC=Max., One Input
Toggling, 50% Duty Cycle,
Outputs Open, OE=GND
VIN=VCC or
VIN=GND
50
75
µA/MHz
IC
Total Power Supply Current[10]
VCC=Max., f1=10 MHz,
50% Duty Cycle, Outputs
Open, One Bit Toggling,
OE=GND
VIN=VCC or
VIN=GND
0.5
0.8
mA
VIN=VCC-0.6V or
VIN=GND
0.5
0.8
mA
VCC=Max., f1=2.5 MHz,
50% Duty Cycle, Outputs
Open, Sixteen Bits Toggling,
OE=GND
VIN=VCC or
VIN=GND
2.0
3.0[11]
mA
VIN=VCC-0.6V or
VIN=GND
2.0
3.3[11]
mA
Switching Characteristics Over the Operating Range VCC = 3.0V to 3.6V[12,15]
CY74FCT163543A
Parameter
Description
CY74FCT163543C
Min.
Max.
Min.
Max.
Unit
Fig. No.[13]
tPLH
tPHL
Propagation Delay, Transparent Mode
A to B or B to A
1.5
6.5
1.5
5.1
ns
1, 3
tPLH
tPHL
Propagation Delay
LEBA to A, LEAB to B
1.5
8.0
1.5
5.6
ns
1, 5
tPZH
tPZL
Output Enable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B
1.5
9.0
1.5
7.8
ns
1, 7, 8
tPHZ
tPLZ
Output Disable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B
1.5
7.5
1.5
6.5
ns
1, 7, 8
tSU
Set-up Time HIGH or LOW
A or B to LEAB or LEBA
2.0
—
2.0
—
ns
4
tH
Hold Time HIGH or LOW
A or B to LEAB or LEBA
2.0
—
2.0
—
ns
4
tW
LEBA or LEAB Pulse Width LOW
4.0
—
4.0
—
ns
5
—
0.5
—
0.5
ns
—
tSK(O)
Output
Skew[14]
Notes:
8. Per TTL driven input; all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10.
= IQUIESCENT + IINPUTS + IDYNAMIC
IC
= ICC+∆ICCDHNT+ICCD(f0NC /2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
= Duty Cycle for TTL inputs HIGH
DH
= Number of TTL inputs at DH
NT
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
f0
= Number of clock inputs changing at f1
NC
f1
= Input signal frequency
= Number of inputs changing at f1
N1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
14. Skew between any two outputs of the same package switching in the same directional. This parameter is ensured by design.
15. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%.
4
CY74FCT163543
Ordering Information CY74FCT163543
Speed
(ns)
5.1
6.5
Package
Name
Ordering Code
Package Type
CY74FCT163543CPACT
Z56
56-Lead (240-Mil) TSSOP
CY74FCT163543CPVC/PVCT
O56
56-Lead (300-Mil) SSOP
CY74FCT163543APVC/PVCT
O56
56-Lead (300-Mil) SSOP
Package Diagrams
56-Lead Shrunk Small Outline Package O56
5
Operating
Range
Industrial
Industrial
CY74FCT163543
Package Diagrams (continued)
56-Lead Thin Shrunk Small Outline Package Z56
6
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Copyright  2000, Texas Instruments Incorporated
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