FUSB2805 USB2.0 High-Speed OTG Transceiver with ULPI Interface Features Description Complies with USB 2.0, OTG Rev 1.3 Supplement, and ULPI Rev 1.1 Specifications Supports 480 Mbps, 12Mbps, and 1.5Mbps USB2.0 Speeds - Integrated Termination Resistors Meet USB2.0 Resistor ECN - Integrated Serializer and Deserializer - Insertion and Removal of Stuffed Bits as Appropriate - USB Clock and Data Recovery to ±150ppm Supports USB OTG Rev 1.3 Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) 15KV ESD, IEC 61000 Board Level, Air Gap Applications Set-Top Box Video Camera, MP3 Player Cell Phone, Digital Still Camera, PDA DVD Recorder, Scanner, Printer The FUSB2805 is a UTMI+ Low-Pin Interface (ULPI) USB2.0 OTG transceiver. It is compliant with the Universal Serial Bus Specification Rev 2.0 (USB2.0), the ULPI Specification Rev. 1.1, and the On-The-Go (OTG) supplement to USB2.0, Rev. 1.3. The FUSB2805 is optimized to connect the USB2.0 host, peripheral, or OTG-controller to the USB connector via the ULPI link. Data can be transmitted and received at high speed (480Mbps), full speed (12Mbps), and low speed (1.5Mbps) through a 12-bit (SDR) interface. Related Resources UTMI+ Low Pin Interface Specification (ULPI), Revision 1.1, October 20, 2004. http://www.ulpi.org UTMI+ Specification, Revision 1.0, February 22, 2004. http://www.ulpi.org For additional performance information, please contact [email protected]. Ordering Information Part Number Top Mark Operating Temperature Range Package FUSB2805MLX FUSB2805 -40 to +85°C 32-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO-220 © 2008 Fairchild Semiconductor Corporation FUSB2805 • Rev. 1.0.1 www.fairchildsemi.com FUSB2805 — USB2.0 High-Speed OTG Transceiver with ULPI Interface October 2010 Clo c k D 0-D 7 D IR S TP NX T ULP I Interf ac e Co ntro ller US B D ata S erializer US B 2.0 A TX DP Reg is ter M ap US B D ata D es erializer Term inatio n Res is to rs DM CHIP _S E LE CT_N VDD 3V3 ID _P ULLUP G lo b al Clo c ks P LL 50k O TG M o d ule Freq uenc y S elec t 400k CFG 1 ID ID D etec to r CLK IN V B US V IO 0.1µF Res et_N V CC3V 3 0.1 µF POR P o wer-O n Res et 4.7µF E x ternal V B US & Fault D etec tio n Co ntro l B lo c k V CC1V 2 0.1 µF 4.7µF V CC V o ltag e Reg ulato r IC (Flo at) A nalo g Ref erenc e M o d ule VR EF Tes t (Flo at) Figure 1. Functional Block Diagram D1 D2 CHIP_SELECT_N D3 VIO CGF1 CLOCK D4 D5 Pin Configuration 32 31 30 29 28 27 26 25 1 24 D6 D0 2 23 D7 VIO 3 22 NXT DM 4 21 STP RREF 5 20 VIO DP 6 19 RESET_N VCC 7 18 DIR ID 8 17 VDD1V2 9 10 11 12 13 14 15 16 VCC TEST(FLOAT) FAULT VCC3V3 VBUS PSW CLIKIN IC(FLOAT) GND Exposed DiePad PSW 10 0k FA ULT RRE F FUSB2805 — USB2.0 High-Speed OTG Transceiver with ULPI Interface Block Diagram Figure 2. Pin Assignments (Through View) © 2008 Fairchild Semiconductor Corporation FUSB2805 • Rev. 1.0.1 www.fairchildsemi.com 2 Symbol Chip Select_N (1) Type I Description Active LOW. HIGH – ULPI pin three-stated; LOW – ULPI operates normally. TTL compatible; CMOS input with hysteresis. RREF AI/O Resistor reference. Connect through 12kΩ ±1% to GND. DM AI/O USB D- pin. USB mode: data minus (D-) pin of the USB cable. DP AI/O USB D+ pin. USB mode: data plus (D+) pin of the USB cable. FAULT I FAULT is used to signal a VBUS over-current/over-voltage condition from an external SMPS or power management IC. The link must enable this function via the ExternalVbusFault register bit and the polarity must be set via the ExternalVbusActiveLow register bit. ID I Identification (ID) pin of the micro-USB cable. TTL; if not used, connect to 3V3. VCC P Input supply voltage or battery source. PSW O Controls an external, active HIGH, VBUS power switch/charge pump and/or an SMPS charger IC. An external 100KΩ pull-down resistor is required. Open source, slew-ratecontrolled output; this pin is referenced to VCC3V3. VBUS AI/O Should be connected to the VBUS pin of the USB cable. Leave open circuit if not used. An internal 90KΩ ±11% pull-down resistor is present on this pin. VCC3V3 P 3.3V regulator output requiring capacitors. Internally powers OTG, analog core, and ATX. CLKIN I Clock input; frequency depends on the CFG1 pin. This is a digital input buffer, not analog for a crystal. I.C. I/O Internally connected; float pin. TEST I/O CFG1 I Configures the clock frequency; 0: input is 19.2MHz. 1: input is 26MHz. Internally connected; float pin. VDD1V2 P 1.2V regulator output requiring capacitors. Internally powers the digital core and analog core. VIO P Input I/O supply rail; 0.1µF capacitor connected to power input. Reset_N I Connect to VIO when not used. Resets the transceiver; active LOW. GND P Connect to ground. DIR O ULPI direction output signal. STP I ULPI stop input signal; CMOS input. NXT O ULPI next output signal. D7 I/O ULPI data pin 7; three-state output. D6 I/O ULPI data pin 6; three-state output. D5 I/O ULPI data pin 5; three-state output. D4 I/O ULPI data pin 4; three-state output. D3 I/O ULPI data pin 3; three-state output. D2 I/O ULPI data pin 2; three-state output. D1 I/O ULPI data pin 1; three-state output. D0 I/O ULPI data pin 0; three-state output. CLOCK O 60MHz clock output when digital 19.2MHz (or 26MHz) clock is applied; Push-pull output. FUSB2805 — USB2.0 High-Speed OTG Transceiver with ULPI Interface Pin Definitions Notes: 1. I=input; O=output; I/O=digital input/output; OD=open-drain output; AI/O=analog input/output; P=power or ground. 2. Per USB2.0, below a supply of 2.97V, USB full-speed and low-speed transactions are not guaranteed; although some devices may continue to function with the FUSB2805 at the lower supply rail. © 2008 Fairchild Semiconductor Corporation FUSB2805 • Rev. 1.0.1 www.fairchildsemi.com 3 5.25 MIN (3.75) 0.15 C 3.10 MAX 5.10 4.90 (2X) B (0.60 ) A (0.48 ) 5.25 MIN 5.10 4.90 3.10 MAX (3.75 ) PIN #1 IDENT (0.21 ) X4 0.15 C (2X) TOP VIEW 0.28 MAX X32 0.50 RECOMMENDED LAND PATTERN 0.80 MAX 0.10 C (0.20) 32X 0.08 C 0.05 0.00 SEATING PLANE C SIDE VIEW NOTES: A. EXCEPT WHERE NOTED, CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION WHHD-6. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. D. LAND PATTERN PER IPC SM-782. E. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR TIE BAR PROTRUSIONS. F. DRAWING FILENAME: MKT-MLP32Brev1. 3.20 3.00 A 1 PIN #1 IDENT 8 9 0. 49 32 0.50 0.30 FUSB2805 — USB2.0 High-Speed OTG Transceiver with ULPI Interface Physical Dimensions 0.50 3.20 3.00 (DATUM B) (DATUM A) 25 16 17 24 0.50 32X 0.18-0.30 0.10 0.05 C A B C BOTTOM VIEW Figure 23. 32-Lead, Molded Leadless Package (MLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation FUSB2805 • Rev. 1.0.1 www.fairchildsemi.com 48 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 2Cool AccuPower AX-CAP* BitSiC Build it Now CorePLUS CorePOWER CROSSVOLT CTL Current Transfer Logic DEUXPEED® Dual Cool™ EcoSPARK® EfficientMax ESBC F-PFS FRFET® SM Global Power Resource GreenBridge Green FPS Green FPS e-Series Gmax GTO IntelliMAX ISOPLANAR Making Small Speakers Sound Louder and Better™ MegaBuck MICROCOUPLER MicroFET MicroPak MicroPak2 MillerDrive MotionMax Motion-SPM mWSaver OptoHiT OPTOLOGIC® OPTOPLANAR® ® Fairchild® Fairchild Semiconductor® FACT Quiet Series FACT® FAST® FastvCore FETBench FlashWriter®* FPS PowerTrench® PowerXS™ Programmable Active Droop QFET® QS Quiet Series RapidConfigure Saving our world, 1mW/W/kW at a time™ SignalWise SmartMax SMART START Solutions for Your Success SPM® STEALTH SuperFET® SuperSOT-3 SuperSOT-6 SuperSOT-8 SupreMOS® SyncFET Sync-Lock™ ® * The Power Franchise® TinyBoost TinyBuck TinyCalc TinyLogic® TINYOPTO TinyPower TinyPWM TinyWire TranSiC TriFault Detect TRUECURRENT®* SerDes UHC® Ultra FRFET UniFET VCX VisualMax VoltagePlus XS™ ® * Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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