Fairchild FAN9612MX Interleaved dual bcm pfc controller Datasheet

PRELIMINARY
FAN9612
Interleaved Dual BCM PFC Controller
Features
Description
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Low Total Harmonic Distortion, High Power Factor
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Minimum Restart Timer Frequency to Avoid Audible
Noise
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Maximum Switching Frequency Clamp
The FAN9612 Interleaved Dual Boundary-ConductionMode
(BCM)
Power-Factor-Correction
Controller
operates two parallel-connected boost power trains 180º
out of phase.
Interleaving extends the maximum
practical power level of the control technique from about
300W to greater than 800W. Unlike the continuous
conduction mode (CCM) technique often used at higher
power levels, BCM offers inherent zero-current switching
of the boost diodes (no reverse-recovery losses), which
permits the use of less expensive diodes without
sacrificing efficiency. Furthermore, the input and output
filters can be made smaller due to ripple current
cancellation and effective doubling of the switching
frequency.
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Open Feedback Protection
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Low Start-Up Current of 80-µA Typical
180° Out of Phase Synchronization
Automatic Phase Disable at Light Load
1.8A Sink, 0.8A Source, High Current Gate Drivers
Trans-conductance (gM) Error Amplifier
2
Voltage-Mode Control with (VIN) Feed Forward
Closed-Loop Soft-Start with User-Programmable
Soft-Start Time for Reduced Overshoot
Brown-Out Protection with Soft-Recovery
Non-Latching OVP on FB pin and Latching Second
Level Protection on OVP Pin
Over-Current & Power-Limit Protection for Each
Phase
Works with DC, 50Hz to 400Hz ac Inputs
Applications
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100-1000W Off-line Power Supplies
Large Screen LCD-TV, PDP-TV, RP-TV Power
High-End Desktop PC and Server Power Supplies
80-PLUS Certified Equipment
The converters operate with variable frequency which is
a function of the load and the instantaneous input /
output voltages. The switching frequency is limited
between 18kHz and 600kHz. The Pulse Width
Modulators implement voltage-mode control with input
voltage feed forward. When configured for PFC
applications, the slow voltage regulation loop results in
constant on-time operation within a line cycle. This PWM
method combined with the BCM operation of the boost
converters provides automatic power factor correction.
The FAN9612 offers bias UVLO, input brown-out, input
over-voltage, over-current, open feedback, overtemperature, output over-voltage and redundant latching
over-voltage protections. Furthermore, the converters’
output power is limited independently of the input RMS
voltage. Synchronization between the power stages is
maintained under all operating conditions. The FAN9612
is available in Lead(Pb)-Free 16-lead SOIC package.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
ZCD2
ZCD1
Simplified Application Diagram
www.fairchildsemi.com
FAN9612 — Interleaved Dual BCM PFC Controller
February 2009
PRELIMINARY
Part Number
Package
Packing Method
Packing (Quantity)
FAN9612M
SOIC-16
Tube / Box
48 / 4800
FAN9612MX
SOIC-16
Tape & Reel
2500
Notes:
All packages are lead free per JEDEC: J-STD-020B standard.
Package Outlines
ZCD1
1
16
CS1
ZCD2
2
15
CS2
5VB
3
14
VDD
MOT
4
13
DRV1
AGND
5
12
DRV2
SS
6
11
PGND
COMP
7
10
VIN
FB
8
9
OVP
FAN9612 — Interleaved Dual BCM PFC Controller
Ordering Information
Figure 1. SOIC-16 (Top View)
Thermal Resistance Table
Thermal Resistance
Package
Suffix
16-Lead SOIC
M
(1)
(2)
ΘJA
ΘJL
35°C/W
50 – 120°C/W
(3)
Notes:
1. Typical ΘJL is specified from semiconductor junction to lead.
2. Typical ΘJA is dependent on the PCB design and operating conditions, such as air flow. The range of values
covers a variety of operating conditions utilizing natural convection with no heatsink on the package.
3. This typical range is an estimate; actual values depend on the application.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com
2
PRELIMINARY
FAN9612 — Interleaved Dual BCM PFC Controller
Typical Application Diagram
Figure 2. Typical Application Diagram
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com
3
PRELIMINARY
ZCD1
CHANNEL 1
VALLEY DETECTOR
1
SYNCHRONIZATION
A
16
CS1
15
CS2
14
VDD
13
DRV1
12
DRV2
11
PGND
10
VIN
9
OVP
B
RESTART TIMERS
FREQUENCY CLAMPS
ZCD2
CHANNEL 2
VALLEY DETECTOR
2
0.2V
VDD
VDD
5V
5VB
5V
5V
BIAS
3
K1
0.195V
2
VIN
UVLO
IMOT
A
IMOT
MOT
4
R
Q
S
Q
R
Q
A
1.25V
5V
0.195V
AGND
K1
5
2
VIN
IMOT
B
B
S
Q
5V
FAN9612 — Interleaved Dual BCM PFC Controller
Block Diagram
5uA
SS
6
3VREF
COMP
gm
FB
INPUT VOLTAGE SENSE
(Input Voltage Squarer,
Input UVLO, Brown-out)
7
8
PHASE
Management
2uA
PROTECTION LOGIC
(Open FB, Input Protections, OVP,
Latched OVP, Thermal Shutdown)
Figure 3. FAN9612 Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com
4
PRELIMINARY
Pin#
Name
Pin Description
1
ZCD1
Zero current detector for Phase 1 of the interleaved boost power stage.
2
ZCD2
Zero current detector for Phase 2 of the interleaved boost power stage.
3
5VB
5V Bias. Bypass pin for the internal supply which powers all control circuitry on the IC.
4
MOT
Maximum On-Time adjust for the individual power stages.
5
AGND
Analog Ground. Reference potential for all setup signals.
6
SS
7
COMP
8
FB
9
OVP
Output Voltage Monitor for the independent second level latched OVP protection.
10
VIN
Input Voltage Monitor for brown-out protection and input voltage feed forward.
11
PGND
Power Ground connection.
12
DRV2
Gate Drive Output for Phase 2 of the interleaved boost power stage.
13
DRV1
Gate Drive Output for Phase 1 of the interleaved boost power stage.
14
VDD
External Bias Supply for the IC.
15
CS2
Current Sense Input for Phase 2 of the interleaved boost power stage.
16
CS1
Current Sense Input for Phase 1 of the interleaved boost power stage.
Soft-Start Capacitor. Connected to the non-inverting input of the error amplifier.
Compensation-Network connection to the output of the gM error amplifier
Feedback pin to sense the converter’s output voltage; inverting input of the error amplifier.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
FAN9612 — Interleaved Dual BCM PFC Controller
Pin Definitions
www.fairchildsemi.com
5
PRELIMINARY
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD
Supply Voltage to AGND & PGND
-0.3
20.0
V
VBIAS
5VB Voltage to AGND & PGND
-0.3
5.5
V
Voltage On Input Pins to AGND (except FB pin)
-0.3
VBIAS + 0.3
V
Voltage On FB Pin (Current Limited)
-0.3
VDD + 0.8
V
Voltage On Output Pins to PGND (DRV1, DRV2)
-0.3
VDD + 0.3
V
2
A
Gate Drive Output Current (DC)
0.05
A
TL
Lead Soldering Temperature (10 seconds)
+260
ºC
TJ
Junction Temperature
-40
+150
ºC
TSTG
Storage Temperature
-65
+150
ºC
ESD
Electrostatic Discharge
Protection Level
IOH, IOL
Gate Drive Peak Output Current (Transient)
Human Body Model, JEDEC JESD22-A114
2
kV
Charged Device Model, JEDEC JESD22-C101
1
kV
FAN9612 — Interleaved Dual BCM PFC Controller
Absolute Maximum Ratings
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VDD
Parameter
Min.
Typ.
Max.
Unit
Supply Voltage Range
9
12
18
V
Signal Input Voltage
0
5
V
Output Current Sinking (DRV1, DRV2)
1.5
2.0
A
Output Current Sourcing (DRV1, DRV2)
0.8
1.0
A
Boost inductor mismatch
TA
±5%
Operating Ambient Temperature
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
-40
±10%
+125
ºC
www.fairchildsemi.com
6
PRELIMINARY
Unless otherwise noted, VDD = 12V, TJ = -40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VDD = VON – 0.2V
80
110
µA
Output Not Switching
2.5
4
mA
3
5
mA
Supply
ISTART_UP
IDD
IDD_DYM
Start-up Supply Current
Operating Current
Dynamic Operating Current
(4)
fSW = 50 kHz; CLOAD = 2 nF
VON
UVLO Start Threshold Voltage
VDD Increasing
12
12.5
13
V
VOFF
UVLO Stop Threshold Voltage
VDD Decreasing
7.0
7.5
8.0
V
UVLO Hysteresis
5.0
V
5.0
V
Bias Regulator (C5VB = 0.1 µF)
TA = 25°C; ILOAD = 1 mA
V5VB
IOUT_MAX
5VB Output Voltage
Total Variation over line, load,
and temperature
4.8
Maximum Output Current
5.2
V
5.0
mA
3.05
V
3.075
V
FAN9612 — Interleaved Dual BCM PFC Controller
Electrical Characteristics
Error Amplifier
TA = 25°C
(±1.4%)
2.95
Voltage Reference
Total Variation over line, load,
and temperature
(±2.6%)
2.925
Line Regulation
VDD = 10 V to 18 V
VSS
3.0
0.1
Temperature Stability
10
20
mV
mV
Input Bias Current
VFB = 1V to 3 V;
|VSS – VFB| ≤ 0.1 V
IOUT_SRC
Output Source Current
VSS = 3 V; VFB = 3.1 V
–10
µA
IOUT_SINK
Output Sink Current
VSS = 3V; VFB = 2.9 V
10
µA
VOH
Output High Voltage
VOL
Output Low Voltage
gM
IBIAS
–0.5
0.5
µA
4.5
4.7
V5VB
V
ISINK < 100µA
0.0
0.1
0.2
V
Transconductance
(Note 1)
80
100
120
µmho
PWM Ramp Offset
TA = 25°C
120
195
270
mV
Minimum On-Time
VFB > VSS
0.0
µs
1.27
V
PWM
Maximum On-Time
VMOT
tON,MAX
Maximum On-time Voltage
R = 125k
Maximum On-Time
R = 125k; VVIN = 2.5V;
VCOMP > 4.5 V; TA = 25°C
4.6
µs
VFB > VPWM_OFFSET
15.5
kHz
Restart Timer
fSW,RT
(4)
1.23
1.25
(each channel)
Minimum Switching Frequency
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com
7
PRELIMINARY
Unless otherwise noted, VDD = 12V, TJ = -40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Frequency Clamp
fSW,CL
(4)
(each channel)
Maximum Switching Frequency
600
kHz
Current Sense
CS Input Threshold Voltage Limit
0.18
CS Input Current
VCSX = 0 V to 1 V
CS to Output Delay
CS stepped from 0V to 5V
0.20
0.22
V
0.1
µA
65
90
ns
0.0
0.1
V
–0.1
Zero Current Detection
Input Voltage Threshold
(4)
-0.1
Input High Clamp voltage
Input Low Clamp voltage
Source Current Capability
Sink Current Capability
IZCD = 0.5mA
0.2
V
IZCD = –0.5mA
-0.2
V
(4)
(4)
--
--
1
mA
--
--
10
mA
60
100
ns
Maximum Turn-on Delay (ZCDx to
(4)
OUTx )
FAN9612 — Interleaved Dual BCM PFC Controller
Electrical Characteristics (Continued)
Output
ISINK
OUTx Current, Mid-Voltage,
(4)
Sinking
VOUTx = VDD/2; CLOAD = 0.1µF
1.8
A
ISOURCE
OUTx Current, Mid-Voltage,
(4)
Sourcing
VOUTx = VDD/2; CLOAD = 0.1µF
0.8
A
tRISE
Rise Time
CLOAD = 1nF, 10% to 90%
--
30
50
ns
tFALL
Fall Time
CLOAD = 1nF, 90% to 10%
--
30
50
ns
Output voltage during UVLO
VCC = 5V; Iout = 100µA
--
--
1
V
500
Reverse Current Withstand
mA
Soft Start (CSS = 0.1 µF)
Maximum Soft Start Current
VCOMP < 3.0 V
5
Minimum Soft Start Current
VCOMP > 4.5 V
0.5
µA
Turn-On / Turn-Off Threshold
1.0
V
VIN OVP Threshold
3.8
V
6
µA
Brown-Out Protection (Input)
VIN Sink Current
VVIN > 1.1 V
VIN Sink Current
VVIN < 0.9 V
100
nA
µA
2
Phase Shedding (Input)
VCOMP
Phase Shedding Threshold
VCOMP
Phase Adding Threshold
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
VCOMP decreasing, transition
from dual to single phase
VCOMP increasing, transition
from single to dual phase
1.5
1.6
1.7
V
1.9
2.05
2.2
V
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8
PRELIMINARY
Unless otherwise noted, VDD = 12V, TJ = -40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Over-Voltage Protection using FB pin – Cycle-by-Cycle (input)
Non-Latching OVP Threshold
OVP Hysteresis
TA = 25°C
DRV1=DRV2=0V
FB decreasing
(+8%)
3.1
3.25
3.4
V
0.24
V
3.5
V
Over-Voltage Protection using OVP pin – Latching (input)
Latching OVP Threshold
DRV1=DRV2=0V
Notes:
4. Not tested in production.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
FAN9612 — Interleaved Dual BCM PFC Controller
Electrical Characteristics (Continued)
www.fairchildsemi.com
9
PRELIMINARY
1. Boundary Conduction Mode
The FAN9612 utilizes the boundary conduction mode
control algorithm. The fundamental concept of this
operating mode is that the inductor current starts from
zero in each switching period as shown in the lower
waveform in Figure 5. When the power transistor of the
boost converter is turned on for a fixed amount of time it
can easily be shown that the peak inductor current will
be proportional to the input voltage. Furthermore, since
the current waveform is triangular the average value in
each switching period will be also proportional to the
input voltage. In case of a sinusoidal input voltage
waveform, the input current of the converter will follow
the input voltage waveform with very high accuracy and
draw a sinusoidal input current from the source. This
behavior makes the boost converter in BCM operation
an ideal candidate for power factor correction.
The boost converter is the most popular topology for
power factor correction in AC-to-DC power supplies.
This popularity can be attributed to the continuous input
current waveform provided by the boost inductor and to
the fact that the boost converter’s input voltage range
includes 0V. These fundamental properties make close
to unity power factor easier to achieve.
L
This mode of control of the boost converter will result in
a variable switching frequency. The frequency depends
primarily on the selected output voltage, the
instantaneous value of the input voltage, the boost
inductor value and the output power delivered to the
load. Thus the operating frequency will change as the
input voltage follows the sinusoidal input voltage
waveform. It can be shown that the lowest frequency
operation corresponds to the peak of the sine waveform
at the input of the boost converter. Even larger
frequency variation can be observed as the output
power of the converter changes, with maximum output
power resulting in the lowest operating frequency.
Theoretically, under zero load condition the operating
frequency of the boost converter would approach
infinity. In practice, there are natural limits to the highest
switching frequency. One such limiting factor is the
resonance taking place between the boost inductor and
the parasitic capacitances of the MOSFET, the diode
and the winding of the choke, in every switching cycle.
Figure 4. Basic PFC Boost Converter
The boost converter can be controlled to operate in
continuous conduction mode (CCM) or in boundary
conduction mode (BCM). These two descriptive names
refer to the current flowing in the energy storage
inductor of the boost power stage.
I
0A
t
Another important characteristic of the BCM boost
converter is the high ripple current of the boost inductor
which goes from zero to a controlled peak value in
every switching period. Accordingly the power switch is
also stressed with high peak current. In addition, the
high ripple current must be filtered by an EMI filter to
meet high frequency noise regulations enforced for
equipments connecting to the mains. These effects
usually limit the practical output power level of the
converter.
Typical Inductor Current Waveform In Continuous Conduction Mode
I
0A
t
Typical Inductor Current Waveform In Boundary Conduction Mode
Figure 5. CCM vs. BCM Control
2. Interleaving
As the names indicate, the current in Continuous
Conduction Mode (CCM) is continuous in the inductor
while in Boundary Conduction Mode (BCM), the new
switching period is initiated when the inductor current
returns to zero.
The FAN9612 control IC is configured to control two
boost converters connected parallel, both operated in
boundary conduction mode. In this arrangement the
input and output voltages of the two parallel converters
are the same and each converter is designed to
process approximately half the total output power of the
system.
There are many fundamental differences in CCM and
BCM operations and the respective designs of the boost
converter.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
FAN9612 — Interleaved Dual BCM PFC Controller
Theory of Operation
www.fairchildsemi.com
10
PRELIMINARY
VRAMP1
VRAMP2
VCONTROL
t
PWM1
PWM2
Figure 6. Interleaved PFC Boost Operation
Figure 7. FAN9612 PWM Operation
Parallel power processing is penalized by the increased
number of power components but offers significant
benefits to keep current and thermal stresses under
control and to increase the power handling capability of
the otherwise limited solution using BCM control
method for boost power factor correction. Furthermore,
the switches of the two boost converters can be
operated 180 degrees out of phase from each other.
The control of parallel converters operating 180
degrees out of phase is called interleaving. Interleaving
provides considerable ripple current reduction at the
input and output terminals of the power supply which
favorably affects the input EMI filter requirements and
reduces the high frequency RMS current of the output
capacitor of the power supply.
In the FAN9612 there are two PWM sections
corresponding to the two parallel power stages. For
proper interleaved operation two independent 180
degrees out of phase ramps are needed which
necessitates the two pulse width modulators. To ensure
that the two converters process the same amount of
power the artificial ramps have the same slope and they
use the same control signal generated by the error
amplifier.
4. Input-Voltage Feed-Forward
Basic voltage mode control, as described in the
previous section, provides satisfactory regulation
performance in most cases. One important
characteristic of the technique is that input voltage
variation to the converter requires a corrective action
from the error amplifier to maintain the output at the
desired voltage. When the error amplifier has adequate
bandwidth like in most DC-DC applications, it is able to
maintain regulation within a tolerable output voltage
range during input voltage changes.
There is an obvious difficulty to interleave two BCM
boost converters. Since the converter’s operating
frequency is influenced by component tolerances in the
power stage and in the controller as well, the two
converters will operate at different frequencies.
Therefore special attention must be paid to ensure that
the two converters will be locked in to 180 degrees out
of phase operation. Consequently, synchronization is a
critical function of an interleaved boundary conduction
mode PFC controller and it is implemented in the
FAN9612 using a dedicated circuitry.
On the other hand, when voltage-mode control is used
in power factor corrector applications, the error amplifier
bandwidth and its capability to quickly react to input
voltage changes, is severely limited. In these cases the
input voltage variation can easily cause excessive
overshoot or droop at the converter output as the input
voltage goes up or down respectively.
3. Voltage Regulation, Voltage Mode Control
The power supply’s output voltage is regulated by a
negative feedback loop and a pulse width modulator.
The negative feedback is provided by an error amplifier
which compares the feedback signal at the inverting
input to a reference voltage connected to the noninverting input of the amplifier. Similarly to other PFC
applications, the error amplifier is compensated with
high DC gain for accurate voltage regulation but very
low bandwidth to suppress line frequency ripple present
across the output capacitor of the converter. The line
frequency ripple is the result of the constant output
power of the converter and the fact that the input power
is the product of a sinusoidal current and a sinusoidal
voltage thus follows a sine square function. Eliminating
the line frequency component from the feedback
system is imperative to maintain low total harmonic
distortion (THD) in the input current waveform.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
FAN9612 — Interleaved Dual BCM PFC Controller
The pulse width modulator of the FAN9612 implements
voltage mode control. This control method compares an
artificial ramp to the output of the error amplifier to
determine the desired on-time of the converter’s power
transistor to achieve output voltage regulation.
To overcome this shortcoming of the voltage mode
PWM circuit in PFC applications, input-voltage feedforward is often employed. It can be shown
mathematically that a PWM ramp proportional to the
square of the input voltage will inherently reject the
effect of input voltage variations on the output voltage
and will eliminate the need of any correction by the error
amplifier.
www.fairchildsemi.com
11
PRELIMINARY
VR@VIN,H
VCONTROL
dV
2
~VIN
dt
t
PWMVIN,L
PWMVIN,H
Figure 8. Input-Voltage Feed-Forward
Figure 10. PWM Cycle Start
When the PWM ramp is made proportional to the input
voltage squared, the system offers other noteworthy
benefits. The first is the input voltage independent small
signal gain of the closed loop power supply which will
make the compensation of the voltage regulation loop
much easier. The second side benefit is that the output
of the error amplifier becomes directly proportional to
the input power of the converter. This phenomenon is
very significant and it will be re-visited in section 9
describing light load operation.
6. Terminating the conduction interval
Terminating the conduction period of the boost
transistor in boundary conduction mode controllers is
similar to any other pulse width modulator. During
normal operation the PWM comparator turns off the
power transistor when the ramp waveform exceeds the
control voltage provided by the error amplifier. In the
FAN9612 and in similar voltage-mode PWMs, the ramp
is a linearly rising waveform at one input of the
comparator circuit.
5. Starting a PWM cycle
The principle of boundary conduction mode calls for a
pulse width modulator which is able to operate with
variable frequency and initiate a switching period
whenever the current in the boost inductor reaches
zero. Therefore, BCM controllers can not utilize a fixed
frequency oscillator circuit to control the operating
frequency. Instead, a Zero Current Detector is used to
sense the inductor current and turn-on the power switch
once the current in the boost inductor reaches zero.
This process is facilitated by an auxiliary winding on the
boost inductor. The voltage waveform of the auxiliary
winding can be used for indirect detection of the zero
inductor current condition of the boost inductor thus it
should be connected to the Zero Current Detect input of
the FAN9612 as shown in Figure 9.
FAN9612 — Interleaved Dual BCM PFC Controller
VR@VIN,L
At start-up condition and the unlikely case of missing
zero current detection, the lack of an oscillator would
mean that the converter stops operating. To overcome
these situations a restart timer is employed to kick start
the controller and provide the first turn-on command as
shown in Figure 10.
Figure 11. Conduction Interval Termination
In addition to the PWM comparator, the current limit
circuit and a timer circuit limiting the maximum on-time
of the boost transistor can also terminate the gate drive
pulse of the controller. These functions provide
protection for the power switch against excessive
current stress.
7. Protecting the Power Components
In general, power converters are designed with
adequate margin for reliable operation under all
operating conditions. However, it might be difficult to
foresee or predict dangerous conditions under transient
or certain fault situations.
Therefore, the FAN9612 contains dedicated protection
circuits to monitor the individual peak currents in the
boost inductors and in the power transistors.
Figure 9. Simple Zero-Current Detection Method
Furthermore, the boost output voltage is sensed by two
independent mechanisms to provide over voltage
protection for the power transistors, rectifier diodes, and
the output energy storage capacitor of the converter.
The auxiliary winding can also be used to generate bias
for the PFC controller when an independent bias power
supply is not present in the system.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com
12
PRELIMINARY
Normalized On-Time Limit
# of Phases
Operating
The architecture and operating principle of the
FAN9612 also provides inherent input power limiting
capability.
Figure 13. Automatic Phase-Control Operation
Normal interleaved operation of the two boost
converters resumes automatically once the output
power exceeds approximately 40% of the nominal
output power of the converter.
Phase management in the FAN9612 is implemented
such that the error amplifier output does not have to
change when the system toggles between one-phase or
two-phase operation. Moreover, the output of the error
amplifier is proportional to the output power of the
converter independently whether one or both phases
are operating in the power supply.
Figure 12. On-Time vs. VIN_RMS
When the slope of the PWM ramp is made proportional
to the square of the input RMS voltage the maximum
on-time of the boost power switch becomes inversely
proportional to the square of VIN,RMS as represented in
Figure 12. In boundary-conduction mode the peak
current of the boost transistor is proportional to its ontime. Therefore, controlling the maximum pulse width of
the gate drive signal according to the curve shown is an
effective method to implement an input-voltage
independent power limit for the boost PFC.
Furthermore, because the maximum on-time limit is
applied independently to each pulse width modulator,
the power handling capability of the converter while only
one phase is running will be approximately half of the
total output power which can be delivered when both
phases are utilized.
9. Light load operation (Phase Control)
10. Brownout protection with soft recovery
One of the parameters determining the operating
frequency of a boundary conduction mode converter is
the output power. As the load decreases, lower peak
currents are commanded by the pulse width modulator
to maintain the output voltage at the desired set point.
Lower peak current means shorter on-time for the
power transistor and shorter time interval to ramp the
inductor current back to zero at any given input voltage.
As a result, the operating frequency of the converter
increases under light load condition.
An additional protection function usually offered by PFC
ICs is input brownout protection to prevent the converter
from operating below a user defined minimum input
voltage level. For this function to work the input voltage
of the converter is monitored by the FAN9612. When
the voltage falls below the brownout protection
threshold the converter stops working. The output
voltage of the boost converter falls until the load stops
drawing current from the output capacitor or until the
input voltage gets back to its nominal range and
operation resumes.
As the operating frequency and corresponding
switching losses increase the currents thus conduction
losses diminish at the same time. Therefore the power
losses of the converter are dominated by switching
losses at light load. This phenomenon is especially
evident in a BCM converter.
As the output falls the voltage at the feedback pin of the
FAN9612 falls proportionally according to the feedback
divider ratio. To facilitate soft recovery after a brownout
condition the soft start capacitor – which is also the
reference voltage of the error amplifier – is pulled lower
by the feedback network. This effectively pre-conditions
the error amplifier to provide closed loop soft-start like
behavior during the converter’s recovery from a
brownout situation. Once the input voltage goes above
the brownout protection threshold the converter
resumes normal operation. The output voltage will be
raised back to the nominal regulation level following the
slowly rising voltage across the soft start capacitor of
the FAN9612.
In order to improve light-load efficiency, the FAN9612
disables one of the two interleaved boost converters
when the output power falls below approximately 30%
of the nominal output power level. By managing the
number of phases used at light load the FAN9612 can
maintain high efficiency for a wider load range of the
power supply.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
FAN9612 — Interleaved Dual BCM PFC Controller
8. Power Limit
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13
PRELIMINARY
FAN9612 — Interleaved Dual BCM PFC Controller
11. Soft Starting the Converter
During startup the boost converter peak charges its
output capacitor to the peak value of the input voltage
waveform. The final voltage level where the output is
regulated during normal operation is reached after the
converter starts switching. There are two fundamentally
different approaches used in PWM controllers to control
the startup characteristics of a switched mode power
supply. Both methods use some kind of a soft start
mechanism to reduce the potential overshoot of the
converter’s output after the desired output voltage level
is reached.
The first method is called open loop soft start and relies
on gradually increasing the current or power limit of the
converter during startup. In this case the voltage error
amplifier is typically saturated commanding maximum
current until the output voltage reaches its final value.
At that time the voltage between the error amplifier
inputs changes polarity and the amplifier slowly comes
out of saturation. While the error amplifier recovers and
before it starts controlling the output voltage, the
converter operates with full power. Thus, output voltage
overshoot is unavoidable in converters utilizing the
open loop soft start scheme.
This method is especially dangerous in power factor
corrector applications because the error amplifier’s
bandwidth is typically limited to a very low cross over
frequency. The slow response of the amplifier can
cause considerable overshoot at the output.
The FAN9612 employs closed loop soft start where the
reference voltage of the error amplifier is slowly
increased to its final value. When current and power
limits of the converter are properly taken into
consideration the output voltage of the converter will
follow the reference voltage. This approach ensures
that the error amplifier stays in regulation during soft
start and the output voltage overshoot can be
eliminated.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
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14
PRELIMINARY
1. Detecting Zero Inductor Current (ZCD1,
ZCD2)
Each ZCD pin is internally clamped close to 0V
(GND). Any capacitance on the pin is ineffective in
providing any delay in ZCD triggering. The internal
sense circuit is a true differentiator to catch the valley
of the drain waveforms. The resistor between the
auxiliary winding of the boost inductor and the ZCD
pin is only used for current limiting. The maximum
source current during zero current detection must be
limited to 0.5mA. Source and sink capability of the pin
is about 1mA providing sufficient margin for the
higher source current required during the on-time of
the power MOSFETs.
Figure 15. 5V Bias
3. Maximum On-Time control (MOT)
MOT stands for maximum on-time (of the boost
MOSFET) and it is set by a resistor to analog ground
(AGND). The FAN9612 implements input-voltage
feed-forward. Therefore the maximum on-time is a
function of the RMS input voltage. The voltage on the
MOT pin is 1.25V during operation (constant DC
voltage). The maximum on-time of the power
MOSFETs can be approximated by:
t ON , MAX = RMOT ⋅120 ⋅10 −12 ⋅
Figure 14. Zero-Current Detect Circuit
2.4
1
⋅ 2
1.25 VINSNS , PK
where VINSNS,PK is the peak of the AC input voltage as
measured at the VIN pin (must be divided down, see
the VIN pin description).
The RZCD resistor value can be approximated by:
RZCD =
FAN9612 — Interleaved Dual BCM PFC Controller
FAN9612 Functional Description
V
N
1
⋅ O ⋅ AUX
0.5mA 2 N BOOST
2. 5V Bias Rail (5VB)
This is the bypass capacitor pin for the internal 5V
bias rail powering the control circuitry. The
recommended capacitor value is 220nF. At least
100nF good quality, high frequency ceramic cap
should be used and placed in close proximity to the
pin.
Figure 16. Maximum On-Time Control (MOT)
The 5V rail is a switched rail. It is actively held low
when the FAN9612 is in under-voltage lockout. Once
the UVLO turn-on threshold is exceeded at the VDD
pin, the 5V rail is turned on, providing a sharp edge
which can be used as an indication that the chip is up
and running. Potentially, this behavior can be utilized
to control the inrush current limiting circuit.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
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15
PRELIMINARY
Analog ground connection (AGND) is the GND for all
control logic biased from the 5V rail. Internally, the
AGND and PGND pins are tied together by two antiparallel diodes to limit ground bounce difference due
to bond wire inductances during the switching actions
of the high current gate drive circuits. It is
recommended to connect AGND and PGND pins
together with a short, low impedance trace on the
PCB (right under the IC).
Furthermore, during brown-out condition the output
voltage of the converter might fall which is reflected at
the FB pin of the FAN9612. When FB voltage goes
0.2V below the voltage on the SS pin, it will start
discharging the soft start capacitor. The soft-start
capacitor remains 0.2V above the FB voltage thus
when the brownout condition is over, the converter
returns to normal operation gracefully, following the
slow ramp up of the soft start capacitor at the noninverting input of the error amplifier.
PGND is the reference potential (0V) for the high
current gate drive circuit. Two bypass capacitors
should be connected between the VDD pin and the
PGND pin. One is the VDD energy storage capacitor
which provides bias power to the FAN9612 during
start up until the bootstrap power supply comes up.
The other capacitor shall be a good quality ceramic
bypass capacitor, as close as possible to PGND and
VDD pins to filter the high peak currents of the gate
driver circuits. The value of the ceramic bypass
capacitor is a strong function of the gate charge
requirement of the power MOSFETs and its
recommended value is between 1µF and 4.7µF to
ensure proper operation.
FAN9612 — Interleaved Dual BCM PFC Controller
rising. This is a problem if closed loop soft start
should be maintained. By clamping the SS voltage to
the FB pin this problem can be mitigated.
4. Analog Ground (AGND) and Power
Ground (PGND)
5. Soft-start (SS)
Soft start is programmed by the user with a capacitor
connected between this pin and AGND. This is the
non-inverting input of the transconductance (gM) error
amplifier of the FAN9612.
Figure 17. Soft-start Programming
At start-up, the soft start capacitor will be quickly precharged to a voltage approximately 0.2V below the
voltage on the feedback pin (FB) to minimize start up
delay. Then a 5µA current source takes over and
charges the soft start capacitor slowly ramping up the
voltage reference of the error amplifier. By ramping
up the reference slowly, the voltage regulation loop
can stay closed, actively controlling the output
voltage during start up. While the SS capacitor is
charging, the output of the error amplifier is
monitored. In case the error voltage (COMP) ever
exceeds 3.5V indicating that the voltage loop is close
to saturation, the 5uA soft start current is reduced.
Therefore the soft start will be automatically extended
to reduce the current needed to charge the output
capacitor thus reducing the output power during start
up. This mechanism is built in to prevent the voltage
loop from saturation. The charge current of the soft
start capacitor can be reduced from the initial 5µA to
as low as 0.5µA minimum.
In addition to modulating the soft start current into the
SS capacitor, the SS pin is clamped approximately
0.2V above the FB pin. This mechanism is useful to
prevent the SS capacitor to run away from the FB pin
and defeat the idea of closed loop soft start. During
the zero crossing of the input source waveform the
input power is almost zero and the output voltage can
not be raised. Therefore the FB voltage would stay
flat or even decay while the SS voltage would keep
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
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16
PRELIMINARY
COMP pin is the output of the error amplifier. The
voltage loop is compensated by a combination of Rs
and Cs to AGND at this pin. The control range of the
error amplifier is between 0.175V and 4.5V. When the
COMP voltage is below about 0.175V, the PWM
circuit will skip pulses. Above 4.5V the maximum ontime limit will terminate the conduction of the boost
switches.
Due to the input-voltage feed-forward, the output of
the error amplifier is proportional to the input power of
FAN9612 — Interleaved Dual BCM PFC Controller
the converter independent of the input voltage. In
addition, also due to the input-voltage feed-forward,
the maximum power capability of the converter and
the loop gain is independent of the input voltage. The
controller’s phase- management circuit monitors the
error amplifier output and will switch to single-phase
operation when the COMP voltage falls below 1.6V
approximately and return to two-phase operation
when the error voltage exceeds 2.1V. These
thresholds correspond to about 30% and 40% of the
maximum power capability of the design.
6. Error Amplifier Compensation (COMP)
Figure 18. Error Amplifier Compensation Circuitry
7. Output Voltage Feedback (FB)
The feedback pin receives the divided-down output
voltage of the converter. In regulation, the FB pin
should be 3V which is the reference used at the noninverting input of the error amplifier. Due to the gM
type error amplifier, the FB pin is always proportional
to the output voltage and can be used for over
voltage protection as well. A non-latching over
voltage detection circuit monitors the FB pin and
prevents the boost MOSFETs from turning on when
the FB voltage exceeds 3.25V. Operation resumes
automatically when the FB voltage returns to its
nominal 3V level.
External
Components
To SS
VOUT
± 200mV
Clamp
To Phase /
Gain
Control
gM Error
Amplifier
8
FB
Also connected to the FB pin is the open feedback
detection circuit. Since the output of the boost
converter is charged to the peak of the input AC
voltage when power is applied to the power supply,
the detection circuit monitors the presence of this
voltage. If the FB pin is below 0.5V which would
indicate a missing feedback divider (or wrong value
causing dangerously- high regulation voltage), the
FAN9612 will not send out its gate drive signals to the
boost transistors.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
Internal
Circuits
Figure 19. Output-Voltage Feedback Circuit
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17
PRELIMINARY
A second-level latching over-voltage protection can
be implemented using the OVP pin of the controller.
The threshold of this circuit is set to 3.5V. There are
two ways to program the secondary OVP.
Option 1, as shown in the figure below, is for the
designer to connect the OVP pin to the FB pin. In
addition to the standard non-latching OVP (set at
~8%), this configuration provides the second OVP
protection (set at ~15%) which is latched.
In the case where latching OVP protection is not
desired at all, the OVP pin should be grounded.
FAN9612 — Interleaved Dual BCM PFC Controller
In the case where redundant over-voltage protection
is preferred (also called double OVP protection), a
second separate divider from the output voltage can
be used as shown by Option 2. In this case the
latching OVP protection level can be independently
established below or above the non-latching OVP
threshold which is based on the feedback voltage (at
the FB pin).
8. Secondary Output Voltage Sense (OVP)
Figure 20. Secondary Over-Voltage Protection Circuit
feed-forward circuit can react immediately without
waiting for a valid integral value at the end of the half
line period. Furthermore, lack of zero crossing
detection could fool the integrator while the peak
detector works properly during light load operation.
9. Input Voltage Sensing (VIN)
The input AC voltage is sensed at the VIN pin. The
input voltage is used in three functions: input undervoltage lockout (brown out protection), input over
voltage protection and input voltage feed forward in
the PWM control circuit. All the functions require the
RMS value of the input voltage waveform. Since the
RMS value of the AC input voltage is directly
proportional to its peak, it is sufficient to find the peak
instead of the more complicated and slower method
of integrating the input voltage over a half line cycle.
The internal circuit of the VIN pin works with peak
detection of the input AC waveforms. One of the
important benefits of this approach is that the peak
indicates the correct RMS value even at no load
when the HF filter capacitor at the input side of the
boost converter is not discharged around the zero
crossing of the line waveform. Another notable benefit
is that during line transients when the peak exceeds
the previously measured value, the input-voltage
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
The valid range for the peak of the AC input is
between approximately 1.0V and 3.8V. This range is
optimized for universal input voltage range operation.
If the peak of the sense voltage remains below the 1V
threshold, input under voltage or brown out condition
is declared and the FAN9612 will stop operating.
Similarly when the VIN voltage exceeds 3.8V, the
FAN9612 will stop switching due to input over
voltage. The input voltage is measured by a tracking
analog to digital converter which keeps the highest
value (peak voltage) of the input voltage waveform.
Once a measurement is taken the converter will track
the input for at least 12ms before a new value is
taken. This delay guarantees that at least one new
peak value is captured before the new value is used.
www.fairchildsemi.com
18
PRELIMINARY
periods, this technique does not feed any AC ripple
into the control loop. In case line zero crossing
detection is missing, the FAN9612 measures the
input voltage in every 32ms, thus it can operate from
a DC input as well. The following figures provide
more detail about the input voltage sensing method of
the
controller:
The measured peak value is then used in the
following half line cycle while a new measurement is
executed which will be used in the next half line cycle.
This operation is synchronized to the zero crossing of
the line waveform. Since the input voltage
measurement is held steady during the line half
FAN9612 — Interleaved Dual BCM PFC Controller
Figure 21. Input Voltage Sensing Circuit
AC “RMS value” used
for feed forward and
protection functions
AC input voltage
waveform sensed
at VIN pin
50Hz
50Hz
50Hz
10ms
DC
forced reset after 32ms
forced reset after 32ms
Figure 22. Input Voltage Sensing Waveforms
increases and has a half line cycle delay when the
input voltage decreases. Any increase in input
voltage would cause output over voltage due to the
As can be seen from the waveforms, input voltage
feed forward is instantaneous when the line voltage
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
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19
PRELIMINARY
12. Current Sense Protection (CS1, CS2)
10. Gate drive outputs (DRV1; DRV2)
The FAN9612 uses independent over current
protection for each of the power MOSFETs. The
current sense thresholds at the CS1 and CS2 pins
are approximately 0.2V. The current measurements
are strictly for protection purposes and are not part of
the control algorithm. The pins can be directly
connected to the non-grounded end of the current
sense resistors because the usual R-C filters of the
leading edge current spike are integrated in the IC.
High current driver outputs DRV1 and DRV2 have the
capability to sink a minimum of 2A and source 1A.
Due to the low impedance of these drivers, the 1A
source current must be actively limited by an external
gate resistor. Thus the minimum external gate
resistance is given as:
RGATE =
VDD
1A
To take advantage of the higher sink current
capability of the drivers, the gate resistor can be
bypassed by a small diode to facilitate faster turn-off
of the power MOSFETs. Traditional fast turn-off circuit
using a pnp transistor instead of a simple bypass
diode can be considered as well.
It is also imperative that the inductance of the gate
drive loop is minimized to avoid excessive ringing. In
case optimum layout is not possible or the controller
is placed on a daughter card, it is recommended to
use an external driver circuit located near the gate
and source terminals of the boost MOSFET
transistors. Small gate charge power MOSFETs can
be driven by a FAN3111C driver IC while higher gate
charge devices might require FAN3100C or
FAN3227C family of drivers.
Figure 23. Current Sense Protection Circuits
The time constant
approximately:
of
τ = 27 kΩ ⋅ 5 pF = 130ns
11. Bias Supply (VDD)
This is the main bias source for the FAN9612. The
operating voltage range is between ~8V and 18V.
The VDD voltage is monitored by the under voltage
lock out (UVLO) circuit. At power up the VDD voltage
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
FAN9612 — Interleaved Dual BCM PFC Controller
must exceed 12.5V (±1V) in order to enable
operation. The FAN9612 will stop operating when the
VDD voltage falls below 8V (±1V). See PGND pin
description for important bypass information.
slow nature of the voltage regulation loop. This is
successfully mitigated by the immediate action of the
input-voltage feed-forward circuit.
ωP =
the
internal
filter
is
or
1
= 1.2 MHz
2 ⋅ π ⋅ 27 kΩ ⋅ 5 pF
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20
PRELIMINARY
The FAN9612 is designed so that power to it can be
provided without a dedicated startup resistor. This
configuration also allows the controller to start up
when the bias voltage is less than the controller’s
under-voltage lockout start threshold.
1. Synchronization and Timing Functions
The FAN9612 employs a highly sophisticated
synchronization sub-system based on digital
techniques. At the heart of the system is a dualchannel
switching-frequency
detector
which
measures the switching period of each channel in
every switching cycle and locks their operating phase
180 degrees out of phase from each other. The
slower operating frequency channel is dominant but
there is no master-slave arrangement. Moreover, as
the frequency constantly changes due to the varying
input voltage, either channel can be the slower
dominant channel.
In the boost PFC topology, the output voltage is precharged to the peak line voltage by the boost diode.
As soon as voltage is present at the output of the
boost converter, current starts to flow through the
feedback resistors from the boost output to GND.
Using an external, low-voltage MOSFET in series with
the lower resistor in the feedback divider, this current
can be diverted to charge the VCC bypass capacitor
of the controller. The upper resistor becomes a
current source used to charge the VCC capacitor.
As opposed to the most commonly used technique
where the phase relationship between the channels is
provided by changing the on-time of one of the
MOSFETs, the FAN9612 controls the phase
relationship by inserting a turn-on delay before the
next switching period starts for the faster running
phase. As it is shown in the literature, the on-time
modulation technique is not stable under all operating
conditions while the off-time modulation (or delaying
the turn-on) is unconditionally stable under all
operating conditions.
a.
To accomplish this, a small external diode should be
connected between the VCC and FB pins as shown
in Figure 24. As the VCC voltage rises past the
under-voltage lockout threshold, the 5V reference is
turned on, which drives the external MOSFET gate
and connects the resistor of the feedback divider to
ground. At the same time, the diode between the FB
pin and the VCC bias is reverse biased and the FB
pin reverts to its normal role of output voltage
sensing. If, for whatever reason, the bias to the IC
drops below the under-voltage lockout level, the
startup process is repeated. A simplified circuit
implementation for this startup method is shown
below.
Restart Timer
The restart timer is an integral part of the
synchronizing circuit and ensures exact 180 degrees
out of phase operation in restart timer operation. This
is an important safety feature as well because in case
of a non-operating phase (no ZCD detection, missing
gate drive connection in one of the phases or similar
errors which can render one of the phases
inoperable) the other phase will be locked into restart
timer operation as well preventing it from trying to
deliver full power to the load.
Bootstrap or
Bias PS
VDD
FB
VOUT
The restart timer of the FAN9612 is set to
approximately 18kHz which is just above the audible
frequency range to avoid any acoustic noise
generation.
b.
UVLO
5VB
5VBIAS
Frequency Clamp
Just as the restart timer, the frequency clamp is
integrated into the synchronization and ensures exact
180 degrees out of phase operation when the
operating frequency is limited. This might happen at
very light load operation or near the zero crossing
region of the line voltage waveform. Limiting the
switching frequency at light load can improve
efficiency but has a negative effect on power factor
since the converter will also enter true DCM
operation. The frequency clamp is set to
approximately 600kHz.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
FAN9612 — Interleaved Dual BCM PFC Controller
2. Start-up with 12V bias (less than UVLO)
Key Application Information
Figure 24. Simplified start-up Circuit using the
output feedback resistors to provide a
charging current
This technique can also be utilized if the auxiliary bias
voltage is lower than the minimum start up voltage of
the FAN9612.
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21
PRELIMINARY
There are four ways to disable the FAN9612. It is
important to understand how the part reacts for the
various shutdown procedures.
1.
2.
3.
Pull the SS pin to GND. This method uses
the error amplifier to stop the operation of
the power supply. By pulling the SS pin to
GND the error amplifier’s non-inverting input
is pulled to GND. The amplifier will sense
that the inverting input (FB pin) is higher
than the reference voltage and it will try to
adjust its output (COMP pin) to make the FB
pin equal to the reference at the SS pin. Due
to the slow speed of the voltage loop in PFC
applications, this might take several line
cycles. Thus, it is important to consider that
by pulling the SS pin to GND, the power
supply can not be shut down immediately.
Recovery from a shut down state will follow
normal soft-start procedure when the SS pin
is released.
4.
Pull the FB pin to GND. By pulling the FB pin
below the open feedback protection
threshold of approximately 0.5V, the power
supply can be shut down immediately. It is
imperative that the FB is pulled below the
threshold very quickly since the power
supply keeps switching until this threshold is
crossed. If the feedback would be pulled low
softly and would not cross the threshold, the
power supply would try to deliver maximum
power because the FB pin would be forced
below the reference voltage of the error
amplifier on the SS pin. Eventually, as FB is
pulled to GND, the SS capacitor will be
pulled low by the internal clamp between the
FB and SS pins. The SS pin will stay
approximately 0.2V higher than the FB pin
itself. Therefore, recovery from a shut down
state will follow normal soft-start procedure
when the FB pin is released as the voltage
across the SS capacitor will start ramping
from a low value.
4. Layout and Connection Guidelines
The FAN9612 incorporates fast reacting input
circuits, short propagation delays, and strong output
stages capable of delivering current peaks over 1.5
amps to facilitate fast voltage transition times. The
following layout and connection guidelines are
recommended:
Pulling the COMP pin to GND. When the
COMP pin is pulled below the PWM Ramp
Offset, approximately 0.195V, the FAN9612
stops sending gate drive pulses to the power
MOSFETs. This condition is similar to pulse
skipping under no load condition. If any load
is still present at the output of the boost PFC
stage the output voltage will decrease.
Consequently the FB pin will decrease and
the SS capacitor voltage will be pulled low
by the internal clamp between the FB and
SS pins. At that point the operation and
eventual recovery to normal operation is
similar to the mechanism described above in
section 3.2. If the COMP pin is held low for
sufficiently long time to pull the SS pin low,
the recovery will follow normal soft-start
procedure when the COMP pin is released.
If the SS capacitor is not pulled low as a
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
Pull the VIN pin to GND. Since the VIN
sense circuit is configured to ride through a
single line cycle dropout test without shutting
down the power supply this method will
result in a delayed shutdown of the
converter. The FAN9612 will stop operation
approximately 20ms to 32ms after the VIN
pin is pulled low. The delay depends on at
what phase of the line cycle the pulled down
happens. This method triggers the input
brownout protection of the FAN9612 (input
under voltage lock out) which will gradually
discharge the compensation capacitor. As
the output voltage will decrease, the FB pin
will fall pulling low the SS capacitor voltage.
Similarly to the shutdown, once the VIN pin
is released operation will resume after
several milliseconds of delay which is
needed to determine that the input voltage is
above the turn-on threshold. Thus at least
one line cycle peak must be detected above
the turn-on threshold before operation can
resume at the following line voltage zerocrossing. The converter will start following
normal soft-start procedure.
FAN9612 — Interleaved Dual BCM PFC Controller
result of a momentary pull down of the
COMP pin the recovery will still be soft due
to the fact that a limited current source is
charging the compensation capacitors at the
output of the error amplifier. Nevertheless, in
this case output voltage overshoot can
happen before the voltage loop enters
closed loop operation and resumes
controlling the output voltage again.
3. Disabling the FAN9612
ƒ
Keep high current output and power ground
paths separate from analog input signals and
signal ground paths.
ƒ
Keep the controller as close to the MOSFETs as
possible. This minimizes the length and the loop
area (series inductance) of the high current gate
drive traces.
ƒ
Many high speed power circuits can be
susceptible to noise injected from their own
output or other external sources, possibly
causing output re-triggering. These effects can
be especially obvious if the circuit is tested in
breadboard or non-optimal circuit layouts with
long input, enable, or output leads. For best
results, make connections to all pins as short
and direct as possible.
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22
PRELIMINARY
Compensation Capacitor
CCOMP,LF
The FAN9612 can easily be configured following the
next few steps outlined in this section. This Quick
Setup Guide refers to the schematic diagram and
component references of Figure 26. It uses the
equations derived and explained in the FAN9612
Application Note, AN-6086.
Compensation Resistor
RCOMP
Compensation Capacitor
CCOMP,HF
Feedback Divider
RFB1
Feedback Divider
RFB2
Over Voltage Sense Divider
ROV1
Over Voltage Sense Divider
ROV2
Input Voltage Sense Divider
RIN1
Input Voltage Sense Divider
RIN2
Brown-Out Hysteresis Set
RINHYST
Gate Drive Resistor
RG1, RG2
Gate Drive Speed-up Diode
DG1, DG2
Bypass Capacitor for VDD - HF
CVDD1
2.2µ
Startup Energy Storage for VDD
CVDD2
47µ
Current Sense Resistor
RCS1, RCS2
Description
Name
Your
Value
From Power Supply Specification:
Min. AC RMS Input (turn-on)
VLINE.ON
Min. AC RMS Input (turn-off) 1
VLINE.OFF
Max. AC RMS Input (OVP) 1
VLINE.MAX
Min. Line Frequency
fLINE,MIN
Nominal DC Output
VOUT
Output Voltage Ripple (2 · fLINE)
VOUT,RIPPLE
Latching Output OVP
VOUT,LATCH
Nominal Output Power (to load)
POUT
Desired Hold Up Time
tHOLD
Min. DC Output (end of tHOLD)
VOUT,MIN
Min. Switching Frequency
fSW,MIN
Max. DC Bias (for FAN9612)
VDDMAX
In preparation to calculate the setup component
values the power supply specification must be known
to the designer. Furthermore, a few power stage
components must be pre-calculated before the
controller design begins as their values determine the
component selections around the FAN9612.
Step 1: Input Voltage Range
Pre-calculated Power Stage parameters:
Estimated Conversion Efficiency
η
Max. Output Power per Channel
PMAX,CH
Output Capacitance
COUT
Boost Inductance per Channel
L
Max. On-Time per Channel
tON,MAX
Turns Ratio (NBOOST / NAUX)
N
0.95
The FAN9612 utilizes a single pin (VIN) for input
voltage sensing. The valid voltage range of the VIN
pin is from 1V to 3.8V. A VIN pin voltage below 1V
activates the line under voltage lockout while anything
above 3.8V halts the operation due to input over
voltage protection. Thus, the ratio of VLINE.MAX and
VLINE.OFF is always 3.8. Consequently, only one of
those two parameters can be freely chosen by the
designer. The turn-on voltage (VLINE.ON) can be set
independently of the other two thresholds as
demonstrated below.
10
Other variables used during the calculations:
Peak Inductor Current
IL,PK
Max. DC Output Current (to load)
IO,MAX
ON
Calculated Component Values:
Zero Current Detect Resistor
RZCD1,
RZCD2
Bypass Capacitor for 5V Bias
C5VB
Maximum On-time Set
RMOT
Soft-Start Capacitor
CSS
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
FAN9612 — Interleaved Dual BCM PFC Controller
Quick Setup Guide
OFF
0.15µ
0
1.0V
3.8V
VIN Pin Voltage
Figure 25. Simplified Turn-on and Turn-off
Thresholds at the VIN Pin of FAN9612
www.fairchildsemi.com
23
PRELIMINARY
D1
VOUT
L1b
L2a
VLINE
EMI
filter
D2
COUT
CIN
L2b
Q1
RCS1
Q2
RCS2
RZCD1
RZCD2
FAN9612
C5VB
RMOT
CSS
RCOMP CCOMP,LF
CCOMP,HF
1
ZCD1
CS1
16
2
ZCD2
CS2
15
3
5VB
VDD
14
4
MOT DRV1
5
AGND DRV2 12
6
SS
PGND
7
COMP
8
FB
13
VBIAS
RG1
RG2
11
VIN
10
OVP
9
FAN9612 — Interleaved Dual BCM PFC Controller
L1a
VIN
RIN1
ROV1
RFB1
RIN2
ROV2
RFB2
RINHYST
CVDD1 CVDD2
Figure 26. Interleaved BCM PFC Schematic Using FAN9612
Step 2: Estimated Conversion
Efficiency
Step 3: Maximum Output Power per
Channel
Use the estimated full load power conversion
efficiency. Typical value for an interleaved BCP PFC
converter is in the 0.92 to 0.98 range. The efficiency
is in the lower half of the range for low power
applications. Using state of the art semiconductors,
good quality ferrite inductors and selecting lower limit
for minimum switching frequency will positively impact
the efficiency of the system. In general, the value of
0.95 can be used unless a more accurate power
budget is available.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
PMAX,CH = 1.2 ⋅
POUT
2
A margin of 20% has been added to the nominal
output power to cover reference inaccuracy, internal
component tolerances, inductance mismatch and
current sense resistor variation to the per channel
power rating.
www.fairchildsemi.com
24
PRELIMINARY
COUT(RIPPLE) =
C OUT(HOLD) =
Step 7: Peak Inductor Current per
Channel
POUT
4 ⋅ fLINE,MIN ⋅ VOUT ⋅ VOUT,RIPPLE
IL,PK =
2 ⋅ POUT ⋅ t HOLD
V
⎛
⎜⎜ VOUT − OUT,RIPPLE
2
⎝
IOUT,MAX =
(
2
η ⋅ VLINE,
OFF ⋅ VOUT − 2 ⋅ VLINE,OFF
2 ⋅ fSW,MIN ⋅ VOUT ⋅ PMAX,CH
(
2
η ⋅ VLINE,
MAX ⋅ VOUT − 2 ⋅ VLINE,MAX
2 ⋅ PMAX,CH
VOUT
Step 9: Zero Current Detect Resistors
R ZCD1 = R ZCD2 =
0.5 ⋅ VOUT
N ⋅ 0.5mA
where 0.5·VOUT is the maximum amplitude of the
resonant waveform across the boost inductor during
zero current detection, N is the turns ratio of the
boost inductor and the auxiliary winding utilized for
the zero current detection and 0.5mA is thee
maximum current of the ZCD pin during the zero
current detection period.
Step 5: Boost Inductance per
Channel
Step 10: Maximum On-Time Setting
Resistor
)
RMOT = 4340 ⋅ 10 6 ⋅ t ON,MAX
)
where RMOT should be between 40kOhms and
130kOhms.
2 ⋅ fSW,MIN ⋅ VOUT ⋅ PMAX,CH
Step 11: Output Voltage Setting
Resistors (Feedback)
The minimum switching frequency can occur either at
the lowest or at the highest input line voltage.
Accordingly, two boost inductor values are calculated
and the lower of the two inductances must be
selected. This L value will keep the minimum
operating frequency above fSW,MIN under all operating
conditions.
RFB2 =
3V ⋅ VOUT 3V
=
PFB
IFB
where 3V is the reference voltage of the error
amplifier at its non-inverting input and PFB or IFB are
selected by the designer. If the power loss associated
to the feedback divider is critical to meet stand-by
power consumption regulations, it might be beneficial
to start the calculation by choosing PFB. Otherwise,
the current of feedback divider, IFB should be set to
approximately 0.4mA at the desired output voltage
set point. This value ensures that parasitic circuit
board and pin capacitances do not introduce
unwanted filtering effect in the feedback path.
Step 6: Maximum On-Time per
Channel
t ON,MAX =
⋅ t ON,MAX
Step 8: Maximum DC Output Current
The second expression yields the minimum output
capacitance based on the required holdup time based
on the power supply specification. Ultimately, the
larger of the two values will satisfy both design
requirements and has to be selected for COUT.
L LINE,MAX =
L
2
⎞
2
⎟⎟ − VOUT,
MIN
⎠
The output capacitance must be calculated by two
different methods. The first equation determines the
capacitor value based on the allowable ripple voltage
at the minimum line frequency. It is important to
remember that the scaled version of this ripple will be
present at the FB pin. The feedback voltage is
continuously monitored by the non-latching over
voltage protection circuit. Its threshold is about 8%
higher the nominal output voltage. To avoid triggering
the OVP protection during normal operation,
VOUT,RIPPLE should be limited to less 12% of the
nominal output voltage, VOUT.
L LINE,OFF =
2 ⋅ VLINE,OFF
FAN9612 — Interleaved Dual BCM PFC Controller
Step 4: Output Capacitance
2 ⋅ L ⋅ PMAX,CH
2
η ⋅ VLINE,
OFF
In case the feedback divider is used to provide
startup power for the FAN9612 (see AN-6086 for
implementation details) the following equation can be
used to calculate RFB2:
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com
25
PRELIMINARY
3V ⋅
[ 2⋅V
LINE,ON
]
− (12.5V + 3 ⋅ 0.7V )
CCOMP,HF < 4 ⋅ CSS
0.12mA ⋅ VOUT
This relationship is determined by the ratio between
the maximum output current of the gM error amplifier
to the maximum charge current of the soft start
capacitor. By observing this correlation between the
two capacitor values it is ensured that the
compensation capacitor voltage can be adjusted
faster than any voltage change taking place across
the soft start capacitor. Therefore, during startup the
voltage regulation loop’s response to the increasing
soft start voltage is not limited by the finite current
capability of the error amplifier.
where 3V is the reference voltage of the error
amplifier at its non-inverting input, 12.5V is the
controller’s UVLO turn-on threshold, 0.12mA is the
worst case startup current required by the FAN9612
to start operation and 3·0.7V accounts for the forward
voltage drop of three diodes in series of the startup
current. Once the value of RFB2 is determined RFB1 is
given by the following formula:
⎞
⎛V
RFB1 = ⎜ OUT − 1⎟ ⋅ RFB2
⎠
⎝ 3V
RCOMP =
RFB1 might have to be implemented as a series
combination of two or three resistors depending on
safety regulations, maximum voltage and or power
rating of the selected resistor type.
CCOMP,HF =
5 µA ⋅ COUT ⋅ (RFB1 + RFB2 )
0.3 ⋅ IOUT,MAX ⋅ RFB2
where 5µA is the charge current of the soft start
capacitor provided by the FAN9612 and 0.3·IOUT,MAX
is the maximum output current charging the output
capacitor of the converter during the soft start
process. It is imperative to limit the charge current of
the output capacitor to be able to maintain closed
loop soft start of the converter. The 0.3 factor used in
the CSS equation can prevent output over voltage at
the end of the soft start period and provides sufficient
margin to supply current to the load while the output
capacitor is charging.
gM ⋅ IOUT,MAX
4.2V ⋅ C OUT ⋅ (2 ⋅ π ⋅ f0 )
2
⋅
2 ⋅ π ⋅ fHFP ⋅ RCOMP
Step 14: Over Voltage Protection
Setting (OVP)
R OV2 =
3.5V ⋅ VOUT,LATCH
POVP
where 3.5V is the threshold voltage of the OVP
comparator and POVP is the total dissipation of the
resistive divider network. Typical POVP power loss is in
the 50mW to 100mW range.
Step 13: Compensation Components
C COMP,LF =
1
where fHFP is the frequency of a pole implemented in
the error amplifier compensation network against high
frequency noise in the feedback loop. The pole
should be placed at least a decade higher than f0 to
ensure that it does not interfere with the phase
margin of the voltage regulation loop at its crossover
frequency. It should also be sufficiently lower then the
switching frequency of the converter so noise can be
effectively attenuated. The recommended fHFP
frequency is around 120Hz in PFC applications.
Step 12: Soft Start Capacitor
C SS =
1
2 ⋅ π ⋅ f0 ⋅ CCOMP,LF
FAN9612 — Interleaved Dual BCM PFC Controller
R FB2 =
R FB2
RFB1 + RFB2
where 4.2V is the control range of the error amplifier
and f0 is the desired voltage loop crossover
frequency. It is important to consider that the lowest
output ripple frequency limits the voltage loop
crossover frequency. In PFC applications that
frequency is two times the AC line frequency.
Therefore, the voltage loop bandwidth (f0), is typically
in the 5Hz to 15Hz range.
⎛V
⎞
R OV1 = ⎜⎜ OUT,LATCH − 1⎟⎟ ⋅ R OV2
⎝ 3.5V
⎠
ROV1 might have to be implemented as a series
combination of two or three resistors depending on
safety regulations, maximum voltage and or power
rating of the selected resistor type.
In order to guarantee closed loop soft start operation
under all conditions it is recommended that:
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com
26
PRELIMINARY
RIN2 =
RG
DG
3.6V ⋅ VLINE,MAX
2 ⋅ PINSNS
where 3.8V is the threshold voltage of the line OVP
comparator and PINSNS is the total dissipation of the
resistive divider network. Typical PINSNS power loss is
in the 50mW to 100mW range.
RIN1
Figure 27. Recommended Speed Up Diode and
Gate Resistor Schematic
Step 17: Current Sense Resistors
⎞
⎛ 2 ⋅ VLINE,MAX
=⎜
− 1⎟ ⋅ RIN2
⎟
⎜
3.6V
⎠
⎝
R CS1 = R CS2 =
RIN1 might have to be implemented as a series
combination of two or three resistors depending on
safety regulations, maximum voltage and or power
rating of the selected resistor type.
RINHYST
RCS
where 0.18V is the worst case threshold of the
current limit comparator. The size and type of current
sense resistors depends on their power dissipation
and manufacturing considerations.
⎞
⎛ 2 ⋅ VLINE,ON ⋅ RIN2
⎜
− 0 .9 V ⎟
⎟
⎜
RIN1 + RIN2
⎠
⎝
=
2µA
⎛ 1 4 ⋅ 2 ⋅ VLINE,OFF ⎞
⎟
PRCS1 = 1.5 ⋅ IL,2 PK ⋅ R CS1 ⋅ ⎜ −
⎜6
⎟
⋅
⋅
9
π
V
OUT
⎝
⎠
where the 1.5 factor is used for the worst case effect
of the current limit threshold variation. When the
current sense resistor is determined the minimum
current sense threshold must be used to avoid
activating over current protection too early as the
power supply approaches full load condition. The
worst case power dissipation of the current sense
resistor happens when the current sense threshold is
at its maximum value as defined in the datasheet.
The ratio between the minimum and maximum
thresholds squared (since the square of the current
determines power dissipation) yields exactly the 1.5
factor used in the calculation.
where 0.9V is the threshold voltage of the line under
voltage lockout comparator and 2µA is the sink
current provided by the FAN9612 at the VIN pin
during line under voltage (brownout) condition. The
sink current, together with the terminating impedance
of the VIN pin determines the hysteresis between the
turn-on and turn-off thresholds.
Step 16: Gate Resistors
It is recommended to place a low value resistor
between the gate drive outputs, DRV1 and DRV2
pins of the FAN9612 and their corresponding power
devices. The gate drive resistors have a beneficial
effect to limit the current drawn from the VDD bypass
capacitor during the turn-on of the power MOSFETs
and to attenuate any potential oscillation in the gate
drive circuits.
R G1 = R G2 =
0.18V
IL,PK
FAN9612 — Interleaved Dual BCM PFC Controller
Step 15: Input Line Voltage Sense
Resistors
VDDMAX
1.0 A
where 1.0A is the recommended peak value of the
gate drive current. In order to take full advantage of
the low output impedance of the drivers the gate
resistor could be bypassed by a small diode to speed
up the turn-off action of the power MOSFETs.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com
27
PRELIMINARY
Typical Performance Characteristics — Supply
Typical characteristics are provided at TA = 25°C and VDD = 12V unless otherwise noted.
Figure 28. ISTARTUP vs. Temperature
Figure 29. Operating Current vs. Temperature
Figure 30. UVLO Thresholds vs. Temperature
Figure 31. UVLO Hysteresis vs. Temperature
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com
28
PRELIMINARY
Typical characteristics are provided at TA = 25°C and VDD = 12V unless otherwise noted.
Figure 32. Transfer Function (Max ON Time vs. VIN)
Figure 33. Soft-start Current vs. Temperature
Figure 34. 5V Reference vs. Temperature.
Figure 35. EA Reference vs. Temperature
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
FAN9612 — Interleaved Dual BCM PFC Controller
Typical Performance Characteristics — Control
www.fairchildsemi.com
29
PRELIMINARY
Typical characteristics are provided at TA = 25°C and VDD = 12V unless otherwise noted.
Figure 36. Phase-Control Thresholds vs. Temperature
Gate Drive 1
Gate Drive 1
Gate Drive 2
Gate Drive 2
Inductor Current 1
Inductor Current 1
Inductor Current 2
Inductor Current 2
Figure 37. Phase-Shedding Operation
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
FAN9612 — Interleaved Dual BCM PFC Controller
Typical Performance Characteristics — Control
Figure 38. Phase-Adding Operation
www.fairchildsemi.com
30
PRELIMINARY
Typical characteristics are provided at TA = 25°C and VDD = 12V unless otherwise noted.
Figure 39. CS Threshold vs. Temperature
Figure 40. CS to OUT Delay vs. Temperature
Figure 41. Brown-Out Threshold vs. Temperature
Figure 42. Line OVP vs. Temperature
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
FAN9612 — Interleaved Dual BCM PFC Controller
Typical Performance Characteristics — Protection
www.fairchildsemi.com
31
PRELIMINARY
Typical characteristics are provided at TA = 25°C and VDD = 12V unless otherwise noted.
Figure 43. Non-Latching OVP vs. Temperature
Figure 44. Latching OVP vs. Temperature
FAN9612 — Interleaved Dual BCM PFC Controller
Typical Performance Characteristics — Protection
Figure 45. OVP Hysteresis vs. Temperature
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com
32
PRELIMINARY
Typical characteristics are provided at TA = 25°C and VDD = 12V unless otherwise noted.
IL1
IL1
IL2
IL2
IL1 + IL2
IL1 + IL2
Figure 46. Ripple-Current Cancellation (110Vac)
Figure 47. Ripple-Current Cancellation (110Vac)
Vout
FAN9612 — Interleaved Dual BCM PFC Controller
Typical Performance Characteristics — Operation
Vout
Line
Cur
Line
Cur
Figure 48. No-load startup at 115Vac
Figure 49. Full-load startup at 115Vac
Line
Vol
110Vac
220Vac
Vout
COMP
Line
Cur
Figure 50. Input Voltage Feed-forward
Notes: For full performance operational characteristics at both low line (110Vac) and high line (220Vac), as well as
at no-load and full-load, please refer to FEB279 Evaluation Board User Guide: 400W Evaluation Board using
FAN9612.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com
33
PRELIMINARY
FEB279: 400W Evaluation Board using FAN9612
FEB279 is an evaluation board for an interleaved dual boundary-conduction mode PFC converter rated at 400W
(400V/1A) power. With phase management, the efficiency is maintained above 96% even down at 10% of the rated
output power. The efficiencies for full load condition are 96.4% and 98.2% at line voltages of 115Vac and 230Vac
respectively as shown below. For the full specification, design schematic, bill of materials and test results, see the
evaluation board User Guide.
Input Voltage
VIN nominal: 85V~264Vac
VDD supply: 13V~18Vdc
Rated Output Power
400W
Output Voltage (Rated Current)
400V (1A)
FAN9612 Efficiency vs. Load
(115 VAC Input, 400 VDC Output, 400 W)
100
Efficiency (%)
95
With Phase Management
FAN9612 — Interleaved Dual BCM PFC Controller
Evaluation Board
Without Phase Management
90
85
0
10
20
30
40
50
60
70
80
90
100
Output Power (%)
Figure 51.
Measured efficiency at 115Vac
FAN9612 Efficiency vs. Load
(230 VAC Input, 400 VDC Output, 400 W)
100
Efficiency (%)
95
With Phase Management
Without Phase Management
90
85
0
10
20
30
40
50
60
70
80
90
100
Output Power (%)
Figure 52.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
Measured efficiency at 230Vac
www.fairchildsemi.com
34
PRELIMINARY
Part
Number
Related Products
Description
PFC Control
Number
of Pins
Comments
FAN7527B
Boundary Mode PFC Control IC
Single BCM (CRM)
8
Industry Standard Pin-out.
FAN7528
Dual Output Critical Conduction Mode
PFC Controller
Single BCM (CRM)
8
Low THD. For Boost Follower
implementation.
FAN7529
Critical Conduction Mode PFC Controller
Single BCM (CRM)
8
Low THD
FAN7530
Critical Conduction Mode PFC Controller
Single BCM (CRM)
8
Low THD, Alternate pin-out of FAN7529
(pins 2 and 3 reversed).
SG6961
Green mode PFC
Single BCM (CRM)
8
Industry Standard Pin-out with Green
Mode Functions
FAN9612
Interleaved Dual BCM PFC Controller
Dual BCM (CRM)
16
Dual BCM (CRM), 180° Out-of-Phase
Related Documents
Application Note AN-6086: Design Consideration for Interleaved Boundary Conduction Mode (BCM) PFC using
FAN9612
Evaluation Board User Guide FEB279: 400W Evaluation Board using FAN9612
Fairchild Power Seminars 2008-2009 Paper: Understanding Interleaved Boundary Conduction Mode PFC
Converters
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
FAN9612 — Interleaved Dual BCM PFC Controller
Table 1.
www.fairchildsemi.com
35
PRELIMINARY
FAN9612 — Interleaved Dual BCM PFC Controller
Physical Dimensions
Figure 53. 16-Lead SOIC Package (M)
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com
38
PRELIMINARY
FAN9612 — Interleaved Dual BCM PFC Controller
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com
39