ICST ICS8530DYI-01T Low skew, 1-to-16 differential-to-3.3v lvpecl fanout buffer Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8530I-01 is a low skew, 1-to-16 Differential-to-3.3V LVPECL Fanout Buffer and a memHiPerClockS™
ber of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The CLK, nCLK
pair can accept most standard differential input
levels. The high gain differential amplifier accepts peak-topeak input voltages as small as 150mV as long as the common mode voltage is within the specified minimum and maximum range.
• (16) differential 3.3V LVPECL outputs
Guaranteed output and part-to-part skew characteristics make
the ICS8530I-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
• Output skew: 50ps (typical)
ICS
• CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 500MHz
• Translates any single-ended input signal to
3.3V LVPECL levels with a resistor bias on nCLK input
• Part-to-part skew: 100ps (typical)
• Additive phase jitter, RMS @ 106.25MHz:
0.022ps (typical) @ 25°C
• 3.3V output operating supply
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
nCLK
VCCO
Q15
nQ15
Q14
nQ14
VEE
Q13
nQ13
Q12
nQ12
VCCO
CLK
nCLK
Q15
nQ15
Q1
nQ1
Q14
nQ14
Q2
nQ2
Q13
nQ13
Q3
nQ3
Q12
nQ12
Q4
nQ4
Q11
nQ11
Q5
nQ5
Q10
nQ10
Q6
nQ6
Q9
nQ9
Q7
nQ7
Q8
nQ8
VCCO
Q11
nQ11
Q10
nQ10
VEE
Q9
nQ9
Q8
nQ8
VCCO
VCC
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS8530I-01
CLK
VCCO
nQ0
Q0
nQ1
Q1
VEE
nQ2
Q2
nQ3
Q3
Vcco
VCCO
nQ4
Q4
nQ5
Q5
VEE
nQ6
Q6
nQ7
Q7
VCCO
VCC
Q0
nQ0
48-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm body package
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8530DYI-01
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REV. A FEBRUARY 25, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 11, 14, 24,
25, 35, 38, 48
2, 3
Name
Type
Description
VCCO
Power
Output supply pins.
Q11, nQ11
Output
Differential output pair. LVPECL interface levels.
4, 5
Q10, nQ10
Output
Differential output pair. LVPECL interface levels.
6, 19, 30, 43
V EE
Power
Negative supply pins.
7, 8
Q9, nQ9
Output
Differential output pair. LVPECL interface levels.
9, 10
Q8, nQ8
Output
Differential output pair. LVPECL interface levels.
12, 13
VCC
Power
Core supply pins.
15, 16
Q7, nQ7
Output
Differential output pair. LVPECL interface levels.
17, 18
Q6, nQ6
Output
Differential output pair. LVPECL interface levels.
20, 21
Q5, nQ5
Output
Differential output pair. LVPECL interface levels..
22, 23
Q4, nQ4
Output
Differential output pair. LVPECL interface levels.
26, 27
28, 29
Q3, nQ3
Q2, nQ2
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
36
37
39, 40
41, 42
44, 45
46, 47
NOTE: Pullup and
CLK
Input
Pulldown Non-inver ting differential clock input.
nCLK
Input
Pullup
Inver ting differential clock input.
Q15, nQ15
Output
Differential output pair. LVPECL interface levels.
Q14, nQ14
Output
Differential output pair. LVPECL interface levels.
Q13, nQ13
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Q12, nQ12
Output
Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
Minimum
Typical
Maximum
Units
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
TABLE 3. FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
HIGH
Differential to Differential
Non Inver ting
HIGH
LOW
Differential to Differential
Non Inver ting
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential
Non Inver ting
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential
Non Inver ting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
CLK
nCLK
Q0:Q15
nQ0:nQ15
0
1
LOW
1
0
0
1
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8530DYI-01
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2
REV. A FEBRUARY 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
27.6°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
I EE
Power Supply Current
115
mA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
VCC = VIN = 3.465V
CLK
Maximum
Units
150
µA
5
µA
nCLK
VCC = VIN = 3.465V
CLK
VCC = 3.465V, VIN = 0V
-5
µA
nCLK
VCC = 3.465V, VIN = 0V
-150
µA
VPP
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
VCMR
VEE + 0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
1.3
V
VCC - 0.85
V
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
VCCO - 1.4
Typical
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCCO-2V.
8530DYI-01
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3
REV. A FEBRUARY 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 4
Test Conditions
tR
Output Rise Time
106.25MHz, 25°C
Integration Range: 12KHz to 20MHz
106.25MHz, 85°C
Integration Range: 12KHz to 20MHz
212.5MHz, 25°C
Integration Range: 12KHz to 20MHz
212.5MHz, 85°C
Integration Range: 12KHz to 20MHz
20% to 80% @ 50MHz
tF
Output Fall Time
20% to 80% @ 50MHz
tjit
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Minimum
Typical
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4
Units
500
MHz
1.35
ns
50
ps
100
ps
0.022
ps
0.026
ps
0.033
ps
0.034
ps
300
700
ps
300
700
ps
odc
Output Duty Cycle
50
All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8530DYI-01
Maximum
%
REV. A FEBRUARY 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
Additive Phase Jitter @
106.25MHz, 25°C (12KHz to 20MHz)
= 0.022ps typical
-10
-20
-30
-40
-50
SSB PHASE NOISE dBc/HZ
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
8530DYI-01
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
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5
REV. A FEBRUARY 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
Additive Phase Jitter @
106.25MHz, 85°C (12KHz to 20MHz)
= 0.026ps typical
-10
-20
-30
-40
-50
SSB PHASE NOISE dBc/HZ
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
8530DYI-01
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
www.icst.com/products/hiperclocks.html
6
REV. A FEBRUARY 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
Additive Phase Jitter @
212.5MHz, 25°C (12KHz to 20MHz)
= 0.033ps typical
-10
-20
-30
-40
-50
SSB PHASE NOISE dBc/HZ
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
8530DYI-01
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
www.icst.com/products/hiperclocks.html
7
REV. A FEBRUARY 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
Additive Phase Jitter @
212.5MHz, 85°C (12KHz to 20MHz)
= 0.034ps typical
-10
-20
-30
-40
-50
SSB PHASE NOISE dBc/HZ
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
8530DYI-01
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
www.icst.com/products/hiperclocks.html
8
REV. A FEBRUARY 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
V CC
V CC,
VCCO
Qx
SCOPE
nCLK
V
LVPECL
nQx
V
Cross Points
PP
CMR
CLK
VEE
VEE
-1.3V ± 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
nQx
nQx
Qx
Qx
PART 2
nQy
nQy
Qy
Qy
t sk(pp)
t sk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK
80%
80%
CLK
VSW I N G
Clock
Outputs
nQ0:nQ15
20%
20%
Q0:Q15
tR
tF
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0:nQ15
Q0:Q15
Pulse Width
t
odc =
PERIOD
t PW
t PERIOD
OUTPUT DUTY CYLE/PULSE WIDTH/PERIOD
8530DYI-01
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REV. A FEBRUARY 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
1
RTT =
Z
((VOH + VOL) / (VCC – 2)) – 2 o
Zo = 50Ω
VCC - 2V
RTT
FIGURE 2A. LVPECL OUTPUT TERMINATION
8530DYI-01
FIN
50Ω
84Ω
84Ω
FIGURE 2B. LVPECL OUTPUT TERMINATION
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REV. A FEBRUARY 25, 2005
PRELIMINARY
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Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
3.3V
R3
125
BY
R4
125
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
125
R4
125
CLK
nCLK
R5
100 - 200
R6
100 - 200
R1
84
HiPerClockS
Input
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
3.3V LVPECL DRIVER WITH AC COUPLE
8530DYI-01
BY
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11
REV. A FEBRUARY 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
THERMAL RELEASE PATH
The expose metal pad provides heat transfer from the device to
the P.C. board. The expose metal pad is ground pad connected
to ground plane through thermal via. The exposed pad on the
device to the exposed metal pad on the PCB is contacted through
solder as shown in Figure 4. For further information, please refer to the Application Note on Surface Mount Assembly of
Amkor’s Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology.
EXPOSED PAD
SOLDER M ASK
SOLDER
SIGNAL
TRACE
SIGNAL
TRACE
GROUND PLANE
THERM AL VIA
FIGURE 4. P.C. BOARD
8530DYI-01
FOR
Expose Metal Pad
(GROUND PAD)
EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
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12
REV. A FEBRUARY 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8530I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8530I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 115mA = 398.5mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 16 * 30mW = 480mW
Total Power_MAX (3.465V, with all outputs switching) = 398.5mW + 480mW = 878.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 22.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.879W * 22.6°C/W = 104.9°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
48-PIN TQFP, E-PAD FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
8530DYI-01
27.6°C/W
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13
200
500
22.6°C/W
20.7°C/W
REV. A FEBRUARY 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT
TERMINATION
AND
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = V
OH_MAX
(V
CCO_MAX
•
-V
OH_MAX
=V
OL_MAX
CCO_MAX
-V
CCO_MAX
– 0.9V
) = 0.9V
For logic low, VOUT = V
(V
=V
CCO_MAX
– 1.7V
) = 1.7V
OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
CCO_MAX
L
-V
) = [(2V - (V
OH_MAX
CCO_MAX
-V
OH_MAX
))/R ] * (V
CCO_MAX
L
-V
OH_MAX
)=
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
))/R ] * (V
OL_MAX
L
CCO_MAX
-V
)=
OL_MAX
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
8530DYI-01
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14
REV. A FEBRUARY 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7.
θJAVS. AIR FLOW TABLE FOR 48 LEAD TQFP, E-PAD
θJA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
27.6°C/W
200
500
22.6°C/W
20.7°C/W
TRANSISTOR COUNT
The transistor count for ICS8530I-01 is: 930
8530DYI-01
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REV. A FEBRUARY 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FOR
48 LEAD TQFP, E-PAD
-HD VERSION
HEAT SLUG DOWN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
ABC - HD
MINIMUM
MAXIMUM
48
N
A
NOMINAL
--
--
1.20
0.15
A1
0.05
--
A2
0.95
1.00
1.05
b
0.17
0.22
0.27
c
0.09
0.20
9.00 BASIC
D
D1
7.00 BASIC
D2
5.50 BASIC
E
9.00 BASIC
E1
7.00 BASIC
E2
5.50 BASIC
0.5 BASIC
e
L
0.45
θ
0°
ccc
--
D3 & E 3
2.00
0.60
0.75
--
0.08
7°
7.00
Reference Document: JEDEC Publication 95, MS-026
8530DYI-01
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16
REV. A FEBRUARY 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS8530DYI-01
ICS8530DYI-01T
Marking
ICS8530DYI01
ICS8530DYI01
Package
48 Lead TQFP, E-Pad
48 Lead TQFP, E-Pad
Shipping Packaging
tray
1000 tape & reel
Temperature
-40°C to 85°C
-40°C to 85°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
8530DYI-01
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17
REV. A FEBRUARY 25, 2005
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