Fairchild EEFUE0G181R Dual ddr / dual-output pwm controller Datasheet

FAN5026
Dual DDR / Dual-Output PWM Controller
Features
Description
The FAN5026 PWM controller provides high efficiency
and regulation for two output voltages adjustable in the
range of 0.9V to 5.5V required to power I/O, chip-sets,
and memory banks in high-performance computers,
set-top boxes, and VGA cards. Synchronous
rectification and hysteretic operation at light loads
contribute to high efficiency over a wide range of loads.
Efficiency is enhanced by using MOSFET RDS(ON) as a
current-sense component.
Highly Flexible, Dual Synchronous Switching PWM
Controller that Includes Modes for:
-
DDR Mode with In-phase Operation for
Reduced Channel Interference
-
90° Phase-shifted, Two-stage DDR Mode
for Reduced Input Ripple
-
Dual Independent Regulators, 180° Phase
Shifted
Complete DDR Memory Power Solution
-
VTT Tracks VDDQ/2
VDDQ/2 Buffered Reference Output
Lossless Current Sensing on Low-Side MOSFET or
Precision Over-Current Using Sense Resistor
VCC Under-Voltage Lockout
Power-Good Signal
Wide Input Range: 3V to 16V
Excellent Dynamic Response with Voltage
Feedforward and Average Current-Mode Control
Supports DDR-II and HSTL
28-Lead Thin-Shrink Small-Outline Package
Applications
Feedforward ramp modulation, average-current mode
control, and internal feedback compensation provide
fast response to load transients. Out-of-phase operation
with 180-degree phase shift reduces input current
ripple. The controller can be transformed into a
complete DDR memory power supply solution by
activating a designated pin. In DDR Mode, one of the
channels tracks the output voltage of another channel
and provides output current sink and source capability
— essential for proper powering of DDR chips. The
buffered reference voltage required by this type of
memory is also provided. The FAN5026 monitors these
outputs and generates separate PGx (power good)
signals when the soft-start is completed and the output
is within ±10% of the set point.
FAN5026 — Dual DDR / Dual-Output PWM Controller
March 2011
DDR VDDQ and VTT Voltage Generation
PC Dual Power Supply
Server DDR Power
Desktop Computer
Graphics Cards
Over-voltage protection prevents the output voltage
from exceeding 120% of the set point. Normal operation
is automatically restored when over-voltage conditions
cease. Under-voltage protection latches the chip off
when output drops below 75% of the set value after the
soft-start sequence for this output is completed. An
adjustable over-current function monitors the output
current by sensing the voltage drop across the lower
MOSFET. If precision current-sensing is required, an
external current-sense resistor may be used.
Related Resources
Application Note — AN-6002 Component
Calculations and Simulation Tools
Ordering Information
Part Number
FAN5026MTCX
Operating
Temperature
Range
-40 to +85°C
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
Package
28-Lead Thin-Shrink Small-Outline Package (TSSOP)
Packing Method
Tape and Reel
www.fairchildsemi.com
FAN5026 — Dual DDR / Dual-Output PWM Controller
Block Diagrams
Figure 1. Dual-Output Regulator
Figure 2. Typical Application
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
www.fairchildsemi.com
2
FAN5026 — Dual DDR / Dual-Output PWM Controller
Pin Configuration
Figure 3. TSSOP-28
Pin Definitions
Pin #
Name
Description
1
AGND
Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured
with respect to this pin
2
LDRV1
27
LDRV2
Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side
MOSFET.
3
PGND1
26
PGND2
4
SW1
25
SW2
5
HDRV1
24
HDRV2
6
BOOT1
23
BOOT2
7
ISNS1
22
ISNS2
8
EN1
21
EN2
Enable. Enables operation when pulled to logic HIGH. Toggling EN resets the regulator after a
latched fault condition. These are CMOS inputs whose state is indeterminate if left open.
GND
Ground
9
20
10
VSEN1
19
VSEN2
Power Ground. The return for the low-side MOSFET driver. Connect to source of low-side
MOSFET.
Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect
to source of high-side MOSFET and low-side MOSFET drain.
High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side
MOSFET.
BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 4.
Current-Sense Input. Monitors the voltage drop across the lower MOSFET or external sense
resistor for current feedback.
Output Voltage Sense. The feedback from the outputs; used for regulation as well as PG,
under-voltage, and over-voltage protection and monitoring.
Continued on the following page…
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
www.fairchildsemi.com
3
Pin #
Name
11
ILIM1
Current Limit 1. A resistor from this pin to GND sets the current limit.
12
SS1
17
SS2
Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during
initialization. During initialization, this pin is charged with a 5mA current source.
13
DDR
DDR Mode Control. HIGH = DDR Mode. LOW = two separate regulators operating 180
degrees out of phase.
14
VIN
Input Voltage. Normally connected to the battery, providing voltage feedforward to set the
amplitude of the internal oscillator ramp. When using the IC for two-step conversion from 5V
input, connect through 100KΩ resistor to ground, which sets the appropriate ramp gain and
synchronizes the channels 90° out of phase.
15
PG1
Power-Good Flag. An open-drain output that pulls LOW when VSEN is outside a ±10% range of
the 0.9V reference.
16
Description
Power-Good 2. When not in DDR Mode, open-drain output that pulls LOW when the VOUT is
out of regulation or in a fault condition.
PG2 /
REF2OUT Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically used as
the VDDQ/2 reference.
18
ILIM2 /
REF2
28
VCC
Current Limit 2. When not in DDR Mode, a resistor from this pin to GND sets the current limit.
Reference for reg #2 when in DDR Mode. Typically set to VOUT1/2.
VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when
voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V
(UVLO falling).
FAN5026 — Dual DDR / Dual-Output PWM Controller
Pin Definitions
Block Diagram
Figure 4. IC Block Diagram
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VCC
VIN
Parameter
Min.
Max.
Unit
VCC Supply Voltage
6.5
V
VIN Supply Voltage
18
V
BOOT, SW, ISNS, HDRV
24
V
BOOTx to SWx
6.5
V
All Other Pins
-0.3
VCC+0.3
V
TJ
Junction Temperature
-40
+150
ºC
TSTG
Storage Temperature
-65
+150
ºC
+300
ºC
TL
Lead Temperature (Soldering,10 Seconds)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
VCC
VCC Supply Voltage
VIN
VIN Supply Voltage
TA
Ambient Temperature
ΘJA
Thermal Resistance, Junction to Ambient
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
Min.
Typ.
Max.
Unit
4.75
5.00
5.25
V
16
V
+85
°C
90
°C/W
-40
FAN5026 — Dual DDR / Dual-Output PWM Controller
Absolute Maximum Ratings
www.fairchildsemi.com
5
Recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
2.2
3.0
µA
30
µA
Power Supplies
IVCC
VCC Current
LDRV, HDRV Open, VSEN Forced
Above Regulation Point
Shutdown (EN-0)
VIN Current, Sinking
VIN = 15V
ISOURCE
ISINK
VIN Current, Sourcing
VIN = 0V
ISD
VIN Current, Shutdown
VUVLO
UVLO Threshold
VUVLOH
UVLO Hysteresis
10
30
µA
-15
-30
µA
1
µA
Rising VCC
4.30
4.55
4.75
V
Falling
4.10
4.25
4.45
300
V
mV
Oscillator
fosc
Frequency
VPP
Ramp Amplitude
VRAMP
G
255
345
KHz
VIN = 16V
2
VIN = 5V
1.25
V
0.5
V
VIN ≤ 3V
125
mV/V
1V < VIN < 3V
250
mV/V
Ramp Offset
Ramp / VIN Gain
300
V
FAN5026 — Dual DDR / Dual-Output PWM Controller
Electrical Characteristics
Reference and Soft-Start
VREF
Internal Reference Voltage
ISS
Soft-Start Current
VSS
Soft-Start Complete Threshold
0.891
At Startup
0.900
0.909
V
5
µA
1.5
V
PWM Converters
Load Regulation
ISEN
IOUTX from 0 to 5A, VIN from 5 to 15V
+2
%
50
80
120
nA
% of Set Point, 2µs Noise Filter
70
75
80
%
% of Set Point, 2µs Noise Filter
115
120
125
%
RILIM= 68.5KΩ, Figure 12
112
140
168
µA
VSEN Bias Current
UVLOTSD Under-Voltage Shutdown
UVLO
Over-Voltage Threshold
ISNS
Over-Current Threshold
Minimum Duty Cycle
-2
10
%
Output Drivers
HDRV Output Resistance
LDRV Output Resistance
Sourcing
12
15
Sinking
2.4
4.0
Sourcing
12
15
Sinking
1.2
2.0
Ω
Ω
Power-Good Output and Control Pins
Lower Threshold
% of Set Point, 2µs Noise Filter
-86
-94
%
Upper Threshold
% of Set Point, 2µs Noise Filter
108
116
%
PG Output Low
IPG = 4mA
0.5
V
Leakage Current
VPULLUP = 5V
1
µA
PG2/REF2OUT Voltage
DDR = 1, 0 mA < IREF2OUT ≤10mA
1.01
%
VREF2
99.00
DDR, EN Inputs
VINH
Input High
VINL
Input Low
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
2
V
0.8
V
www.fairchildsemi.com
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FAN5026 — Dual DDR / Dual-Output PWM Controller
Typical Application
Figure 5. DDR Regulator Application
Table 1. DDR Regulator BOM
Description
Qty.
Ref.
Vendor
Capacitor 68µf, Tantalum, 25V, ESR 150mΩ
1
C1
AVX
Capacitor 10nf, Ceramic
2
C2, C3
Any
Part Number
TPSV686*025#0150
Capacitor 68µf, Tantalum, 6V, ESR 1.8Ω
1
C4
AVX
Capacitor 150nF, Ceramic
2
C5, C7
Any
TAJB686*006
Capacitor 180µf, Specialty Polymer 4V, ESR 15mΩ
2
C6A, C6B(1)
Panasonic
EEFUE0G181R
Capacitor 1000µf, Specialty Polymer 4V, ESR 10mΩ
1
C8
Kemet
T510E108(1)004AS4115
Capacitor 0.1µF, Ceramic
2
C9
Any
1.82KΩ, 1% Resistor
3
R1, R2, R3
Any
56.2KΩ, 1% Resistor
1
R3
Any
10KΩ, 5% Resistor
2
R4
Any
3.24KΩ, 1% Resistor
1
R5
Any
1.5KΩ, 1% Resistor
2
R7, R8
Any
Schottky Diode 30V
2
D1, D2
Fairchild Semiconductor
BAT54
Inductor 6.4µH, 6A, 8.64mΩ
1
L1
Panasonic
ETQ-P6F6R4HFA
Inductor 0.8µH, 6A, 2.24mΩ
1
L2
Panasonic
ETQ-P6F0R8LFA
Dual MOSFET with Schottky
2
Q1, Q2
Fairchild Semiconductor
FDS6986AS(2)
DDR Controller
1
U1
Fairchild Semiconductor
FAN5026
Notes:
1. C6 = 2 X 180µF in parallel.
2. Suitable for typical notebook computer application of 4A continuous, 6A peak for VDDQ. If continuous operation
above 6A is required, use single SO-8 packages. For more information, refer to the Power MOSFET Selection
Section and use AN-6002 for design calculations.
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
www.fairchildsemi.com
7
FAN5026 — Dual DDR / Dual-Output PWM Controller
Typical Applications (Continued)
Figure 6. Dual Regulator Application
Table 2. Dual Regulator BOM
Description
Qty.
Ref.
Vendor
Capacitor 68µf, Tantalum, 25V, ESR 95mΩ
1
C1
AVX
Capacitor 10nf, Ceramic
2
C2, C3
Any
Capacitor 68µf, Tantalum, 6V, ESR 1.8Ω
1
C4
AVX
Capacitor 150nF, Ceramic
2
C5, C7
Any
Capacitor 330µf, Poscap, 4V, ESR 40mΩ
2
C6, C8
Sanyo
Capacitor 0.1µF, Ceramic
2
C9
Any
56.2KΩ, 1% Resistor
1
R1, R2
Any
10KΩ, 5% Resistor
1
R3
Any
3.24KΩ, 1% Resistor
1
R4
Any
Part Number
TPSV686*025#095
TAJB686*006
4TPB330ML
1.82KΩ, 1% Resistor
3
R5, R8, R9
Any
1.5KΩ, 1% Resistor
2
R6, R7
Any
Schottky Diode 30V
2
D1, D2
Fairchild Semiconductor
BAT54
Inductor 6.4µH, 6A, 8.64mΩ
2
L1, L2
Panasonic
ETQ-P6F6R4HFA
Dual MOSFETs with Schottky
1
Q1, Q2
Fairchild Semiconductor
FDS6986AS(3)
DDR Controller
1
U1
Fairchild Semiconductor
FAN5026
Note:
3. If currents above 4A continuous are required, use single SO-8 packages. For more information, refer to the
Power MOSFET Selection Section and AN-6002 for design calculations.
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
www.fairchildsemi.com
8
Overview
CLK
The FAN5026 is a multi-mode, dual-channel PWM
controller intended for graphic chipset, SDRAM, DDR
DRAM, or other low-voltage power applications in
modern notebook, desktop, and sub-notebook PCs.
The IC integrates control circuitry for two synchronous
buck converters. The output voltage of each controller
can be set in the range of 0.9V to 5.5V by an external
resistor divider.
VD DQ
VTT
Figure 7. Noise-Susceptible 180° Phasing
for DDR1
In-phase operation is optimal to reduce inter-converter
interference when VIN is higher than 5V, (when VIN is
from a battery), as shown in Figure 8. Because the duty
cycle of PWM1 (generating VDDQ) is short, the switching
point occurs far away from the decision point for the VTT
regulator, whose duty cycle is nominally 50%.
The two synchronous buck converters can operate from
an unregulated DC source (such as a notebook
battery), with voltage ranging from 5.0V to 16V, or from
a regulated system rail of 3.3V to 5.0V. In either mode,
the IC is biased from a +5V source. The PWM
modulators use an average current-mode control with
input voltage feedforward for simplified feedback loop
compensation and improved line regulation. Both PWM
controllers have integrated feedback loop compensation
that reduces the external components needed.
CLK
VDDQ
The FAN5026 can be configured to operate as a
complete DDR solution. When the DDR pin is set HIGH,
the second channel provides the capability to track the
output voltage of the first channel. The PWM2 converter
is prevented from going into Hysteretic Mode if the DDR
pin is HIGH. In DDR Mode, a buffered reference voltage
(buffered voltage of the REF2 pin), required by DDR
memory chips, is provided by the PG2 pin.
VTT
Figure 8. Optimal In-Phase Operation for DDR1
When VIN ≈ 5V, 180° phase-shifted operation can be
rejected for the reasons demonstrated in Figure 7.
In-phase operation with VIN ≈ 5V is even worse, since
the switch point of either converter occurs near the
switch point of the other converter, as seen in Figure 9.
In this case, as VIN is a little higher than 5V, it tends to
cause early termination of the VTT pulse width.
Conversely, the VTT switch point can cause early
termination of the VDDQ pulse width when VIN is slightly
lower than 5V.
Converter Modes and Synchronization
Table 3. Converter Modes and Synchronization
Mode
VIN
VIN
Pin
DDR
Pin
PWM 2
w.r.t.
PWM1
DDR1
Battery
VIN
HIGH
IN PHASE
DDR2
+5V
R to
GND
HIGH
+90°
DUAL
ANY
VIN
LOW
+180°
FAN5026 — Dual DDR / Dual-Output PWM Controller
Circuit Description
CLK
VDDQ
VTT
When used as a dual converter, as shown in Figure 6,
out-of-phase operation with 180-degree phase shift
reduces input current ripple.
Figure 9.
Noise-Susceptible In-Phase Operation
for DDR2
These problems are solved by delaying the second
converter’s clock by 90°, as shown in Figure 10. In this
way, all switching transitions in one converter take place
far away from the decision points of the other converter.
For “two-step” conversion (where the VTT is converted
from VDDQ as in Figure 5) used in DDR Mode, the duty
cycle of the second converter is nominally 50% and the
optimal phasing depends on VIN. The objective is to
keep noise generated from the switching transition in
one converter from influencing the "decision" to switch
in the other converter.
CLK
VDDQ
When VIN is from the battery, it’s typically higher than
7.5V. As shown in Figure 7, 180° operation is
undesirable because the turn-on of the VDDQ converter
occurs very near the decision point of the VTT converter.
VTT
Figure 10. Optimal 90° Phasing for DDR2
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
www.fairchildsemi.com
9
Assuming EN is HIGH, FAN5026 is initialized when VCC
exceeds the rising UVLO threshold. Should VCC drop
below the UVLO threshold, an internal power-on reset
function disables the chip.
‫= ܵܰܵܫ‬
‫ = ܵܰܵܫ‬12 ∙
‫= ܦܣܱܮܫ‬
(1)
The current through the RSENSE resistor (ISNS) is
sampled (typically 400ns) after Q2 is turned on, as
shown in Figure 12. That current is held and summed
with the output of the error amplifier. This effectively
creates a current-mode control loop. The resistor
connected to ISNSx pin (RSENSE) sets the gain in the
current feedback loop. For stable operation, the voltage
induced by the current feedback at the PWM
comparator input should be set to 30% of the ramp
amplitude at maximum load current and line voltage.
The following expression estimates the recommended
value of RSENSE as a function of the maximum load
current (ILOAD(MAX)) and the value of the MOSFET
RDS(ON):
ܴ‫= ܯܫܮܫ‬
(2a)
5A
(4)
Q2
(2b)
LDRV
ISNS
RSENSE
R1
PGND
Setting the Current Limit
Figure 11.
A ratio of ISNS is compared to the current established
when a 0.9V internal reference drives the ILIM pin. The
threshold is determined as follows:
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
≈
10.8 100 + ܴܵ‫ܧܵܰܧ‬
∙
‫ܶܫܯܫܮܫ‬
ܴ‫)ܱܰ(ܵܦ‬
The 100Ω is the internal resistor in series with the
ISNSx pins and has ±15% typical variation. Because
RSENSE is in series with the internal 100Ω resistor, the
gain in the current feedback loop and the current limit
accuracy is affected if RSENSE is close to 100Ω.
‫ ܵܰܵܫ‬4
= ‫ = ܵܰܵܫ ݎ݋ ܯܫܮܫ‬12 ∙ ‫ܯܫܮܫ‬
9
3
(3d)
Since the tolerance on the current limit is largely
dependent on the ratio of the external resistors, it is
fairly accurate if the voltage drop on the switching-node
side of RSENSE is an accurate representation of the load
current. When using the MOSFET as the sensing
element, the variation of RDS(ON) causes proportional
variation in the ISNS. This value varies from device to
device and has a typical junction temperature
coefficient of about 0.4%/°C (consult the MOSFET
datasheet for actual values), so the actual current limit
set point decreases proportional to increasing MOSFET
die temperature. A factor of 1.6 in the current limit set
point should compensate for MOSFET RDS(ON)
variations, assuming the MOSFET heat sinking keeps
its operating die temperature below 125°C.
RSENSE must, however, be kept higher than:
‫)ܱܰ(ܵܦܴ ∙ ) ܺܣܯ( ܦܣܱܮܫ‬
− 100
150µ‫ܣ‬
10.8 100 + ܴܵ‫ܧܵܰܧ‬
∙
ܴ‫ܯܫܮܫ‬
ܴ‫)ܱܰ(ܵܦ‬
ILIMIT > 1.2 x 1.25 x 1.6 x 2A
The following discussion refers to Figure 12.
ܴܵ‫= ܧܵܰܧ‬
(3c)
Current limit (ILIMIT) should be set high enough to allow
inductor current to rise in response to an output load
transient. Typically, a factor of 1.2 is sufficient. In
addition, since ILIMIT is a peak current cut-off value,
multiply ILOAD(MAX) by the inductor ripple current (e.g.
25%). For example, in Figure 6, the target for ILIMIT:
Current Processing Section
‫ ∙ )ܱܰ(ܵܦܴ ∙ ) ܺܣܯ( ܦܣܱܮܫ‬4.1‫ܭ‬
− 100
30% ∙ 0.125 ∙ ܸ‫) ܺܣܯ(ܰܫ‬
0.9
10.8
=
ܴ‫ܯܫܮܫܴ ܯܫܮܫ‬
therefore:
When SS reaches 1.5V, the power-good outputs are
enabled and Hysteretic Mode is allowed. The converter
is forced into PWM Mode during soft-start.
ܴܵ‫= ܧܵܰܧ‬
(3b)
and at the ILIM 0.9V threshold:
The voltage at the positive input of the error amplifier is
limited by the voltage at the SS pin, which is charged
with a 5µA current source. Once CSS has charged to
VREF (0.9V) the output voltage is in regulation. The time
it takes SS to reach 0.9V is:
0.9 xCSS
t 0.9 =
5
where t0.9 is in seconds if CSS is in µF.
‫)ܱܰ(ܵܦܴ ∙ ܦܣܱܮܫ‬
100 + ܴܵ‫ܧܵܰܧ‬
FAN5026 — Dual DDR / Dual-Output PWM Controller
Since
Initialization and Soft Start
Improving Current-Sensing Accuracy
More accurate sensing can be achieved by using a
resistor (R1) instead of the RDS(ON) of the FET, as shown
in Figure 11. This approach causes higher losses, but
yields greater accuracy in both VDROOP and ILIMIT. R1 is a
low value resistor (e.g. 10mΩ).
(3a)
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10
During severe load increase, the error amplifier output
can go to its upper limit, pushing a duty cycle to almost
100% for significant amount of time. This could cause a
large increase of the inductor current and lead to a long
recovery from a transient, over-current condition, or
even to a failure at especially high input voltages. To
prevent this, the output of the error amplifier is clamped
to a fixed value after two clock cycles if severe output
Figure 12.
DC MAX =
V IN
 2 .4
+ 
 VIN




(5)
This is designed to not interfere with normal PWM
operation. When FPWM is grounded, the duty cycle
clamp is disabled and the maximum duty cycle is 87%.
Current Limit / Summing Circuits
There must be a low-resistance, low-inductance path
between the driver pin and the MOSFET gate for the
adaptive dead-time circuit to function properly. Any
delay along that path subtracts from the delay
generated by the adaptive dead-time circuit and shootthrough may occur.
Gate Driver Section
The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive
signals, providing necessary amplification, level shifting,
and shoot-through protection. Also, it has functions that
optimize the IC performance over a wide range of
operating conditions. Since MOSFET switching time
can vary dramatically from type to type and with the
input voltage, the gate control logic provides adaptive
dead time by monitoring the gate-to-source voltages of
both upper and lower MOSFETs. The lower MOSFET
drive is not turned on until the gate-to-source voltage of
the upper MOSFET has decreased to less than
approximately 1V. Similarly, the upper MOSFET is not
turned on until the gate-to-source voltage of the lower
MOSFET has decreased to less than approximately 1V.
This allows a wide variety of upper and lower MOSFETs
to be used without a concern for simultaneous
conduction or shoot-through.
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
V OUT
FAN5026 — Dual DDR / Dual-Output PWM Controller
voltage excursion is detected, limiting the maximum
duty cycle to:
Duty Cycle Clamp
Frequency Loop Compensation
Due to the implemented current-mode control, the
modulator has a single-pole response with -1 slope at
frequency determined by load:
f PO =
1
2π R O CO
(6)
where RO is load resistance; CO is load capacitance.
www.fairchildsemi.com
11
fZ =
1
= 6kHz
2π R 2C1
(7)
fP =
1
= 600kHz
2πR 2 C 2
(8)
L(OUT)
VOUT
R5
C(Z)
C(OUT)
VSEN
R6
Figure 14.
Improving Phase Margin
This region is also associated with phase “bump” or
reduced phase shift. The amount of phase-shift
reduction depends on the width of the region of flat gain
and has a maximum value of 90°. To further simplify the
converter compensation, the modulator gain is kept
independent of the input voltage variation by providing
feedforward of VIN to the oscillator ramp.
The optimal value of C(Z) is:
The zero frequency, the amplifier high-frequency gain,
and the modulator gain are chosen to satisfy most
typical applications. The crossover frequency appears
at the point where the modulator attenuation equals the
amplifier high-frequency gain. The system designer
must specify the output filter capacitors to position the
load main pole somewhere within a decade lower than
the amplifier zero frequency. With this type of
compensation, plenty of phase margin is achieved due
to zero-pole pair phase “boost.”
The converter output is monitored and protected
against extreme overload, short-circuit, over-voltage,
and under-voltage conditions.
C(Z) =
A sustained overload on an output sets the PGx pin
LOW and latches-off the regulator on which the fault
occurs. Operation can be restored by cycling the VCC
voltage or by toggling the EN pin.
If VOUT drops below the under-voltage threshold, the
regulator shuts down immediately.
Over-Current Sensing
If the circuit’s current-limit signal (“ILIM det” in Figure
12) is HIGH at the beginning of a clock cycle, a pulseskipping circuit is activated and HDRV is inhibited. The
circuit continues to pulse skip in this manner for the
next eight clock cycles. If, at any time from the ninth to
the sixteenth clock cycle, the ILIM det is again reached;
the over-current protection latch is set, disabling the
regulator. If ILIM det does not occur between cycles
nine and sixteen, normal operation is restored and the
over-current circuit resets itself.
C1
R1
VIN
EA Out
REF
C
rt e
am
ve
or
on
err
r
p
(9)
Protections
C2
R2
L(OUT) ×C(OUT)
R
FAN5026 — Dual DDR / Dual-Output PWM Controller
If a larger inductor value or low-ESR values are
required by the application, additional phase margin can
be achieved by putting a zero at the LC crossover
frequency. This can be achieved with a capacitor across
the feedback resistor (e.g. R5 from Figure 6), as shown
in Figure 14.
For this type of modulator, a Type-2 compensation
circuit is usually sufficient. To reduce the number of
external components and simplify the design, the PWM
controller has an internally compensated error amplifier.
Figure 13 shows a Type-2 amplifier and its response
with the responses of a current-mode modulator and
the converter. The Type-2 amplifier, in addition to the
pole at the origin, has a zero-pole pair that causes a flat
gain region at frequencies between zero and the pole.
modul ator
18
14
0
f
P0
Figure 13.
f
Z
f
P
Compensation
Conditional stability may occur only when the main load
pole is positioned too much to the left on the frequency
axis due to excessive output filter capacitance. In this
case, an ESR zero placed within the 10kHz to 50kHz
range gives some additional phase boost. Fortunately,
there is an opposite trend in mobile applications to keep
the output capacitor as small as possible.
Figure 15.
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
Over-Current Protection Waveforms
www.fairchildsemi.com
12
Over-Temperature Protection
The chip incorporates an over-temperature protection
circuit that shuts the chip down if a die temperature of
about 150°C is reached. Normal operation is restored at
die temperature below 125°C with internal power-on
reset asserted, resulting in a full soft-start cycle.
This OVP scheme provides a ”soft” crowbar function,
which accommodates severe load transients and does
not invert the output voltage when activated —
a common problem for latched OVP schemes.
Design and Component Selection Guidelines
As an initial step, define the operating input voltage
range, output voltage, and minimum and maximum load
currents for the controller.
for this example, use:
VIN = 12, V OUT = 2.5
∆I = 25% • 6 A = 1.5 A
Setting the Output Voltage
The internal reference voltage is 0.9V. The output is
divided down by a voltage divider to the VSEN pin (for
example, R5 and R6 in Figure 5). The output voltage
therefore is:
therefore:
0.9 V V OUT − 0.9 V
=
R6
R5
Output Capacitor Selection
L ≈ 4.4µH
(10)
(1.82 KΩ )(VOUT
− 0 .9
0 .9
) = 3.24KΩ
(11)
ESR <
For DDR applications converting from 3.3V to 2.5V or
other applications requiring high duty cycles, the duty
cycle clamp must be disabled by tying the converter’s
FPWM to GND. When converter’s FPWM is at GND,
the converter’s maximum duty cycle is greater than
90%. When using as a DDR converter with 3.3V input,
set up the converter for in-phase synchronization by
tying the VIN pin to +5V.
∆V =
The minimum practical output inductor value keeps the
inductor current just on the boundary of continuous
conduction at some minimum load. Industry standard
practice is to choose the minimum current somewhere
from 15% to 35% of the nominal current. At light load,
the controller can automatically switch to Hysteretic
Mode to sustain high efficiency. The following equations
select the proper value of the output filter inductor:
∆V
OUT
VIN − V OUT
f SW × ∆I
V OUT
VIN
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
∆I
COUT × 8 × fSW
(17)
The capacitor must also be rated to withstand the RMS
current, which is approximately 0.3 X (∆I), or about
400mA, for the converter in Figure 6. High-frequency
decoupling capacitors should be placed as close to the
loads as physically possible.
Input Capacitor Selection
(12)
The input capacitor should be selected by its ripple
current rating.
ESR
×
(16)
which is only about 1.5mV for the converter in Figure 6
and can be ignored.
where ∆I is the inductor ripple current and ∆VOUT is the
maximum ripple allowed:
L=
∆V
∆I
In addition, the capacitor’s ESR must be low enough to
allow the converter to stay in regulation during a load
step. The ripple voltage due to ESR for the converter in
Figure 6 is 120mVPP. Some additional ripple appears
due to the capacitance value itself:
Output Inductor Selection
∆I = 2 × 1MIN =
(15)
The output capacitor serves two major functions in a
switching power supply. Along with the inductor, it filters
the sequence of pulses produced by the switcher and it
supplies the load transient currents. The requirements
are usually dictated by ESR, inductor ripple current (∆I),
and the allowable ripple voltage (∆V):
To minimize noise pickup on this node, keep the
resistor to GND (R6) below 2K; for example, R6 at
1.82KΩ. Then choose R5:
R5 =
(14)
f SW = 300KHz
FAN5026 — Dual DDR / Dual-Output PWM Controller
Similarly, if an output short-circuit or severe load
transient causes the output to drop to less than 75% of
the regulation set point, the regulator shuts down.
Over-Voltage / Under-Voltage Protection
Should the VSNS voltage exceed 120% of VREF (0.9V)
due to an upper MOSFET failure or for other reasons,
the over-voltage protection comparator forces LDRV
HIGH. This action actively pulls down the output voltage
and, in the event of the upper MOSFET failure,
eventually blows the battery fuse. As soon as the output
voltage drops below the threshold, the OVP comparator
is disengaged.
(13)
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13
In DDR Mode (Figure 5), the VTT power input is
powered by the VDDQ output; therefore all of the input
capacitor ripple current is produced by the VDDQ
converter. A conservative estimate of the output current
required for the 2.5V regulator is:
I REGI = I VDDQ +
I VTT
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1’s switching losses
occur during the shaded time when the MOSFET has
voltage across it and current through it.
(18)
2
These losses are given by:
As an example, if the average IVDDQ is 3A and average
IVTT is 1A, IVDDQ current is about 3.5A. If average input
voltage is 16V, RMS input ripple current is:
I RMS = I OUT ( MAX ) D − D
2
(19)
where D is the duty cycle of the PWM1 converter and:
D<
VOUT
VIN
2.5
=
12
I RMS
2
(21)
= I
IRMS =
2
RMS(1)
+I
2
RMS( 2 )
or
(I1 )2 (D1 − D12 ) + (I2 )2 (D 2 − D 2 2 )
V OUT
VIN
× I OUT 2 × R DS( ON)
(27)
and
tS is the switching period (rise or fall time), shown as t2
and t3 in Figure 16.
In Dual Mode (shown in Figure 5), both converters
contribute to the capacitor input ripple current. With
each converter operating 180° out of phase, the RMS
currents add in the following fashion:
RMS
(26)
RDS(ON) is at the maximum junction temperature (TJ);
Dual Converter 180° Phased
I
 V ×I

PSW =  DS L × 2 × t s  f SW


2


where:
PUPPER is the upper MOSFET’s total losses and PSW
and PCOND are the switching and conduction losses for a
given MOSFET;
therefore:

 = 1.42A


(25)
PCOND =
(20)
2.5  2.5
= 3.5
−
12  12

PUPPER = PSW + PCOND
FAN5026 — Dual DDR / Dual-Output PWM Controller
(QG). CISS = CGD + CGS and it controls t1, t2, and t4
timing. CGD receives the current from the gate driver
during t3 (as VDS is falling). The gate charge (QG)
parameters on the lower graph are either specified in or
can be derived from MOSFET datasheets.
Two-Stage Converter Case
The driver’s impedance and CISS determine t2, while
t3’s period is controlled by the driver’s impedance and
QGD. Since most of tS occurs when VGS = VSP, use a
constant current assumption for the driver to simplify
the calculation of tS:
(22)
CISS
C GD
QGS
QGD
C ISS
VDS
(23)
which, for the dual 3A converters of Figure 6, calculates:
IRMS = 1.51A
(24)
Power MOSFET Selection
ID
Losses in a MOSFET are the sum of its switching (PSW)
and conduction (PCOND) losses.
In typical applications, the FAN5026 converter’s output
voltage is low with respect to its input voltage.
Therefore, the lower MOSFET (Q2) is conducting the
full load current for most of the cycle. Q2 should
therefore be selected to minimize conduction losses,
thereby selecting a MOSFET with low RDS(ON).
4.5V
VSP
VTH
QG(SW)
VGS
t1
In contrast, the high-side MOSFET (Q1) has a much
shorter duty cycle and it’s conduction loss has less
impact. Q1, however, sees most of the switching losses,
the primary selection criteria should be gate charge.
Figure 16.
t2
t3
t4
t5
Switching Losses and QG
VIN
5V
C GD
High-Side Losses
RD
Figure 16 shows a MOSFET’s switching interval, with
the upper graph being the voltage and current on the
drain-to-source and the lower graph detailing VGS vs.
time with a constant current charging the gate. The X
axis, therefore, is also representative of gate charge
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
HDRV
RGATE
G
CGS
SW
Figure 17.
Drive Equivalent Circuit
www.fairchildsemi.com
14
Q G( SW )
Q G( SW )
=
Layout Considerations
 V −V

(28)
CC
SP


R

R
+
GATE 
 DRIVER
Most MOSFET vendors specify QGD and QGS. QG(SW)
can be determined as:
I DRIVER
Q G(SW ) = Q GD + Q GS − Q TH
Switching converters, even during normal operation,
produce short pulses of current that could cause
substantial ringing and be a source of EMI if layout
constraints are not observed.
There are two sets of critical components in a DC-DC
converter. The switching power components process
large amounts of energy at high rates and are noise
generators. The low-power components responsible for
bias and feedback functions are sensitive to noise.
(29)
where QTH is the gate charge required to get the
MOSFET to it’s threshold (VTH).
A multi-layer printed circuit board is recommended.
Dedicate one solid layer for a ground plane. Dedicate
another solid layer as a power plane and break this
plane into smaller islands of common voltage levels.
For the high-side MOSFET, VDS = VIN, which can be as
high as 20V in a typical portable application. Care
should be taken to include the delivery of the
MOSFET’s gate power (PGATE) in calculating the
power dissipation required for the FAN5026:
PG
ATE
= Q G × V CC × f SW
Notice all the nodes that are subjected to high-dV/dt
voltage swing; such as SW, HDRV, and LDRV. All
surrounding circuitry tends to couple the signals from
these nodes through stray capacitance. Do not oversize
copper traces connected to these nodes. Do not place
traces connected to the feedback components adjacent
to these traces. It is not recommended to use highdensity interconnect systems, or micro-vias, on these
signals. The use of blind or buried vias should be
limited to the low-current signals only. The use of
normal thermal vias is at the discretion of the designer.
(30)
where QG is the total gate charge to reach VCC.
Low-Side Losses
Q2, however, switches on or off with its parallel
Schottky diode conducting, therefore VDS ≈ 0.5V. Since
PSW is proportional to VDS, Q2’s switching losses are
negligible and Q2 is selected based on RDS(ON) only.
Keep the wiring traces from the IC to the MOSFET gate
and source as short as possible and capable of
handling peak currents of 2A. Minimize the area within
the gate-source path to reduce stray inductance and
eliminate parasitic ringing at the gate.
Conduction losses for Q2 are given by:
PCOND = (1 − D ) × I OUT 2 × R DS( ON)
(31)
where RDS(ON) is the RDS(ON) of the MOSFET at the
highest operating junction temperature, and:
D=
V OUT
Locate small critical components, like the soft-start
capacitor and current-sense resistors, as close as
possible to the respective pins of the IC.
(32)
VIN
FAN5026 — Dual DDR / Dual-Output PWM Controller
ts =
The FAN5026 utilizes advanced packaging technology
with lead pitch of 0.6mm. High-performance analog
semiconductors utilizing narrow lead spacing may
require special considerations in design and
manufacturing. It is critical to maintain proper
cleanliness of the area surrounding these devices.
is the minimum duty cycle for the converter.
Since DMIN < 20% for portable computers, (1-D) ≈ 1
produces a conservative result, further simplifying the
calculation.
The maximum power dissipation (PD(MAX)) is a function of
the maximum allowable die temperature of the low-side
MOSFET; the ΘJA, and the maximum allowable ambient
temperature rise:
PD(MAX ) =
T J(MAX ) − T A (MAX )
Θ JA
(33)
ΘJA depends primarily on the amount of PCB area that
can be devoted to heat sinking (see Application Note
AN-1029, Maximum Power Enhancement Techniques
for SO-8 Power MOSFETs for SO-8 MOSFET thermal
information).
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
www.fairchildsemi.com
15
FAN5026 — Dual DDR / Dual-Output PWM Controller
Physical Dimensions
Figure 18.
28-Lead, Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
www.fairchildsemi.com
16
FAN5026 — Dual DDR / Dual-Output PWM Controller
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
www.fairchildsemi.com
17
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