ICST ICS83947AYI-147 Low skew, 1-to-9 lvcmos/lvttl fanout buffer Datasheet

ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83947I-147 is a low skew, 1-to-9
LVCMOS/LVTTL Fanout Buffer and a member of
HiPerClockS™
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50Ω
series or parallel terminated transmission lines. The effective
fanout can be increased from 9 to 18 by utilizing the ability of
the outputs to drive two series terminated lines.
• 9 LVCMOS/LVTTL outputs
Guaranteed output and part-to-part skew characteristics make
the ICS83947I-147 ideal for high performance, 3.3V or 2.5V
single ended applications.
• Additive phase jitter, RMS: 0.02ps (typical) @ 3.3V
ICS
• Selectable CLK0 and CLK1 can accept the following
input levels: LVCMOS and LVTTL
• Maximum output frequency: 250MHz
• Output skew: 115ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Pin compatible with the MPC947
BLOCK DIAGRAM
PIN ASSIGNMENT
GND
32 31 30 29 28 27 26 25
Q0
Q1
CLK_SEL
Q2
1
VDDO
CLK1
Q1
0
GND
CLK0
Q0
Q
LE
VDDO
GND
D
CLK_EN
Q2
Q3
Q4
Q5
GND
1
24
GND
CLK_SEL
2
23
Q3
CLK0
3
22
VDDO
CLK1
4
21
Q4
CLK_EN
5
20
GND
OE
6
19
Q5
VDD
7
18
VDDO
GND
8
17
GND
ICS83947I-147
9 10 11 12 13 14 15 16
GND
Q6
VDDO
Q7
GND
Q8
Q7
VDDO
GND
Q6
Q8
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
OE
83947AYI-147
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1
REV. A SEPTEMBER 24, 2004
ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 8, 9, 12, 16, 17,
20, 24, 25, 29, 32
GND
Power
2
CLK_SEL
Input
3, 4
CLK0, CLK1
Input
5
CLK_EN
Input
Pullup Clock enable. LVCMOS / LVTTL interface levels.
6
OE
Input
Pullup Output enable. LVCMOS / LVTTL interface levels.
7
VDD
Power
Power supply ground.
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
Pullup
Core supply pin.
10, 14, 18, 22, 27, 31
VDDO
Power
Output supply pins.
Q0 thru Q8 clock outputs.
11, 13, 15, 19, 21,
Q8, Q7, Q6, Q5,
Output
23, 26, 28, 30
Q4, Q3, Q2, Q1, Q0
LVCMOS / LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
4
pF
12
pF
RPULLUP
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
51
KΩ
ROUT
Output Impedance
7
Ω
CPD
Test Conditions
TABLE 3. OUTPUT ENABLE
Control Inputs
AND
Typical
Maximum
Units
CLOCK ENABLE FUNCTION TABLE
Output
OE
CLK_EN
0
X
Hi-Z
1
0
LOW
1
1
Follows CLK input
83947AYI-147
Minimum
Q0:Q8
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REV. A SEPTEMBER 24, 2004
ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V OR 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
VDD
Test Conditions
Core Supply Voltage
Minimum
Typical
Maximum
Units
3.0
3.3
3.6
V
2.375
2.5
2.625
V
3.0
3.3
3.6
V
2.375
2.5
VDDO
Output Supply Voltage
2.625
V
IDD
Input Supply Current
50
mA
IDDO
Output Supply Current
9
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VIH
Input High Voltage
VIL
Input Low Voltage
Minimum
Typical
2
CLK0, CLK1, OE,
CLK_SEL, CLK_EN
IIN
Input Current
VOH
Output High Voltage; NOTE 1
IOH = -20mA
Maximum
Units
3.6
V
0.8
V
-100
µA
2.5
V
VOL
Output Low Voltage; NOTE 1
IOL = 20mA
0.4
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section, 3.3V Output Load Test
Circuit Diagram.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
VIH
Test Conditions
Minimum
Input High Voltage
Typical
Maximum
Units
2
VDD + 0.3
V
CLK0, CLK1
-0.3
1.3
V
CLK_SEL, CLK_EN, OE
-0.3
0.8
V
5
µA
VIL
Input Low Voltage
IIH
Input High Current
CLK0, CLK1, OE,
CLK_SEL, CLK_EN
IIL
Input Low Current
CLK0, CLK1, OE,
CLK_SEL, CLK_EN
VOH
Output High Voltage; NOTE 1
VDD = VIN = 2.625V
VDD = 32.625V,
VIN = 0V
-150
µA
1.8
V
VOL
Output Low Voltage; NOTE 1
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section, 2.5V Output Load Test
Circuit Diagram.
83947AYI-147
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3
REV. A SEPTEMBER 24, 2004
ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
fMAX
Output Frequency
tPD
Propagation Delay, NOTE 1
tsk(o)
Output Skew; NOTE 2, 5
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 5
t R / tF
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Output Rise/Fall Time
tjit(Ø)
Test Conditions
Minimum
f ≤ 250MHZ
Measured on
rising edge @VDDO/2
Measured on
rising edge @VDDO/2
2
(12KHz to 20MHz)
Typical
Maximum
250
Units
MHz
4.2
ns
115
ps
500
ps
ps
0.2
0.8V to 2.0V
0.2
1
ns
tPW
Output Pulse Width
f > 133MHz
tPeriod/2 - 1
tPeriod/2 + 1
ns
odc
Output Duty Cycle
f ≤ 133MHz
40
60
%
tEN
Output Enable Time; NOTE 4
10
ns
tDIS
Output Disable Time; NOTE 4
10
tS
Clock Enable Setup Time
0
ns
ns
Clock Enable Hold Time
1
ns
tS
All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
fMAX
Output Frequency
tPD
Propagation Delay, NOTE 1
tsk(o)
Output Skew; NOTE 2, 5
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 5
tR / tF
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Output Rise/Fall Time
tjit(Ø)
Test Conditions
Minimum
f ≤ 250MHZ
Measured on
rising edge @VDDO/2
Measured on
rising edge @VDDO/2
2.4
(12KHz to 20MHz)
20% - 80%
Typical
Maximum
250
Units
MHz
4.5
ns
130
ps
600
ps
0.1
ps
300
800
ps
tPeriod/2 - 1.2
tPW
Output Pulse Width
tPeriod/2 + 1.2
ns
t EN
Output Enable Time; NOTE 4
10
ns
tDIS
Output Disable Time; NOTE 4
10
ns
tS
Clock Enable Setup Time
0
ns
Clock Enable Hold Time
1
ns
tS
All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
83947AYI-147
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REV. A SEPTEMBER 24, 2004
ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
SSB PHASE NOISE dBc/HZ
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz)
= 0.02ps typical @ 3.3V
10k
100k
1M
10M
100M
SSB PHASE NOISE dBc/HZ
OFFSET FROM CARRIER FREQUENCY (HZ)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz)
= 0.01ps typical @ 2.5V
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de83947AYI-147
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
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REV. A SEPTEMBER 24, 2004
ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V ± 0.15V
1.25V±5%
SCOPE
VDD,
SCOPE
VDD,
VDDO
VDDO
Qx
LVCMOS
Qx
LVCMOS
GND
GND
-1.65V ± 0.15V
-1.25V±5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
PART 1
2.5V OUTPUT LOAD AC TEST CIRCUIT
V
V
DDO
DDO
Qx
Qx
2
PART 2
2
V
V
DDO
DDO
Qy
Qy
2
t sk(pp)
PART-TO-PART SKEW
OUTPUT SKEW
VDD
2
CLK0,CLK1
2
t sk(o)
Q0:Q8
VDDO
VDDO
VDDO
2
2
2
t PW
t PERIOD
VDDO
2
Q0:Q8
t
odc =
PD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
2V
Clock
Outputs
2V
0.8V
0.8V
tR
Clock
Outputs
tF
3.3V OUTPUT RISE/FALL TIME
83947AYI-147
t PW
t PERIOD
80%
80%
tR
tF
20%
20%
2.5V OUTPUT RISE/FALL TIME
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REV. A SEPTEMBER 24, 2004
ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
APPLICATION SCHEMATIC EXAMPLE
Figure 1 shows an example of ICS83947I-147 application schematic. In this example, the device is operated at VCC=3.3V. The
decoupling capacitors should be located as close as possible
to the power pin. The input is driven by a 3.3V LVCMOS driver.
For the LVCMOS output drivers, only one termination example
is shown in this schematic. Additional termination approaches
are shown in the LVCMOS Termination Application Note (refer
to ICS website).
VDDO
R1
43
Zo = 50
R2
43
Zo = 50
VCC
43
Zo = 50 Ohm
LVCMOS
R3
43
Zo = 50 Ohm
GND
CLK_SEL
CLK0
CLK1
CLK_EN
OE
VDD
GND
VDD
LVCMOS
GND
Q3
VDDO
Q4
GND
Q5
VDDO
GND
24
23
22
21
20
19
18
17
GND
VDDO
Q8
GND
Q7
VDDO
Q6
GND
1
2
3
4
5
6
7
8
VCC
U1
ICS83947I-147
GND
VDDO
Q0
GND
Q1
VDDO
Q2
GND
32
31
30
29
28
27
26
25
R3
9
10
11
12
13
14
15
16
C5
0.1u
VDD=3.3V
VDDO=3.3V
VDDO
(U1-10)
C1
0.1u
(U1-14)
(U1-18)
C2
0.1u
C3
0.1u
(U1-31)
(U1-27)
(U1-22)
C4
0.1u
C2
0.1u
C3
0.1u
FIGURE 1. ICS83947I-147 SCHEMATIC LAYOUT
83947AYI-147
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REV. A SEPTEMBER 24, 2004
ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
200
500
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83947I-147 is: 1040
83947AYI-147
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REV. A SEPTEMBER 24, 2004
ICS83947I-147
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
FOR
32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
0.80 BASIC
e
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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REV. A SEPTEMBER 24, 2004
ICS83947I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS83947AYI-147
ICS83947AI147
32 Lead LQFP
250 per tray
-40°C to 85°C
ICS83947AYI-147T
ICS83947AI147
32 Lead LQFP on Tape and Reel
1000
-40°C to 85°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83947AYI-147
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10
REV. A SEPTEMBER 24, 2004
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