Infineon AUIRF1324STRL Automotive grade Datasheet

AUIRF1324S
AUIRF1324L
AUTOMOTIVE GRADE
HEXFET® Power MOSFET
Features
 Advanced Process Technology
 Ultra Low On-Resistance
 Dynamic dV/dT Rating
 175°C Operating Temperature
 Fast Switching
 Repetitive Avalanche Allowed up to Tjmax
 Lead-Free, RoHS Compliant
 Automotive Qualified *
VDSS
RDS(on) typ.
Package Type
AUIRF1324L
TO-262
AUIRF1324S
D2-Pak
1.3m
max.
ID (Silicon Limited)
1.65m
340A
ID (Package Limited)
195A
D
D
Description
Specifically designed for Automotive applications, this HEXFET®
Power MOSFET utilizes the latest processing techniques to achieve
extremely low on-resistance per silicon area. Additional features of
this design are a 175°C junction operating temperature, fast
switching speed and improved repetitive avalanche rating . These
features combine to make this design an extremely efficient and
reliable device for use in Automotive applications and a wide variety
of other applications.
Base part number
24V
S
D
S
G
D2Pak
G
TO-262
AUIRF1324S
AUIRF1324L
G
Gate
D
Drain
Standard Pack
Form
Quantity
Tube
50
Tube
50
Tape and Reel Left
800
S
Source
Orderable Part Number
AUIRF1324L
AUIRF1324S
AUIRF1324STRL
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance
Symbol
Parameter
Max.
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
340
ID @ TC = 100°C
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Package Limited)
240
195
IDM
PD @TC = 25°C
Pulsed Drain Current 
Maximum Power Dissipation
1420
300
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy (Thermally Limited) 
Avalanche Current 
Repetitive Avalanche Energy 
Peak Diode Recovery 
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
Thermal Resistance
Symbol
RJC
RJA
Parameter
Junction-to-Case 
Junction-to-Ambient (PCB Mount), D2 Pak
Units
A
W
2.0
± 20
270
See Fig.14,15, 18a, 18b
0.46
-55 to + 175
W/°C
V
mJ
A
mJ
V/ns
°C
300
Typ.
Max.
Units
–––
–––
0.50
40
°C/W
HEXFET® is a registered trademark of Infineon.
*Qualification standards can be found at www.infineon.com
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AUIRF1324S/L
Static @ TJ = 25°C (unless otherwise specified)
Parameter
V(BR)DSS
Drain-to-Source Breakdown Voltage
Min.
Typ. Max.
Units
V
Conditions
24
–––
–––
VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient
–––
22
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
1.3
1.65
VGS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
VDS = VGS, ID = 250µA
gfs
RG
Forward Trans conductance
Gate Resistance
–––
–––
20
VDS = 10V, ID = 195A
Drain-to-Source Leakage Current
–––
2.3
–––
S

IDSS
180
–––
–––
–––
–––
250
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
–––
–––
–––
–––
100
-100
mV/°C Reference to 25°C, ID = 5mA 
m VGS = 10V, ID = 195A 
µA
nA
VDS = 24V, VGS = 0V
VDS = 24V,VGS = 0V,TJ =125°C
VGS = 20V
VGS = -20V
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
160
84
49
76
17
190
83
120
7590
3440
240
–––
–––
–––
–––
–––
–––
–––
–––
–––
Crss
Reverse Transfer Capacitance
–––
1960
–––
Coss eff.(ER)
Effective Output Capacitance (Energy Related)
–––
4700
–––
VGS = 0V, VDS = 0V to 19V
Coss eff.(TR)
Effective Output Capacitance (Time Related)
–––
4490
–––
VGS = 0V, VDS = 0V to 19V
Min.
Typ. Max.
–––
––– 350
–––
–––
1420
–––
–––
–––
–––
–––
–––
–––
46
71
160
430
7.7
1.3
–––
–––
–––
–––
–––
Diode Characteristics
Parameter
Continuous Source Current
IS
(Body Diode)
Pulsed Source Current
ISM
(Body Diode)
VSD
Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
nC
ns
pF
Units
A
V
ns
nC
A
ID = 195A
VDS = 12V
VGS = 10V
VDD = 16V
ID = 195A
RG= 2.7
VGS = 10V
VGS = 0V
VDS = 24V
ƒ = 1.0MHz, See Fig. 5
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
TJ = 25°C,IS = 195A,VGS = 0V 
TJ = 25°C
VDD = 20V
TJ = 125°C
IF = 195A,
TJ = 25°C di/dt = 100A/µs 
TJ = 125°C
TJ = 25°C 
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 195A. Note that
current limitations arising from heating of the device leads may occur with some lead mounting arrangements.
 Repetitive rating; pulse width limited by max. junction temperature.
 Limited by TJmax, starting TJ = 25°C, L = 0.014mH, RG = 25, IAS = 195A, VGS =10V. Part not recommended for use above this value.
 ISD 195A, di/dt 450A/µs, VDD V(BR)DSS, TJ  175°C.
 Pulse width 400µs; duty cycle  2%.
 Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
 Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
 When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994
 R is measured at TJ approximately 90°C.
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10000
60µs PULSE WIDTH
Tj = 25°C
1000
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.5V
4.0V
TOP
BOTTOM
100
60µs PULSE WIDTH
Tj = 175°C
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
10000
TOP
1000
10
BOTTOM
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.5V
4.0V
100
1
4.0V
4.0V
0.1
10
0.1
1
10
100
0.1
V DS, Drain-to-Source Voltage (V)
Fig. 2 Typical Output Characteristics
R DS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
100
2.0
1000
100
T J = 175°C
T J = 25°C
10
1
VDS = 15V
60µs PULSE WIDTH
ID = 195A
VGS = 10V
1.5
1.0
0.5
0.1
2
3
4
5
6
7
8
9
-60 -40 -20 0 20 40 60 80 100 120 140160 180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig. 4 Normalized On-Resistance vs. Temperature
Fig. 3 Typical Transfer Characteristics
100000
14.0
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
ID = 195A
= C gd
VGS, Gate-to-Source Voltage (V)
Crss
Coss = Cds + Cgd
C, Capacitance (pF)
10
V DS, Drain-to-Source Voltage (V)
Fig. 1 Typical Output Characteristics
Ciss
C oss
10000
Crss
1000
12.0
VDS = 19V
VDS = 12V
10.0
8.0
6.0
4.0
2.0
0.0
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
3
1
0
50
100
150
200
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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AUIRF1324S/L
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
T J = 175°C
100
T J = 25°C
10
OPERATION IN THIS AREA
LIMITED BY R DS (on)
1000
1msec
100
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.5
1.0
Limited by
package
10msec
10
1
1.5
10
ID, Drain Current (A)
Limited By Package
250
200
150
100
50
0
25
50
75
100
125
150
175
Fig 8. Maximum Safe Operating Area
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
300
32
Id = 5mA
30
28
26
24
-60 -40 -20 0 20 40 60 80 100 120 140160 180
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs. Case Temperature
EAS , Single Pulse Avalanche Energy (mJ)
1.8
ID
44A
83A
BOTTOM 195A
TOP
1000
1.6
1.4
Energy (µJ)
Fig 10. Drain-to-Source Breakdown Voltage
1200
2.0
1.2
1.0
0.8
0.6
0.4
0.2
800
600
400
200
0
0.0
-5
0
5
10
15
20
25
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
100
VDS , Drain-to-Source Voltage (V)
VSD , Source-to-Drain Voltage (V)
350
DC
1
1.0
0.0
100µsec
30
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. Drain Current
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AUIRF1324S/L
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
Ri (°C/W)
0.20
0.1
0.10
J
0.05
R1
R1
J
1
0.02
0.01
0.01
R2
R2
R3
R3
R4
R4
C
2
1
2
3
3
4
Ci= iRi
Ci= iRi
1E-005
0.0125
0.000008
0.0822
0.000078
0.2019
0.001110
0.2036
0.007197
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
4
C
I (sec)
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
Duty Cycle = Single Pulse
0.01
100
0.05
0.10
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming  j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Avalanche Current vs. Pulse width
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Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.infineon.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 18a, 18b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 13, 14).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
EAR , Avalanche Energy (mJ)
300
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 195A
250
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy vs. Temperature
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
VGS(th) , Gate threshold Voltage (V)
4.5
4.0
3.5
3.0
2.5
2.0
ID = 250µA
ID = 1.0mA
ID = 1.0A
1.5
1.0
-75 -50 -25 0
25 50 75 100 125 150 175 200
T J , Temperature ( °C )
Fig 16. Threshold Voltage vs. Temperature
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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
15V
tp
L
VDS
D.U.T
RG
IAS
20V
tp
DRIVER
+
V
- DD
A
0.01
Fig 18a. Unclamped Inductive Test Circuit
Fig 19a. Switching Time Test Circuit
I AS
Fig 18b. Unclamped Inductive Waveforms
Fig 19b. Switching Time Waveforms
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Fig 20a. Gate Charge Test Circuit
7
Qgd
Qgodr
Fig 20b. Gate Charge Waveform
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AUIRF1324S/L
D2Pak (TO-263AB) Package Outline (Dimensions are shown in millimeters (inches))
D2Pak (TO-263AB) Part Marking Information
Part Number
AUIRF1324S
Date Code
YWWA
IR Logo
XX

Y= Year
WW= Work Week
XX
Lot Code
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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AUIRF1324S/L
TO-262 Package Outline (Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
Part Number
AUIRF1324L
Date Code
YWWA
IR Logo
XX

Y= Year
WW= Work Week
XX
Lot Code
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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AUIRF1324S/L
D2Pak (TO-263AB) Tape & Reel Information (Dimensions are shown in millimeters (inches))
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
60.00 (2.362)
MIN.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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AUIRF1324S/L
Qualification Information
Automotive
(per AEC-Q101)
Comments: This part number(s) passed Automotive qualification. Infineon’s
Industrial and Consumer qualification level is granted by extension of the higher
Automotive level.
Qualification Level
Moisture Sensitivity Level
D2-Pak
MSL1
TO-262
Machine Model
Human Body Model
ESD
Charged Device Model
RoHS Compliant
Class M4†
AEC-Q101-002
Class H3A†
AEC-Q101-001
Class C5†
AEC-Q101-005
Yes
† Highest passing voltage.
Revision History
Date
11/11/2015
Comments


Updated datasheet with corporate template
Corrected ordering table on page 1.
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third
party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
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the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (www.infineon.com).
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Due to technical requirements products may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies office.
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