TI1 BQ296111DSGR Overvoltage protection for 2-series, 3-series, and 4-series cell li-ion batteries with regulated output supply Datasheet

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bq296xxx Overvoltage Protection for 2-Series, 3-Series, and 4-Series Cell
Li-Ion Batteries with Regulated Output Supply
1 Features
3 Description
•
The bq296xxx family is a high accuracy, low power
overvoltage protector with a 1-mA regulated output
supply for Li-Ion battery pack applications.
1
•
•
•
•
•
•
•
•
•
2-Series, 3-Series, and 4-Series Cell Overvoltage
Protection (OVP)
Fixed Delay Timer to Trigger FET Drive Output
(3-s, 4-s, 5.5-s or 6.5-s Options)
Factory Programmed OVP Threshold (Threshold
Range 3.85 V to 4.6 V)
Output Options: Active High
High-Accuracy Overvoltage Protection:
±10 mV
Regulated Supply Output with self-disable and/or
external enable/disable control
– Options: 3.3-V, 2.5-V, and 1.8-V (bq2960/61)
– Options: 3.3-V, 3.15-V, 3.0-V (bq2962)
Low Power Consumption ICC ≈ 4 µA
(VCELL(ALL) < VPROTECT)
Extra Low Power Consumption with REG output
disabled, ICC ~ 1.2 µA
Low Leakage Current Per Cell Input < 100 nA
Small Package Footprint
– 8-Pin WSON (2 mm × 2 mm)
The regulated output supply delivers up to 1-mA
(max) output current to drive always-on circuits, such
as a real-time clock (RTC) oscillator. The bq296xxx
family has a self-disable function to turn off the
regulated output if any cell voltage falls below a
certain threshold, thereby preventing drain on the
battery, and provides an external control to enable or
disable the regulated output.
Device Information(1)(2)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
WSON (8)
2.00 mm × 2.00 mm
bq2960
bq2961
bq2962
2 Applications
•
•
•
•
Each cell in a 2-series to 4-series cell stack is
individually monitored for an overvoltage condition.
An internally fixed-delay timer is initiated upon
detection of an overvoltage condition on any cell;
upon expiration of the delay timer, an output pin is
triggered into an active state to indicate that an
overvoltage condition has occurred.
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
(2) The bq2960 is a 2-S to 3-S device. The bq2961 and bq2962
are 2-S to 4-S devices.
Notebook PC
Ultrabooks
Medical
UPS Battery Backup
Simplified Schematic
Protector
FETs
Pack +
Protector
FETs
100 Q
Pack +
100 Q
1 kQ
VCELL3
VCELL2
VCELL1
1 kQ
1 kQ
OUT
VDD
0.1 µF
0.1 µF
V3
V2
V1
5
(*)
External
Circuit
e.g., RTC
REG
bq2960xy
VSS
* can be removed if Vss will be
connected first during cell
connection
REG_EN
PWPD
0.1 µF
0.1 µF
1 kQ
VCELL4
1 kQ 0.1 µF
VCELL3
1 kQ 0.1 µF
VCELL2
0.47 µF
Pack ±
VCELL1
1 kQ
0.1 µF
0.1 µF
VDD
OUT
V4
REG
V3
bq2961xy
5
(*)
VSS
* can be removed if Vss will be
connected first during cell
connection
V1
V2
External
Circuit
e.g., RTC
PWPD
0.1 µF 0.47 µF
Pack ±
MCU
bq2960xy REG out is controlled by MCU
CTL
10 M
(Optional)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
bq2961, bq2962
SLUSBU5C – NOVEMBER 2013 – REVISED OCTOBER 2016
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 14
9
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 16
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
Changes from Revision B (May 2016) to Revision C
Page
•
Added bq2962 REG options .................................................................................................................................................. 1
•
Changed Part number to bq2960, bq2961, bq2962 to identify each spin family throughout the datasheet ......................... 1
•
Added bq2962 device to Recommened Operating Conditions ............................................................................................. 2
•
Added bq296202, bq296203, bq296212, bq296213 .............................................................................................................. 3
•
Added bq2962 pinout ............................................................................................................................................................ 4
•
Added bq2962 device to Recommened Operating Conditions ............................................................................................. 5
•
Added bq2962 VREG specification ....................................................................................................................................... 7
•
Added bq2962 regulator programmable option ................................................................................................................... 10
•
Changed figure title to apply to bq2962 family .................................................................................................................... 17
•
Changed figure title to apply to bq2962 .............................................................................................................................. 20
Changes from Revision A (January 2016) to Revision B
•
Page
Added bq296114 to Device Comparison Table...................................................................................................................... 3
Changes from Original (November 2013) to Revision A
Page
•
Changed the device listing in the data sheet header information to: bq2961 ....................................................................... 1
•
Changed bq296106, '107, '111 From: Preview To: Released status .................................................................................... 3
•
Added bq296112 to Device Comparison Table ..................................................................................................................... 3
•
Added bq296113 to Device Comparison Table...................................................................................................................... 3
•
Added Available the bq2961xy configuration range to Device Comparison Table ................................................................ 3
2
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5 Device Comparison Table
bq2961 Family
bq2962 Family
OVP (V)
OVP DELAY (s)
UV (V)
LDO (V)
bq296100 (1)
—
4.35
6.5
2.5
3.3
bq296101 (1)
—
4.40
6.5
2.5
3.3
bq296102 (1)
bq296202 (1)
4.45
6.5
2.5
3.3
bq296103
bq296203 (1)
4.50
6.5
2.5
3.3
(1)
—
4.35
6.5
2.8
3.3
bq296105 (1)
—
4.40
6.5
2.8
3.3
bq296106
—
4.45
6.5
2.8
3.3
bq296107
—
4.50
6.5
2.8
3.3
bq296108 (1)
—
4.50
6.5
2.4
3.3
bq296109 (1)
—
4.325
3.0
2.5
3.3
bq296110 (1)
—
4.45
3.0
2.5
3.3
bq296111
—
4.45
4.0
2.5
3.3
bq296112
bq296212 (1)
4.50
3.0
2.5
3.3
bq296113
bq296213 (1)
4.35
3.0
2.5
3.3
bq296114
—
4.50
4.0
2.5
3.3
bq2961xy
bq2962xy
3.85V - 4.60V in
50mV step
3.0, 4.0, 5.5, 6.5
2.0V - 2.8V in 50mV
step
1.8, 2.5, 3.3 (bq2961)
3, 3.15, 3.3 (bq2962)
bq296104
(1)
Product Preview only
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6 Pin Configuration and Functions
2s-to-3s bq2960xy
(Top View)
2s-to-4s bq2962xy
(Top View)
1
VDD
OUT
8
1
VDD
REG
8
2
V3
REG
7
2
V4
OUT
7
3
V2
VSS
6
3
V3
VSS
6
4
V1
REG_EN
5
4
V2
V1
5
2s-to-4s bq2961xy
(Top View)
1
VDD
OUT
8
2
V4
REG
7
3
V3
VSS
6
4
V2
V1
5
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
BQ2960
BQ2961
BQ2962
OUT
8
8
7
OA
PWPD
9
9
9
P
REG
7
7
8
OA
Regulated Supply Output. Requires an external ceramic capacitor for
stability.
REG_EN
5
—
—
IA
Regulated Supply Output Enable. A "high" to enable REG output and
"low" to disable REG output.
V1
4
5
5
IA
Sense input for positive voltage of the lowest cell from the bottom of the
stack.
V2
3
4
4
IA
Sense input for positive voltage of the second cell from the bottom of the
stack.
V3
2
3
3
IA
Sense input for positive voltage of the third cell from the bottom of the
stack.
V4
—
2
2
IA
Sense input for positive voltage of the fourth cell from the bottom of the
stack.
VDD
1
1
1
P
Power supply input
VSS
6
6
6
P
Electrically connected to integrated circuit ground and negative terminal
of the lowest cell in the stack.
(1)
4
Analog Output drive for overvoltage fault signal, CMOS Output High or
Open Drain Active Low.
TI recommends connecting the exposed pad to VSS on PCB.
IA = Analog input, OA = Analog Output, P = Power connection
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VDD – VSS
–0.3
30
V4 – V3, V3 – V2, V2 – V1, V1 – VSS
–0.3
30
REG – VSS
–0.3
3.6
REG_EN – VSS
–0.3
28
–0.3
30
Supply voltage range
Input voltage range
Output voltage range
OUT – VSS
Continuous total power dissipation, PTOT
UNIT
V
See Thermal Information.
Lead temperature (soldering, 10 s), TSOLDER
300
300
°C
Storage temperature,Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Procedures. Exposure to absolute-maximum–rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
V
500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
MIN
Supply voltage,
VDD (1)
Input voltage
range
MAX
UNIT
(1)
3
15
Supply voltage, VDD
(1)
3
20
V
5
V
, bq2960xy
, bq2961xy, bq2962xy
Supply voltage, VDD with REG output on
4
Vn - Vn-1 , V1 – VSS
0
REG_EN
Operating ambient temperature range, TA
(1)
NOM
Supply voltage, VDD
0
15
V
–40
110
°C
See Typical Application.
7.4 Thermal Information
bq2960xy
THERMAL METRIC (1)
DSG (WSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
62
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
72
°C/W
RθJB
Junction-to-board thermal resistance
32.5
°C/W
ψJT
Junction-to-top characterization parameter
1.6
°C/W
ψJB
Junction-to-board characterization parameter
33
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
10
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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7.5 Electrical Characteristics
Typical values stated where TA = 25°C and VDD = 14.4 V, MIN/MAX values stated where TA = –40°C to 110°C, and VDD =
3 V to 15 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage Protection Thresholds
VOV
V(PROTECT)
Overvoltage
Detection
VHYS
OV Detection
Hysteresis
VOA
OV Detection
Accuracy
VOADRIFT
OV Detection
Accuracy Across
Temperature
Applicable Voltage: 3.85 V
to 4.6 V in 50 mV steps
RIN = 1 kΩ
250
300
V
400
mV
TA = 25°C
–10
10
mV
TA = –40°C
–40
40
mV
TA = 0°C
–20
20
mV
TA = 60°C
–24
24
mV
TA = 110°C
–54
54
mV
TA = 110°C
–54
54
mV
6
µA
8
µA
2
µA
4
µA
0.1
µA
Supply and Leakage Current
(Vn – Vn-1) = 3.8 V and (V1 – VSS) > VUVREG , VDD = top Vn
voltage, IREG = 0 mA, TA = 0°C to 60°C
IDD
Supply Current
4
(Vn – Vn-1) = 3.8 V and (V1 – VSS) > VUVREG , VDD = top Vn
voltage, IREG = 0 mA, TA = –40°C to 110°C
(Vn – Vn-1) = 3.8 V and (V1 – VSS) < VUVREG , VDD = top Vn
voltage, TA = 0°C to 60°C
1
(Vn – Vn-1) = 3.8 V and (V1 – VSS) < VUVREG , VDD = top Vn
voltage, TA = –40°C to 110°C
Input Current at Vx
Pins
IIN
(Vn – Vn-1) = (V1 – VSS) = 3.8 V, VDD = top Vn voltage, TA =
25°C
–0.1
Output Drive OUT, CMOS Active High
(Vn – Vn-1) or (V1 – VSS) > VOV, IOH = 100 µA, VDD = top Vn
voltage
Output Drive
Voltage, Active High
VOUT
6
If three of four cells are short circuited, only one cell remains
powered and > VOV, VDD = Vn (the remaining cell voltage), IOH
= 100 µA
VDD –
0.3
(Vn – Vn-1) and (V1 – VSS) < VOV, VDD = sum of the cell stack
voltage, IOL = 100 µA measured into OUT pin
IOUTH
(Vn – Vn-1), (V3 – V2), or (V1 – VSS) > VOV, VDD = top Vn
OUT Source Current voltage,
(during OV)
forced OUT = 0 V, measured out of OUT pin
IOUTL
OUT Sink Current
(no OV)
V
250
V
400
mV
4.5
mA
14
mA
(Vn – Vn-1) and (V1 – VSS) < VOV, VDD = top Vn voltage, forced
OUT = VDD, measured into OUT pin. Pull-up resistor RPU = 5
kΩ to VDD
0.5
Internal Fixed Delay, 3 second delay option
2.4
3
3.6
s
Internal Fixed Delay, 4 second delay option
3.2
4
4.8
s
Internal Fixed Delay, 5.5 second delay option
4.4
5.5
6.6
s
Internal Fixed Delay, 6.5 second delay option
5.2
6.5
7.8
s
Internal Fixed Delay Timer
OV Delay Time (1)
tDELAY
tDELAY_CTM
(1)
6
Fault Detection
Delay Time in Test
Mode OV Delay
Time
Internal Fixed delay
15
ms
Specified by design. Not 100% tested in production.
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Electrical Characteristics (continued)
Typical values stated where TA = 25°C and VDD = 14.4 V, MIN/MAX values stated where TA = –40°C to 110°C, and VDD =
3 V to 15 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.2
3.3
3.4
V
3.05
3.15
3.25
V
Regulated Supply Output, REG
VREG = 3.3 V , bq2960, bq2961,
bq2962
VREG
REG Supply
VREG = 3.15 V , bq2962
VDD ≥ 4 V, I REG = 0 µA
to 1 mA, CREG = 0.47 µF VREG = 3.0 V , bq2962
2.9
3
3.1
V
VREG = 2.5 V , bq2960, bq2961
2.425
2.5
2.575
V
VREG = 1.8 V , bq2960, bq2961
1.746
1.8
1.854
IREG
REG Current Output VDD ≥ 4 V, CREG = 0.47 µF
0
IREG_
REG Output Short
Circuit Current Limit
REG = VSS, CREG = 0.47 µF
4
REG pull-down
resistor
REG is disabled
SC_Limit
RREG_
PD
20
1
V
mA
mA
30
45
kΩ
Regulated Supply Output Enable, REG_EN
VIH
High-level Input
VIL
Low-level Input
ILKG
Input Leakage
Current
1.6
V
VIH < 6 V
0.4
V
0.1
µA
50
mV
Regulated Supply Undervoltage Self-disable
VUVREG
Undervoltage
detection
VUVHYS
Undervoltage
Detection Hysteresis
250
300
400
mV
tUVDELAY
Undervoltage
Detection Delay
4.5
6
7.5
s
VUVQUAL
Cell voltage to
qualify for UV
detection
Factory Configuration: 2.0 V to 2.8 V in 50 mV steps, TA = 25 °C
–50
0.5
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15
350
10
340
Overvoltage Hysteresis (mV)
Overvoltage Accuracy (mV)
7.6 Typical Characteristics
5
0
-5
-10
-15
Mean
Min
Max
-20
-25
-60
-40
-20
0
20
40
60
Temperature (qC)
80
100
330
320
310
300
290
280
-60
120
Supply Current (PA)
-5
80
100
120
D002
-10
-15
Mean
Min
Max
-40
-20
0
20
40
60
Temperature (qC)
80
100
4
3.5
3
Mean
Min
Max
2.5
2
-60
120
-40
-20
D003
Figure 3. Undervoltage Accuracy
0
20
40
60
Temperature (qC)
80
100
120
D004
Figure 4. IDD with Regulator On
3.31
1.2
Regulator Output (V)
3.305
Supply Current (PA)
20
40
60
Temperature (qC)
4.5
1.4
1
0.8
0.6
0.4
-40
-20
0
20
40
60
Temperature (qC)
80
100
Mean
Min
Max
3.3
3.295
3.29
Mean
Min
Max
0.2
120
3.285
-60
-40
D005
Figure 5. IDD with Regulator Off
8
0
5
0
0
-60
-20
Figure 2. Hysteresis VHYS vs Temperature
5
Undervoltage Accuracy (mV)
-40
D001
Figure 1. Overvoltage Threshold (VOV) vs Temperature
-20
-60
Mean
Min
Max
-20
0
20
40
60
Temperature (qC)
80
100
120
D006
Figure 6. Regulator Output Without Load
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Typical Characteristics (continued)
8
Mean
Min
Max
-3.4
7
6
-3.45
Output Voltage (V)
High-Level Output Current (mA)
-3.35
-3.5
-3.55
-3.6
4
3
2
-3.65
-3.7
-60
5
1
0
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
0
5
D008
Figure 7. IOUTH vs Temperature
10
15
20
Supply Voltage (V)
25
30
Figure 8. VOUT vs VDD
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8 Detailed Description
8.1 Overview
The bq2960, bq2961 and bq2962 are second-level overvoltage (OV) protectors with a regulated output. Each cell
is monitored independently by comparing the actual cell voltage to an overvoltage threshold VOV. The
overvoltage threshold is preprogrammed at the factory with a range between 3.85 V to 4.65 V.
The regulated output is enabled unless any of the cell voltages fall below the VUVREG threshold. This threshold is
preprogrammed at the factory with a range between 2 V to 2.8 V. For bq2960xy family, an external control pin,
REG_EN, is available to enable or disable the regulated output in addition to the VUVREG detection.
Table 1. Programmable Parameters
OVERVOLTAGE RANGE (V)
3.85 to 4.6 in 50 mV step
OVERVOLTAGE DELAY (s)
UNDERVOLTAGE RANGE (V)
3, 4, 5.5, 6.5
2.0 to 2.8 in 50 mV step
REGULATOR (V)
1.8, 2.5, 3.3 (bq2960, bq2961)
3.0, 3.15, 3.3 (bq2962)
8.2 Functional Block Diagram
PACK+
R VD
C VD
VDD
1
Vref
R IN
V3
2
C IN
R IN
V2
3
C IN
Multiplexer S witch Net work
+
Amp
V1
R IN
4
-
Comp
+
5 REG_EN
UVP_Vref
-
7 REG
Programmable
setting
V OV
Enable
Delay Charging/
Discharge circuit
Active
OUT
8
Delay
Timer
C IN
VSS
6
9
PWPD
PACK±
Figure 9. bq2960 Block Diagram
10
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Functional Block Diagram (continued)
PACK+
R VD
C VD
VDD
1
Vref
V4
R IN
2
R IN
V3
3
C IN
R IN
V2
4
C IN
Comp
+
Multiplexer S witch Net work
C IN
UVP_Vref
-
7
REG_EN
REG
Programmable
setting
Enable
V OV
V1
R IN
+
Amp
-
Delay Charging/
Discharge circuit
5
C IN
Active
OUT
8
Delay
Timer
REG_EN
VSS
6
9
PWPD
PACK±
Figure 10. bq2961 and bq2962 Block Diagram
8.3 Feature Description
8.3.1 Pin Details
8.3.1.1 Input Sense Voltage, Vx
These inputs sense each battery cell voltage. A series resistor and a capacitor across the cell for each input is
required for noise filtering and stable voltage monitoring.
8.3.1.2 Output Drive, OUT
This terminal serves as the fault signal output in Active High.
8.3.1.3 Supply Input, VDD
This terminal is the unregulated input power source for the device. A series resistor is connected to limit the
current, and a capacitor is connected to ground for noise filtering.
8.3.1.4 Regulated Supply Output, REG
This terminal is connected to an external capacitor and provides a regulated supply to power a circuit such as a
Real Time Clock integrated circuit, or functions requiring a well-regulated supply. Maximum current load on this
pin cannot exceed 1 mA.
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Feature Description (continued)
The REG output has protection for overcurrent, using a current limit protection circuit, and also detects and
protects for excessive power dissipation due to short circuit of the external load. This pin requires a ceramic 1-µF
capacitor connection to VSS for improved stability, noise immunity, and ESD performance of the supply output.
This capacitor must be placed close to the REG and VSS pins for connection.
8.3.1.5 Regulated Supply Output Enable, REG_EN (bq2960 Only)
This terminal is a high voltage input drain to enable and disable the regulated supply output, REG terminal.
When the VREG_EN > VIH, the REG terminal output is enabled including the cell undervoltage detection function
to self-disable the regulated supply. When the VREG_EN < VIL, the REG terminal output, the cell undervoltage
detection and the regulated supply self-disable functions are disabled.
To keep the REG output enabled at all times, the recommendation is to connect the REG_EN to the V1
termination. There is a 6-V clamp to protect the REG_EN terminal from a high voltage input. By connecting
REG_EN to V1, the clamp circuit is not active.
When the REG output is enabled, VREG_EN > VIH, the REG output can be self-disabled if any of the cell
voltages are < VUVREG. The self-disable function is used to reduce power consumption when the battery pack is
deeply depleted.
8.3.2 Overvoltage Sensing for OUT
Cell Voltage (V)
(V4-V3, V3-V2, V2-V1, V1-VSS)
In the bq296xxx device, each cell is monitored independently. Overvoltage is detected by comparing the actual
cell voltage to a protection voltage reference, VOV. If any cell voltage exceeds the programmed OV value, an
internal timer circuit is activated. This timer circuit causes a factory pre-programmed fixed delay before the OUT
terminal goes from inactive to active state.
VOV
VOV - VHYS
tDELAY
OUT (V)
Figure 11. Timing for Overvoltage Sensing for OUT
8.3.3 Regulated Output Voltage and REG_EN Pin
For bq2960 and bq2961, there are three factory-preprogrammed options for the regulated output voltage, 3.3 V,
2.5 V, and 1.8 V. For bq2962, the regulated output voltage options are 3.3 V, 3.15 V, and 3.0 V. bq2962xy can
potentially provide other regulated voltage output between 3.3 V to 3.0 V, contact Texas Instruments for detail.
At power up, the regulated output is on by default. If any cell voltage is below VUVREG at device power up, the
regulated output will remain on until the tUV_DELAY time has passed, the regulated out turns off after the delay
time.
During discharge, if any cell voltage falls below the VUVREG threshold for tUV_DELAY time, the regulated output is
self-disabled. The regulated output turns on again when all the cell voltages are above VUVREG + VUVHYS.
12
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Cell Voltage (V)
(V3-V2, V2-V1, V1-VSS)
Feature Description (continued)
VUVREG + VUVHYS
VUVREG
tUVDELAY
REG (V)
Figure 12. REG Output Timing
For bq2960 family, an external REG_EN pin is available to enable and disable the regulated output function. To
enable both the regulated output and the undervoltage self-disable features, the REG_EN pin must be above VIH.
A microcontroller can be used to control the REG_EN pin. Alternatively, connecting the REG_EN pin to the
bottom cell is another option to enable the regulated output function always.
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Feature Description (continued)
Pack +
Protector FETs
100 Q
VCELL3
VCELL2
1 kQ
0.1 µF
1 kQ
0.1 µF
1 kQ
VCELL1
VDD
OUT
V3
REG
bq2960xy
V2
5
(*)
X2
MFP
GND
VSS
VCC
Supply
Enable
SCL
RTC IC
0.1 µF
0.1 µF
VCC
VBAT SDA
REG_EN
PWPD
V1
X1
* can be removed if Vss will be connected
first during cell connection
0.47 µF
Pack ±
REG out is always enabled
Pack +
Protector FETs
100 Q
1 kQ
VCELL3
1 kQ
VCELL2
0.1 µF
V2
REG
bq2960xy
5
(*)
MFP
Enable
RTC IC
0.1 µF
0.1 µF
X2
VCC
supply
GND SCL
VSS
REG_EN
PWPD
V1
VCC
VBAT SDA
0.1 µF
1 kQ
VCELL1
OUT
VDD
V3
X1
* can be removed if Vss will be connected
first during cell connection
0.47 µF
Pack ±
REG output is enabled or disabled by MCU
MCU
CTL
Figure 13. bq2960xy Application Schematic
8.4 Device Functional Modes
8.4.1 NORMAL Mode
When all of the cell voltages are below the VOV threshold AND above VUVREG threshold, the device operates in
NORMAL mode. The device monitors the differential cell voltages connected across (V1–VSS), (V2–V1),
(V3–V2), and (V4–V3). The OUT pin is inactive in this mode. The regulated output is always enabled for bq2961.
For bq2960, the regulated output is on only if the voltage on the REG_EN pin is above VIH.
8.4.2 OVERVOLTAGE Mode
OVERVOLTAGE mode is detected if any of the cell voltages exceed the overvoltage threshold, VOV, for
configured OV delay time. The OUT pin is activated after a delay time preprogrammed at the factory. The OUT
pin will pull high internally. Then an external FET is turned on, shorting the fuse to ground, which allows the
battery and/or charger power to blow the fuse. When all of the cell voltages fall below (VOV – VHYS), the device
returns to NORMAL mode. The regulated output (if enabled) remains on in this mode.
14
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Device Functional Modes (continued)
8.4.3 UNDERVOLTAGE Mode
The UNDERVOLTAGE mode is detected if any of the cell voltage across (V1–VSS), (V2–V1), (V3–V2), or
(V4–V3) is below the VUVREG threshold for tUV_DELAY time. In this mode, the regulated output is disabled. To return
to the NORMAL mode, all the cell voltages must be above (VUVREG + VUVHYS).
For a low cell configuration, Vn pin can be shorted to the (Vn
voltage below VUVQUAL threshold for undervoltage detection.
– 1)
pin. The device ignores any differential cell
8.4.4 CUSTOMER TEST MODE
The Customer Test Mode (CTM) helps to reduce test time for checking the overvoltage delay-timer parameter
once the circuit is implemented into the battery pack. To enter CTM, the VDD pin should be set at least 10 V
higher than V3 (see Figure 14). The delay timer is greater than 10 ms, but considerably shorter than the timer
delay in normal operation. To exit CTM, remove the VDD to VC3 voltage differential of 10 V, so that the
decrease in the value automatically causes an exit.
CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the
device into CTM. Also avoid exceeding Absolute Maximum Voltages for the individual
cell voltages (V3–V2), (V2–V1) and (V1–VSS). Stressing the pins beyond the rated
limits can cause permanent damage to the device.
Figure 14 shows the timing for the Customer Test Mode.
VDD ± V3 = 10V
VDD
V3
> 10ms
OUT (V)
Figure 14. Timing for Customer Test Mode
Figure 15 shows the measurement for current consumption of the product for both VDD and Vx.
ICC
IIN
3.6 V
IIN
3.6 V
3.6 V
IIN
1 VDD
OUT 8
2 V3
REG 7
3 V2
VSS 6
4 V1
REG_EN 5
0.1 µF
VDC
Figure 15. Configuration for Integrated Circuit Current Consumption Test
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The bq296xxx is a family of second-level protectors used for overvoltage protection of the battery pack in the
application. A regulated output is available to drive a small circuit with maximum IREG loading. The device OUT
pin is active high, which drives a NMOS FET that connects the fuse to ground in the event of a fault condition.
This provides a shorted path to use the battery and/or charger power to blow the fuse and cut the power path.
9.2 Typical Application
Figure 13 shows the recommended reference design components.
Pack +
Protector
FETs
Protector
FETs
100 Q
Pack +
100 Q
VDD
1 kQ
VCELL3
VCELL2
VCELL1
1 kQ
1 kQ
OUT
0.1 µF
0.1 µF
V3
V2
V1
5
(*)
External
Circuit
e.g., RTC
REG
bq2960xy
VSS
* can be removed if Vss will be
connected first during cell
connection
REG_EN
PWPD
0.1 µF
0.1 µF
1 kQ
VCELL4
1 kQ 0.1 µF
VCELL3
1 kQ 0.1 µF
VCELL2
0.47 µF
Pack ±
VCELL1
1 kQ
0.1 µF
VDD
OUT
V4
REG
V3
bq2961xy
5
External
Circuit
e.g., RTC
(*)
VSS
* can be removed if Vss will be
connected first during cell
connection
V1
V2
PWPD
0.1 µF 0.47 µF
0.1 µF
Pack ±
MCU
bq2960xy REG out is controlled by MCU
CTL
10 M
(Optional)
Figure 16. Application Schematic
9.2.1 Design Requirements
NOTE
Changes to the ranges stated in Table 2 will impact the accuracy of the cell
measurements.
Table 2. Parameters
PARAMETER
EXTERNAL COMPONENT
MIN
NOM
MAX
Voltage monitor filter resistance
RIN
900
1000
4700
UNIT
Ω
Voltage monitor filter capacitance
CIN
0.01
0.1
1.0
µF
Supply voltage filter resistance
RVD
0.1
—
1
KΩ
Supply voltage filter capacitance
CVD
—
0.1
1.0
µF
REG output capacitance
CREG
0.47
1
—
µF
NOTE
The device is calibrated using an RIN value = 1 kΩ. Using a value other than the
recommended value changes the accuracy of the cell voltage measurements and VOV
trigger level.
16
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9.2.2 Detailed Design Procedure
NOTE
The device VSS must be connected first during PCB test or cell attachment. Failure to do
so can damage the REG pin.
1. If VSS pin cannot be connected first, it is required to add a resistor of a minimum of 5 ohms to a maximum of
10 ohms (a 5-ohm resistor is used in the reference schematic, Figure 17) in series with the REG capacitor.
When VSS is floating, the REG capacitor always charges up to the VDD voltage. When VSS is finally
connected, the REG capacitor will be discharged. Adding a small resistor in series reduces the current
strength and avoids any potential damage to the REG pin. The 5-ohm resistor can be placed in series with
the REG connect circuit (as shown in Figure 17) or in series of the REG capacitor (as shown in Figure 18).
Placing the resistor in series with the REG circuit results in a small drop of VREG (for example: max loading
of 1 mA with a 5-ohm resistor will drop 5 mV on VREG), but such a connection can protect again rush
current discharge from both REG capacitor or external filter capacitor connected to the REG pin. Placing the
resistor in series with the REG capacitor is an alternative to avoid additional drop in VREG if the filer
capacitor used by the external circuit is much smaller than the REG capacitor.
2. After VSS is connected, the device allows random cell connect to the Vx pin.
3. Cell should be connected to the lower Vn pin; the unused Vn pin should be shorted to the (Vn-1) pin. See
Figure 17 for details.
Protector
FETs
Pack +
100 Q
1 kQ
VCELL3
0.1 µF
1 kQ
VCELL2
0.1 µF
VCELL1
1 kQ
0.1 µF
VDD
OUT
V4
V3
REG
bq2961xy
V2
External
Circuit
e.g., RTC
5Q
VSS
V1
PWPD
0.1 µF
0.47 µF
Pack t
Figure 17. 3-Series bq2961 Schematic (also apply to bq2962)
4. A zener diode can be added to the REG pin to VSS as shown in Figure 18. This is recommended to protect
the circuit connected to the REG pin if floating VSS in the field is a risk concern. When VSS is floating
(during cell connection when VSS is not connected first or in system fault with BAT– wire broken), the REG
voltage always pulls up to VDD. In a 4-S configuration, the REG voltage can reach approximately 16 V with
VSS floating. Adding a zener diode clamps the REG voltage to a safe level for the external circuits
connected to the REG pin. Having the zener diode can also protect the external circuits if REG pin is shorted
to OUT pin or any other high-voltage output terminal. If a zener diode is used, TI recommends putting the
diode on the battery side with the bq296xxx device to allow protection on both the REG pin as well as the
circuit connected to REG under floating VSS condition. The resistor in series with the REG pin is not required
in this case.
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REG
The 5-Ÿ UHVLVWRU OLPLWV WKH UXVK FXUUHQW
discharge from the capacitor during cell
connection when Vss is not connected
first.
Loss of Vss connection or REG shorted to
high voltage can bring the REG above the
regulated range. This optional zener
clamp can protect the downstream circuit
under such an event.
5Ÿ
0.47 µF
This resistor is not required if Vss is
connected first in the cell connection
sequence.
Figure 18. 5-V Zener Diode
5. For 2- to 3-series applications, if an external control for the regulated output is required, select the bq2960xy
family. Otherwise, select the bq2961xy family.
9.2.3 Application Curves
18
Figure 19. Overvoltage Protection
Figure 20. Overvoltage Protection Release
Figure 21. Undervoltage Detection to Turn off Regulator
Figure 22. Undervoltage Release to Switch on Regulator
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9.2.4 Other Schematics
Protector
FETs
Pack +
100 Q
VCELL3
1 kQ
0.1 µF
1 kQ
VCELL2
0.1 µF
1 kQ
VCELL1
VDD
OUT
V3
REG
bq2960xy
V2
VSS
V1
REG_EN
5
0.1 µF
PWPD
External
Circuit
e.g., RTC
(*)
0.47 µF
* can be removed if Vss will be
connected first during cell connection
0.1 µF
Pack ±
Protector
FETs
Pack +
100 Q
1 kQ
VCELL3
1 kQ
VCELL2
0.1 µF
OUT
REG
bq2960xy
V2
VSS
V1
REG_EN
PWPD
5
External
Circuit
e.g., RTC
(*)
0.1 µF
1 kQ
VCELL1
VDD
V3
* can be removed if Vss will be
connected first during cell connection
0.1 µF
0.1 µF
0.47 µF
Pack ±
MCU
REG output can be enabled or disabled by MCU
CTL
10 M
(Optional)
Figure 23. bq2960 Schematic with REG Output Always Enabled
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Protector
FETs
Pack +
100 Q
1 kQ
VCELL4
1 kQ 0.1 µF
VCELL3
1 kQ 0.1 µF
VCELL2
1 kQ
0.1 µF
VDD
OUT
V4
REG
V3
bq2961xy
5
VSS
* can be removed if Vss will be
connected first during cell
connection
V1
V2
PWPD
0.1 µF
0.1 µF
VCELL1
External
Circuit
e.g., RTC
(*)
0.47 µF
Pack ±
Figure 24. bq2961 Schematic (also apply to bq2962)
10 Power Supply Recommendations
The maximum power is 15 V for bq2960 and 20 V for bq2961 and bq2962 on VDD.
NOTE
Connect VSS first during power up.
11 Layout
11.1 Layout Guidelines
Use the following layout guidelines.
1. Ensure the RC filters for the Vx pins and VDD pin are placed as close as possible to the target terminal,
reducing the tracing loop area.
2. The capacitor for REG should be placed close to the device terminals.
3. Ensure the trace connecting the fuse to the gate, source of the NFET to the Pack– is sufficient to withstand
the current during a fuse blown event.
11.2 Layout Example
Place the RC filters close
to device terminals
VCELL3
VCELL2
Power Trace Line
VDD
OUT
V4
REG
V3
V2
Pack +
5
PWPD
(*)
VSS
External
Circuit
e.g., RTC
Pack ±
V1
VCELL1
* can be removed if Vss
will be connected first
during cell connection
Ensure trace can support sufficient
current flow for fuse blow
Figure 25. Layout Example
20
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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27-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ296103DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 110
6103
BQ296103DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 110
6103
BQ296106DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 110
6106
BQ296106DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 110
6106
BQ296107DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 110
6107
BQ296107DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 110
6107
BQ296111DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 110
6111
BQ296111DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 110
6111
BQ296112DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 110
6112
BQ296112DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 110
6112
BQ296113DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 110
6113
BQ296113DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 110
6113
BQ296114DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 110
6114
BQ296114DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 110
6114
BQ296202DSGR
PREVIEW
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
6202
BQ296202DSGT
PREVIEW
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
6202
BQ296203DSGR
PREVIEW
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
6203
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
27-Oct-2016
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ296203DSGT
PREVIEW
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
6203
BQ296212DSGR
PREVIEW
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
6212
BQ296212DSGT
PREVIEW
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
6212
BQ296213DSGR
PREVIEW
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
6213
BQ296213DSGT
PREVIEW
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
6213
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Oct-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
BQ296103DSGR
WSON
DSG
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296103DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296106DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296106DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296107DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296107DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296111DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296111DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296112DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296112DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296113DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296113DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296114DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296114DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296202DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296202DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296203DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296203DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2016
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ296212DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296212DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296213DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ296213DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ296103DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ296103DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ296106DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ296106DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ296107DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ296107DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ296111DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ296111DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ296112DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ296112DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ296113DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ296113DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ296114DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2016
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ296114DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ296202DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ296202DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ296203DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ296203DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ296212DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ296212DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ296213DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ296213DSGT
WSON
DSG
8
250
210.0
185.0
35.0
Pack Materials-Page 3
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