LINER LTM4642 20vin, dual 4a or single 8a dc/dc î¼module regulator Datasheet

LTM4642
20VIN, Dual 4A or Single 8A
DC/DC µModule Regulator
Features
Description
Small Form Factor Dual 4A Power Supply
nn Wide Input Voltage Range: 4.5V to 20V
(2.375V Min with CPWR Bias)
nn Dual 180° Out-of-Phase Outputs with 4A DC
nn Dual Outputs with 0.6V to 5.5V Range
nn Output Voltage Tracking
nn ±1.5% Maximum Total DC Output Voltage Error
nn Up to 95% Maximum Efficiency
nn Phase-Lockable Fixed Frequency 600kHz to 1.4MHz
nn Constant On-Time, Valley Current Mode Architecture
nn Selectable Burst Mode® Operation
nn Output Overvoltage and Overcurrent Protection
nn 9mm × 11.25mm × 4.92mm BGA Package
The LTM®4642 is a complete dual 4A or single 8A step-down
DC/DC μModule® (micromodule) regulator. Included in the
package are the switching controller, power FETs, inductor,
and all support components. Operating over input voltage
ranges of 4.5V to 20V, (2.375V min with external CPWR
bias), the LTM4642 supports two outputs with voltage
ranges of 0.6V to 5.5V, set by a single external resistor.
Its high efficiency design delivers 4A continuous current
(5A peak) for each output.
nn
High switching frequency and a valley current mode
architecture enable a very fast transient response to line
and load changes without sacrificing stability. The two
outputs are interleaved with 180° phase to minimize the
ripple noise and reduce the I/O capacitors.
Applications
The power module is offered in a 9mm × 11.25mm ×
4.92mm BGA package. The LTM4642 is RoHS compliant
with Pb-free finish.
Telecom and Networking Equipment
Servers
nn FPGA Power
nn
nn
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, µModule and LTpowerCAD
are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their
respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066,
6476589, 6774611, 8163643.
Typical Application
Dual 4A 1V and 1.2V DC/DC µModule Regulator
2.2Ω
22µF
2×
1.2V (650kHz)
VRNG1
RUN1
RUN2
0.1µF
90
DRVCC INTVCC
VIN1 VIN2 CPWR
0.1µF
Efficiency vs Load Current at 12V input
INTVCC
4.7µF
133k
10k
PGOOD1
TRACK/SS1
PGOOD2
VOUT1
TRACK/SS2
LTM4642
VOUT2
VOUT1 1V AT 4A LOAD
VOUT2 1.2V AT 4A LOAD
47µF
+
FREQ
INTVCC
85
10k
EFFICIENCY (%)
VIN
4.75V TO 20V
MODE/PLLIN
+
100µF
VFB2
GND
80
75
100µF
70
VOUTS1
VOUTS–
61.9k
SGND
47µF
470pF
470pF
90.9k
PINS NOT USED: COMP1, COMP2, PHASEMD, CLKOUT, EXTVCC, SW1, SW2
0
0.5
1
2.7 3
1.5 2
LOAD CURRENT (A)
3.5
4
4642 TA01b
VOUT2
VOUT1
VFB1
1V (650kHz)
60.4k
4642 TA01a
4642fb
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1
LTM4642
Absolute Maximum Ratings
Pin Configuration
(Note 1)
2
1
VIN1, VIN2, SW1, SW2, CPWR..................... –0.3V to 22V
INTVCC, DRVCC, PGOOD1,2, RUN1,2, EXTVCC,
VFB1, VFB2 (Note 4) .....................–0.3V to INTVCC + 0.3V
COMP1, COMP2 (Note 4)........................... –0.3V to 2.7V
MODE/PLLIN, FREQ, PHASMD,
VRNG1..........................................–0.3V to INTVCC + 0.3V
VOUT1, VOUT2, VOUTS1.................................... –0.3V to 6V
VOUTS –........................................................0.3V to 2.75V
TK/SS1, TK/SS2.............................................. 0.3V to 5V
Internal Operating Temperature Range
(Note 2)................................................... –40°C to 125°C
Maximum Reflow Body Temperature..................... 245°C
Storage Temperature Range................... –55°C to 125°C
3
4
5
6
7
SW2
A
VOUT2
RUN2
B
VFB2 TRACK/SS2 CPWR
MODE/PLLIN
C
PGOOD2
EXTVCC
COMP2 CLKOUT
GND
D
E
VOUTS1
GND SGND COMP1 FREQ GND DRVCC
VOUTS– VFB1
F
VOUT1
GND
PHASMD
VIN2
INTVCC
PGOOD1 GND
RUN1 VRNG1
TRACK/SS1
VIN1
G
SW1
GND
H
BGA Package
56-Lead (9mm × 11.25mm × 4.92mm)
TJMAX = 125°C, θJA = 15°C/W, θJP = 4°C/W
θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS
WEIGHT = 1.2635g
Order Information
http://www.linear.com/product/LTM4642#orderinfo
PART MARKING*
PART NUMBER
PAD OR BALL FINISH
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(SEE NOTE 2)
LTM4642EY#PBF
SAC305 (RoHS)
LTM4642Y
e1
BGA
3
–40°C to 125°C
LTM4642IY#PBF
SAC305 (RoHS)
LTM4642Y
e1
BGA
3
–40°C to 125°C
SnPb (63/37)
LTM4642Y
e0
BGA
3
–40°C to 125°C
LTM4642IY
• Consult Marketing for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures: www.linear.com/umodule/pcbassembly
• Terminal Finish Part Marking: www.linear.com/leadfree
• LGA and BGA Package and Tray Drawings: www.linear.com/packaging
Electrical Characteristics
The l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 27.
Specified as each channel. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIN(DC)
Input DC Voltage
VIN ≤ 4.5V, Connect CPWR to a Bias > 4.5V
l
2.375
MIN
TYP
20
V
VOUT1,2(RANGE)
Output Voltage Range
VIN = 6V to 20V
l
0.6
5.5
V
VOUT1,2(DC)
Output Voltage, Total Variation
with Line and Load
CIN = 10µF ×2, COUT = 47µF Ceramic, 100µF POSCAP,
RSET = 40.2kΩ
VIN = 12V, VOUT = 1.5V, IOUT = 4A
l
1.4775
1.5225
V
1.5
MAX
UNITS
Input Specifications
IINRUSH(VIN)
2
Input Inrush Current at Start-Up
IOUT = 0A, CIN = 10µF, COUT = 47µF Ceramic and 100µF
POSCAP, VOUT = 1.5V
VIN = 12V
0.25
A
4642fb
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LTM4642
Electrical Characteristics
The l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 27.
Specified as each channel. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
ICPWR
CPWR Bias Current
CPWR = 12V, MODE = Continuous
IQ(VIN)
Input Supply Bias Current
VIN = 12V, VOUT1 = 1.5V, Switching Continuous
VIN = 12V, VOUT2 = 1.5V, Switching Continuous
VIN = 20V, VOUT1 = 1.5V, Switching Continuous
VIN = 20V, VOUT2 = 1.5V, Switching Continuous
Shutdown, RUN = 0, VIN = 12V
IQ(VIN)
Input Supply Bias Current
VIN = 12V, VOUT = 1.5V, IOUT = 4A
VIN = 20V, VOUT = 1.5V, IOUT = 4A
DRVCC
Internal VCC Voltage
6V < VIN < 20V, No Load
IDRVCC(REG)
DRVCC Load Regulation
IDRVCC = 0 to 100mA
EXTVCC(HYS)
EXTVCC Switchover Hysteresis
EXTVCC
EXTVCC Switchover Voltage
MIN
TYP
MAX
20
25
25
22
22
10
A
A
5.3
5.6
V
–1.5
–3
%
200
EXTVCC Ramping Positive
4.4
mA
mA
mA
mA
mA
µA
0.6
0.356
5
UNITS
4.6
mV
4.8
V
4
A
Output Specifications
IOUT1,2(DC)
Output Continuous Current Range
VIN = 12V, VOUT = 1.5V (Note 5)
ΔVOUT1(LINE)
VOUT(NOM)
Line Regulation Accuracy
VOUT = 1.5V, VIN from 4.5V to 20V,
IOUT = 0A For Each Output
ΔVOUT2(LOAD)
VOUT2(NOM)
Load Regulation Accuracy
For Each Output, VOUT = 1.5V, 0A to 4A (Note 5)
VIN = 12V
VOUT1,2(AC)
Output Ripple Voltage
IOUT = 0A, COUT = 100µF X5R Ceramic
VIN = 12V, VOUT = 1.5V
VIN = 20V, VOUT = 1.5V
fS
Output Ripple Voltage Frequency
IOUT = 2A, VIN = 12V, VOUT = 1.5V,
FREQ = 49.9k to Ground
ΔVOUT(START)
Turn-On Overshoot
tSTART
Turn-On Time
0
l
0.1
0.2
%
l
±0.3
±0.5
%
15
15
mV
mV
800
kHz
COUT = 100µF and 47µF X5R Ceramic, VOUT = 1.5V,
IOUT = 0A
VIN = 12V
VIN = 20V
10
10
mV
mV
COUT = 100µF X5R and 47µF Ceramic, VOUT = 1.5V,
IOUT = 0A Resistive Load, TRACK/SS = 10nF
VIN = 12V
6
ms
ΔVOUT(LS)
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load
COUT = 100µF and 47µF X5R Ceramic, VOUT = 1.5V,
VIN = 12V
50
mV
tSETTLE
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load
COUT = 100µF and 47µF X5R Ceramic, VOUT = 1.5V,
VIN = 12V
15
µs
Output Current Limit
COUT = 100µF and 47µF X5R Ceramic,
VIN = 6V, VOUT = 1.5V
VIN = 20V, VOUT = 1.5V
7
7
A
A
VOUTS1(REG)
Regulated Differential Feedback
VOUTS1-VOUTS–
Sensed at Load Point with Resistive Divider
IVOUTS1
VOUTS1 Input Bias Current
IVOUTS–
VOUTS– Input Bias Current
IVFB2
VFB2
IOUT(PK)
Control Section
0.6
0.608
V
(Note 4)
±5
±25
nA
(Note 4)
–25
–50
nA
VFB2 Input Bias Current
(Note 4)
–5
±50
nA
Voltage at VFB2 Pin
IOUT = 0A, VOUT = 2.5V
0.6
0.608
V
l
l
0.592
0.592
4642fb
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3
LTM4642
electrical characteristics
The l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 27.
Specified as each channel. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
ITRACK/SS1,2
Soft-Start Charge Current
0V < TRACK/SS1,2 < 0.6V
1.0
µA
DFMAX
Maximum Duty Factor
In Dropout (Note 4)
97
%
tON(MIN)
Minimum On-Time
(Note 4)
30
ns
tOFF(MIN)
Minimum Off-Time
(Note 4)
fLOW
Low Frequency
RFREQ = 61.9k
600
650
700
kHz
fNOM
Nominal Frequency
RFREQ = 49.9k
730
800
850
kHz
fHIGH
Highest Frequency
RFREQ = 27.5k
1250
1400
1500
kHz
RMODE/PLLIN
MODE/PLLIN Input Resistance
VPLLIN(HIGH)
MODE/PLLIN Clock In High
VPLLIN(LOW)
MODE/PLLIN Clock In Low
VRUN1, 2
RUN Pin ON/OFF Threshold
RUN Rising
VRUN1, 2(HYS)
RUN1, 2, Threshold Hysteresis
Delta RUN Rising to RUN Falling
IRUN1,2
RUN Pin Pull-Up Current When Off RUN1,2 at SGND
90
ns
600
kΩ
2
l
1.1
IRUN1,2(HYST) = IRUN1,2(ON) – IRUN1,2(OFF) (Note 4)
UNITS
V
1.2
0.5
V
1.3
V
200
mV
1.2
µA
IRUN1,2(HYS)
RUN1,2 Pull-Up Hysteresis
RUN1,2 Res
RUN1,2 Resistance to Ground
UVLO
Undervoltage Lockout
RFB1, RFB2
Resistor Between VOUT and VFB
Pins for Each Channel
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
ΔVPGOOD
PGOOD Range
VFB Ramping Negative
VFB Ramping Positive
Ch 2 Phase
Channel 2 Phase (Relative to
Channel 1)
PHASMD = SGND
PHASMD = Floating
PHASMD = INTVCC
180
180
240
Deg
Deg
Deg
CLKOUT Phase
CLKOUT Phase (Relative to
Channel 1)
PHASMD = SGND
PHASMD = Floating
PHASMD = INTVCC
60
90
120
Deg
Deg
Deg
INTVCC Falling (Note 4)
INTVCC Rising
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4642E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the full –40°C to 125°C internal operating temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTM4642I is guaranteed to meet specifications over the full
internal operating temperature range. Note that the maximum ambient
4
l
l
5
µA
100
kΩ
3.3
3.7
4.2
4.5
V
V
60.1
60.4
60.7
kΩ
0.1
0.3
V
±2
µA
–10
10
%
%
–5
5
–7.5
7.5
temperature consistent with these specifications is determined by specific
operating conditions in conjunction with board layout, the rated package
thermal resistance and other environmental factors.
Note 3: The two outputs are tested separately and the same testing
condition is applied to each output.
Note 4: 100% tested at wafer level only.
Note 5: See Output Current Derating curves for different VIN, VOUT and TA.
Note 6: Consult factory for operation down at 2.375V to 2.5V input.
Operating frequency nominal will be reduced.
4642fb
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LTM4642
Typical Performance Characteristics
(Refer to Figures 19 and 20) TA = 25°C, unless otherwise noted.
Efficiency vs Load Current at
3.3VIN, CCM Mode, External 5V
Bias
100
100
98
Efficiency vs Load Current at
5VIN, CCM Mode
100
95
95
90
90
Efficiency vs Load Current at
12VIN, CCM Mode
94
92
90
3.3V TO 2.5V (600kHz)
3.3V TO 1.8V (600kHz)
3.3V TO 1.5V (600kHz)
3.3V TO 1.2V (600kHz)
3.3V TO 1V (600kHz)
88
86
84
0
0.5
1
1.5 2 2.5 3
LOAD CURRENT (A)
85
5V TO 3.3V (800kHz)
5V TO 2.5V (800kHz)
5V TO 1.8V (750kHz)
5V TO 1.5V (650kHz)
5V TO 1.2V (650kHz)
5V TO 1V (650kHz)
80
75
3.5
4
70
0
0.5
1
1.5 2 2.5 3
LOAD CURRENT (A)
4642 G01
IN
EFFICIENCY (%)
90
85
80
75
70
60
0
0.5
1
1.5 2 2.5 3
LOAD CURRENT (A)
75
4
70
3.5
0
0.5
1
1.5 2 2.5 3
LOAD CURRENT (A)
5VIN to 1VOUT Transient Response
OUT
IN
1VOUT
20mV/DIV
ISTEP = 2A/µs
2A/DIV
ISTEP = 2A/µs
2A/DIV
20µs/DIV
4
4
3.5
4642 G02
1VOUT
20mV/DIV
20V TO 1.8V (800kHz)
20V TO 1.5V (800kHz)
20V TO 1.2V (650kHz)
20V TO 1V (650kHz)
65
12V TO 5V (1.2MHz)
12V TO 3.3V (1MHz)
12V TO 2.5V (1MHz)
12V TO 1.8V (800kHz)
12V TO 1.5V (800kHz)
12V TO 1.2V (650kHz)
12V TO 1V (650kHz)
80
3.3VIN to 1VOUT Transient
Response
20V TO 5V (1.2MHz)
20V TO 3.3V (1MHz)
20V TO 2.5V (1MHz)
95
3.5
85
4642 G02
Efficiency vs Load Current at
20VIN, CCM Mode
100
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
96
OUT
4642 G05
20µs/DIV
COUT = 100µF 15mΩ ESR POSCAP,
47µF CERAMIC
CFF = 470pF
fSW = 600kHz
COUT = 100µF 15mΩ ESR POSCAP,
47µF CERAMIC
CFF = 470pF
fSW = 650kHz
3.3VIN to 1.5VOUT Transient
Response
5VIN to 1.5VOUT Transient
Response
4642 G06
4642 G04
12VIN to 1VOUT Transient
Response
IN
OUT
IN
IN
OUT
1VOUT
20mV/DIV
1.5VOUT
50mV/DIV
1.5VOUT
50mV/DIV
ISTEP =
2A/µs
2A/DIV
ISTEP = 2A/µs
2A/DIV
ISTEP = 2A/µs
2A/DIV
20µs/DIV
COUT = 100µF 15mΩ ESR POSCAP,
47µF CERAMIC
CFF = 470pF
fSW = 650kHz
4642 G07
20µs/DIV
4642 G08
COUT = 120µF 22mΩ ESR OSCON SVP,
47µF CERAMIC
CFF = 470pF
fSW = 600kHz
OUT
20µs/DIV
4642 G09
COUT = 120µF 22mΩ ESR OSCON SVP,
47µF CERAMIC
CFF = 470pF
fSW = 650kHz
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5
LTM4642
Typical Performance Characteristics
(Refer to Figures 19 and 20) TA = 25°C, unless otherwise noted.
12VIN to 1.5VOUT Transient
Response
IN
3.3VIN to 2.5VOUT Transient
Response
IN
OUT
5VIN to 2.5VOUT Transient
Response
OUT
IN
1.5VOUT
50mV/DIV
2.5VOUT
100mV/DIV
2.5VOUT
100mV/DIV
ISTEP =
2A/µs
2A/DIV
ISTEP = 2A/µs
2A/DIV
ISTEP = 2A/µs
2A/DIV
20µs/DIV
4642 G10
20µs/DIV
OUT
4642 G11
20µs/DIV
COUT = 120µF 22mΩ ESR OSCON SVP,
47µF CERAMIC
CFF = 470pF
fSW = 800kHz
COUT = 47µF CERAMIC
CFF = 68pF
fSW = 600kHz
COUT = 47µF CERAMIC
CFF = 68pF
fSW = 800kHz
12VIN to 2.5VOUT Transient
Response
5VIN to 3.3VOUT Transient
Response
12VIN to 3.3VOUT Transient
Response
IN
OUT
IN
IN
OUT
2.5VOUT
100mV/DIV
3.3VOUT
100mV/DIV
3.3VOUT
100mV/DIV
ISTEP =
2A/µs
2A/DIV
ISTEP = 2A/µs
2A/DIV
ISTEP = 2A/µs
2A/DIV
20µs/DIV
4642 G13
20µs/DIV
4642 G14
OUT
20µs/DIV
COUT = 47µF CERAMIC
CFF = 68pF
fSW = 1MHz
COUT = 47µF CERAMIC
CFF = 68pF
fSW = 800kHz
COUT = 47µF CERAMIC
CFF = 68pF
fSW = 1MHz
6VIN to 5VOUT Transient Response
12VIN to 5VOUT Transient
Response
Clock Synchronization
IN
IN
OUT
4642 G12
4642 G15
OUT
EXTCLK
5V/DIV
5VOUT
100mV/DIV
5VOUT
100mV/DIV
ISTEP =
2A/µs
2A/DIV
ISTEP = 2A/µs
2A/DIV
20µs/DIV
4642 G16
INPUT CAPACITOR 680µF 10V,
LOW IMPEDANCE INPUT CAN USE MUCH LESS
COUT = 47µF CERAMIC
CFF = 68pF
fSW = 600kHz
6
VSW1
10V/DIV
VSW2
10V/DIV
20µs/DIV
4642 G17
1µs/DIV
4642 G18
COUT = 47µF CERAMIC
CFF = 68pF
fSW = 1.2MHz
4642fb
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LTM4642
Typical Performance Characteristics
(Refer to Figures 19 and 20) TA = 25°C, unless otherwise noted.
Output Ripple, 10mV Typical
Shorted Output
PGOOD
5V/DIV
VSW2
20V/DIV
1.5VOUT
10mV/DIV
VOUT
0.5V/DIV
ISHORT
10A/DIV
2µs/DIV
4642 G19
VIN = 20V
VOUT = 1.5V
12V TO 1.5V AT 4A
COUT = 100µF CERAMIC, 47µF CERAMIC
fSW = 800kHz
4642 G20
50µs/DIV
Load Regulation and Current
Limit (No Airflow)
Start-Up, 20V to 1.5V at 4A
1.8
RUN2
5V/DIV
1.5
VSW2
20V/DIV
1.2
VOUT (V)
VOUT2
1V/DIV
DRVCC
INTVCC
5V/DIV
20ms/DIV
COUT = 100µF CERAMIC, 47µF CERAMIC
CSS = 0.1µF
4642 G21
0.9
VOUT = 1.5V
fSW = 1MHz
MODE = CCM
4.5VIN
12VIN
20VIN
0.6
0.3
0
0
1
4
5
2
3
LOAD CURRENT (A)
6
7
4642 G22
4642fb
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7
LTM4642
Pin Functions
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
GND (A4-A7, C2, D1, D5, E1, E5, E7, F7, H4-H7): Power
ground pins for both input and output returns.
PHASMD (B4): Phase Mode Selection Pin for Programming Clock Out Phase. See Electrical Characteristics and
Applications Information sections.
MODE/PLLIN (C3): Mode Selection or External Synchronization Pin. Tying this pin to SGND enables discontinuous
mode. Tying this pin to INTVCC enables forced continuous
operation. A clock on the pin will force the controller into
the continuous mode of operation and synchronize the
internal oscillator. The suitable synchronizable frequency
range is 600kHz to 1400kHz subject to inductor ripple
current limits described in the FREQ/PLLFLTR pin section.
The external clock input high threshold is 2V, while the
input low threshold is 0.5V.
CPWR (C7): This pin is the main input power to the control
IC. This pin normally connects to the input source directly.
This pin can be biased at a voltage greater than 4.5V to
allow the VIN1 and VIN2 to operate down to 2.375V input for
applications that operate at 2.5V or 3.3V input. If the bias
is less than or equal to 5.3V, connect DRVCC to this pin.
SGND (D2, E2): Signal Ground Pins. Return ground path
for all analog and low power circuitry. Tie a single connection to PGND in the application. See the Recommended
Layout section.
CLKOUT (D4): Clock Out for Synchronizing Other Regulators to the Common Clock. Used for multiphase applications. See Applications Information section.
EXTVCC (D6): External Power Input to Controller. When
EXTVCC is higher than 4.7V, the internal 5.3V regulator is
disabled and the external source supplies current to reduce
the power dissipation in the module. This will improve the
efficiency more at high input voltages.
INTVCC (D7): This pin powers the internal control circuits.
Tie this pin to DRVCC with a 2.2Ω resistor. This pin requires
a few milliamps.
8
COMP1, COMP2 (E3, D3): Current Control Threshold and
Error Amplifier Compensation Point. The module has been
internally compensated for all I/O ranges.
FREQ (E4): Frequency Selection Pin. Tie a resistor from
this pin to SGND to set the frequency of operation between
600kHz to 1.4MHz for the specific output voltages. For
3.3V input applications, 650kHz is an optimized frequency.
For 5V to 20V input applications, the optimized operating
frequency for the output voltage is as follows: 0.8V to 1.2V
(650kHz), 1.5V to 1.8V (800kHz), 2.0V to 5V (1.2MHz), 5V
from 20V input (1.4MHz). The resistor equation:
RFREQ (kΩ) =
41550
– 2.2
FREQ (kHz )
DRVCC (E6): This pin is the LDO 5.3V regulator output
used to power the internal control circuits and MOSFET
drivers. This pin needs a 4.7µF ceramic decoupling capacitor to GND. For input voltages less than or equal to 5.3V,
connect this pin directly to the input voltage.
VOUTS1 (F2): Output Voltage Sense Point for Channel 1
Remote Sensing. This pin has a 49.9Ω resistor connected
to VOUT1. This pin can be connected at the load point for
accurate remote sensing.
VOUTS– (F3): Remote Ground Sense Pin. Connect at remote
ground point.
VFB1, VFB2 (F4, C4): The negative input of the error
amplifier. Internally, this pin is connected to VOUT with
a 60.4k precision resistor. Different output voltages can
be programmed with an additional resistor between VFB
and SGND pins. See the Applications Information section
for details.
TRACK/SS1, TRACK/SS2 (F5, C5): Output Voltage Tracking
and Soft-Start Pins. Internal soft-start currents of 1.0µA
charge the soft-start capacitors. See the Applications
Information section to use the tracking function.
PGOOD1, PGOOD2 (F6, C6): Output Voltage Power Good
Indicator. Open-drain logic output that is pulled to ground
when the output voltage is not within ±7.5% of the regulation point. In single output parallel operation when VFB2 is
tied to INTVCC, the PGOOD2 pin is not to be used.
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LTM4642
Pin Functions
RUN1, RUN2 (G3, B3): Run Control Pins. A source can
be used to enable the RUN pins with an external pull-up
resistor. Forcing either of these pins below 1.2V will shut
down the corresponding outputs. An additional 5µA pullup current is added to this pin, once the RUN pin rises
above 1.2V. Also, active control or pull-up resistors can
be used to enable the RUN pin. The maximum voltage is
6V on these pins. There are 100k resistors on RUN1,2
to ground. It is recommended to use an external pull-up
resistor to VIN to enable the RUN pin. See the Applications
Information section.
VRNG1 (G4): Used at Final Test. Tie to INTVCC in normal
operation. This pin can also be used to adjust the current
limit of channel 1. An external resistive divider from INTVCC
can be used to set the voltage on the VRNG pin between
0.6V to 1V, resulting in a maximum sense voltage between
30mV and 50mV. For applications that require less than
7A of the default peak current limit, the VRNG pin voltage
can be scaled down to obtain a desired current limit level.
VIN1 (G5, G6, 67), VIN2 (B5, B6, B7): Power Input Pins.
Apply input voltage between these pins and GND pins.
Recommend placing input decoupling capacitance directly
between VIN pins and GND pins.
VOUT1 (F1, G1, G2, H1, H2), VOUT2 (A1, A2, B1, B2, C1):
Power Output Pins. Apply output load between these pins
and PGND pins. Recommend placing output decoupling
capacitance directly between these pins and PGND pins.
SW1, SW2 (H3, A3): Switching Test Pins. These pins
are provided externally to check the operation frequency.
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9
LTM4642
Simplified Block Diagram
PGOOD1
PGOOD1
INPUT VOLTAGE SOURCE LESS THAN 5.3V BUT GREATER
THAN 4.5V, CONNECT DRVCC AND CPWR TO VIN. INPUT
VOLTAGE LESS THAN 4.5V BUT GREATER THAN 2.375V,
PROVIDE AN EXTERNAL BIAS TO CPWR 5V OR GREATER
CPWR
R5
2.2Ω
TRACK1
RUN1 = 100k
((MIN VIN/1.3) – 1)
VIN1
TRACK1
C7
0.1µF
SS
CAP
MTOP1
RUN1*
RRUN1
255k
MBOT1
2.2µF
49.9Ω
+
+
COUT1
GND
RFREQ
49.9k
60.4k
VFB1
+
–
COMP1
C3
47µF
VOUTS1
POWER CONTROL
FREQ
COMP1
VOUT1
1.5V/4A
VOUT1
PHASMD
PHASMD
C1
22µF
25V
GND
SW1
1µH
MODE/PLLIN
INTVCC
C7
0.1µF
100k
CLKOUT
CLKOUT
VIN1
4.5V TO 20V
VIN1
VFB1
RSET1
40.2k
VOUTS–
INTERNAL
COMP
TRACK2
VIN2
TRACK2
SGND
PGOOD2
SS
CAP
RUN2
RRUN2
255k
VRNG1
100k
INTVCC
MTOP2
MBOT2
INTVCC
VOUT2
COMP2
SW2 V
OUT2
1.2V/4A
+
1µF
COUT2
GND
C2
1µF
EXTVCC
VIN2
C4
22µF 4.5V TO 20V
25V
GND
SW2
C6
1µF
4.7µF
0.1µF
1µH
DRVCC
R4
2.2Ω
PGOOD2
VIN2
GND
60.4k
VFB2
EXTVCC
RSET2
60.4k
COMP2
VFB2
INTERNAL
COMP
SGND
SGND
4642 F01
* ABSOLUTE MAXIMUM = 6V
Figure 1. Simplified LTM4642 Block Diagram
Decoupling Requirements
TA = 25°C. Use Figure 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
CIN
External Input Capacitor Requirement
VIN = 4.5V to 20V, VOUT1 = 1.5V, VOUT2 = 1.5V
IOUT1 = 4A, IOUT2 = 4A
22
µF
IOUT1 = 4A
IOUT2 = 4A
150
150
µF
µF
COUT1
COUT2
10
External Output Capacitor Requirement
VIN = 4.5V to 20V, VOUT1 = 1.5V, VOUT2 = 1.5V
MIN
TYP
MAX
UNITS
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LTM4642
Operation
The LTM4642 is a dual independent input 4A nonisolated
switching mode DC/DC power supply. It can deliver up to
4A (DC current) for each output with few external input and
output capacitors. This module provides precisely regulated
output voltages programmable via external resistors from
0.6V to 5.5V over a 4.5V to 20V input voltage range. The
Typical Application schematic is shown in Figure 27. The
input voltage source can operate down to 2.375V with an
external bias applied to the CPWR pin. The external bias
needs to be 5V or higher. See the Typical Applications
schematics for examples.
Current mode control provides cycle-by-cycle fast current
limit and current foldback in a short-circuit condition. Internal overvoltage and undervoltage comparators pull the
open-drain PGOOD pins output low if the output feedback
voltage exits a ±7.5% window around the regulation point.
The power good pin is disabled during start-up.
The LTM4642 has integrated constant on-time valley current mode regulators and built-in power MOSFET devices
with fast switching speed. To reduce switching noise, the
two outputs are interleaved with 180° phase internally and
can be synchronized externally using the MODE/PLLIN pin.
The LTM4642 is internally compensated to be stable over
all operating conditions. LTpowerCAD® is available for
transient and stability analysis. The VFB pins are used to
program the output voltage with a single external resistor
to ground. Multiphase operation can be easily employed
with clock synchronization.
With current mode control and internal feedback loop
compensation, the LTM4642 module has sufficient stability margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
Pulling the RUN pins below 1.2V forces the controller
into its shutdown state, by turning off both MOSFETs.
The TRACK/SS pins are used for programming the output
voltage ramp and voltage tracking during start-up. See the
Applications Information section.
High efficiency at light loads can be accomplished with
selectable discontinuous mode using the MODE/PLLIN pin.
Efficiency graphs are provided for light load operations in
the Typical Performance Characteristics section.
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LTM4642
Applications Information
The typical LTM4642 application circuit is shown in
Figure 27. External component selection is primarily determined by the maximum load current and output voltage.
Output Voltage Programming
The PWM controller has an internal 0.6V reference voltage.
As shown in the Block Diagram, a 60.4k internal feedback
resistor RFB connects VOUT to the VFB pin. The output voltage will default to 0.6V with no feedback resistor. Adding
a resistor RSET from the VFB pin to SGND programs the
output voltage:
60.4k +RSET
VOUT = 0.6V •
RSET
or equivalently:
RSET =
60.4k
⎛ VOUT ⎞
– 1⎟
⎜
⎝ 0.6V ⎠
Table 1. RSET Resistor Table vs Various Output Voltages
VOUT (V)
0.6
1.0
1.2
1.5
1.8
2.5
3.3
5
RSET (kΩ)
Open
90.9
60.4
40.2
30.1
19.1
13.3
8.25
VOUT1 supports feedback voltage referred remote sensing,
as such the VOUTS1 pin can be tied to VOUT1 at the load
sense point, and VOUTS– is tied to ground at the load sense
point. VOUT2 is programmed with a resistor to ground. For
a 2-phase single 8A output, the VFB2 pin can be connected
to INTVCC to disable the channel 2 error amplifier, and internally connect the COMP2 pin to COMP1 pin. The COMP2
pin can be left floating or connected to COMP1 externally.
The TRACK/SS2 and PGOOD2 pins are not functional in
this mode, thus they can be left floating. See the Typical
Applications at the end of the data sheet.
Input Capacitors
The LTM4642 module should be connected to a low ACimpedance DC source. A 47µF to 100µF surface mount
aluminum electrolytic capacitor can be used for more input
bulk capacitance. This bulk capacitor is only needed if the
input source impedance is compromised by long inductive
leads, traces or not enough source capacitance.
12
For a buck converter, the switching duty-cycle can be
estimated as:
D=
VOUT
VIN
Without considering the inductor ripple current, for each
output, the RMS current of the input capacitor can be
estimated as:
ICIN(RMS) =
IOUT(MAX)
η
• D•(1−D)
In the above equation, η is the estimated efficiency of the
power module. The bulk capacitor can be a switcher-rated
aluminum electrolytic capacitor or a polymer capacitor. One
22µF ceramic input capacitor is typically rated for 2A of
RMS ripple current, so the RMS input current at the worst
case for each output at 4A maximum current is about 2A.
If a low inductance plane is used to power the device, then
two 22µF ceramic capacitors are enough for both outputs
at 4A load and no external input bulk capacitor is required.
Output Capacitors
The LTM4642 is designed for low output voltage ripple
noise. The bulk output capacitors defined as COUT are
chosen with low enough effective series resistance (ESR)
to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, a low
ESR polymer capacitor or ceramic capacitor. The typical
output capacitance range for each output is from 47µF
to 220µF. Additional output filtering may be required by
the system designer, if further reduction of output ripple
or dynamic transient spikes is required. LTpowerCAD is
available for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the number
of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the
output capacitance should be considered carefully as a
function of stability and transient response. LTpowerCAD
calculates the output ripple reduction as the number of
implemented phases increased by N times. See Table 6
for output capacitor suggestions.
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LTM4642
applications information
Mode Selections and Phase-Locked Loop
The LTM4642 can be enabled to operate in discontinuous
or forced continuous mode. To select the forced continuous
operation, tie the MODE/PLLIN pin to INTVCC. To select
discontinuous operation, or tie the MODE/PLLIN pin to
ground. This will improve the light load efficiency.
Frequency Selection and External Clock
Synchronization
An internal oscillator (clock generator) provides phase
interleaved internal clock signals for individual channels
to lock on to. The switching frequency and phase of each
switching channel is independently controlled by adjusting the top MOSFET turn-on time (on-time) through the
one-shot timer. This is achieved by sensing the phase
relationship between a top MOSFET turn-on signal and
its internal reference clock through a phase detector, and
the time interval of the one-shot timer is adjusted on a
cycle-by-cycle basis, so that the rising edge of the top
MOSFET turn-on is always trying to synchronize to the
internal reference clock signal for the respective channel.
The frequency of the internal oscillator can be programmed
from 600kHz to 1.4MHz by connecting a resistor, RFREQ,
from the FREQ pin to signal ground (SGND). The equation:
41550
RFREQ (kΩ) =
– 2.2
FREQ (kHz )
For applications with stringent frequency or interference
requirements, an external clock source connected to the
MODE/PLLIN pin can be used to synchronize the internal
clock signals through a clock phase-locked loop (Clock
PLL). The LTM4642 operates in forced continuous mode
of operation when it is synchronized to the external clock.
The external clock frequency has to be within ±30% of the
internal oscillator frequency for successful synchronization. The clock input levels should be no less than 2V for
“high” and no greater than 0.5V for “low”. The MODE/
PLLIN pin has an internal 600k pull-down resistor.
PHASMD Pin Programming
The PHASMD pin determines the relative phases between
the internal reference clock signals for the two channels
as well as the CLKOUT signal, as shown in Table 2. The
phases tabulated are relative to zero degree (0°) being
defined as the rising edge of the internal reference clock
signal of channel 1. The CLKOUT signal can be used to
synchronize additional power regulator modules. The
system can be configured for up to 12-phase operation
with a multichannel solution. Typical configurations are
shown in Table 3 to interleave the phases of the channels.
The applications will validate a 6 phase multiple regulator
solution with multiple outputs.
Each of the LTM4642 channels can be paralleled up to 8A
of output, but cannot be paralleled from one module to
the other modules. Twelve phases can be paralleled with
no more than two phases per module.
Table 2
PHASMD
SGND
FLOAT
INTVCC
Channel 1
0°
0°
0°
Channel 2
180°
180°
240°
CLKOUT
60°
90°
120°
Table 3
NUMBER OF
PHASES
NUMBER OF
LTM4642*
PIN CONNECTIONS
[PIN NAME (CHIP NUMBER)]
2
1
PHASMD(1) = FLOAT or SGND
3
2 or
PHASMD(1) = INTVCC
1 + ½(LTM4642) MODE/PLLIN(2) = CLKOUT(1)
4
2
PHASMD(1) = FLOAT
PHASEMD(2) = FLOAT or SGND
MODE/PLLIN(2) = CLKOUT(1)
6
3
PHASMD(1) = SGND
PHASMD(2) = SGND
MODE/PLLIN(2) = CLKOUT(1)
PHASMD(3) = FLOAT or SGND
MODE/PLLIN(3) = CLKOUT(2)
*No more than two channels of any one module may be paralleled.
Soft-Start and Tracking
The LTM4642 has the ability to either soft-start by itself
with a capacitor or track the output of another channel or
external supply. When one particular channel is configured
to soft-start by itself, a capacitor should be connected to
its TRACK/SS pin. This channel is in the shutdown state
if its RUN pin voltage is below 1.2V. Its TRACK/SS pin is
actively pulled to ground in this shutdown state.
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LTM4642
Applications Information
Once the RUN pin voltage is above 1.2V, the channel powers up. A soft-start current of 1µA then starts to charge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TRACK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
defined to be the voltage range from 0V to 0.6V on the
TRACK/SS pin. The total soft-start time can be calculated as:
tSOFT-START =
VTRACK is the track ramp applied to the slave’s TRACK/SS2
pin. VTRACK has a control range of 0V to 0.6V. When the
master’s output is divided down with the same resistor
values used to set the slave’s output, then the slave will
coincident track with the master until it reaches its final
value. The master will continue to its final value from the
slave’s regulation point.
Ratiometric modes of tracking can be achieved by selecting different divider resistors values to change the output
tracking ratio. The master output must be greater than the
0.6V •CSS (µF )
1µA
MASTER OUTPUT
Output voltage tracking can be programmed externally
using the TRACK/SS pin. The master channel is divided
down with an external resistor divider that is the same
as the slave channel’s feedback divider to implement coincident tracking. The LTM4642 uses an accurate 60.4k
resistor internally for the top feedback resistor. Figure 2
shows an example of coincident tracking. Figure 3 shows
the output voltages with coincident tracking.
4642 F03
TIME
⎛ R1 ⎞
VSLAVE = ⎜1+ ⎟ • VTRACK
⎝ R2 ⎠
VIN
4.75V TO 20V
SLAVE OUTPUT
OUTPUT
VOLTAGE
Figure 3. Coincident Tracking
2.2Ω
CIN2
22µF
CIN1
22µF
131k
DRVCC INTVCC
VRNG1
VIN1 VIN2 CPWR
RUN1
RUN2
PGOOD1
PGOOD1
PGOOD2
PGOOD2
TRACK/SS1
0.1µF
TRACK/SS2
R1
60.4k
INTVCC
4.7µF
VOUT1
R2
90.9k
LTM4642
VOUT1
VOUT2
10k
VOUT1 1.5V AT 4A LOAD
COUT3
47µF
VOUT2 1.0V AT 4A LOAD
COUT1 +
47µF
FREQ
INTVCC
10k
COUT2
100µF
+
COUT4
100µF
VOUTS1
MODE/PLLIN
VOUTS–
RFREQ
61.9k
VFB2
SGND
GND
VFB1
470pF
RFB1
40.2k
470pF
VOUT1
RFB2
90.9k
VOUT2
4642 F02
PINS NOT USED: COMP1, COMP2, PHASEMD, CLKOUT, EXTVCC, SW1, SW2
Figure 2. Example of Coincident Tracking
14
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LTM4642
Applications Information
slave output for the tracking to work. Master and slave
data inputs can be used to implement the correct resistors
values for coincident or ratiometric tracking.
Multiphase Operation
Multiphase operation with the LTM4642 two regulator
channels in parallel will lower the effective input RMS
ripple current as well as the output ripple current due
to the interleaving operation of the regulators. Figure 4
provides a ratio of input RMS ripple current to DC load
current as a function of duty cycle and the number of
paralleled phases. Choose the corresponding duty cycle
and the number of phases to get the correct ripple current
value. For example, the 2-phase parallel for one LTM4642
design provides 8A at 2.5V output from a 12V input. The
duty cycle is DC = 2.5V/12V = 0.21. The 2-phase curve
has a ratio of ~0.25 for a duty cycle of 0.21. This 0.25
ratio of RMS ripple current to a DC load current of 8A
equals ~2A of input RMS ripple current for the external
input capacitors. No more than two phases of a module
may be paralleled.
The effective output ripple current is lowered with
multiphase operations as well. Figure 5 provides a ratio
of peak-to-peak output ripple current to the normalized
output ripple current as a function of duty cycle and the
number of paralleled phases. Choose the corresponding
duty cycle and the number of phases to get the correct
output ripple current ratio value. If a 2-phase operation is
chosen at 12VIN to 2.5VOUT with a duty cycle of 21%, then
0.6 is the ratio of the normalized output ripple current to
inductor ripple DIr at the corresponding duty cycle. This
leads to ~1.3A of the effective output ripple current ΔIL
if the DIr is at 2.2A. Refer to Application Note 77 for a
detailed explanation of the output ripple current reduction
as a function of paralleled phases.
The output ripple voltage has two components that are
related to the amount of bulk capacitance and effective
series resistance (ESR) of the output bulk capacitance.
Therefore, the output ripple voltage can be calculated with
the known effective output ripple current. The equation:
ΔVOUT(P-P) ≈ ΔIL/(8 • f • N • COUT) + ESR • ΔIL
where f is frequency and N is the number of parallel phases.
RUN Pin
The RUN pins can be used to enable or sequence the
particular regulator channel. The RUN pins have their own
internal 1.2µA current source to pull up the RUN pins to
1.2V, and the current will increase to 5µA above 1.2V. Board
contamination or residue can load down these small pull-up
currents, so a 100k resistor is placed from the RUN pins
to ground. This 100k resistor can be used with a resistor
to VIN to set the turn-on threshold for the RUN pins
The resistor divider needs to be low enough resistance
to swamp out the pull-up current sources to prevent
unintended activation of the device. The RUN pin has a
maximum rated voltage of 6V. See Figure 1 Block Diagram
for set turn on equation.
Power Good
The PGOOD pin is connected to the open drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when either VFB pin voltage is not within
±7.5% of the 0.6V reference voltage. The PGOOD pin is
also pulled low when either RUN pin is below 1.2V or when
the LTM4642 is in the soft-start or tracking phase. When
the VFB pin voltage is within the ±7.5% requirement, the
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source of up to 6V. The
PGOOD pin will flag power good immediately when both
VFB pins are within the ±7.5% window. However, there is
an internal 17µs power bad mask when either VFB goes out
of the ±7.5% window. In parallel single output operation,
only use PGOOD1.
CPWR, DRVCC, INTVCC and EXTVCC
The CPWR is the main power input to the internal control IC.
This pin is normally connected to the input voltage source.
This pin can be biased with a 5V supply when operating
at input voltages below 4.5V. When 4.5V < VIN < 5.3V,
Then tie CPWR to DRVCC. See the Typical Applications.
The DRVCC is the internal 5.3V regulator that powers the
LTM4642 internal MOSFET drivers for the internal power
MOSFETs. The DRVCC requires a 4.7µF ceramic capacitor
to ground. INTVCC powers the internal controller circuits
and is connected to DRVCC through a 2.2Ω resistor. This
INTVCC bias is ≤ 20mA.
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15
LTM4642
applications information
0.60
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.55
0.50
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
*The LTM4642 can only have the two
channels per module paralleled
0.1 0.15
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VOUT/VIN)
4642 F04
Figure 4. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six Phases*
1.00
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.95
0.90
0.85
0.80
RATIO =
PEAK-TO-PEAK OUTPUT RIPPLE CURRENT
DIr
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VOUT/VIN)
4642 F05
Figure 5. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOUT T/L
16
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LTM4642
applications information
A 5V output on channel 1 or 2 can be used to power the
EXTVCC pin when the input voltage is at the high end of the
supply range to reduce power dissipation in the module.
For example, the dropout voltage for 20V input would be
20V – 5V = 15V. This 15V headroom then multiplied by
the power MOSFET drive current of ~30mA would equal
~0.45W additional power dissipation. So utilizing a 5V
output on the EXTVCC would improve design efficiency and
reduce device temperature rise. Otherwise try to operate
CWPR off of a 5V bias when operating at higher supply
voltages. See the Typical Applications section.
Fault Conditions: Current Limit and Overcurrent
Foldback
The LTM4642 has a current mode controller, which inherently limits the cycle-by-cycle inductor current not only in
steady-state operation, but also in transient.
To further limit current in the event of an overload condition, the LTM4642 provides foldback current limiting. If the
output voltage falls by more than 50%, then the maximum
output current is progressively lowered to one-fourth of
its full current limit value. Foldback current limiting is
disabled during soft-start and tracking up.
SW Pins
The SW pins are generally for testing purposes by monitoring these pins. These pins can also be used to dampen
out switch node ringing caused by LC parasitic in the
switched current paths. Usually a series R-C combination is used called a snubber circuit. The resistor will
dampen the resonance and the capacitor is chosen to
only affect the high frequency ringing across the resistor.
If the stray inductance or capacitance can be measured or
approximated then a somewhat analytical technique can
be used to select the snubber values. The inductance is
usually easier to predict. It combines the power path board
inductance in combination with the MOSFET interconnect
bond wire inductance.
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring frequency can be measured for its value. The impedance Z
can be calculated:
Z (L) = 2πfL,
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by: Z (C) = 1/(2πfC). These values are a good
place to start with. Modification to these components
should be made to attenuate the ringing with the least
amount of power loss.
Thermal Considerations and Output Current Derating
In different applications, the LTM4642 operates in a variety
of thermal environments. The maximum output current is
limited by the environmental thermal condition. Sufficient
cooling should be provided to ensure reliable operation.
When the cooling is limited, proper output current derating is necessary, considering the ambient temperature,
airflow, input/output conditions, and the need for increased
reliability.
The two outputs of the LTM4642 are paralleled to characterize the output current derating curves. The power loss
curves in Figure 8 to Figure 10 can be used in coordination
with load current derating curves in Figure 11 to Figure 24
for calculating an approximate θJA for the module with
various cooling methods. Application Note 103 provides
detailed explanation of the analysis for the thermal models
and the derating curves. Tables 4 and 5 provide a summary of the equivalent θJA parameters are correlated to
the measured values, and are improved with airflow.
The power loss curves are taken at room temperature, and
are increased with multiplicative factors according to the
ambient temperature. The approximate factors are: 1.35 for
115°C and 1.4 for 120°C. The derating curves are plotted
with CH1 and CH2 paralleled output current starting at 8A
and the ambient temperature starting at 50°C. The derated
output voltages are 1.0V, 2.5V, 3.3V and 5.0V. Tables 4
and 5 specify the approximate θJA with airflow conditions
for 1V and 5V outputs. These two conditions are chosen to
include the lower and higher output voltage ranges for correlating the thermal resistance, but any derating curve point
along with power loss curve can be used to calculate the
θJA. Thermal models are derived from several temperature
measurements in a controlled temperature chamber along
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17
LTM4642
applications information
Table 4. 1V Output
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
ΘJA (°C/W)
Figures 11, 13
5, 12
Figures 8, 9
0
none
13
Figures 11, 13
5, 12
Figures 8, 9
200
none
10
Figures 11, 13
5, 12
Figures 8, 9
400
none
9
Figures 12, 14
5, 12
Figures 8, 9
0
BGA Heat Sink
13
Figures 12, 14
5, 12
Figures 8, 9
200
BGA Heat Sink
8
Figures 12, 14
5, 12
Figures 8, 9
400
BGA Heat Sink
7.5
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
ΘJA (°C/W)
Figures 21, 23
12, 20
Figures 9, 10
0
none
15
Figures 21, 23
12, 20
Figures 9, 10
200
none
13
Figures 21, 23
12, 20
Figures 9, 10
400
none
12
Figures 22, 24
12, 20
Figures 9, 10
0
BGA Heat Sink
14
Figures 22, 24
12, 20
Figures 9, 10
200
BGA Heat Sink
10
Figures 22, 24
12, 20
Figures 9, 10
400
BGA Heat Sink
10
Table 5. 5V Output
Table 6. Output Voltage Response vs Component Matrix (Refer to Figure 27) 0A to 2A Load Step Typical Measured Values
CERAMIC CAPACITOR
VENDORS
VALUE
PART NUMBER
BULK VENDORS
VALUE
PART NUMBER
ESR
Murata
COUT: 47µF 6.3V, X5R
GRM21BR60J476ME15
Sanyo OSCON SVPC
COUT: 120µF 10V
10SVPC120MV
22mΩ
Murata
COUT: 47µF 10V, X5R
GRM31CR61A476KE15
Panasonic SP
COUT: 100µF 6.3V
EEFCTOJ101R
15mΩ
Murata
CIN: 22µF, X7R, 16V
GRM32ER71C226KEA8
CIN
COUT1
CIN
VOUT (V) (CERAMIC) (BULK)** (CERAMIC)
COUT2 (CER
AND BULK)
CFF
(pF)
VIN (V)
DROOP PEAK TO RECOVERY LOAD STEP
(mV)
PEAK
TIME (µs)
(A/µs)
RFB
(kΩ)
FREQ
(kHz)
1
22µF × 2
56µF
47µF
100µF or 120µF
470
3.3, 5, 12
31
62
20
2
90.9
650
1.2
22µF × 2
56µF
47µF
100µF or 120µF
470
3.3, 5, 12
30
63
20
2
60.4
650
1.5
22µF × 2
56µF
47µF
100µF or 120µF
470
3.3, 5, 12
35
70
20
2
40.2
700
1.8
22µF × 2
56µF
47µF
100µF or 120µF
470
3.3, 5, 12
38
80
25
2
30.1
750
2.5
22µF × 2
56µF
47µF
68
3.3, 5, 12
100
200
20
2
19.1
1000
3.3
22µF × 2
56µF
47µF
68
5, 12
120
240
20
2
13.3
1000
5
22µF × 2
56µF
47µF
68
185
390
20
2
8.25
1200
** Bulk capacitance is optional if VIN has very low input impedance.
HEAT SINK MANUFACTURER
PART NUMBER
WEBSITE
Cool Innovations
3-05040
www.coolinnovations.com
Chomerics
T411 Interface
www.chomerics.com
18
4642fb
For more information www.linear.com/LTM4642
LTM4642
applications information
with thermal modeling analysis. The junction temperatures
are monitored while ambient temperature is increased with
and without airflow. The power loss increase with ambient
temperature change is factored into the derating curves.
The junctions are maintained at 120°C maximum while
lowering output current or power with increasing ambient
temperature. The decreased output current will decrease the
internal module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus
the ambient operating temperature specifies how much
module temperature rise can be allowed. As an example
in Figure 14 the load current is derated to ~7A at ~100°C
with no air or heat sink and the power loss for the 12V to
1.0V at 7A output is about 1.2W (power loss at 3.5A load
multiplied by 2). The 1.2W loss is multiplied by the 1.4
multiplying factor at 120°C junction to get 1.68W. If the
100°C ambient temperature is subtracted from the 120°C
junction temperature, then the difference of 20°C divided
by 1.68W equals a 12°C/W thermal resistance. Table 4
specifies a 13°C/W value which is very close. Table 4 and
Table 5 provide equivalent thermal resistances for 1.0V
and 5V outputs with and without airflow and heat sinking.
The derived thermal resistances in Tables 4 and 5 for the
various conditions can be multiplied by the calculated
power loss as a function of ambient temperature to derive
temperature rise above ambient, thus maximum junction
temperature. The printed circuit board is a 1.6mm thick
four layer board with two ounce copper for the two outer
layers and one ounce copper for the two inner layers. The
PCB dimensions are 95mm × 76mm. The BGA heat sinks
are listed below Table 5.
The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those
parameters defined by JESD51-12 and are intended for
use with finite element analysis (FEA) software modeling
tools that leverage the outcome of thermal modeling,
simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware
test board defined by JESD51-9 (“Test Boards for Area
Array Surface Mount Package Thermal Measurements”).
The motivation for providing these thermal coefficients is
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulator’s thermal performance in their application at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in the data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section gives four thermal coefficients explicitly defined in JESD51-12; these coefficients
are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as “still air” although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
2. θJCbottom, the thermal resistance from junction to the
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical µModule, the bulk
of the heat flows out the bottom of the package, but
there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be
useful for comparing packages but the test conditions
don’t generally match the user’s application.
3. θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
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19
LTM4642
applications information
4. θJB, the thermal resistance from junction to the
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the µModule and into the board, and
is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD51-9.
A graphical representation of the aforementioned thermal resistances is given in Figure 6; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom of the µModule package—as the standard defines
for θJCtop and θJCbottom, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4642, be aware there are multiple power
devices and components dissipating power, with a consequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
values supplied in this data sheet: (1) Initially, FEA software
is used to accurately build the mechanical geometry of
the LTM4642 and the specified PCB with all of the correct material coefficients along with accurate power loss
source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JESD51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4642 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power
loss as that which was simulated. An outcome of this
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
4642 F06
µModule DEVICE
Figure 6. Graphical Representation of JESD51-12 Thermal Coefficients
20
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LTM4642
applications information
process and due diligence yields a set of derating curves
provided in other sections of this data sheet. After these
laboratory tests have been performed, then the θJB and
θBA are summed together to correlate quite well with the
LTM4642 model with no airflow or heat sinking in a properly
define chamber. This θJB + θBA value is shown in the Pin
Configuration section and should accurately equal the θJA
value because approximately 100% of power loss flows
from the junction through the board into ambient with no
airflow or top mounted heat sink. Each system has its own
thermal characteristics, therefore thermal analysis must
be performed by the user in a particular system.
The LTM4642 has been designed to effectively remove
heat from both the top and bottom of the package. The
bottom substrate material has very low thermal resistance
to the printed circuit board and the exposed top metal is
thermally connected to the power devices and the power
inductors. An external heat sink can be applied to the top of
the device for excellent heat sinking with airflow. Basically
all power dissipating devices are mounted directly to the
substrate and the top exposed metal. This provides two
low thermal resistance paths to remove heat.
Safety Considerations
The LTM4642 modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
VIN (V)
VOUT1 (V)
VOUT2 (V)
ILOAD PER
PHASE (A)
fSW (kHz)
HOT TEMP
PEAK TEMP (°C)
12
2.5
1.5
4
1000
56.6
Figure 7. Thermal Plot for the Specified Operation. The Temperature Rise About 25°C Ambient Is About 30°C Rise
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21
LTM4642
applications information
0.6
0.4
0.2
0
2.2
12V to 5V
12V to 3.3V
12V to 2.5V
12V to 1.8V
12V to 1.5V
12V to 1.2V
12V to 1V
1.2
POWER LOSS (W)
0.8
POWER LOSS (W)
1.4
5V to 3.3V
5V to 2.5V
5V to 1.8V
5V to 1.5V
5V to 1.2V
5V to 1V
1.0
0.8
1.8
0.6
0.4
0
0.5
1
1.5
2
2.5
3
3.5
4
1.2
1.0
0.8
0.2
0
0.5
1
1.5
2
2.5
3
0
4
3.5
4642 F08
7
7
7
6
6
6
3
60
70
5
4
3
2
0 LFM
200 LFM
400 LFM
50
IOUT(MAX) (A)
8
IOUT(MAX) (A)
9
4
90
100
110
0
120
50
60
70
tAMB (°C)
80
90
100
0 LFM
200 LFM
400 LFM
110
0
120
50
8
8
8
7
7
6
6
0
IOUT(MAX) (A)
60
70
4
3
80
90
100
110
120
0
50
60
70
80
90
4642 F14
120
110
4
3
0 LFM
200 LFM
400 LFM
1
100
110
120
0
50
60
70
80
90
100
110
120
tAMB (°C)
tAMB (°C)
Figure 14. 12VIN, 1VOUT 650kHz,
with Heat Sink
100
5
2
0 LFM
200 LFM
400 LFM
1
tAMB (°C)
22
5
2
0 LFM
200 LFM
400 LFM
50
IOUT(MAX) (A)
9
3
90
4642 F13
9
4
80
Figure 13. 12VIN, 1VOUT 650kHz,
No Heat Sink
9
1
70
4642 F12
10
2
60
tAMB (°C)
Figure 12. 5VIN, 1VOUT 650kHz,
with Heat Sink
7
4
3.5
3
1
4642 F11
Figure 11. 5VIN, 1VOUT 650kHz,
No Heat Sink
5
3
4
tAMB (°C)
6
2.5
5
2
0 LFM
200 LFM
400 LFM
1
80
2
4642 F10
8
5
1.5
Figure 10. 20V Input Power Loss
9
0
1
4642 F09
Figure 9. 12V Input Power Loss
8
1
0.5
CURRENT LOAD (A)
9
2
0
CURRENT LOAD (A)
Figure 8. 5V Input Power Loss
IOUT(MAX) (A)
1.4
0.4
CURRENT LOAD (A)
IOUT(MAX) (A)
1.6
0.6
0.2
0
20V to 1.5V
20V to 1.2V
20V to 1V
20V to 5V
20V to 3.3V
20V to 2.5V
20V to 1.8V
2.0
POWER LOSS (W)
1.0
4642 F15
Figure 15. 5VIN, 3.3VOUT 650kHz,
No Heat Sink
4642 F16
Figure 16. 5VIN, 3.3VOUT 650kHz,
with Heat Sink
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LTM4642
9
9
8
8
8
7
7
7
6
6
6
5
4
3
2
0
50
60
70
5
4
3
2
0 LFM
200 LFM
400 LFM
1
IOUT(MAX) (A)
9
IOUT(MAX) (A)
IOUT(MAX) (A)
applications information
80
90
100
110
0
120
50
60
70
tAMB (°C)
3
80
90
100
0
120
110
7
7
7
6
6
6
5
4
3
IOUT(MAX) (A)
8
IOUT(MAX) (A)
9
8
5
4
3
2
0 LFM
200 LFM
400 LFM
60
80
90
100
110
0
120
50
60
70
80
90
100
8
7
7
6
6
IOUT(MAX) (A)
IOUT(MAX) (A)
9
4
3
60
70
80
70
90
100
110
120
100
110
120
4642 F22
Figure 22. 12VIN, 5VOUT 1.2MHz,
with Heat Sink
4
3
0 LFM
200 LFM
400 LFM
1
80
90
5
2
0 LFM
200 LFM
400 LFM
60
50
4642 F21
8
50
0 LFM
200 LFM
400 LFM
tAMB (°C)
9
0
0
120
110
Figure 21. 12VIN, 5VOUT 1.2MHz,
No Heat Sink
5
120
110
3
1
4642 F20
Figure 20. 20VIN, 2.5VOUT 1MHz,
with Heat Sink
1
100
4
tAMB (°C)
tAMB (°C)
2
90
5
2
0 LFM
200 LFM
400 LFM
1
70
80
4642 F19
9
50
70
Figure 19. 20VIN, 2.5VOUT 1MHz,
No Heat Sink
8
0
60
4642 F18
Figure 18. 12VIN, 2.5VOUT 1MHz,
with Heat Sink
9
1
50
tAMB (°C)
4642 F17
2
0 LFM
200 LFM
400 LFM
1
tAMB (°C)
Figure 17. 12VIN, 2.5VOUT 1MHz,
No Heat Sink
IOUT(MAX) (A)
4
2
0 LFM
200 LFM
400 LFM
1
5
0
50
60
tAMB (°C)
70
80
90
100
110
120
tAMB (°C)
4642 F23
Figure 23. 20VIN, 5VOUT 1.2MHz,
No Heat Sink
4642 F24
Figure 24. 20VIN, 5VOUT 1.2MHz,
with Heat Sink
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LTM4642
Applications information
Layout Checklist/Example
The high integration of LTM4642 makes the PCB board
layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations
are still necessary.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnections
between top layer and other power layers.
• Do not put vias directly on the pads.
• Use large PCB copper areas for high current path, including VIN1, VIN2, PGND, VOUT1 and VOUT2. It helps to
minimize the PCB conduction loss and thermal stress.
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to PGND underneath the unit.
• Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize
high frequency noise.
• Decouple the input and output grounds to lower the
output ripple noise.
Figure 25 gives a good example of the recommended layout.
• Place a dedicated power ground layer underneath the
unit.
GND
VOUT2
GND
COUT2
3
4
5
A
B
RFB2
VOUT2
2
6
7
CTK/SS2
1
CIN2
CIN4
VIN2
D
GND
RFREQ
C
CINTVCC
E
GND
VOUT1
H
COUT2
CTK/SS1
G
RFB1
F
VIN1
CIN3
CIN1
GND
VOUT1
GND
4642 F25
Figure 25. Recommended PCB Layout
24
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For more information www.linear.com/LTM4642
LTM4642
Typical Applications
VIN
4.5V TO 20V
2.2Ω
CIN1
22µF
CIN2
22µF
131k
DRVCC INTVCC
VRNG1
VIN1 VIN2 CPWR
RUN1
RUN2
0.1µF
0.1µF
INTVCC
4.7µF
10k
PGOOD1
PGOOD1
PGOOD2
PGOOD2
TRACK/SS1
TRACK/SS2
VOUT1
VOUT2
LTM4642
10k
VOUT1 0.9V AT 4A LOAD
+
COUT1
47µF
COUT2
100µF
FREQ
INTVCC
COUT3
47µF
VOUT2 1V AT 4A LOAD
+
COUT4
100µF
VOUTS1
MODE/PLLIN
VOUTS–
RFREQ
61.9k
VFB2
VOUT1
VFB1
SGND
GND
VOUT2
RFB2
CFF
90.9k 470pF
RFB1 CFF
121k 470pF
4642 F26
PINS NOT USED: COMP1, COMP2, PHASEMD, CLKOUT, EXTVCC, SW1, SW2
Figure 26. 4.5V to 20V Input, 650kHz, 0.9V and 1.2V Outputs at 4A Each
VIN
5V
2.2Ω
CIN1
22µF
CIN2
22µF
131k
DRVCC INTVCC
VRNG1
VIN1 VIN2 CPWR
RUN1
RUN2
0.1µF
0.1µF
INTVCC
4.7µF
PGOOD1
PGOOD1
PGOOD2
PGOOD2
TRACK/SS1
TRACK/SS2
VOUT1
LTM4642
VOUT2
10k
VOUT1 1.8V AT 4A LOAD
COUT2
47µF
VOUT2 2.5V AT 4A LOAD
+
COUT1
47µF
FREQ
INTVCC
10k
COUT3
120µF
OSCON SVP
VOUTS1
MODE/PLLIN
VOUTS–
RFREQ
49.9k
VFB2
SGND
GND
VFB1
470pF
RFB1
30.2k
470pF
VOUT1
RFB2
19.1k
VOUT2
4642 F27
PINS NOT USED: COMP1, COMP2, PHASEMD, CLKOUT, EXTVCC, SW1, SW2
Figure 27. 5V Input, 800kHz, 2.5V and 1.8V Outputs at 4A Each
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25
LTM4642
TYPICAL applications
VIN
4.75V TO 20V
2.2Ω
CIN1
22µF
CIN2
22µF
131k
DRVCC INTVCC
VRNG1
VIN1 VIN2 CPWR
RUN1
RUN2
60.4k
10k
TRACK/SS1
PGOOD1
PGOOD2
TRACK/SS2
VOUT1
60.4k
60.4k
INTVCC1
4.7µF
19.1k
LTM4642
VOUT2
10k
1.2V AT 4A LOAD
COUT1
47µF
2.5V AT 4A LOAD
+
COUT3
47µF
FREQ
COUT2
100µF
VOUTS1
INTVCC1
VFB2
RFREQ
39.2k
VIN
4.75V TO 20V
3.3V
VOUTS–
MODE/PLLIN
SGND
VFB1
GND
2.2Ω
CIN3
22µF
CIN4
22µF
VOUT2
RFB2
19.1k
INTVCC2
10k
TRACK/SS1
0.1µF
VOUT1
RFB1
60.4k
DRVCC INTVCC
VRNG1
VIN1 VIN2 CPWR
RUN1
RUN2
121k
68pF
4.7µF
131k
60.4k
470pF
10k
PGOOD1
PGOOD2
TRACK/SS2
VOUT1
LTM4642
VOUT2
0.9V AT 4A LOAD
COUT4
47µF
3.3V AT 4A LOAD
+
COUT6
47µF
FREQ
COUT6
100µF
VOUTS1
INTVCC2
RFREQ1
39.2k
VOUTS–
MODE/PLLIN
VFB2
SGND
GND
VFB1
470pF
RFB3
121k
68pF
VOUT1
RFB2
13.3k
VOUT2
4642 F28
PINS NOT USED: COMP1, COMP2, PHASEMD, CLKOUT, EXTVCC, SW1, SW2
Figure 28. 1MHz 4-Phase, Four Outputs (3.3V, 2.5V, 1.2V, 0.9V) with Tracking to the 3.3V Output
26
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For more information www.linear.com/LTM4642
LTM4642
TYPICAL applications
VIN
4.75V TO 20V
2.2Ω
CIN1
22µF
CIN2
22µF
131k
DRVCC INTVCC
VRNG1
VIN1 VIN2 CPWR
RUN1
RUN2
0.1µF
INTVCC
4.7µF
TRACK/SS1
TRACK/SS2
PGOOD1
PGOOD2
PGOOD1
COMP1
COMP2
INTVCC
RFREQ
39.2k
1MHz
LTM4642
VOUT1
FREQ
VOUT2
VOUTS1
MODE/PLLIN
VOUTS–
VFB2
10k
3.3V AT 8A
COUT1
47µF
COUT2
47µF
INTVCC
68pF
SGND
GND
VFB1
RFB1
13.3k
4642 F29
PINS NOT USED: PHASEMD, CLKOUT, EXTVCC, SW1, SW2
Figure 29. Output Paralleled LTM4642 Module for 3.3V at 8A Each
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For more information www.linear.com/LTM4642
27
LTM4642
TYPICAL applications
VIN
3.3V
5V BIAS
(~30mA)
CIN1
22µF
CIN2
22µF
2.2Ω
4.7µF
100k
RUN2
PGOOD1
TRACK/SS1
0.1µF
0.1µF
3.3V
DRVCC INTVCC
VRNG1
VIN1 VIN2 CPWR
RUN1
PGOOD1
INTVCC
PGOOD2
TRACK/SS2
VOUT1
LTM4642
VOUT2
PGOOD1
MODE/PLLIN
10k
PGOOD2
VOUT1 1V AT 4A LOAD
COUT1
47µF
VOUT2 1.8V AT 4A LOAD
COUT3
47µF
FREQ
INTVCC
10k
+
+
COUT4
100µF
COUT2
150µF
15mΩ SANYO
POSCAP
VOUTS1
VOUTS–
RFREQ
66.5k
600kHz
VFB2
SGND
GND
VFB1
470pF
RFB1
90.9k
470pF
VOUT1
RFB2
30.2k
VOUT2
4642 F30
PINS USED: COMP1, COMP2, PHASEMD, CLKOUT, EXTVCC, SW1, SW2
Figure 30. 3.3V Input to 1V and 1.8V at 4A Each, 1V Sequencing 1.8V Using PGOOD1 to Enable RUN2
28
4642fb
For more information www.linear.com/LTM4642
LTM4642
Package Description
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Table 5. Pin Assignment
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
A1
VOUT2
B1
VOUT2
C1
VOUT2
D1
GND
E1
GND
F1
VOUT1
A2
VOUT2
B2
VOUT2
C2
GND
D2
SGND
E2
SGND
F2
VOUTS1
A3
SW2
B3
RUN2
C3
MODE/PLLIN
D3
COMP2
E3
COMP1
F3
VOUTS–
A4
GND
B4
PHASMD
C4
VFB2
D4
CLKOUT
E4
FREQ
F4
VFB1
A5
GND
B5
VIN2
C5
TRACK/SS2
D5
GND
E5
GND
F5
TRACK/SS1
A6
GND
B6
VIN2
C6
PGOOD2
D6
EXTVCC
E6
DVRCC
F6
PGOOD1
A7
GND
B7
VIN2
C7
CPWR
D7
INTVCC
E7
GND
F7
GND
PIN ID
FUNCTION
PIN ID
FUNCTION
G1
VOUT1
H1
VOUT1
G2
VOUT1
H2
VOUT1
G3
RUN1
H3
SW1
G4
VRNG1
H4
GND
G5
VIN1
H5
GND
G6
VIN1
H6
GND
G7
VIN1
H7
GND
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For more information www.linear.com/LTM4642
29
4
For more information www.linear.com/LTM4642
E
SUGGESTED PCB LAYOUT
TOP VIEW
2.540
PACKAGE TOP VIEW
1.270
PIN “A1”
CORNER
0.3175
0.000
0.3175
aaa Z
1.270
Y
4.445
3.175
1.905
0.635
0.000
0.635
1.905
3.175
4.445
D
X
4.7625
4.1275
aaa Z
3.95 – 4.05
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
aaa
bbb
ccc
ddd
eee
NOM
4.92
0.60
4.32
0.75
0.63
11.25
9.0
1.27
8.89
7.62
DIMENSIONS
0.15
0.10
0.20
0.30
0.15
MAX
5.12
0.70
4.42
0.90
0.66
NOTES
DETAIL B
PACKAGE SIDE VIEW
TOTAL NUMBER OF BALLS: 56
MIN
4.72
0.50
4.22
0.60
0.60
DETAIL A
b1
0.27 – 0.37
SUBSTRATE
ddd M Z X Y
eee M Z
DETAIL B
MOLD
CAP
ccc Z
A1
A2
A
Z
(Reference LTC DWG# 05-08-1961 Rev Ø)
Øb (56 PLACES)
// bbb Z
30
2.540
b
3
F
e
SEE NOTES
7
5
4
3
2
1
DETAIL A
PACKAGE BOTTOM VIEW
6
G
H
G
F
E
D
C
B
A
PIN 1
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
BALL DESIGNATION PER JESD MS-028 AND JEP95
7
TRAY PIN 1
BEVEL
!
BGA 56 1113 REV Ø
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
7
SEE NOTES
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN “A1”
BGA Package
56-Lead (11.25mm × 9.00mm × 4.92mm)
LTM4642
Package Description
Please refer to http://www.linear.com/product/LTM4642#packaging for the most recent package drawings.
4642fb
3.810
3.810
LTM4642
Revision History
REV
DATE
DESCRIPTION
A
12/16
Absolute Maximum Rating VFB1, VFB2 changed to INTVCC to 0.3V
PAGE NUMBER
2
B
6/17
Twelve phases can be paralleled with no more than two phases per regulator output
13
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTM4642
31
LTM4642
Package Photograph
Design Resources
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
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32
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LT 0617 Rev B • PRINTED IN USA
www.linear.com/LTM4642
For more information www.linear.com/LTM4642
 LINEAR TECHNOLOGY CORPORATION 2016