Fairchild ML4425IP Sensorless bldc motor controller Datasheet

www.fairchildsemi.com
ML4425
Sensorless BLDC Motor Controller
Features
General Description
•
•
•
•
The ML4425 PWM motor controller provides all of the
functions necessary for starting and controlling the speed of
delta or wye wound Brushless DC (BLDC) motors without
Hall Effect sensors. Back EMF voltage is sensed from the
motor windings to determine the proper commutation phase
sequence using a PLL. This patented sensing technique will
commutate a wide range of 3-Phase BLDC motors and is
insensitive to PWM noise and motor snubbing circuitry.
•
•
•
•
Stand-alone operation
Motor starts and stops with power to IC
On-board start sequence: Align ♦ Ramp ♦ Set Speed
Patented Back-EMF commutation technique provides
jitterless torque for minimum “spin-up” time
Onboard speed control loop
PLL used for commutation provides noise immunity from
PWM spikes, compared to noise sensitive zero crossing
technique
PWM control for maximum efficiency
Direct FET drive for 12V motors; drives high voltage
motors with IC buffers
The ML4425 limits the motor current using a constant offtime PWM control loop. The velocity loop is controlled with
an onboard amplifier. The ML4425 has circuitry to ensure
that there is no shoot-through in directly driven external
power MOSFETs.
The timing of the start-up sequence is determined by the
selection of three timing capacitors. This allows optimization
for a wide range of motors and loads.
Block Diagram
17
VDD
VDD
CAT
21
CRT
20
750nA
15
16
SPEED CVCO
FB
CRR
750nA
RVCO
–
–
FB A
+
1.5V
+
1.5V
22
19
VDD
FB B
23
FB C
24
500nA
BACK
EMF
SAMPLER
VCO/TACH
VOLTAGE
CONTROLLED
OSCILLATOR
13
VCO
OUT
VCO
OUT
R
A
F
B
+
COMMUTATION
STATE MACHINE
–
8
E
3.9V
SPEED SET
HA
C
D
5
HB
–
SPEED COMP
1.7V
–
CT
×5
6
20kHz
ISENSE
1.7V
–
VREF
+
1.4V
ILIMIT
1-SHOT
+
HC
LA
LB
LC
UVLO
VDD
16kΩ
UV FAULT
1
4kΩ
ILIMIT
12
GATING
LOGIC
&
OUTPUT
DRIVERS
+
2
3
4
9
10
11
18
REFERENCE
8kΩ
CIOS
26
VDD
BRAKE
25
14
GND
28
RREF
27
VREF
7
REV. 1.0.2 7/2/01
ML4425
PRODUCT SPECIFICATION
Pin Configuration
ML4425
28-Pin Narrow PDIP (P28N)
28-Pin SOIC (S28)
ISENSE
1
28
GND
HA
2
27
RREF
HB
3
26
CIOS
HC
4
25
BRAKE
SPEED COMP
5
24
FB C
CT
6
23
FB B
VREF
7
22
FB A
SPEED SET
8
21
CRR
LA
9
20
SPEED FB
LB 10
19
CRT
LC 11
18
UV FAULT
ILIMIT 12
17
CAT
VCO/TACH 13
16
RVCO
VDD 14
15
CVCO
TOP VIEW
Pin Description
2
Pin
1
Name
ISENSE
2
3
4
5
6
HA
HB
HC
SPEED
COMP
CT
8
9
10
11
12
VREF
SPEED SET
LA
LB
LC
ILIMIT
13
VCO/TACH
14
15
VDD
CVCO
Function
Motor current sense input. When ISENSE exceeds 0.2 ↔ ILIMIT, the output drivers LA,
LB, and LC are shut off for a fixed time determined by CIOS.
Active low output driver for the phase A high-side switch.
Active low output driver for the phase B high-side switch.
Active low output driver for the phase C high-side switch.
Speed control loop compensation is set by a series resistor and capacitor from
SPEED COMP to GND.
A capacitor from CT to GND sets the PWM oscillator frequency.
6.9V reference voltage output.
Speed loop input which ranges from 0 (stopped) to VREF (maximum speed).
Active high output driver for the phase A low-side switch.
Active high output driver for the phase B low-side switch.
Active high output driver for the phase C low-side switch.
Voltage on this pin sets the ISENSE threshold voltage at 0.2 ↔ ILIMIT, leaving this pin
unconnected selects an internally set threshold.
This TTL level output corresponds to the signal used to clock the commutation state
machine. The output frequency is proportional to the motor speed when the backEMF sensing loop is locked onto the rotor position.
12V power supply input.
A capacitor to GND sets the voltage-to-frequency ratio of the VCO.
REV. 1.0.2 7/2/01
PRODUCT SPECIFICATION
Pin Description
ML4425
(continued)
Pin
16
17
18
Name
RVCO
CAT
UV FAULT
19
20
CRT
SPEED FB
21
CRR
22
FB A
23
FB B
24
FB C
25
BRAKE
26
CIOS
27
RREF
28
GND
Function
An resistor to GND sets up a current proportional to the input voltage of the VCO.
A capacitor to GND sets the time that the controller stays in the align mode.
This output goes low when VDD drops below the UVLO threshold, and indicates that
all output drivers have been disabled.
A capacitor to GND sets the time that the controller stays in the ramp mode.
Output of the back-EMF sampling circuit and input to the VCO. An RC network
connected to SPEED FB sets the compensation for the PLL loop formed by the
back-EMF sampling circuit, the VCO, and the commutation state machine.
A capacitor to between CRR and SPEED FB sets the ramp rate (acceleration) of the
motor when the controller is in ramp mode.
The motor feedback voltage from phase A is monitored through a resistor divider for
back-EMF sensing at this pin.
The motor feedback voltage from phase B is monitored through a resistor divider for
back-EMF sensing at this pin.
The motor feedback voltage from phase C is monitored through a resistor divider for
back-EMF sensing at this pin.
A logic low input activates motor braking by shutting off the high-side output drivers
and turning on the low-side output drivers.
A capacitor to GND sets the time that the low-side output drivers remain off after
ISENSE exceeds its threshold .
An 137kΩ resistor to GND sets a current proportional to VREF that is used to set all
the internal bias currents except for the VCO.
Signal and power ground.
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum
ratings are stress ratings only and functional device operation is not implied.
Parameter
Min.
VDD
Max.
Units
14
V
Logic Inputs (SPEED FB, BRAKE)
GND – 0.3
7
V
All Other Inputs and Outputs
GND – 0.3
VDD + 0.3
V
Output Current (LA, LB, LC, HA, HB, HC)
±50
mA
Junction Temperature
150
°C
150
°C
Lead Temperature (Soldering 10 sec.)
260
°C
Thermal Resistance (θJA)
28-Pin Narrow PDIP
28-Pin SOIC
48
75
°C/W
°C/W
Storage Temperature Range
-65
Operating Conditions
Parameter
Min.
Max.
Units
Temperature Range
ML4425CX
ML4425IX
0
–40
70
85
°C
°C
VDD
10.8
13.2
V
REV. 1.0.2 7/2/01
3
ML4425
PRODUCT SPECIFICATION
Electrical Characteristics
Unless otherwise specified, VDD = 12V ± 10%, RSENSE = 1Ω, CVCO = 10nF, CIOS = 100pF, RREF = 137kΩ,
TA = Operating Temperature Range (Notes 1, 2).
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
6.5
6.9
7.5
V
Reference
VREF
Total Variation
Line, Temp
PWM Oscillator
Total Variation
CT = 1nF
28
kHz
Ramp Peak
3.9
V
Ramp Valley
1.7
V
Ramp Charging Current
µA
Speed Control Loop
SPEED SET Input Voltage
Range
0
VREF
V
SPEED FB Input Voltage Range
0
VREF
V
SPEED COMP Output Current
±5
±20
µA
VSPEED SET = xV,
VSPEED FB = yV
144
µ
Ω
SPEED SET Error Amp
Transconductance
Start-up
CAT Charging Current
C Suffix
0.68
0.98
µA
I Suffix
0.5
1.1
µA
1.4
1.7
V
C Suffix
0.68
0.98
µA
I Suffix
0.5
1.1
µA
1.4
1.7
V
CAT Threshold Voltage
CRT Charging Current
CRT Threshold Voltage
Voltage Controlled Oscillator
Frequency Range
RVCO = 5V, SPEED FB = 6V
Frequency vs. SPEED FB
RVCO = 5V, 0.5V ≤ SPEED FB ≤
7V
1.5
1.85
2.2
300
kHz
Hz/V
Current Limit
ISENSE Gain
V(ILIMIT) ≤ 2.5V
One Shot OFF-Time
CIOS = 100pF
4.5
5.0
5.5
V/V
C Suffix
9
18
µs
I Suffix
9
20
µs
0.8
V
Logic Inputs (BRAKE) (Note 3)
4
VIH
Input High Voltage
VIL
Input Low Voltage
2
V
IIH
Input High Current
VIH = 2.4V
2.4
mA
IIL
Input Low Current
VIL = 0.4V
2.9
mA
REV. 1.0.2 7/2/01
PRODUCT SPECIFICATION
ML4425
Electrical Characteristics (continued)
Unless otherwise specified, VDD = 12V ± 10%, RSENSE = 1Ω, CVCO = 10nF, CIOS = 100pF, RREF = 137kΩ,
TA = Operating Temperature Range (Notes 1, 2).
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Logic Outputs (VCO/TACH, UV FAULT) (Note 3)
VCO/TACH Output High Voltage IOUT = –100µA
VCO/TACH Output Low Voltage
IOUT = 400µA
UV FAULT Output High Voltage
IOUT = –10µA
UV FAULT Output Low Voltage
2.2
C Suffix
3.4
I Suffix
3.2
V
4.5
IOUT = 400µA
0.6
V
5.4
V
5.6
V
0.6
V
250
mV
Back-EMF Sampler
SPEED FB Align Mode Voltage
125
SPEED FB Ramp Mode Current
SPEED FB Run Mode Current
State A, CRT = 5V,
VPHB = VDD/3
C Suffix
500
720
nA
I Suffix
500
750
nA
C Suffix
30
90
µA
I Suffix
27
90
µA
State A, CRT = 5V, VPHB = VDD/2
–15
15
µA
State A, CRT = 5V,
VPHB = 2↔VDD/3
C Suffix
–90
–30
µA
I Suffix
–90
–27
µA
0.5
1.2
mA
Output Drivers
High Side Driver Output Low
Current
VHX = 2V
High Side Driver Output High
Voltage
IHX = –10µA
Low Side Driver Output Low
Voltage
ILX = 1mA
Low Side Driver Output High
Voltage
V(ISENSE) = 0V
VCC – 1.3
V
0.2
0.7
V
C Suffix VDD – 2.2
V
I Suffix
V
VDD – 2.9
Phase C Cross-conduction
Lockout Threshold
VDD – 3.0
V
Supply
IDD
VDD Current
UVLO Threshold
C Suffix
8.8
I Suffix
8.6
UVLO Hysteresis
32
50
mA
9.5
10.2
V
10.3
V
150
mV
Notes:
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
2. For explanation of states, see Figure 4 and Table 1.
3. The BRAKE and UV FAULT pins each have an internal 4kΩ resistor to the internal reference.
REV. 1.0.2 7/2/01
5
ML4425
Functional Description
General
The ML4425 provides all the circuitry for sensorless speed
control of 3-phase Brushless DC (BLDC) motors. Controller
functions include start-up circuitry, back-EMF commutation
control, Pulse Width Modulation (PWM) speed control,
fixed OFF-time current limiting, braking, and undervoltage
protection.
The start-up circuitry aligns the motor to a known position,
then ramps up the motor speed to generate a back-EMF
signal. A back-EMF sampling circuit controls commutation
timing by forming a Phase Locked Loop (PLL). The commutation control circuitry also outputs a speed feedback
(SPEED FB) signal used in the speed control loop. The
speed control loop consists of an error amplifier and PWM
comparator that produce a PWM duty cycle for speed regulation. Motor current is limited by a fixed OFF-time PWM
shutdown comparator that is controlled by an external sense
resistor. Commutation control, PWM speed control, and
current limiting are combined to produce the output driver
signals. Six output drivers are used to provide gating signals
to an external 3 phase bridge power stage sized for the
BLDC motor voltage and current requirements. Additional
functions include a braking function and undervoltage
protection circuit to shut down the output drivers in the event
of a low voltage condition on VDD of the ML4425.
Component Selection
Selecting external components for the ML4425 requires
calculations based on the motor’s electrical and mechanical
parameters. The following is a list of the motor parameters
needed for these calculations :
•
•
•
•
•
•
•
•
6
DC motor supply voltage – VMOTOR (V)
Maximum operating current – IMAX (A)
Number of magnetic poles – N
Back EMF constant – Ke (V-s/Rad)
Motor torque constant – Kt (Nm/A) (Kt = Ke in SI units)
Maximum speed of operation RPMMAX (RPM)
Moment of inertia of the motor and load – J (Kg-m2)
Viscous damping factor of the motor and load – ζ
PRODUCT SPECIFICATION
If one or more of the above values is not known, it is still
possible to pick components for the ML4425, but some
experimentation may be necessary to determine the optimal
values. All quantities are in SI units unless otherwise specified. The following formulas should be considered as a starting point for optimization. All calculations for capacitors and
resistors should be used as the first approximation for selecting the closest standard value.
Power Supply and Reference
The supply voltage (VDD) is nominally 12V ±10%. A 100nF
bypass capacitor to ground should be placed as close as possible to VDD. A 6.9V voltage reference output (VREF) is provided to set the speed command and current limit of the
ML4425. A 137kΩ from RREF to GND is required to set up a
reference current for internal functions.
Output Drivers
The output drivers LA, LB, LC, HA, HB, and HC provide
totem pole output drive signals for a 3 phase bridge power
stage. All control functions in the ML4425 translate to outputs at these pins. LA, LB, and LC provide the low-side
drive signals for phases A, B, and C of the 3 phase power
stage and are 12V active high signals. HA, HB, and HC
provide the high-side signals and are 12V active low signals.
VMOTOR
12V
DC SUPPLY
CAPACITOR
HA
HB
HC
MOTOR
PHASE A
LA
LB
MOTOR
PHASE B
MOTOR
PHASE C
LC
RSENSE
Figure 1. Using RSENSE in a 3-Phase 12V Power Stage
REV. 1.0.2 7/2/01
PRODUCT SPECIFICATION
ML4425
Current Limiting in the Power Stage
The current sense resistor (RSENSE) shown in Figure 1 regulates the maximum current in the power stage and the BLDC
motor. Current regulation is accomplished by shutting off the
output drivers LA, LB, and LC for a fixed amount of time if
the voltage across RSENSE exceeds the current limit threshold.
ILIMIT
The voltage on the ILIMIT pin sets the current limit threshold.
The ML4425 has an internal voltage divider from VREF that
sets a default current limit threshold of 2.3V (see Figure 2).
An external voltage divider referenced to VREF can be used
to override the default ILIMIT setting. The external divider
should have at least 10 times the current flow of the internal
divider.
starting values for this circuit are R = 1kΩ and C = 330pF.
This gives a time constant of 330ns, and will filter out spikes
of shorter duration. C can be increased to as much as 2.2nF,
but should not exceed a time constant of more than a few
microseconds.
CIOS
When ISENSE exceeds 0.2 ↔ ILIMIT, the current limit oneshot is activated, turning off LA, LB, and LC for a fixed
amount of time (tOFF). tOFF is set by the amount of capacitance connected to CIOS. CIOS is usually set for a fixed off
time equal to or less than the PWM period. For a 25kHz
PWM frequency, the PWM period is 40µs; tOFF should be
between 20µs and 40µs. The lower limit of tOFF is dictated
by the minimum on time of the power stage; a safe approximation is 5µs or less. The equation for finding the CIOS
capacitance value is as follows:
RSENSE
The function of RSENSE is to provide a voltage proportional
to the motor current to set the current limit trip point. The
default trip voltage across RSENSE is 460mV, set by the
internal ILIMIT divider ratio. The current sense resistor
should be a low inductance resistor such as a carbon composition. For resistors in the milliohms range, wire-wound
resistors tend to have low values of inductance. RSENSE
should be sized to handle the power dissipation (IMAX2 ↔
RSENSE).
ISENSE Filter
The ISENSE RC lowpass filter is placed in series with the current sense signal as shown in Figure 2. The purpose of this
filter is to remove the diode reverse recovery shootthrough
current. This current causes a voltage spike on the leading
edge of the current sense signal which may falsely trigger the
current limit. The current sense voltage waveform is shown
before and after filtering in Figure 3. The recommended
FROM
RSENSE
t OFF × 50µA
C OS = -------------------------------2.4V
(1)
Commutation Control
A 3-phase BLDC motor requires electronic commutation to
achieve rotational motion. Electronic commutation requires
the switching on and off of the power switches of a 3-phase
half bridge. For torque production to be achieved in one
direction, the commutation is dictated by the rotor position.
Electronic commutation in the ML4425 is achieved by turning on and off, in the proper sequence, one N output from
one phase and one P output from another phase. There are
six combinations of N and P outputs (six switching states)
that constitute a full commutation cycle. These combinations
are illustrated in Table 1 and Figure 4, and are labeled states
A through F. This sequence is programmed into the commutation state machine. Clocking of the commutation state
machine is provided by a voltage controlled oscillator
(VCO).
PWM
ON/OFF
ISENSE
×5
–
+
VREF
VREF
S
Q
R
Q
16kΩ
ILIMIT
2.9V
8kΩ
0V
STOP
START
460mV
30µA
CIOS
0V
(a)
Figure 2. Current Sense Circuitry
REV. 1.0.2 7/2/01
(b)
Figure 3. Current Sense Resistor Waveforms
(a) Without Filtering, and (b) With Filtering
7
ML4425
PRODUCT SPECIFICATION
Outputs
LA
LB
LC
HA
HB
HC
Input
Sampling
R
OFF
ON
OFF
ON
OFF
ON
N/A
A
OFF
OFF
ON
ON
OFF
OFF
FB B
State
B
OFF
OFF
ON
OFF
ON
OFF
FB A
C
ON
OFF
OFF
OFF
ON
OFF
FB C
D
ON
OFF
OFF
OFF
OFF
ON
FB B
E
OFF
ON
OFF
OFF
OFF
ON
FB A
F
OFF
ON
OFF
ON
OFF
OFF
FB C
Table 1. Commutation State Functions
A
B
C
D
E
F
A
B
C
D
E
F
HA
HIGH
SIDE
DRIVE
OUTPUTS
HB
HC
LA
LOW
SIDE
DRIVE
OUTPUTS
LB
LC
Figure 4. Output Commutation Sequence Timing Diagram
Cycle 1 – Full Commutation, Cycle 2 – Commutation with 50% PWM Duty Cycle
Voltage Controlled Oscillator (VCO)
The VCO provides a TTL compatible clock output on the
VCO/TACH pin proportional to the VCO input voltage at the
SPEED FB pin. The proportion of frequency to voltage
(VCO constant, Kv) is set by an 80.6kΩ resistor on RVCO
and a capacitor on CVCO as shown in Figure 5. RVCO sets up
a current proportional the VCO input voltage at SPEED FB.
This current is used to charge and discharge CVCO between
the threshold voltages of 2.3V and 4.3V. The resulting triangle wave on CVCO corresponds to the clock on VCO. Kv
should be set so that the VCO output frequency corresponds
8
to the maximum commutation frequency or maximum motor
speed when the VCO input is equal to or slightly less than
VREF. CVCO is calculated using the following equation:
C VCO
– 6 Hz • Farad
6.5V × 3.101 × 10 -----------------------------V
= ----------------------------------------------------------------------------------Hz
0.05 -------------- × N × SPEED MAX
RPM
(2)
The closest standard value that is equal to or less than the
calculated CVCO should be used.
REV. 1.0.2 7/2/01
PRODUCT SPECIFICATION
ML4425
The maximum frequency on the VCO pin is found by:
f MAX = 0.05 × N × RPM MAX
(3)
CVCO
The voltage at the VCO/TACH pin is equal to the rotor
speed. The voltage at SPEED FB is controlled by the back
EMF sampler.
RVCO
SPEED CVCO
FB
Back EMF Sampler
The input to the voltage controlled oscillator is the back
EMF sampler. The back EMF sense pins FB A, FB B, and
FB C inputs to the back EMF sampler require a signal from
the motor phase leads that is below the VDD of the ML4425.
The phase sense input impedance is 8kΩ. This requires a
series resistor RES1 from the motor phase lead as shown in
Figure 6 based on the following equation:
FROM
BACK EMF
SAMPLER
& RAMP
GENERATOR
RESET
(FROM CAT)
RVCO
VOLTAGE
CONTROLLED
OSCILLATOR
VCO/TACH
4.3V
CVCO
2.3V
RES1 = 670Ω ⁄ V × ( V MOTOR – 10V )
(4)
5V
The back EMF sampler takes the motor phase voltages
divided down to signals that are less than VDD (12V nominal) and calculates the neutral point of the motor by the following equation:
PH1 + PH2 + PH3
Neutral = ------------------------------------------------3
(5)
This allows the ML4425 to compare the back EMF signal to
the motor’s neutral point without the need for bringing out an
extra wire on a WYE wound motor. For DELTA wound
motors there is no physical neutral to bring out, so this reference point must be calculated in any case.
MOTOR ΦA
MOTOR ΦB
MOTOR ΦC
VCO/TACH
0V
Figure 5. External VCO Component Connections
The back EMF sampler measures the motor phase that is not
driven (i.e. if LA and HB are on, then phase A is driven low,
phase B is driven high, and phase C is sampled). The sampled phase provides a back EMF signal that is compared
against the neutral of the motor. The sampler is controlled by
the commutation state machine. The sampled back EMF is
compared to the neutral through an error amplifier. The output of the error amplifier outputs a charging or discharging
current to SPEED FB, which provides the control voltage to
the VCO.
RES1
FB A
RES2
FB B
NEUTRAL
SIMULATOR
RES3
FB C
ΦA + ΦB + ΦC
6
4kΩ
4kΩ
gm =
SIGN
CHANGER
4kΩ
+
–
1
8kΩ
TO
SPEED FB
MULTIPLEXER
4kΩ
4kΩ
4kΩ
F/R
F/R
COMMUTATION
STATE MACHINE
Figure 6. Back EMF Sampler Detailed Block Diagram
REV. 1.0.2 7/2/01
9
ML4425
PRODUCT SPECIFICATION
Back EMF Sensing PLL Commutation Control
Three blocks form a phase locked loop that locks the commutation clock onto the back EMF signal: the commutation
state machine, the voltage controlled oscillator, and the back
EMF sampler. The complete phase locked loop is illustrated
in Figure 7. The phased locked loop requires a lead lag filter
that is set by external components on SPEED FB. The components are selected as follows:
CSPEEDFB1
CSPEEDFB2
20
SPEED
FB
FB A
VDD
22
C SPEEDFB1


2
K O1 
NS

-
= 0.25 × ---------- ×  -----------------------------------------------d 2
M    --------2 
  In  100- × f VCO 
f VCO
d
R SPEEDFB = 2 × M × In  ---------- × ------------------------------------------------- 100 N S × K O1 × ( 1 – M )
RSPEEDFB
FB B
23
(6a)
FB C
24
500nA
BACK
EMF
SAMPLER
VOLTAGE
CONTROLLED
OSCILLATOR
VCO/TACH
13
(6b
R
A
C SPEEDFB2 = C SPEEDFB1 × ( M – 1 )
(6c)
F
B
E
PHASE
LOCKED
LOOP
C
D
Start-Up Sequence
When power is first applied to the ML4425 and the motor is
at rest, the back EMF is equal to zero. The motor needs to be
rotating for the back EMF sampler to lock onto the rotor
position and commutate the motor. The ML4425 uses an
open loop start-up technique to bring the rotor from rest up
to a speed fast enough to allow back EMF sensing. Start-up
is comprised of three modes: align mode, ramp mode, and
run mode.
Align Mode (RESET)
Before the motor can be started, the rotor must be in a known
position. When power is first applied to the ML4425, the
controller is reset into the align mode. Align mode turns on
the output drivers LB, HA, and HC which aligns the motor
into a position 30 electrical degrees before the center of the
first commutation state. This is shown as state R in the commutation states of Table 1. Align mode must last long enough
to allow the motor and its load to settle into this position. The
align mode time is set by a capacitor connected to the CAT
pin as shown in Figure 8. CAT is charged by a constant
750µA current from GND to 1.5 V until the align comparator
trips to end the align mode. A starting point for CAT is calculated as follows:
–7
t S × 7.5 × 10 × amp
C AT = ------------------------------------------------------1.5V
(7)
If the align time is not long enough to allow the rotor to settle
for reliable starting, then increase CAT until the desired performance is achieved.
10
COMMUTATION
STATE MACHINE
Figure 7. Back EMF Commutation Phase Locked Loop
Ramp Mode
At the end of align mode the controller goes into ramp mode.
Ramp mode starts commutating through the states A through
F as shown in Table 1. This ramps up the commutation frequency, and therefore the motor speed, for a fixed length of
time. This allows the motor to reach a sufficient speed for the
back EMF sampler to lock commutation onto the motor’s
back EMF. The amount of time the ML4425 stays in ramp
mode is determined by a capacitor connected to the CRT pin
as shown in Figure 8. CRT is charged by a constant 750µA
current from GND to 1.5 V until the ramp comparator trips
to end the ramp mode. This gives a fixed ramp time. CRT is
calculated as follows:
–7
2π × J × 5 × 10 × amp × K
C RT = ---------------------------------------------------------------------------VI MAX × K t × 3 × N
(8)
The rate at which the ML4425 ramps up the motor speed is
determined by a fixed 500µA current source on the SPEED
FB pin. The current sources charges up the PLL filter components causing the VCO frequency to ramp up. During
ramp mode, the back EMF sampler is disabled to allow control of the ramping to be set only by the 500µA current
source. The ramp based on the SPEED FB filter is generally
too fast for the motor to keep up, so a capacitor from CRR to
SPEED FB can be added to slow down the ramping rate. The
optimal ramp rate is based on the motor and load parameters
and is can be adjusted by varying the value of CRR.
REV. 1.0.2 7/2/01
PRODUCT SPECIFICATION
ML4425
CRR
CAT
VDD
CRT
VDD
CAT
FB B
FB C
SPEED CVCO
FB
RVCO
–
–
1.5V
FB A
CRR
CRT
750nA
750nA
TO
SPEED FB
FILTER
+
1.5V
+
VDD
500nA
BACK
EMF
SAMPLER
VCO/TACH
VOLTAGE
CONTROLLED
OSCILLATOR
TO RESET INPUT
OF COMMUTATION
STATE MACHINE
Figure 8. ML4425 Start-up Circuitry for Controlling the Align and Ramp Times
Run Mode (Back EMF Sensing)
At the end of ramp mode the controller goes into run mode.
In run mode, the back EMF sensing is enabled and commutation is now under the control of the phase locked loop. Motor
speed is now regulated by the speed control loop.
FROM
SPEED FB
TO
GATING
LOGIC &
OUTPUT
DRIVERS
VREF
+
PWM Speed Control
10kΩ
Speed control is accomplished by setting a speed command
at SPEED SET with an input voltage from 0 to 6.9V (VREF).
The accuracy of the speed command is determined by the
external components RVCO and CVCO. There are a number of
methods that can be used to control the speed command of
the ML4425. One is to use a 10kΩ potentiometer from VREF
to ground with the wiper connected to SPEED SET. If
SPEED SET is controlled from a microcontroller, one of its
DACs can be used with VREF as its input reference.
–
3.9V
SPEED SET
–
SPEED COMP
RSC
+
1.7V
CSC
CT
CT
20kHz
1.7V
PWM ON/OFF
FROM ILIMIT
ONE-SHOT
Figure 9. Speed Control Loop Component Connections
The speed command is compared with the sensed speed from
SPEED FB through a transconductance error amplifier. The
output of the speed error amplifier is SPEED COMP. SPEED
COMP is clamped between one diode drop above 3.9V
(approximately 4.6V) and one diode drop below 1.7V
(approximately 1V) to prevent speed loop “wind-up”. Speed
loop compensation components are connected to this pin as
shown in Figure 9. The speed loop compensation components are calculated as follows:
26.9 × N × V MOTOR × C VCO
C SC = -----------------------------------------------------------------------------------------2
f SB × K e 2.5 + 98.696 × τm × f SB2
10
R SC = --------------------------------------2π × f SB × C SC
The voltage on SPEED COMP is compared with a ramp
oscillator to create a PWM duty cycle. The PWM ramp oscillator creates a sawtooth function from 1.7V to 3.9V as shown
in Figure 9. A negative clamp at one diode drop below 1.7V
(approximately 1V) starts the oscillator on power up. The
frequency of the ramp oscillator is set by a capacitor to
ground CIOS and is selected using the following equation:
CT
(9a)
(9b)
I
-------------- × 50µA
f PWM
= ----------------------------------2.4V
(10)
Where fPWM is the PWM frequency in Hz. The PWM duty
cycle from the speed control loop is gated the current limit
one shot that controls the LA, LB, and LC output drivers.
Where fSB is the speed loop bandwidth in Hz.
REV. 1.0.2 7/2/01
11
ML4425
Cross Conduction Comparator
When the ML4425 goes from align mode into ramp mode,
there is a possibility of cross conduction in phase 3 of the
bridge power stage. This cross conduction can happen when
HC is on in the align mode shown as state R in Table 1, and
the controller transitions to state A in ramp mode where HC
is turned off and LC is turned on. Cross conduction can
appear due to the differences in turn on and turn off times of
the power devices. To solve this problem, the LC output
driver is gated off until the HC is equal to VDD – 3V as
shown in Figure 10.
Braking
When the BRAKE pin is pulled below 1.4V, the low side
output drivers LA, LB, and LC are turned on and the high
side output drivers HA, HB, HC are turned off. Braking
causes rapid deceleration of the motor and current limiting is
de-activated, and care should be taken when using the
BRAKE pin. BRAKE is has an internal 4kΩ pull-up as
shown in Figure 10, and can be driven by a switch to ground,
an open collector or drain logic signal, or a TTL logic signal.
PRODUCT SPECIFICATION
The most flexible configuration is to use high side drivers to
control N-Channel MOSFETs (or IGBTs) which allows
applications from less than 12V up to 600V. Figure 12 shows
the interface between the ML4425 and IR2118 high side
drivers from International Rectifier. This configuration is
capable of driving motors from busses of up to 320V. The
BRAKE pin can be pulsed prior to startup with an RC
circuit. This charges the bootstrap capacitors (C19, C20, and
C21) for the three high side drivers, allowing the reset phase
to operate normally. These capacitors must be sized so that
they stay sufficiently charged during the align mode. Refer to
AN-43 for additional applications information on the
ML4425.
FROM
COMMUTATION
STATE MACHINE
Design Considerations
HB
GATING
LOGIC
&
OUTPUT
DRIVERS
–
+
1.4V
Undervoltage Lockout
Undervoltage lockout is used to protect the 3-phase bridge
power stage from a low VDD condition. Undervoltage is triggered at VDD of 9.5V or less and is indicated by a TTL low
output on the UV FAULT pin. Undervoltage lockout also
turns off all output drivers (LA, LB, LC, HA, HB, and HC).
The comparator that triggers undervoltage lockout has
150mV of hystresis.
HA
FROM
SPEED CONTROL LOOP
& CURRENT LIMIT
9.5V
HC
LA
LB
+
LC
–
2
3
4
9
10
11
VDD
UV FAULT
4kΩ
18
REFERENCE
VDD
BRAKE
25
14
GND
28
RREF
27
VREF
7
Figure 10. Cross Conduction, Brake, and UVLO Circuits
Interfacing to a 3-Phase Bridge Power Stage
The ML4425 output drivers are configured to drive a 3 phase
bridge power stage. For applications with buss voltages from
12V up to 80V, level shifting circuitry can be used to drive
higher voltage P-channel MOSFETS for the high side
switches as shown in Figure 11.
12
REV. 1.0.2 7/2/01
PRODUCT SPECIFICATION
VBUSS
24V–80V
C2
330µF
100V
C1
100nF
100V
ML4425
R2
10kΩ
R3
10kΩ
Q4
FQD8P10
12V
Q1
TN6718A
R4
10kΩ
Q5
FQD8P10
Q6
FQD8P10
Q2
TN6718A
Q3
TN6718A
Q7
IRFR120
Q8
IRFR120
C3
1µF
Q9
IRFR120
MOTOR
R1
470mΩ
2W
R12
2kΩ
R14
2kΩ
R13
2kΩ
R15
1kΩ
C5
2.2nF
ML4425
ISENSE
HA
R20
137kΩ
GND
RREF
HB
CIOS
HC
BRAKE
SPEED COMP
FB C
CT
FB B
VREF
FB A
SPEED SET
CRR
RUN
C16
330pF
S1
R8 (RES1)
R9 (RES1)
R16
10kΩ
C17
1nF
C9
100nF
C12
R18
10kΩ
R21
787Ω
R7
100Ω
LA
SPEED FB
LB
CRT
LC
UV FAULT
ILIMIT
R5
100Ω
R6
100Ω
12V
C14
1µF
R10 (RES1)
C8
1µF
R17
10kΩ
C6
1µF
C7
100nF
CAT
VCO/TACH
RVCO
VDD
CVCO
C13
100nF
BRAKE
C14
C15
470nF
C4
R19
80.5kΩ
Figure 11. Driving Lower Voltage Motors (12 to 80V)
REV. 1.0.2 7/2/01
13
ML4425
PRODUCT SPECIFICATION
12V
IR2118
C16
100nF
25V
VBUSS
24V–80V
C5
330µF
400V
VCC
VB
IN
HO
COM
VS
NC
NC
D1
MUR150
IR2118
C17
100nF
25V
C19
2.2µF
25V
VCC
VB
IN
HO
COM
VS
NC
NC
R6
100Ω
R7
100Ω
R8
100Ω
Q1
FQP4P40
Q3
FQP4P40
Q5
FQP4P40
Q2
FQP5N40
Q4
FQP5N40
D2
MUR150
IR2118
C18
100nF
25V
C20
2.2µF
25V
VCC
VB
IN
HO
COM
VS
NC
NC
D3
MUR150
C21
2.2µF
25V
Q6
FQP5N40
MOTOR
R12
470mΩ
2W
R1
1kΩ
C1
2.2nF
BOOTSTRAP
PRE-CHARGE
CAPACITOR
ML4425
ISENSE
C4
1nF
C3
100nF
C15
100nF
R20
10kΩ
R19
787Ω
R9
100Ω
D6
(3×1N5819)
RREF
HB
CIOS
HC
BRAKE
SPEED COMP
FB C
CT
FB B
VREF
FB A
RUN
C14
330pF
S1
R15 (RES1)
R11
100Ω
12V
C6
1µF
R13 (RES1)
BRAKE
C13*
SPEED SETRAMP COMP
LA
SPEED FB
LB
CRT
LC
UV FAULT
ILIMIT
R10
100Ω
D5
HA
R14 (RES1)
R5
10kΩ
D4
R18
137kΩ
GND
C11
100nF
CAT
VCO/TACH
RVCO
VDD
CVCO
C7
100nF
C10
1µF
R17
10kΩ
C12
1µF
C9
470nF
C8
10nF
R16
80.6kΩ
Figure 12. ML4425 High Voltage Motor Drive Application Circuit
14
REV. 1.0.2 7/2/01
PRODUCT SPECIFICATION
ML4425
Mechanical Dimensions inches (millimeters)
Package: P28N
28-Pin Narrow PDIP
1.355 - 1.365
(34.42 - 34.67)
28
0.280 - 0.296 0.299 - 0.325
(7.11 - 7.52) (7.60 - 8.26)
PIN 1 ID
1
0.045 - 0.055
(1.14 - 1.40)
0.100 BSC
(2.54 BSC)
0.020 MIN
(0.51 MIN)
0.180 MAX
(4.57 MAX)
SEATING PLANE
0.015 - 0.021
(0.38 - 0.53)
0.125 - 0.135
(3.18 - 3.43)
0º - 15º
0.008 - 0.012
(0.20 - 0.31)
Package: S28
28-Pin SOIC
0.699 - 0.713
(17.75 - 18.11)
28
0.291 - 0.301 0.398 - 0.412
(7.39 - 7.65) (10.11 - 10.47)
PIN 1 ID
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.095 - 0.107
(2.41 - 2.72)
0º - 8º
0.090 - 0.094
(2.28 - 2.39)
REV. 1.0.2 7/2/01
0.012 - 0.020
(0.30 - 0.51)
SEATING PLANE 0.005 - 0.013
(0.13 - 0.33)
0.022 - 0.042
(0.56 - 1.07)
0.009 - 0.013
(0.22 - 0.33)
15
ML4425
PRODUCT SPECIFICATION
Ordering Information
Part Number
Temperature Range
Package
ML4425CP
0°C to 70°C
28-Pin PDIP (P28N)
ML4425CS
0°C to 70°C
28-Pin SOIC (S28)
ML4425IP
-40°C to 85°C
28-Pin PDIP (P28N)
ML4425IS
-40°C to 85°C
28-Pin SOIC (S28)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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