AD ADF4111BCPZ-RL7 Rf pll frequency synthesizer Datasheet

RF PLL Frequency Synthesizers
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
FEATURES
GENERAL DESCRIPTION
ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz;
ADF4113: 4.0 GHz
2.7 V to 5.5 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler 8/9, 16/17, 32/33,
64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
The ADF4110 family of frequency synthesizers can be used to
implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. They
consist of a low noise digital PFD (phase frequency detector), a
precision charge pump, a programmable reference divider,
programmable A and B counters, and a dual-modulus prescaler
(P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction
with the dual-modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R counter) allows selectable REFIN frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO).
APPLICATIONS
Base stations for wireless radio (GSM, PCS, DCS, CDMA,
WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications test equipment
CATV equipment
Control of all the on-chip registers is via a simple 3-wire
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD
VP
DVDD
RSET
CPGND
REFERENCE
14-BIT
R COUNTER
REFIN
PHASE
FREQUENCY
DETECTOR
14
CHARGE
PUMP
CP
R COUNTER
LATCH
24-BIT
INPUT REGISTER
FUNCTION
LATCH
22
A, B COUNTER
LATCH
SDOUT
LOCK
DETECT
HIGH Z
13
AVDD
MUX
N = BP + A
RFINA
PRESCALER
P/P +1
RFINB
13-BIT
B COUNTER
LOAD
AGND
MUXOUT
SDOUT
LOAD
6-BIT
A COUNTER
6
CE
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
19
FROM
FUNCTION
LATCH
CURRENT
SETTING 1
M3
ADF4110/ADF4111
ADF4112/ADF4113
DGND
M2 M1
03496-0-001
CLK
DATA
LE
Figure 1. Functional Block Diagram
Rev. F
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ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Phase Frequency Detector (PFD) and Charge Pump............ 13
Applications ....................................................................................... 1
Muxout and Lock Detect ........................................................... 13
General Description ......................................................................... 1
Input Shift Register .................................................................... 13
Functional Block Diagram .............................................................. 1
Function Latch ............................................................................ 19
Revision History ............................................................................... 2
Initialization Latch ..................................................................... 20
Specifications..................................................................................... 3
Device Programming after Initial Power-Up ......................... 20
Timing Characteristics ..................................................................... 5
Resynchronizing the Prescaler Output .................................... 21
Absolute Maximum Ratings ............................................................ 6
Applications..................................................................................... 22
Transistor Count ........................................................................... 6
Local Oscillator for GSM Base Station Transmitter .............. 22
ESD Caution .................................................................................. 6
Using a D/A Converter to Drive the RSET Pin ......................... 23
Pin Configurations and Function Descriptions ........................... 7
Shutdown Circuit ....................................................................... 23
Typical Performance Characteristics ............................................. 8
Wideband PLL ............................................................................ 23
Circuit Description ......................................................................... 12
Direct Conversion Modulator .................................................. 25
Reference Input Section ............................................................. 12
Interfacing ................................................................................... 26
RF Input Stage ............................................................................. 12
PCB Design Guidelines for Chip Scale Package .................... 26
Prescaler (P/P + 1) ...................................................................... 12
Outline Dimensions ....................................................................... 27
A and B Counters ....................................................................... 12
Ordering Guide ............................................................................... 28
R Counter .................................................................................... 12
REVISION HISTORY
1/13—Rev. E to Rev. F
Changes to Table 1 ............................................................................. 4
Changes to Ordering Guide ...........................................................28
3/03—Data sheet changed from Rev. A to Rev. B.
Edits to Specifications ....................................................................... 2
Updated OUTLINE DIMENSIONS ............................................. 24
8/12—Rev. D to Rev. E
Changed CP-20-1 to CP-20-6 ........................................... Universal
Updated Outline Dimensions ........................................................28
Changes to Ordering Guide ...........................................................28
1/01—Data sheet changed from Rev. 0 to Rev. A.
Changes to DC Specifications in B Version, B Chips,
Unit, and Test Conditions/Comments Columns ..................... 2
Changes to Absolute Maximum Rating ......................................... 4
Changes to FRINA Function Test ..................................................... 5
Changes to Figure 8 ........................................................................... 7
New Graph Added—TPC 22 ........................................................... 9
Change to PD Polarity Box in Table V ......................................... 15
Change to PD Polarity Box in Table VI ........................................ 16
Change to PD Polarity Paragraph ................................................. 17
Addition of New Material
(PCB Design Guidelines for Chip–Scale package) ................ 23
Replacement of CP-20 Outline with CP-20 [2] Outline ............ 24
5/12—Rev. C to Rev. D
Changes to Figure 2 ........................................................................... 5
Changes to Figure 4 and Table 4 ...................................................... 7
Updated Outline Dimensions ........................................................28
Changes to Ordering Guide ...........................................................28
3/04—Data sheet changed from Rev. B to Rev. C.
Updated Format .................................................................. Universal
Changes to Specifications ................................................................. 2
Changes to Figure 32 .......................................................................22
Changes to the Ordering Guide.....................................................28
Rev. F | Page 2 of 28
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; dBm referred to 50 Ω;
TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is as follows: B Version: −40°C to +85°C.
Table 1.
Parameter
RF CHARACTERISTICS (3 V)
RF Input Sensitivity
RF Input Frequency
ADF4110
ADF4110
ADF4111
ADF4112
ADF4112
ADF4113
Maximum Allowable Prescaler Output
Frequency 2
RF CHARACTERISTICS (5 V)
RF Input Sensitivity
RF Input Frequency
ADF4110
ADF4111
ADF4112
ADF4113
ADF4113
Maximum Allowable Prescaler Output
Frequency2
REFIN CHARACTERISTICS
REFIN Input Frequency
Reference Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR FREQUENCY 4
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP 3-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
B Version
B Chips 1
Unit
−15/0
−15/0
dBm min/max
80/550
80/550
MHz min/max
50/550
0.08/1.2
0.2/3.0
0.1/3.0
0.2/3.7
50/550
0.08/1.2
0.2/3.0
0.1/3.0
0.2/3.7
MHz min/max
GHz min/max
GHz min/max
GHz min/max
GHz min/max
165
165
MHz max
−10/0
−10/0
dBm min/max
80/550
0.08/1.4
0.1/3.0
0.2/3.7
0.2/4.0
80/550
0.08/1.4
0.1/3.0
0.2/3.7
0.2/4.0
MHz min/max
GHz min/max
GHz min/max
GHz min/max
GHz min/max
200
200
MHz max
5/104
0.4/AVDD
3.0/AVDD
10
±100
55
5/104
0.4/AVDD
3.0/AVDD
10
±100
55
MHz min/max
V p-p min/max
V p-p min/max
pF max
µA max
MHz max
5
625
2.5
2.7/10
1
2
1.5
2
5
625
2.5
2.7/10
1
2
1.5
2
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
0.8 × DVDD
0.2 × DVDD
±1
10
0.8 × DVDD
0.2 × DVDD
±1
10
V min
V max
µA max
pF max
DVDD – 0.4
0.4
DVDD – 0.4
0.4
V min
V max
Rev. F | Page 3 of 28
Test Conditions/Comments
See Figure 29 for input circuit.
For lower frequencies, ensure slew rate
(SR) > 30 V/µs.
Input level = −10 dBm.
For lower frequencies, ensure SR > 30 V/µs.
For lower frequencies, ensure SR > 75 V/µs.
Input level = −10 dBm.
Input level = −10 dBm. For lower frequencies,
ensure SR > 130 V/µs.
For lower frequencies, ensure SR > 50 V/µs.
For lower frequencies, ensure SR > 50 V/µs.
For lower frequencies, ensure SR > 75 V/µs.
For lower frequencies, ensure SR > 130 V/µs.
Input level = −5 dBm.
For f < 5 MHz, ensure SR > 100 V/µs.
AVDD = 3.3 V, biased at AVDD/2. See Note 3.
AVDD = 5 V, biased at AVDD/2. See Note 3.
Programmable (see Table 9).
With RSET = 4.7 kΩ.
With RSET = 4.7 kΩ.
See Table 9.
0.5 V ≤ VCP ≤ VP – 0.5 V.
0.5 V ≤ VCP ≤ VP – 0.5 V.
VCP = VP/2.
IOH = 500 µA.
IOL = 500 µA.
ADF4110/ADF4111/ADF4112/ADF4113
Parameter
POWER SUPPLIES
AVDD
DVDD
VP
IDD 5 (AIDD + DIDD)
ADF4110
ADF4111
ADF4112
ADF4113
IP
Low Power Sleep Mode
NOISE CHARACTERISTICS
ADF4113 Normalized Phase Noise Floor 6
Phase Noise Performance 7
ADF4110: 540 MHz Output 8
ADF4111: 900 MHz Output 9
ADF4112: 900 MHz Output9
ADF4113: 900 MHz Output9
ADF4111: 836 MHz Output 10
ADF4112: 1750 MHz Output 11
ADF4112: 1750 MHz Output 12
ADF4112: 1960 MHz Output 13
ADF4113: 1960 MHz Output13
ADF4113: 3100 MHz Output 14
Spurious Signals
ADF4110: 540 MHz Output9
ADF4111: 900 MHz Output9
ADF4112: 900 MHz Output9
ADF4113: 900 MHz Output9
ADF4111: 836 MHz Output10
ADF4112: 1750 MHz Output11
ADF4112: 1750 MHz Output12
ADF4112: 1960 MHz Output13
ADF4113: 1960 MHz Output13
ADF4113: 3100 MHz Output14
Data Sheet
B Version
B Chips 1
Unit
Test Conditions/Comments
2.7/5.5
AVDD
AVDD/6.0
2.7/5.5
AVDD
AVDD/6.0
V min/V max
V min/V max
AVDD ≤ VP ≤ 6.0 V. See Figure 25 and Figure 26.
5.5
5.5
7.5
11
0.5
1
4.5
4.5
6.5
8.5
0.5
1
mA max
mA max
mA max
mA max
mA max
µA typ
4.5 mA typical.
4.5 mA typical.
6.5 mA typical.
8.5 mA typical.
TA = 25°C.
−215
−215
dBc/Hz typ
−91
−87
−90
−91
−78
−86
−66
−84
−85
−86
−91
−87
−90
−91
−78
−86
−66
−84
−85
−86
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ VCO output.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 300 Hz offset and 30 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 200 Hz offset and 10 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 1 MHz PFD frequency.
−97/−106
−98/−110
−91/−100
−100/−110
−81/−84
−88/−90
−65/−73
−80/−84
−80/−84
−80/−82
−97/−106
−98/−110
−91/−100
−100/−110
−81/−84
−88/−90
−65/−73
−80/−84
−80/−84
−82/−82
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 30 kHz/60 kHz and 30 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 10 kHz/20 kHz and 10 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 1 MHz/2 MHz and 1 MHz PFD frequency.
The B chip specifications are given as typical values.
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3
AC coupling ensures AVDD/2 bias. See Figure 33 for a typical circuit.
4
Guaranteed by design.
5
TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz.
6
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider
value) and 10logFPFD: PNSYNTH = PNTOT – 10logFPFD – 20logN.
7
The phase noise is measured with the EV-ADF411XSD1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the
synthesizer (fREFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (Table 7).
8
fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; loop B/W = 20 kHz.
9
fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz.
10
fREFIN = 10 MHz; fPFD = 30 kHz; offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; loop B/W = 3 kHz.
11
fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop B/W = 20 kHz
12
fREFIN = 10 MHz; fPFD = 10 kHz; offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; loop B/W = 1 kHz.
13
fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; loop B/W = 20 kHz.
14
fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; loop B/W = 20 kHz.
1
2
Rev. F | Page 4 of 28
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
TIMING CHARACTERISTICS
Guaranteed by design but not production tested. AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP ≤ 6 V;
AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
Limit at TMIN to TMAX (B Version)
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
t3
Test Conditions/Comments
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
t4
CLOCK
t1
DATA
DB23 (MSB)
t2
DB22
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
LE
03496-002
t5
LE
Figure 2. Timing Diagram
Rev. F | Page 5 of 28
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted
Table 3.
Parameter
AVDD to GND 1
AVDD to DVDD
VP to GND
VP to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFINA, RFINB to GND
RFINA to RFINB
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
LFCSP θJA Thermal Impedance
(Paddle Soldered)
LFCSP θJA Thermal Impedance
(Paddle Not Soldered)
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
1
Rating
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to +7 V
−0.3 V to +5.5 V
−0.3 V to VDD + 0.3 V
−0.3 V to VP + 0.3 V
−0.3 V to VDD + 0.3 V
±320 mV
−40°C to +85°C
−65°C to +150°C
150°C
150.4°C/W
122°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
TRANSISTOR COUNT
6425 (CMOS) and 303 (Bipolar).
216°C/W
215°C
220°C
GND = AGND = DGND = 0 V.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. F | Page 6 of 28
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
6
AVDD
7
REFIN
8
12
DATA
11 CLK
TOP VIEW
(Not to Scale) 10 CE
9
DGND
AGND 3
RFINB 4
RFINA 5
18 VP
16 DVDD
15 MUXOUT
ADF4110
ADF4111
ADF4112
ADF4113
14 LE
13 DATA
TOP VIEW
(Not to Scale)
12 CLK
11 CE
NOTES
1. THE EXPOSED PADDLE SHOULD BE CONNECTED TO AGND.
Figure 3. TSSOP Pin Configuration
03496-0-004
RFINA
LE
AGND 2
DGND 10
5
13
CPGND 1
9
RFINB
MUXOUT
REFIN 8
4
DVDD
14
DGND
AGND
VP
15
6
3
16
7
CPGND
ADF4110
ADF4111
ADF4112
ADF4113
AVDD
2
AVDD
1
CP
03496-0-003
RSET
17 DVDD
20 CP
19 RSET
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
TSSOP
Pin No.
1
LFCSP
Pin No.
19
Mnemonic
RSET
Function
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.56 V. The relationship between ICP and RSET is
I CPmax =
2
20
CP
3
4
5
1
2, 3
4
CPGND
AGND
RFINB
6
7
5
6, 7
RFINA
AVDD
8
8
REFIN
9
10
9, 10
11
DGND
CE
11
12
CLK
12
13
DATA
13
14
LE
14
15
MUXOUT
15
16, 17
DVDD
16
18
VP
EPAD
23.5
R SET
So, with RSET = 4.7 kΩ, ICPmax = 5 mA.
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn
drives the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 29.
Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2, and an equivalent input
resistance of 100 kΩ. See Figure 28. This input can be driven from a TTL or CMOS crystal oscillator, or
can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking the pin high powers up the device depending on the status of the powerdown Bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches; the latch is selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
VP can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V. 1
Exposed Pad (LFCSP Only). The exposed paddle should be connected to AGND.
Rev. F | Page 7 of 28
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
KEYWORD
DATA
–FORMAT
MA
R
FREQ
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
MAGS11
0.89207
0.8886
0.89022
0.96323
0.90566
0.90307
0.89318
0.89806
0.89565
0.88538
0.89699
0.89927
0.87797
0.90765
0.88526
0.81267
0.90357
0.92954
0.92087
0.93788
ANGS11
–2.0571
–4.4427
–6.3212
–2.1393
–12.13
–13.52
–15.746
–18.056
–19.693
–22.246
–24.336
–25.948
–28.457
–29.735
–31.879
–32.681
–31.522
–34.222
–36.961
–39.343
MAGS11
0.9512
0.93458
0.94782
0.96875
0.92216
0.93755
0.96178
0.94354
0.95189
0.97647
0.98619
0.95459
0.97945
0.98864
0.97399
0.97216
REFERENCE
LEVEL = –4.2dBm
–10
ANGS11
–40.134
–43.747
–44.393
–46.937
–49.6
–51.884
–51.21
–53.55
–56.786
–58.781
–60.545
–61.43
–61.241
–64.051
–66.19
–63.775
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 s
AVERAGES = 19
–20
–30
–40
–50
–60
–92.5dBc/Hz
–70
–80
03496-0-005
FREQ
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
0
IMPEDANCE
–OHMS
50
–90
–100
–2.0kHz
–1.0kHz
900MHz
1.0kHz
03496-0-008
PARAM
–TYPE
S
OUTPUT POWER (dB)
FREQ
–UNIT
GHz
2.0kHz
FREQUENCY
Figure 8. ADF4113 Phase Noise
(900 MHz, 200kHz, 20 kHz) with DLY and SYNC Enabled
Figure 5. S-Parameter Data for the ADF4113 RF Input (up to 1.8 GHz)
0
–40
VDD = 3V
VP = 3V
–50
–60
–10
PHASE NOISE (dBc/Hz)
–15
TA = +25°C
TA = +85°C
–20
–25
–80
–90
–100
–110
–120
–30
1
2
3
4
5
RF INPUT FREQUENCY (GHz)
–140
100
1k
10k
100k
1M
FREQUENCY OFFSET FROM 900MHz CARRIER (Hz)
03496-0-009
0
03496-0-006
–130
TA = –40°C
–35
Figure 9. ADF4113 Integrated Phase Noise
(900 MHz, 200 kHz, 20 kHz, Typical Lock Time: 400 µs)
Figure 6. Input Sensitivity (ADF4113)
0
–40
–20
–30
–40
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 s
AVERAGES = 19
–50
–60
PHASE NOISE (dBc/Hz)
REFERENCE
LEVEL = –4.2dBm
–10
–50
–60
–91.0dBc/Hz
–70
–80
RMS NOISE = 0.62°
RL = –40dBc/Hz
–70
–80
–90
–100
–110
–120
–90
–130
–100
–2.0kHz
–1.0kHz
900MHz
1.0kHz
2.0kHz
FREQUENCY
03496-0-007
OUTPUT POWER (dB)
RMS NOISE = 0.52°
RL = –40dBc/Hz
–70
Figure 7. ADF4113 Phase Noise (900 MHz, 200 kHz, 20 kHz)
–140
100
1k
10k
100k
1M
FREQUENCY OFFSET FROM 900MHz CARRIER (Hz)
Figure 10. ADF4113 Integrated Phase Noise
(900 MHz, 200 kHz, 35 kHz, Typical Lock Time: 200 µs)
Rev. F | Page 8 of 28
03496-0-010
RF INPUT POWER (dBm)
–5
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
–40
0
–30
–40
–50
–60
–50
–60
–70
–90.2dBc/Hz
–80
–80
–90
–100
–110
–120
–200kHz
900MHz
200kHz
400kHz
FREQUENCY
–140
100
03496-0-011
–400kHz
10k
100k
1M
Figure 14. ADF4113 Integrated Phase Noise
(1750 MHz, 30 kHz, 3 kHz)
Figure 11. ADF4113 Reference Spurs (900 MHz, 200 kHz, 20 kHz)
0
0
–20
–30
–40
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 35kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5s
AVERAGES = 30
–20
–50
–60
–70
–89.3dBc/Hz
–80
REFERENCE
LEVEL = –5.7dBm
–10
OUTPUT POWER (dB)
REFERENCE
LEVEL = –4.2dBm
–10
–30
–40
–50
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 30kHz
LOOP BANDWIDTH = 3kHz
RES. BANDWIDTH = 3Hz
VIDEO BANDWIDTH = 3Hz
SWEEP = 255s
POSITIVE PEEK DETECT
MODE
–60
–79.6dBc/Hz
–70
–80
–90
–400kHz
–200kHz
900MHz
200kHz
400kHz
FREQUENCY
03496-0-012
–90
–100
–100
–80kHz
–40kHz
1750MHz
40kHz
80kHz
FREQUENCY
Figure 12. ADF4113 (900 MHz, 200 kHz, 35 kHz)
03496-0-015
OUTPUT POWER (dB)
1k
FREQUENCY OFFSET FROM 1750MHz CARRIER (Hz)
03496-0-014
–130
–90
–100
Figure 15. ADF4113 Reference Spurs (1750 MHz, 30 kHz, 3 kHz)
0
0
–20
–30
–40
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 30kHz
LOOP BANDWIDTH = 3kHz
RES. BANDWIDTH = 10kHz
VIDEO BANDWIDTH = 10kHz
SWEEP = 477ms
AVERAGES = 10
–20
–50
–60
–70
–75.2dBc/Hz
–80
–30
–40
–60
–86.6dBc/Hz
–70
–80
–90
–100
1750MHz
200Hz
400Hz
FREQUENCY
03496-0-013
–90
–200Hz
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9s
AVERAGES = 45
–50
–100
–400Hz
REFERENCE
LEVEL = –4.2dBm
–10
OUTPUT POWER (dB)
REFERENCE
LEVEL = –8.0dBm
–10
OUTPUT POWER (dB)
RMS NOISE = 1.6°
RL = –40dBc/Hz
–70
Figure 13. ADF4113 Phase Noise (1750 MHz, 30 kHz, 3 kHz)
–2.0kHz
–1.0kHz
3100MHz
1.0kHz
2.0kHz
FREQUENCY
Figure 16. ADF4113 Phase Noise (3100 MHz, 1 MHz, 100 kHz)
Rev. F | Page 9 of 28
03496-0-016
OUTPUT POWER (dB)
–20
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5s
AVERAGES = 30
PHASE NOISE (dBc/Hz)
REFERENCE
LEVEL = –4.2dBm
–10
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
–60
–40
–50
VDD = 3V
VP = 3V
RMS NOISE = 1.7°
RL = 40dBc/Hz
–70
–70
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–60
–80
–90
–100
–110
–80
–90
–120
106
105
104
103
FREQUENCY OFFSET FROM 3100MHz CARRIER (Hz)
–100
–40
03496-0-017
–140
102
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 17. ADF4113 Integrated Phase Noise
(3100 MHz, 1 MHz, 100 kHz)
Figure 20. ADF4113 Phase Noise vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
–60
0
REFERENCE
LEVEL = –17.2dBm
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 13s
AVERAGES = 1
–20
–30
–40
–50
–60
–80.6dBc/Hz
–70
VDD = 3V
VP = 5V
FIRST REFERENCE SPUR (dBc)
–10
OUTPUT POWER (dB)
–20
03496-0-020
–130
–80
–70
–80
–90
–2.0MHz
–1.0MHz
3100MHz
1.0MHz
2.0MHz
FREQUENCY
–100
–40
03496-0-018
–100
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 18. Reference Spurs (3100 MHz, 1 MHz, 100 kHz)
Figure 21. ADF4113 Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
–120
–5
–15
FIRST REFERENCE SPUR (dBc)
VDD = 3V
VP = 5V
–130
–140
–150
–160
–170
VDD = 3V
VP = 5V
–25
–35
–45
–55
–65
–75
–85
1
10
100
1000
10000
PHASE DETECTOR FREQUENCY (kHz)
–105
Figure 19. ADF4113 Phase Noise (Referred to CP Output)
vs. Phase Detector Frequency
0
1
2
3
4
TUNING VOLTAGE (V)
Figure 22. ADF4113 Reference Spurs (200 kHz) vs. VTUNE
(900 MHz, 200 kHz, 20 kHz)
Rev. F | Page 10 of 28
5
03496-0-022
–95
–180
03496-0-019
PHASE NOISE (dBc/Hz)
–20
03496-0-021
–90
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
–60
3.0
VDD = 3V
VP = 3V
2.5
–70
2.0
DIDD (mA)
PHASE NOISE (dBc/Hz)
VDD = 3V
VP = 5V
–80
1.5
1.0
–90
–20
0
20
40
60
80
100
TEMPERATURE (°C)
0
03496-0-023
–100
–40
0
Figure 23. ADF4113 Phase Noise vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
100
150
200
Figure 26. DIDD vs. Prescaler Output Frequency
(ADF4110, ADF4111, ADF4112, ADF4113)
–60
6
5
VDD = 3V
VP = 5V
VPP = 5V
ICP = 5mA
4
–70
3
2
1
ICP (mA)
FIRST REFERENCE SPUR (dBc)
50
PRESCALER OUTPUT FREQUENCY (MHz)
03496-0-026
0.5
–80
0
–1
–2
–90
–3
–4
40
20
60
80
100
TEMPERATURE (°C)
Figure 24. ADF4113 Reference Spurs vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
9
ADF4113
6
5
ADF4112
3
2
ADF4110
ADF4111
1
0
0
8/9
16/17
32/33
PRESCALER VALUE
64/65
03496-0-025
AIDD (mA)
7
4
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VCP (V)
Figure 27. Charge Pump Output Characteristics for ADF4110 Family
10
8
–6
Figure 25. AIDD vs. Prescaler Value
Rev. F | Page 11 of 28
03496-0-027
0
–20
03496-0-024
–5
–100
–40
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
A AND B COUNTERS
The reference input stage is shown in Figure 28. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 200 MHz or less. Thus, with an RF input
frequency of 2.5 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not.
POWER-DOWN
CONTROL
Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
equation for the VCO frequency is
100k
NC
SW2
REFIN NC
TO R COUNTER
BUFFER
03496-0-028
SW1
SW3
NO
fVCO = [(P × B) + A]fREFIN/R
Figure 28. Reference Input Stage
where:
RF INPUT STAGE
The RF input stage is shown in Figure 29. It is followed by a
two-stage limiting amplifier to generate the current mode logic
(CML) clock levels needed for the prescaler.
BIAS
GENERATOR
500
1.6V
AVDD
500
fVCO = output frequency of external voltage controlled oscillator
(VCO)
P = preset modulus of dual-modulus prescaler
B = preset divide ratio of binary 13-bit counter(3 to 8191)
A = preset divide ratio of binary 6-bit swallow counter (0 to 63)
fREFIN = output frequency of the external reference frequency
oscillator
R = preset divide ratio of binary 14-bit programmable reference
counter (1 to 16383)
R COUNTER
RFINA
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
AGND
03496-0-029
RFINB
Figure 29. RF Input Stage
N = BP + A
Along with the A and B counters, the dual-modulus prescaler
(P/P + 1) enables the large division ratio, N, to be realized (N =
BP + A). The dual-modulus prescaler, operating at CML levels,
takes the clock from the RF input stage and divides it down to a
manageable frequency for the CMOS A and B counters. The
prescaler is programmable; it can be set in software to 8/9,
16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core.
Rev. F | Page 12 of 28
13-BIT B
COUNTER
FROM RF
INPUT STAGE
PRESCALER
P/P + 1
MODULUS
CONTROL
TO PFD
LOAD
LOAD
6-BIT A
COUNTER
Figure 30. A and B Counters
03496-0-030
PRESCALER (P/P + 1)
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
Lock Detect
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 31 is a simplified
schematic. The PFD includes a programmable delay element
that controls the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
reference counter latch, ABP2 and ABP1, control the width of
the pulse. See Table 7.
VP
HI
D1
Q1
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive phase detector (PD) cycles is less
than 15 ns. With LDP set to 1, five consecutive cycles of less
than 15 ns are required to set the lock detect. It stays high until
a phase error greater than 25 ns is detected on any subsequent
PD cycle.
The N-channel open-drain analog lock detect should be
operated with a 10 kΩ nominal external pull-up resistor. When
lock has been detected, this output is high with narrow lowgoing pulses.
CHARGE
PUMP
UP
U1
DVDD
R DIVIDER
CLR1
ABP1
CLR2
D2
HI
Q2
CP
U3
ABP2
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUX
MUXOUT
CONTROL
DOWN
U2
DGND
03496-0-032
PROGRAMMABLE
DELAY
Figure 32. MUXOUT Circuit
N DIVIDER
CPGND
INPUT SHIFT REGISTER
R DIVIDER
CP OUTPUT
03496-0-031
N DIVIDER
Figure 31. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4110 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Table 9 shows the full truth table. Figure 32 shows the
MUXOUT section in block diagram form.
The ADF4110 family digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter comprised of
a 6-bit A counter and a 13-bit B counter. Data is clocked into
the 24-bit shift register on each rising edge of CLK MSB first.
Data is transferred from the shift register to one of four latches
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2, C1) in the shift register.
These are the two LSBs, DB1 and DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 5.
Table 6 shows a summary of how the latches are programmed.
Table 5. C2, C1 Truth Table
Control Bits
C2
C1
0
0
0
1
1
0
1
1
Rev. F | Page 13 of 28
Data Latch
R Counter
N Counter (A and B)
Function Latch (Including Prescaler)
Initialization Latch
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
Table 6. ADF4110 Family Latch Summary
DB23
X
DLY
SYNC
LOCK
DETECT
PRECISION
RESERVED
REFERENCE COUNTER LATCH
TEST
MODE BITS
DB22 DB21
DB20 DB19
DLY
LDP
SYNC
ANTIBACKLASH
WIDTH
DB16 DB15
DB18 DB17
T1
T2
ABP2 ABP1
CONTROL
BITS
14-BIT REFERENCE COUNTER, R
R14
DB14 DB13
R12
R13
DB12 DB11
R11
R10
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
R9
R8
R7
R6
R5
R4
R3
R2
R1
DB1
DB0
C2 (0) C1 (0)
X = DON'T CARE
RESERVED
DB23 DB22
X
X
CP GAIN
N COUNTER LATCH
DB21 DB20
G1
DB19
DB18 DB17 DB16 DB15
B12
B13
B11
B9
B10
B8
DB14 DB13
B6
B7
CONTROL
BITS
6-BIT A COUNTER
13-BIT B COUNTER
DB12 DB11
B5
B4
DB0
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
B3
B2
B1
A6
A5
A4
A3
A2
A1
C2 (0) C1 (1)
CONTROL
BITS
DB1
X = DON'T CARE
DB20 DB19
CPI6
CPI5
DB18 DB17
CPI4
CPI3
DB16 DB15 DB14 DB13 DB12 DB11
CPI2
CPI1
TC3
TC4
TC2
TC1
COUNTER
RESET
PD2
POWERDOWN 1
P1
PD
POLARITY
DB22 DB21
TIMER COUNTER
CONTROL
CP
THREESTATE
P2
CURRENT
SETTING
1
FASTLOCK
ENABLE
DB23
CURRENT
SETTING
2
FASTLOCK
MODE
PRESCALER
VALUE
POWERDOWN 2
FUNCTION LATCH
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1) C1 (0)
MUXOUT
CONTROL
F5
MUXOUT
CONTROL
DB1
DB0
CPI3
CPI6
CPI4
CPI2
DB15 DB14
CPI1
TC4
DB13 DB12
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
TC3
TC2
F4
F3
F2
M3
M2
M1
PD1
F1
TC1
F5
DB0
C2 (1) C1 (1)
03496-0-033
CPI5
P1
COUNTER
RESET
PD2
P2
POWERDOWN 1
DB17 DB16
CONTROL
BITS
TIMER COUNTER
CONTROL
PD
POLARITY
DB19 DB18
CP
THREE-STATE
DB21 DB20
CURRENT
SETTING
1
FASTLOCK
ENABLE
DB23 DB22
CURRENT
SETTING
2
FASTLOCK
MODE
PRESCALER
VALUE
POWERDOWN 2
INITIALIZATION LATCH
Rev. F | Page 14 of 28
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
DLY
SYNC
DB23 DB22
X
DLY
LOCK
DETECT
PRECISION
RESERVED
Table 7. Reference Counter Latch Map
DB21 DB20
SYNC
LDP
TEST
MODE BITS
ANTIBACKLASH
WIDTH
DB19 DB18
DB17 DB16
DB15 DB14
DB13 DB12
DB11 DB10
ABP2 ABP1
R14
R12
R10
T2
T1
CONTROL
BITS
14-BIT REFERENCE COUNTER
R13
R11
R9
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
R8
R7
R6
R5
R4
R3
R2
R1
DB1
DB0
C2 (0) C1 (0)
X = DON'T
CARE
ABP2 ABP1
R14
R13
R12
••••••••••
R3
R2
R1
DIVIDE RATIO
0
0
0
••••••••• •
0
0
1
1
0
0
0
••••••••• •
0
1
0
2
0
0
0
••••••••• •
0
1
1
3
0
0
0
••••••••• •
1
0
0
4
•
•
•
••••••••• •
•
•
•
•
•
•
•
••••••••• •
•
•
•
•
•
•
•
••••••••• •
•
•
•
•
1
1
1
••••••••• •
1
0
0
16380
1
1
1
••••••••• •
1
0
1
16381
1
1
1
••••••••• •
1
1
0
16382
1
1
1
••••••••• •
1
1
1
16383
ANTIBACKLASH PULSE WIDTH
0
0
3.0ns
0
1
1.5ns
1
0
6.0ns
1
1
3.0ns
TEST MODE BITS SHOULD
BE SET TO 00 FOR NORMAL
OPERATION
LDP
SYNC
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
OPERATION
0
0
NORMAL OPERATION
0
1
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH NONDELAYED VERSION OF RF INPUT
1
0
NORMAL OPERATION
1
1
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH DELAYED VERSION OF RF INPUT
03496-0-034
DLY
OPERATION
0
Rev. F | Page 15 of 28
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
RESERVED
DB23 DB22
X
X
CP GAIN
Table 8. AB Counter Latch Map
DB21 DB20
G1
DB19 DB18
B13
B12
B11
DB17 DB16
B10
DB15 DB14
B8
B9
DB13 DB12
B7
CONTROL
BITS
6-BIT A COUNTER
13-BIT B COUNTER
B6
B5
DB11 DB10
B4
B3
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
B2
B1
A6
A5
A4
A3
A2
A1
DB1
DB0
C2 (0) C1 (1)
X = DON'T CARE
A6
A5
0
0
0
••••••••• •
1
0
2
0
0
••••••••• •
1
1
3
•
•
••••••••• •
•
•
•
•
•
••••••••• •
•
•
•
•
•
••••••••• •
•
•
•
1
1
••••••••• •
0
0
60
1
1
••••••••• •
0
1
61
1
1
••••••••• •
1
0
62
1
1
••••••••• •
1
1
63
••••••••• •
0
0
1
NOT ALLOWED
0
1
0
NOT ALLOWED
0
••••••••• •
0
1
1
3
0
••••••••• •
1
0
0
4
•
•
••••••••• •
•
•
•
•
•
•
••••••••• •
•
•
•
•
0
0
0
0
0
•
•
B2
0
B1
0
B COUNTER DIVIDE RATIO
NOT ALLOWED
•
•
•
••••••••• •
•
•
•
•
1
1
1
••••••••• •
1
0
0
8188
1
1
1
••••••••• •
1
0
1
8189
1
1
1
••••••••• •
1
1
0
8190
1
1
1
••••••••• •
1
1
1
8191
F4 (FUNCTION LATCH)
FASTLOCK ENABLE*
CP GAIN
1
0
••••••••• •
0
0
0
1
••••••••• •
0
0
0
0
••••••••• •
0
0
B11
0
0
0
B3
0
B12
0
A COUNTER
DIVIDE RATIO
A2
••••••••• •
••••••••• •
B13
0
A1
••••••••• •
OPERATION
0
0
CHARGE PUMP CURRENT SETTING 1
IS PERMANENTLY USED.
0
1
CHARGE PUMP CURRENT SETTING 2
IS PERMANENTLY USED.
1
0
CHARGE PUMP CURRENT SETTING 1
IS USED.
1
1
CHARGE PUMP CURRENT IS SWITCHED
TO SETTING 2. THE TIME SPENT IN
SETTING 2 IS DEPENDENT UPON WHICH
FASTLOCK MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.
*SEE TABLE 9
03496-0-035
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS
N = BP + A, P IS PRESCALER VALUE SET IN THE
FUNCTION LATCH, B MUST BE GREATER THAN OR
EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES
OF (NX FREF), AT THE OUTPUT, NMIN IS (P2–P).
Rev. F | Page 16 of 28
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
CPI6
DB17 DB16
DB15 DB14
CPI5
CPI3
CPI1
CPI2
DB13
DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
TC3
TC2
F4
F3
F2
M3
M2
M1
PD1
F1
C2(1)
C1(0)
TIMER COUNTER
CONTROL
DB19 DB18
CPI4
COUNTER
RESET
PD2
POW ERDOW N 1
P1
PD
POLARITY
DB22 DB21 DB20
CP
THREE-STATE
P2
CURRENT
SETTING
1
FASTLOCK
ENABLE
DB23
CURRENT
SETTING
2
FASTLOCK
MODE
PRESCALER
VALUE
POW ERDOW N 2
Table 9. Function Latch Map
TC4
TC1
F5
MUXOUT
CONTROL
F1
F2
F3
CPI6
CPI5
CPI4
CPI3
CPI2
FASTLOCK MODE 2
TIMEOUT
(PFD CYCLES)
7
1
0
11
0
0
1
1
15
0
1
0
0
19
0
1
0
1
23
0
1
1
0
27
0
1
1
1
31
1
0
0
0
35
M3
M2
1
0
0
1
39
0
0
0
THREE-STATE OUTPUT
1
0
1
0
43
0
0
1
1
0
1
1
47
DIGITAL LOCK DETECT
(ACTIVE HIGH)
1
1
0
0
51
0
1
0
N DIVIDER OUTPUT
1
1
0
1
55
0
1
1
DVDD
1
1
1
0
59
1
1
1
1
63
1
0
0
R DIVIDER OUTPUT
1
0
1
ANALOG LOCK DETECT
(N-CHANNEL OPEN-DRAIN)
1
1
0
SERIAL DATA OUTPUT
1
1
1
DGND
ICP (mA)
CPI1
2.7kΩ
4.7kΩ
10kΩ
0
0
1.09
0.63
0.29
0
0
1
2.18
1.25
0.59
0
1
0
3.26
1.88
0.88
0
1
1
4.35
2.50
1.76
1
0
0
5.44
3.13
1.47
1
0
1
6.53
3.75
1.76
1
1
0
7.62
4.38
2.06
1
1
1
8.70
5.00
2.35
3
SEE FUNCTION LATCH,
TIMER COUNTER CONTROL
SECTION
M1
OUTPUT
MODE
ASYNCHRONOUS POWER-DOWN
1
SYNCHRONOUS POWER-DOWN
64/65
1
0
1
32/33
FASTLOCK MODE 1
1
0
1
1
0
1
NORMAL OPERATION
1
FASTLOCK DISABLED
1
0
1
16/17
FASTLOCK MODE
X
0
0
0
F5
0
0
0
1
F4
0
X
1
THREE-STATE
0
1
0
NORMAL
1
0
1
8/9
CHARGE PUMP OUTPUT
0
0
ASYNCHRONOUS POWER-DOWN
0
R, A, B COUNTERS
HELD IN RESET
TC1
X
P1
POSITIVE
NORMAL
1
TC2
X
0
NEGATIVE
1
0
TC3
0
P2
0
COUNTER
OPERATION
TC4
0
CE PIN PD2 PD1
PHASE DETECTOR
POLARITY
CONTROL
BITS
03496-0-036
PRESCALER VALUE
Rev. F | Page 17 of 28
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
DB21
DB20
DB19
DB18
DB17
DB16
DB15 DB14
DB13 DB12
P1
PD2
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
TC3
TC4
DB11 DB10
TC2
TC1
COUNTER
RESET
DB22
P2
POW ERDOWN 1
DB23
PD
POLARITY
TIMER COUNTER
CONTROL
CP
THREE-STATE
CURRENT
SETTING
1
FASTLOCK
ENABLE
CURRENT
SETTING
2
FASTLOCK
MODE
PRESCALER
VALUE
POW ERDOW N 2
Table 10. Initialization Latch Map
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
F4
F3
F2
M3
M2
M1
PD1
F1
F5
MUXOUT
CONTROL
F1
F2
CE PIN
PHASE DETECTOR
POLARITY
0
NEGATIVE
1
POSITIVE
F3
CHARGE PUMP
0
OUTPUT NORMAL
1
THREE-STATE
F4
F5
0
X
FASTLOCK DISABLED
1
0
FASTLOCK MODE 1
1
1
FASTLOCK MODE 2
TC3
TC2
TC1
TIMEOUT
(PFD CYCLES)
0
0
0
0
3
0
0
0
1
7
0
0
1
0
11
0
0
1
1
15
0
1
0
0
19
0
1
0
1
23
0
1
1
0
27
0
1
1
1
31
1
0
0
0
35
1
0
0
1
39
1
0
1
0
43
1
0
1
1
47
1
1
0
0
51
1
1
0
1
55
1
1
1
0
59
1
1
1
1
63
CPI5
CPI4
CPI3
CPI2
CPI1
2.7kΩ
4.7kΩ
10kΩ
0
0
0
1.09
0.63
0.29
0
0
1
2.18
1.25
0.59
0
1
0
3.27
1.88
0.88
0
1
1
4.35
2.50
1.76
1
0
0
5.44
3.13
1.47
1
0
1
6.53
3.75
1.76
1
1
0
7.62
4.38
2.06
1
1
1
8.70
5.00
2.35
ICP (mA)
DB1
DB0
C2 (1) C1 (1)
COUNTER
OPERATION
0
NORMAL
1
R, A, B COUNTERS
HELD IN RESET
FASTLOCK MODE
TC4
CPI6
CONTROL
BITS
SEE FUNCTION LATCH,
TIMER COUNTER CONTROL
SECTION
M3
M2
M1
OUTPUT
0
0
0
THREE-STATE OUTPUT
0
0
1
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
0
1
0
0
1
1
DV DD
1
0
0
R DIVIDER OUTPUT
1
0
1
ANALOG LOCK DETECT
(N-CHANNEL OPEN-DRAIN)
1
1
0
SERIAL DATA OUTPUT
1
1
1
DGND
MODE
PD2 PD1
0
X
X
ASYNCHRONOUS POWER-DOWN
1
X
0
NORMAL OPERATION
1
0
1
ASYNCHRONOUS POWER-DOWN
1
1
1
SYNCHRONOUS POWER-DOWN
P1
0
0
8/9
0
1
16/17
1
0
32/33
1
1
64/65
03496-0-037
PRESCALER VALUE
P2
Rev. F | Page 18 of 28
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
FUNCTION LATCH
The on-chip function latch is programmed with C2, C1 set to 1.
Table 9 shows the input data format for programming the
function latch.
Counter Reset
DB2 (F1) is the counter reset bit. When DB2 is 1, the R counter
and the AB counters are reset. For normal operation, this bit
should be 0. Upon powering up, the F1 bit must be disabled,
and the N counter resumes counting in “close” alignment with
the R counter. (The maximum error is one prescaler cycle.)
Power-Down
DB3 (PD1) and DB21 (PD2) on the ADF411x provide
program-mable power-down modes. They are enabled by the
CE pin.
When the CE pin is low, the device is immediately disabled
regardless of the states of PD2, PD1.
In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into Bit PD1,
provided PD2 has been loaded with a 0.
In the programmed synchronous power-down, the device
power-down is gated by the charge pump to prevent unwanted
frequency jumps. Once power-down is enabled by writing a 1
into Bit PD1 (provided a 1 has also been loaded to PD2), the
device goes into power-down on the next charge pump event.
When a power-down is activated (either synchronous or
asynchronous mode including CE pin activated power-down),
the following events occur:
•
All active dc current paths are removed.
•
The R, N, and timeout counters are forced to their load
state conditions.
•
The charge pump is forced into three-state mode.
•
The digital clock detect circuitry is reset.
•
The RFIN input is debiased.
•
The reference input buffer circuitry is disabled.
•
The input register remains active and capable of loading
and latching data.
Fastlock Mode Bit
DB10 of the function latch is the fastlock enable bit. When
fastlock is enabled, this bit determines which fastlock mode is
used. If the fastlock mode bit is 0, fastlock mode 1 is selected; if
the fastlock mode bit is 1, fastlock mode 2 is selected.
Fastlock Mode 1
The charge pump current is switched to the contents of Current
Setting 2.
The device enters fastlock by having a 1 written to the CP gain
bit in the AB counter latch. The device exits fastlock by having a
0 written to the CP gain bit in the AB counter latch.
Fastlock Mode 2
The charge pump current is switched to the contents of Current
Setting 2. The device enters fastlock by having a 1 written to the
CP gain bit in the AB counter latch. The device exits fastlock
under the control of the timer counter. After the timeout period
determined by the value in TC4 through TC1, the CP gain bit in
the AB counter latch is automatically reset to 0 and the device
reverts to normal mode instead of fastlock. See Table 9 for the
timeout periods.
Timer Counter Control
The user has the option of programming two charge pump currents. Current Setting 1 is meant to be used when the RF output
is stable and the system is in a static state. Current Setting 2 is
meant to be used when the system is dynamic and in a state of
change (i.e., when a new output frequency is programmed).
The normal sequence of events is as follows:
The user initially decides what the preferred charge pump
currents are going to be. For example, they may choose 2.5 mA
as Current Setting 1 and 5 mA as Current Setting 2.
At the same time, they must also decide how long they want the
secondary current to stay active before reverting to the primary
current. This is controlled by the timer counter control bits,
DB14 through DB11 (TC4 through TC1) in the function latch.
The truth table is given in Table 10.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1 on
the ADF4110 family. Table 9 shows the truth table.
Fastlock Enable Bit
DB9 of the function latch is the fastlock enable bit. Fastlock is
enables only when this is 1.
A user can program a new output frequency simply by programming the AB counter latch with new values for A and B. At
the same time, the CP gain bit can be set to 1, which sets the
charge pump with the value in CPI6–CPI4 for a period determined by TC4 through TC1. When this time is up, the charge
pump current reverts to the value set by CPI3–CPI1. At the
same time, the CP gain bit in the AB counter latch is reset to 0
and is ready for the next time the user wishes to change the
frequency.
Rev. F | Page 19 of 28
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
Note that there is an enable feature on the timer counter. It is
enabled when Fastlock Mode 2 is chosen by setting the fastlock
mode bit (DB10) in the function latch to 1.
When the initialization latch is loaded, the following occurs:
1.
The function latch contents are loaded.
Charge Pump Currents
2.
An internal pulse resets the R, A, B, and timeout counters
to load state conditions and three-states the charge pump.
Note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse,
allowing close phase alignment when counting resumes.
3.
Latching the first AB counter data after the initialization
word activates the same internal reset pulse. Successive AB
loads do not trigger the internal reset pulse unless there is
another initialization.
CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Table 10.
Prescaler Value
P2 and P1 in the function latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 200 MHz. Thus, with
an RF frequency of 2 GHz, a prescaler value of 16/17 is valid but
a value of 8/9 is not.
CE Pin Method
PD Polarity
1.
Apply VDD.
This bit sets the phase detector polarity bit. See Table 10.
2.
Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
3.
Program the function latch (10). Program the R counter
latch (00). Program the AB counter latch (01).
4.
Bring CE high to take the device out of power-down. The R
and AB counters now resume counting in close alignment.
CP Three-State
This bit controls the CP output pin. With the bit set high, the
CP output is put into three-state. With the bit set low, the CP
output is enabled.
INITIALIZATION LATCH
When C2, C1 = 1, 1, the initialization latch is programmed.
This is essentially the same as the function latch (programmed
when C2, C1 = 1, 0).
After CE goes high, a duration of 1 µs may be required for the
prescaler band gap voltage and oscillator input buffer bias to
reach steady state.
However, when the initialization latch is programmed, an additional internal reset pulse is applied to the R and AB counters.
This pulse ensures that the AB counter is at load point when the
AB counter data is latched, and the device begins counting in
close phase alignment.
CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after VDD was
initially applied.
If the latch is programmed for synchronous power-down (CE
pin high; PD1 bit high; PD2 bit low), the internal pulse also
triggers this power-down. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse,
so close phase alignment is maintained when counting resumes.
Counter Reset Method
When the first AB counter data is latched after initialization, the
internal reset pulse is again activated. However, successive AB
counter loads after this will not trigger the internal reset pulse.
DEVICE PROGRAMMING AFTER INITIAL
POWER-UP
After initial power-up of the device, there are three ways to
program the device.
Initialization Latch Method
Apply VDD. Program the initialization latch (11 in 2 LSBs of
input word). Make sure the F1 bit is programmed to 0. Then, do
an R load (00 in 2 LSBs). Then do an AB load (01 in 2 LSBs).
1.
Apply VDD.
2.
Do a function latch load (10 in 2 LSBs). As part of this,
load 1 to the F1 bit. This enables the counter reset.
3.
Do an R counter load (00 in 2 LSBs). Do an AB counter
load (01 in 2 LSBs). Do a function latch load (10 in 2
LSBs). As part of this, load 0 to the F1 bit. This disables the
counter reset.
This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and
three states the charge pump but does not trigger synchronous
power-down. The counter reset method requires an extra
function latch load compared to the initialization latch method.
Rev. F | Page 20 of 28
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
RESYNCHRONIZING THE PRESCALER OUTPUT
Table 7 (the Reference Counter Latch Map) shows two bits,
DB22 and DB21, which are labeled DLY and SYNC,
respectively. These bits affect the operation of the prescaler.
With SYNC = 1, the prescaler output is resynchronized with the
RF input. This has the effect of reducing jitter due to the
prescaler and can lead to an overall improvement in synthesizer
phase noise performance. Typically, a 1 dB to 2 dB
improvement is seen in the ADF4113. The lower bandwidth
devices can show an even greater improvement. For example,
the ADF4110 phase noise is typically improved by 3 dB when
SYNC is enabled.
With DLY = 1, the prescaler output is resynchronized with a
delayed version of the RF input.
If the SYNC feature is used on the synthesizer, some care must
be taken. At some point, (at certain temperatures and output
frequencies), the delay through the prescaler coincides with the
active edge on RF input; this causes the SYNC feature to break
down. It is important to be aware of this when using the SYNC
feature. Adding a delay to the RF signal, by programming
DLY = 1, extends the operating frequency and temperature
somewhat. Using the SYNC feature also increases the value of
the AIDD for the device. With a 900 MHz output, the ADF4113
AIDD increases by about 1.3 mA when SYNC is enabled and by
an additional 0.3 mA if DLY is enabled.
All the typical performance plots in this data sheet, except for
Figure 8, apply for DLY and SYNC = 0, i.e., no resynchronization or delay enabled.
Rev. F | Page 21 of 28
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
APPLICATIONS
LOCAL OSCILLATOR FOR GSM BASE STATION TRANSMITTER
All of these specifications are needed and used to come up with
the loop filter component values shown in Figure 33.
Figure 33 shows the ADF4111/ADF4112/ADF4113 being used
with a VCO to produce the LO for a GSM base station
transmitter.
The loop filter output drives the VCO, which in turn is fed back
to the RF input of the PLL synthesizer. It also drives the RF output terminal. A T-circuit configuration provides 50 Ω matching
between the VCO output, the RF output, and the RFIN terminal
of the synthesizer.
The reference input signal is applied to the circuit at FREFIN
and, in this case, is terminated in 50 Ω. A typical GSM system
would have a 13 MHz TCXO driving the reference input without any 50 Ω termination. In order to have channel spacing of
200 kHz (GSM standard), the reference input must be divided
by 65, using the on-chip reference divider of the ADF4111/
ADF4112/ADF4113.
In a PLL system, it is important to know when the system is in
lock. In Figure 33, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be programmed to monitor various internal signals in the synthesizer.
One of these is the LD or lock-detect signal.
The charge pump output of the ADF4111/ADF4112/ADF4113
(Pin 2) drives the loop filter. In calculating the loop filter
component values, a number of items need to be considered. In
this example, the loop filter was designed so that the overall
phase margin for the system would be 45 degrees. Other PLL
system specifications are
KD = 5 mA
KV = 12 MHz/V
Loop Bandwidth = 20 kHz
FREF = 200 kHz
N = 4500
Extra Reference Spur Attenuation = 10 dB
VDD
VP
RFOUT
100pF
7
1000pF
3.3kΩ
C
1nF
51Ω1
5.6kΩ
ADF4111
ADF4112
ADF4113
LE
VCC
620pF
VCO190-902T
18Ω
18Ω
P
18Ω
8.2nF
LOCK
DETECT
100pF
RFINA 6
51Ω2
RFINB 5
DGND
4.7kΩ
RSET
AGND
1
CPGND
SPI COMPATIBLE SERIAL BUS
CE
MUXOUT 14
CLK
DATA
100pF
B
AVDD DVDD VP
CP 2
8 REFIN
3
4
9
100pF
1TO BE USED WHEN GENERATOR SOURCE IMPEDANCE IS 50Ω.
2OPTIONAL MATCHING RESISTOR DEPENDING ON RF
OUT FREQUENCY.
DECOUPLING CAPACITORS ON AVDD, DVDD, AND VP OF THE ADF411x
AND ON THE POSITIVE SUPPLY OF THE VCO190-902T HAVE BEEN
OMITTED FROM THE DIAGRAM TO INCREASE CLARITY.
Figure 33. Local Oscillator for GSM Base Station
Rev. F | Page 22 of 28
03496-0-038
1000pF
FREFIN
16
15
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
RFOUT
100pF
FREFIN
VCO
LOOP
FILTER
CP 2
8 REFIN
INPUT OUTPUT
ADF4111
ADF4112
ADF4113
CE
CLK
DATA
LE
MUXOUT 14
1 RSET
2.7kΩ
100pF
18Ω
18Ω
18Ω
GND
LOCK
DETECT
100pF
RFINA 6
51Ω
RFINB 5
100pF
AD5320
12-BIT
V-OUT DAC
03496-0-039
POWER SUPPLY CONNECTIONS AND DECOUPLING
CAPACITORS ARE OMITTED FOR CLARITY.
SPI COMPATIBLE SERIAL BUS
Figure 34. Driving the RSET Pin with a D/A Converter
USING A D/A CONVERTER TO DRIVE THE RSET PIN
A D/A converter can be used to drive the RSET pin of the
ADF4110 family, thus increasing the level of control over the
charge pump current, ICP. This can be advantageous in wideband applications where the sensitivity of the VCO varies over
the tuning range. To compensate for this, the ICP may be varied
to maintain good phase margin and ensure loop stability. See
Figure 34.
SHUTDOWN CIRCUIT
The attached circuit in Figure 35 shows how to shut down both
the ADF4110 family and the accompanying VCO. The ADG701
switch goes closed circuit when a Logic 1 is applied to the IN
input. The low cost switch is available in both SOT-23 and
MSOP packages.
WIDEBAND PLL
Many of the wireless applications for synthesizers and VCOs in
PLLs are narrow band in nature. These applications include the
various wireless standards like GSM, DSC1800, CDMA, and
WCDMA. In each of these cases, the total tuning range for the
local oscillator is less than 100 MHz. However, there are also
wideband applications for which the local oscillator could have
a tuning range as wide as an octave. For example, cable TV
tuners have a total range of about 400 MHz. Figure 36 shows an
application where the ADF4113 is used to control and program
the Micronetics M3500-2235. The loop filter was designed for
an RF output of 2900 MHz, a loop bandwidth of 40 kHz, a PFD
frequency of 1 MHz, ICP of 10 mA (2.5 mA synthesizer ICP
multiplied by the gain factor of 4), VCO KD of 90 MHz/V
(sensitivity of the M3500-2235 at an output of 2900 MHz), and
a phase margin of 45°C.
In narrow-band applications, there is generally a small variation
in output frequency (generally less than 10%) and a small
variation in VCO sensitivity over the range (typically 10% to
15%). However, in wideband applications, both of these
parameters have a much greater variation. In Figure 36, for
example, there is a −25% and +17% variation in the RF output
from the nominal 2.9 GHz. The sensitivity of the VCO can vary
from 120 MHz/V at 2750 MHz to 75 MHz/V at 3400 MHz
(+33%, −17%). Variations in these parameters change the loop
bandwidth. This in turn can affect stability and lock time. By
changing the programmable ICP, it is possible to get compensation for these varying loop conditions and ensure that the loop
is always operating close to optimal conditions.
Rev. F | Page 23 of 28
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
VP
POWER-DOWN CONTROL
S
D
7
15
16
FREFIN
VCC
LOOP
FILTER
RFOUT
GND
10
AVDD DVDD VP CE
CP 2
8
REFIN
RSET 1
VDD
ADG701
IN
VDD
100pF
18Ω
100pF 18Ω
VCO
18Ω
GND
4.7kΩ
ADF4110
ADF4111
ADF4112
ADF4113
100pF
AGND
DGND
3
4
9
51Ω
RFINB 5
100pF
DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE
BEEN OMITTED FROM THE DIAGRAM TO INCREASE CLARITY.
03496-0-040
CP GND
RFINA 6
Figure 35. Local Oscillator Shutdown Circuit
RFOUT
20V
VDD
VP
12V
3kΩ
1kΩ
7
15
16
AVDD DVDD VP
1000pF 1000pF
3.3kΩ
2
VCC
AD820
RSET 1
51Ω
V_TUNE
OUT
M3500-2235
CP
8 REFIN
FREFIN
100pF
2.8nF
19nF
130pF
100pF
18Ω
18Ω
18Ω
GND
680Ω
4.7kΩ
RFINA 6
LOCK
DETECT
100pF
AGND
DGND
RFINB 5
3
4
9
51Ω
100pF
DECOUPLING CAPACITORS ON AVDD, DVDD, VP OF THE ADF4113
AND ON VCC OF THE M3500-2250 HAVE BEEN OMITTED FROM
THE DIAGRAM TO AID CLARITY.
Figure 36. Wideband Phase-Locked Loop
Rev. F | Page 24 of 28
03496-0-041
CE
CLK MUXOUT 14
DATA
LE
CPGND
SPI-COMPATIBLE SERIAL BUS
ADF4113
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
DIRECT CONVERSION MODULATOR
In some applications, a direct conversion architecture can be
used in base station transmitters. Figure 37 shows the combination available from ADI to implement this solution.
The circuit diagram shows the AD9761 being used with the
AD8346. The use of dual integrated DACs such as the AD9761
with specified ±0.02 dB and ±0.004 dB gain and offset matching
characteristics ensures minimum error contribution (over
temperature) from this portion of the signal chain.
The local oscillator (LO) is implemented using the ADF4113. In
this case, the OSC 3B1-13M0 provides the stable 13 MHz
reference frequency. The system is designed for a 200 kHz
channel spacing and an output center frequency of 1960 MHz.
The target application is a WCDMA base station transmitter.
REFIO
IOUTA
The LO port of the AD8346 is driven in single-ended fashion.
LOIN is ac-coupled to ground with the 100 pF capacitor; LOIP
is driven through the ac coupling capacitor from a 50 Ω source.
An LO drive level of between −6 dBm and −12 dBm is required.
The circuit of Figure 37 gives a typical level of −8 dBm.
The RF output is designed to drive a 50 Ω load but must be accoupled as shown in Figure 37. If the I and Q inputs are driven
in quadrature by 2 V p-p signals, the resulting output power is
around −10 dBm.
IBBP
LOW-PASS
FILTER
IOUTB
100pF
VOUT
IBBN
AD9761
TxDAC
AD8346
QOUTA
FS ADJ
QBBP
LOW-PASS
FILTER
QOUTB
QBBN
2kΩ
LOIN
4.7kΩ
LOIP
100pF
OSC 3B1-13M0
TCXO
RSET
100pF 18Ω
3.3kΩ
CP
910pF
ADF4113
3.9kΩ
VCO190-1960T
620pF
9.1nF
RFINB
100pF
100pF
18Ω
REFIN
SERIAL
DIGITAL
INTERFACE
RFOUT
18Ω
RFINA
100pF
51Ω
POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS
ARE OMITTED FROM DIAGRAM TO INCREASE CLARITY.
Figure 37. Direct Conversion Transmitter Solution
Rev. F | Page 25 of 28
03496-0-042
MODULATED
DIGITAL
DATA
Typical phase noise performance from this LO is −85 dBc/Hz at
a 1 kHz offset.
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
INTERFACING
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
833 kHz, or one update every 1.2 µs. This is certainly more than
adequate for systems that have typical lock times in the
hundreds of microseconds.
ADSP-2181 Interface
Figure 39 shows the interface between the ADF4110 family and
the ADSP-21xx digital signal processor. The ADF4110 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
auto buffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated.
SCLK
ADSP-21xx
ADuC812 Interface
TFS
Figure 38 shows the interface between the ADF4110 family and
the ADuC812 MicroConverter®. Since the ADuC812 is based
on an 8051 core, this interface can be used with any 8051 based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4110 family
needs a 24-bit word. This is accomplished by writing three 8-bit
bytes from the MicroConverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.
When power is first applied to the ADF4110 family, three writes
are needed (one each to the R counter latch, N counter latch,
and initialization latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control powerdown (CE input), and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When the ADuC812 is operating in the mode described above,
the maximum SCLOCK rate of the ADuC812 is 4 MHz. This
means that the maximum rate at which the output frequency
can be changed is 166 kHz.
ADuC812
MOSI
SCLK
SDATA
LE
I/O PORTS
CE
ADF4110
ADF4111
ADF4112
ADF4113
MUXOUT
(LOCK DETECT)
Figure 38. ADuC812 to ADF4110 Family Interface
03496-0-043
SCLOCK
DT
I/O FLAGS
SCLK
SDATA
LE
CE
ADF4110
ADF4111
ADF4112
ADF4113
MUXOUT
(LOCK DETECT)
03496-0-044
The ADF4110 family has a simple SPI® compatible serial interface for writing to the device. SCLK, SDATA, and LE control the
data transfer. When latch enable (LE) goes high, the 24 bits that
have been clocked into the input register on each rising edge of
SCLK get transferred to the appropriate latch. See Figure 2 for
the timing diagram and Table 5 for the latch truth table.
Figure 39. ADSP-21xx to ADF4110 Family Interface
Set up the word length for 8 bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the three 8-bit bytes, enable the auto buffered mode, and
then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer.
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This ensures that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This ensures that
shorting is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 oz. copper
to plug the via.
The user should connect the printed circuit board thermal pad
to AGND.
Rev. F | Page 26 of 28
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
20
16
15
0.50
BSC
1
EXPOSED
PAD
2.30
2.10 SQ
2.00
11
TOP VIEW
0.80
0.75
0.70
5
6
10
0.65
0.60
0.55
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.20 MIN
BOTTOM VIEW
08-16-2010-B
PIN 1
INDICATOR
0.30
0.25
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1.
Figure 40. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-6)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
8
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.65
BSC
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. F | Page 27 of 28
0.75
0.60
0.45
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
ORDERING GUIDE
Model 1
ADF4110BCPZ
ADF4110BCPZ-RL
ADF4110BCPZ-RL7
ADF4110BRU
ADF4110BRU-REEL
ADF4110BRU-REEL7
ADF4110BRUZ
ADF4110BRUZ-RL
ADF4110BRUZ-RL7
ADF4111BCPZ
ADF4111BCPZ-RL
ADF4111BCPZ-RL7
ADF4111BRU
ADF4111BRUZ
ADF4111BRUZ-RL
ADF4111BRUZ-RL7
ADF4112BCPZ
ADF4112BCPZ-RL
ADF4112BCPZ-RL7
ADF4112BRU
ADF4112BRU-REEL7
ADF4112BRUZ
ADF4112BRUZ-REEL
ADF4112BRUZ-REEL7
ADF4113BCPZ
ADF4113BCPZ-RL
ADF4113BCPZ-RL7
ADF4113BRU
ADF4113BRU-REEL7
ADF4113BRUZ
ADF4113BRUZ-REEL
ADF4113BRUZ-REEL7
ADF4113BCHIPS
EVAL-ADF4113EBZ1
EVAL-ADF4113EBZ2
EV-ADF411XSD1Z
1
2
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
-40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
20-Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
DIE
Evaluation Board
Evaluation Board
Evaluation Board
Package Option 2
CP-20-6
CP-20-6
CP-20-6
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
CP-20-6
CP-20-6
CP-20-6
RU-16
RU-16
RU-16
RU-16
CP-20-6
CP-20-6
CP-20-6
RU-16
RU-16
RU-16
RU-16
RU-16
CP-20-6
CP-20-6
CP-20-6
RU-16
RU-16
RU-16
RU-16
RU-16
Z = RoHS Compliant Part.
CP-20-6 package was formerly CP-20-1 package.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03496-0-1/13(F)
Rev. F | Page 28 of 28